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hm51w4405bs series 1,048,576-word 4-bit dynamic random access memory ade-203-686a (z) rev. 1.0 nov. 29, 1996 description the hitachi hm51w4405bs series is a cmos dynamic ram organized 1,048,576-word 4-bit. hm51w4405bs series has realized higher density, higher performance and various functions by employing 0.8 m m cmos process technology and some new cmos circuit design technologies. the hm51w4405bs series offers extended data out (edo) page mode as a high speed access mode. it has the package variations of standard 26-pin plastic soj. features single 3.3 v ( 0.3 v) (hm51w4405bs-7) single 3.3 v (+0.3 v/C0.15 v) (HM51W4405BS-6R) high speed ? access time: 60/70 ns (max) low power dissipation ? active mode: 288/252 mw (max) ? standby mode: 7.2 mw (max) edo page mode capability 1024 refresh cycles : 16 ms 3 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh ordering information type no. access time package HM51W4405BS-6R hm51w4405bs-7 60 ns 70 ns 300-mil 26-pin plastic soj (cp-26/20d)
hm51w4405bs series 2 pin arrangement 1 2 3 4 5 9 10 11 12 13 i/o1 i/o2 we ras a9 a0 a1 a2 a3 v cc v i/o4 i/o3 cas oe a8 a7 a6 a5 a4 ss 26 25 24 23 22 18 17 16 15 14 hm51w4405bs series (top view) pin description pin name function a0 to a9 address input row/refresh: a0 to a9 column: a0 to a9 i/o1 to i/o4 data-in/data-out ras row address strobe cas column address strobe we read/write enable oe output enable v cc power supply v ss ground
hm51w4405bs series 3 block diagram 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder i/o bus & column decoder i/o bus & column decoder 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder i/o bus & column decoder i/o bus & column decoder row driver row driver row driver row driver row driver row driver row driver row driver row decoder & peripheral circuit we ras cas row driver row driver row driver row driver row driver row driver row driver row driver row address buffer column address buffer address a0?9 i/o4 buffer ras control circuit cas control circuit we control circuit oe oe control circuit i/o3 buffer i/o2 buffer i/o1 buffer i/o1 i/o2 i/o3 i/o4
hm51w4405bs series 4 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to +4.6 v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v ss 000v (HM51W4405BS-6R) v cc 3.15 3.3 3.6 v 1 (hm51w4405bs-7) v cc 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 note: 1. all voltage referred to v ss .
hm51w4405bs series 5 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v +0.3 v/C0.15 v, v ss = 0 v) (HM51W4405BS-6R) (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w4405bs-7) hm51w4405b -6r -7 parameter symbol min max min max unit test conditions operating current* 1, 2 i cc1 80 70 ma ras , cas cycling, t rc = min standby current i cc2 2 2 ma ttl interface, ras , cas = v ih dout = high-z standby current i cc2 1 1 ma cmos interface ras , cas 3 v cc C0.2 v dout = high-z ras -only refresh current* 2 i cc3 80 70 ma t rc = min standby current* 1 i cc5 4 4 ma ras = v ih , cas = v il dout = enable cas -before- ras refresh current i cc6 80 70 ma t rc = min edo page mode current* 1, 3 i cc4 100 85 ma t hpc = min input leakage current i li C10 10 C10 10 m a 0 v vin 4.6 v output leakage current i lo C10 10 C10 10 m a 0 v vout 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras = v il . 3. address can be changed once or less while cas = v ih . capacitance (ta = 25 c, v cc = 3.3 v +0.3 v/C0.15 v) (HM51W4405BS-6R) (ta = 25 c, v cc = 3.3 v 0.3 v) (hm51w4405bs-7) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-in, data-out) c i/o 7 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras and cas = v ih to disable dout.
hm51w4405bs series 6 ac characteristics ( ta = 0 to + 70 c, v c c = 3.3 v + 0.3 v /C0.15 v , v s s = 0 v ) (h m 51w4405bs - 6r) * 1 , *1 4 , *1 5 (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w4405bs-7) *1, *14, *15 test conditions input rise and fall time : 2 ns input level : v il = 0 v, v ih = 3.0 v input timing reference levels : 0.8 v, 2.0 v output timing reference levels : 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) hm51w4405b -6r -7 parameter symbol min max min max unit notes random read or write cycle time t rc 104 124 ns ras precharge time t rp 40 50 ns ras pulse width t ras 60 10000 70 10000 ns 17 cas pulse width t cas 10 10000 13 10000 ns 18 row address setup time t asr 00ns row address hold time t rah 10 10 ns column address setup time t asc 00ns column address hold time t cah 10 13 ns ras to cas delay time t rcd 20 45 20 50 ns 8 ras to column address delay time t rad 15 30 15 35 ns 9 ras hold time t rsh 15 18 ns cas hold time t csh 48 58 ns 21 cas to ras precharge time t crp 10 10 ns oe to din delay time t odd 15 18 ns oe delay time from din t dzo 00ns cas setup time from din t dzc 00ns transition time (rise and fall) t t 2 50 2 50 ns 7 refresh period t ref 16 16 ms
hm51w4405bs series 7 read cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes access time from ras t rac 60 70 ns 2, 3 access time from cas t cac 15 18 ns 3, 4, 13 access time from address t aa 30 35 ns 3, 5, 13 access time from oe t oac 15 18 ns 3 read command setup time t rcs 00ns read command hold time to cas t rch 00ns16 read command hold time to ras t rrh 00ns16 column address to ras lead time t ral 30 35 ns column address to cas lead time t cal 18 23 ns output buffer turn-off time t off1 15 15 ns 6,19 output buffer turn-off time to oe t off2 15 15 ns 6 cas to din delay time t cdd 15 18 ns ras to din delay time t rdd 15 18 ns we to din delay time t wdd 15 18 ns oe pulse width t oep 15 18 ns turn-off to ras t ofr 15 15 ns 6, 19 turn-off to we t wez 15 15 ns 6 output data hold time t oh 55ns output data hold time from ras t ohr 55ns read command hold time from ras t rchr 60 70 ns read command hold time from cas t rchc 15 18 ns read command hold time from column address t rcha 30 35 ns
hm51w4405bs series 8 write cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes write command setup time t wcs 00ns10 write command hold time t wch 10 13 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 10 13 ns write command to cas lead time t cwl 10 13 ns data-in setup time t ds 00ns11 data-in hold time t dh 10 13 ns 11 read-modify-write cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes read-modify-write cycle time t rwc 133 159 ns ras to we delay time t rwd 77 90 ns 10 cas to we delay time t cwd 32 38 ns 10 column address to we delay time t awd 47 55 ns 10 oe hold time from we t oeh 15 18 ns refresh cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 ns cas hold time (cbr refresh cycle) t chr 10 10 ns ras precharge to cas hold time t rpc 10 10 ns cas precharge time in normal mode t cpn 10 13 ns cbr refresh cycle we setup time t ws 00ns cbr refresh cycle we hold time t wh 10 10 ns
hm51w4405bs series 9 edo page mode cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes edo page mode cycle time t hpc 25 30 ns 20 edo page mode cas precharge time t cp 10 13 ns edo page mode ras pulse width t rasc 100000 100000 ns 12 access time from cas precharge t acp 35 40 ns 3, 13 ras hold time from cas precharge t rhcp 35 40 ns output data hold time from cas low t doh 33ns cas hold time referred oe t col 10 13 ns cas to oe setup time t cop 55ns read command hold time from cas precharge t rchp 35 40 ns edo page mode read-modify-write cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes edo page mode read-modify-write cycle time t hpcm 66 77 ns edo page mode read-modify-write cycle cas precharge to we delay time t cpw 52 60 ns 10
hm51w4405bs series 10 counter test cycle hm51w4405b -6r -7 parameter symbol min max min max unit notes cas precharge time in counter test cycle t cpt 40 40 ns notes: 1. ac measurements assume t t = 2 ns. 2. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 4. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 5. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 6. t off1 (max), t off2 (max), t ofr (max) and t wez (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd , t cpw and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t cpw 3 t cpw (min) and t awd 3 t awd (min), the cycle is a read-modify- write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referred to cas leading edge in an early write cycle and to we leading edge in a delayed write or read-modify-write cycle. 12. t rasc defines ras pulse width in fast page mode cycles. 13. access time is determined by the longest among t aa , t cac and t acp . 14. an initial pause of 100 m s is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 15. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 16. either t rch or t rrh must be satisfied 17. t ras (min) = t rwd (min) + t rwl (min) + t t in read-modify-write cycle. 18. t cas (min) = t cwd (min) + t cwl (min) + t t in read-modify-write cycle. 19. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . 20. t hpc (min) can be achieved during a series of edo page mode early write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle t hpc (t cas + t cp + 2t t ) becomes greater than the specified t hpc (min) value. 21. t csh (min) can be achieved when t rcd t csh (min) Ct cas (min). 22. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max))
hm51w4405bs series 11 ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm51w4405bs series 12 timing waveforms *22 read cycle ras cas address we dout oe din t rc t ras t rp t crp t rcd t rsh t cas t t t rad t ral t asc t cah t asr row column t rah t rcs t rrh t dzc high-z dout t dzo t odd t rac t oep t aa t cac t off1 t csh t cdd t off2 t oac t cal t rdd t ofr t wdd t wez t rchr t rcha t oh t ohr t rch t rchc
hm51w4405bs series 13 early write cycle ras cas address we din dout t rc t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din * t wcs wcs (min) high-z* t
hm51w4405bs series 14 delayed write cycle address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t odd t oeh t off2 * high-z din invalid dout comes out, when oe is low level. invalid dout* *
hm51w4405bs series 15 read-modify-write cycle address ras din dout oe we cas t rwc t ras t rp t crp t cas t rcd t t t rad t asr tt asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t odd t t oep t cac t aa t oac t rac t off2 oeh rah dout
hm51w4405bs series 16 ras -only refresh cycle cas ras address t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z dout
hm51w4405bs series 17 cas -before- ras refresh cycle rpc ras cas we * dout address t rp t ras t rp t rc t crp t chr t csr t rpc t t t t ws t wh t cpn t high-z off1 t ofr t cpn * t ws and t wh must be satisfied while cas = v il .
hm51w4405bs series 18 hidden refresh cycle din oe dout we address cas ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rcd t rsh t chr t crp t rad t ral t cah t asr t rah t asc t rcs cdd dzo t odd t t t cac t aa t rac t column row oac t high-z t cas rrh t rch t off1 t dzc t (read) (refresh) (refresh) ohr t t oh rdd t wez t wdd t off2 dout
hm51w4405bs series 19 edo page mode read cycle (t hpc minimum cycle operation) we din oe dout address cas ras t rasc t rhcp t rp t t t csh t rcd t cas t cp t cas t hpc t rsh t cp t cas t crp t ral t cah t asc t t asc t t rad t asr t rah t t rrh t rch t cdd t wez t high-z t t aa t t acp t t rac t aa t cac t cac t cac dout 3 dout 2 dout 1 row column 3 cah cah rcs asc t dzc t off1 t off2 t oac t dzo column 2 column 1 t rchp t rchc t rcha t oh t ohr t doh t doh t ofr acp aa t cal t cal t cal odd
hm51w4405bs series 20 edo page mode read cycle (high-z control by we and oe ) din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t off2 t off1 t oh t ohr t t col t t acp t aa t cac t cac t oac t aa t rac t aa t cac t acp t t oac t off2 t aa t cac t t rasc cop t rp t cas t cas t cas t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wdd t ral t cal t cal t cal row dout 2 dout 4 acp dout 1 t cas t rcs t t rcs dout 3 t doh t rhcp t hpc t cal t oac t wez dzo t odd dout 2 off2 rch t rchr t rchp t rchc t rcha t rchc asc
hm51w4405bs series 21 edo page mode early write cycle (t hpc minimum cycle operation) ras cas address we din dout t rasc t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row t wcs t wcs t wcs t wch t wch t wch t ds t dh t ds t dh t ds t dh din din din high-z column column column
hm51w4405bs series 22 edo page mode delayed write cycle din we address ras dout cas t rasc t rp t t t csh t hpc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t t asc t cah t asc t cah row column t t rcs tt wp t cwl t cwl t t t t ds t t ds t dh din din din t rwl t rcs wp cah t rcs wp cwl dh ds dh oe t odd t oeh high-z column column
hm51w4405bs series 23 edo page mode read-modify-write cycle din dout address ras t rasc t t cp t hpcm t t t rcd t t cp t rad t asr t asc t t t rah t t cah t t cpw t t cpw t cwl t rwd t awd t awd t awd t cwd t t cwd t cwd t rcs t wp t t wp t ds t t dh t t ds t dzc t dh t odd t dh t t dzo t oeh t oeh t oeh t aa t t off2 din din din t rp t rwl t oac t odd t off2 t t odd t dzo t off2 t t t dzo aa t we cas oe dout dout dout t cah t ds column column column row rac cwl acp wp cwl t crp asc acp t asc rcs high-z high-z oac t dzc dzc rcs oac t cas t cas t cas aa t t oep t oep t oep cah cac cac high-z cac
hm51w4405bs series 24 edo page mode mix cycle (1) *20 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t off2 t off1 t oh t t cac t aa t cac t t t aa t oac t t rasc t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal t cal t cal row dout 2 dout 4 acp t cas t wcs dout 3 t doh t wp t wch t wdd t wez t ds t dh t ds t dh din 3 din 1 t cal t oac t odd t cac t asc t cpw t awd off2 acp aa t acp rchp t dzo t rchc t rcha t t csh t asc
hm51w4405bs series 25 edo page mode mix cycle (2) *20 din oe dout we address ras cas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t off2 t off1 t oh t acp t aa t cac t aa t cac t off2 t aa t oac t t rasc t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t cal t cal t cal row dout 1 dout 4 acp t cas dout 3 t wdd t wez t ds t dh t ds t din 3 din 2 t cal t oac t t cac t asc t wcs t rch t rcs t wch t rac t odd t dzo t oac t off2 dh odd t rchr t cpw t wp t cwl t rchp t rchc t rcha t dzo
hm51w4405bs series 26 cas -before- ras refresh counter check cycle (read) dout address ras cas we t ras t rp t chr t csr t t t cpt t rsh t cas t crp t cah t asc column t ws t wh t rcs t rch t rrh t off1 t aa t cac dout din t cdd t high-z oe t dzo t odd dzc t off2 t oac t oep t ohr t ofr t oh t cal
hm51w4405bs series 27 cas -before- ras refresh counter check cycle (write) ras cas address we din dout t rp t t t csr t chr t cpt t rsh t crp t cas t asc t cah column t wch t wcs t wh t ws t ds t dh din high-z oe t ras t cal
hm51w4405bs series 28 package dimensions hm51w4405bs series (cp-26/20d) unit: mm 16.90 17.27 max 0.74 6.71 ?0.28 7.62 ?0.13 8.51 ?0.13 26 14 1 13 0.10 5.08 0.43 ?0.10 3.50 ?0.26 + 0.21 ?0.24 2.40 1.30 max 59 22 18 0.80 +0.25 ?.17 1.27 hitachi code jedec code eiaj code weight cp-26/20d mo-077-aa sc-633a 0.6 g 0.41 ?0.08
hm51w4405bs series 29 disclaimer when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. sales offices hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071
hm51w4405bs series 30 revision record rev. date contents of modification drawn by approved by 1.0 nov. 29, 1996 initial issue

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