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tnt4882 single-chip ieee 488.2 talker/listener asic description the tnt4882 provides a single-chip ieee 488.2 talker/listener interface to the general-purpose interface bus (gpib). the tnt4882 combines the circuitry of the nat4882 ieee 488.2 application-specific integrated circuit (asic), turbo488 performance-enhancing asic, and gpib transceivers to create a single-chip ieee 488.2 interface. because the tnt4882 contains the nat4882 register set, which in turn has the nec pd7210 and ti tms 9914a register sets, developers using any of these chips can easily port existing code directly to the tnt4882, thereby signi?cantly reducing software development time. also, with just a few modifications, you can implement all the improved features of the ieee 488.2 standard. the tnt4882 is ideal for use in all ieee 488 instrument designs because of its small size, surface-mount ability, and performance enhancements that include hs488, a new high-speed mode for gpib transfers. hs488 overview the hs488 high-speed mode for gpib transfers increases the maximum data transfer rate of devices on a gpib network up to 8 mbytes/s. the tnt4882 completely and transparently handles the hs488 protocol without additional circuitry, a method that is a superset of the ieee 488 standard. thus, you can mix existing gpib devices with hs488 devices without changing your application programs. the tnt4882 can implement high-speed data transfers automatically. maximum data transfer rates obtainable using hs488 depend on the host architecture and system con?guration. architecture, modes the tnt4882 integrates the circuitry of the turbo488, nat4882, and ieee 488.1- compatible transceivers. the tnt4882 circuitry logically interconnects these three components in one of two ways C one-chip mode (see figure 1) or two-chip mode (see figure 2). the tnt4882 powers up in two-chip mode, which exactly duplicates the turbo488/nat4882 chipset for software compatibility. during i/o accesses in two-chip mode, the cpu accesses the turbo488 and passes all accesses within a certain address range to the nat4882. the turbo488 also manages transfers between its internal ?rst-in ?rst-out buffers (fifos) and the nat4882, arbitrating between these data transfers and any i/o accesses of the nat4882 by the cpu. accesses to the nat4882 registers take longer than turbo488 accesses because all accesses to the nat4882 registers must go through the turbo488 and its arbiter. to achieve higher data transfer rates, you can switch the tnt4882 to one-chip mode in software. in one-chip mode, the first-in first-out (fifo) buffer connects directly to the gpib transceivers and the cpu accesses all registers directly. you can access nat4882 registers in the same amount of time as turbo488 registers because accesses to these registers do not go through the turbo488. the nat4882 portion of the tnt4882 can emulate either the nec pd7210 or the ti tms9914a gpib controller chips. the state of one of the tnt4882 input pins determines the chip emulation mode on power up, but you can switch the chip emulation mode back and forth between 7210 and 9914 modes through software. features 100-pin plastic quad ?at pack (qfp), surface- mount package ieee 488.1-compatible transceivers on chip fast data transfers C up to 1.5 mbytes/s using interlocked ieee 488.1 handshake C up to 8 mbytes/s using hs488 ? two 8-bit 16-deep fifos buffer data between gpib and cpu with exception of controller, performs all ieee 488 interface functions C sh1, ah1, t5 or te5, l3 or le3, sr1, rl1, pp1 or pp2, dc1, dt1, and c0 meets all ieee 488.2 requirements C bus line monitoring C preferred implementation of requesting service C not sending messages when there are no listeners software compatible with turbo488 ? /nat4882 ? asics reduces software overhead C does not lose a data byte if atn is asserted while transmitting data C static interrupts status bits that do not clear when read C automatically transmits end or performs rfd holdoff on last byte of dma transfer C interrupts when handshake is complete on last byte of a dma transfer C has 32-bit counter for large, uninterrupted data transfers programmable timer interrupt for general-purpose timing use complete in-system functional testing with internal loop-back mode isa bus glue logic on chip direct memory access (dma) device status indicator pins C my address, talk addressed, listen addressed, rem, dcas, trig automatically processes ieee 488 commands and reads unde?ned commands handles 6 primary and secondary addressing modes automatic eos and/or nl message detection programmable data transfer rate C ttl-compatible cmos device new! 340570d-01 030599
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 2 isa interface logic ieee 488 monitor interrupt control configuration and status registers timer read/ write control byte counter ieee 488 transceivers ieee 488 interface functions hs488 interface functions fifos ieee 488 bus gpib turbo488 circuitry read/ write control isa interface logic fifos nat4882 interface circuitry byte counter ieee 488 monitor read/ write control timer gpib data registers ieee 488 interface functions interrupt control interrupt control nat4882 circuitry transfer state machine configuration and status registers configuration and status registers ieee 488 transceivers local gpib signals figure 1. tnt4882 one-chip mode figure 2. tnt4882 two-chip mode the register map of the nat4882 portion of the tnt4882 changes to emulate either the 7210 or the 9914, but the turbo488 registers are identical in both chip emulation modes. you cannot use one-chip mode with the 9914 emulation mode. because the turbo488 was designed to interface to the 7210 and not the 9914, the software can rearrange the register map of the 9914 mode nat4882 registers so that the 9914 mode command/data out register and data in register and the auxiliary command register appear at the same addresses as the corresponding 7210 mode registers. the turbo488 can then perform dma transfers with the nat4882 in 9914 mode. the tnt4882 has two different pin con?gurations C generic (see figure 3) and isa (see figure 4). the tnt4882 determines which con?guration to use by the location of the power (vdd) and ground pins. the generic pin configuration provides a simple interface to any cpu. using the isa pin con?guration, you can connect the tnt4882 directly to an isa (ibm pc at) bus without any external glue logic or data transceivers. you can also use the isa pin con?guration tnt4882 with an 8-bit (pc/xt) bus. you may want to use the isa version for interfaces other than an isa bus to take advantage of the built-in 5-bit address decoder. you can use two-chip mode, one-chip mode, 7210 mode, and 9914 mode identically with either pin con?guration. tnt4882 block diagrams
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 3 dio6n gnd ladcs dio8n gnd ifcn dio5n srqn gnd dio7n atnn renn gnd resetn 80 79 78 77 76 75 74 73 72 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1234567891011121314151617 71 70 69 68 67 66 65 64 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 gnd data5 data4 gnd gnd vdd gnd data0 intr dackn drq burst_rdn davn gnd vdd gnd dio2n dio1n dio3n vdd xtal1 eoin wrn gnd vdd trig cpuacc tadcs abus_oen addr4 addr3 addr2 addr1 addr0 abusn paged gnd rem swapn fifo_rdy tnt4882 generic pin configuration dio4n gnd xtal0 gnd keyclkn keydq keyrstn data3 data2 data1 gnd vdd rdy1 vdd 18 19 20 21 22 23 24 25 26 27 28 29 30 data10 gnd data11 data12 data13 gnd data14 data15 bbus_oen data9 data8 vdd gnd 48 gnd 49 data6 50 data7 63 rdn 62 bbusn 61 gnd 60 vdd 59 gnd 58 vdd 57 gnd 56 gnd 55 csn 54 gnd 53 mode 52 nc 51 dcas 83 gnd 82 nrfdn 81 ndacn generic pin con?guration figure 3. tnt4882 generic pin con?guration table continued on page 4 pin no.(s) name(s) type description 1 bbus_oen o asserts when data7-0 (b bus) is enabled for output 2,3,5,6,7,9,10,11 data15-8 i/o upper 8 bits of bidirectional three-state data bus for transfer of commands, data, and status between tnt4882 and cpu C also known as the a bus 14 abusn i enables register accesses through the a bus (data15-8) C data15 is the most signi?cant bit 19-15 addr4-0 i determines which register to access during a read or write operation 20 abus_oen o asserts when data15-8 (a bus) is enabled for output 21 tadcs o asserts when the tnt4882 is an active or addressed ieee 488 talker (tads, tacs, or spas) 22 cpuacc o asserts in two-chip mode during a nat4882 register i/o access 23 trig o asserts when in dtas or when the auxiliary trigger software command is issued 26 paged i asserting this pin pages in the page-in registers in the 7210 mode 28 rem o asserts when the tnt4882 is in a remote state (rems or rwls) 29 swapn i rearranges the order of the registers when asserted and in 9914 mode 30 fifo_rdy o asserts when the fifo is ready for burst access 31 burst_rdn i when asserted, places the tnt4882 in a burst read mode, in which the ?rst word in the fifo is always driven on the tnt4882 data bus C words are removed from the fifos at each rising edge of rdn C see reference manual for details 32 drq o asserts to request a dma transfer cycle 33 dackn i enables fifo accesses during a dma transfer cycle 34 intr o asserts when one or more of the unmasked interrupt conditions becomes true 38 rdy1 o asserts during an i/o access to indicate that the read data is available or that the write data has been latched C asserts immediately on an access to turbo488 registers or in one-chip mode 50,49,47,46, data7-0 i/o lower eight bits of bidirectional three-state data bus for transfer of commands, data, and 44,43,42,39 status between tnt4882 and cpu C also known as the b bus C data7 is the most signi?cant bit generic pin description all pins with names that end in n are active low; all others are active high. all input (i) and bidirectional (i/o) pins have an internal pull-up resistor between 50 k and 150 k . note: you can also see the hardware considerations chapter of the tnt programmer reference manual (p/n 320724-01) for more information.
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 4 pin no.(s) name(s) type description 51 dcas o asserts when the device clear state machine is in dcas 52 nc o leave this pin unconnected 53 mode i determines whether the tnt4882 powers up in 7210 or 9914 emulation mode C high = 7210 mode, low = 9914 mode 55 csn i chip select enables i/o transfers between the cpu and the tnt4882 62 bbusn i enables register accesses through the b bus (data7-0) 63 rdn i enables the contents of the registers selected by addr 4:0 and csn or the fifos to appear on the data bus selected by abusn and bbusn 64 wrn i latches data on the bus selected by abusn and bbusn into an internal tnt4882 register on the trailing (rising) edge of wrn 66 ladcs o asserts when the tnt4882 is addressed as a listener 67 resetn i holds the tnt4882 in its idle state 71,74,77,80,88, dio8-1n i/o 8-bit bidirectional ieee 488 data bus 89,91,92 70,73,76,79, renn, atnn, srqn, i/o ieee 488 control signals 81,82,84,85 ifcn, ndacn, nrfdn, davn, eoin 95 xtal0 o output of crystal circuit C use only for driving a quartz crystal 96 xtal1 i crystal oscillator input C drive with a 40 mhz cmos input level clock signal 98 keyclkn o strobes data to or from a ds1204 electronic key 99 keydq i/o transmits serial data between the tnt4882 and a ds1204 key 100 keyrstn o resets a ds1204 key 4,8,13,25,27,35,37 gnd _ ground pins C 0 v 41,45,48,54,56,57, 59,61,65,68,72,75, 78,83,86,90,93,97 12,24,36,40,58, vdd _ power pins C +5 v (5%) 60,69,87,94 dio6n gnd iocs16n dio8n gnd ifcn dio5n srqn gnd dio7n atnn renn gnd reset 80 79 78 77 76 75 74 73 72 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1234567891011121314151617 71 70 69 68 67 66 65 64 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 gnd data5 data4 gnd aen_n vdd gnd data0 intr dackn drq addr9 davn gnd vdd gnd dio2n dio1n dio3n vdd xtal1 eoin iown gnd vdd sw7 sw6 nc d15_8_oen addr4 addr3 addr2 addr1 addr0 bhen_n addr5 gnd addr6 addr7 addr8 tnt4882 isa pin configuration dio4n gnd xtal0 gnd keyclkn keydq keyrstn data3 data2 data1 gnd vdd iochrdy vdd 18 19 20 21 22 23 24 25 26 27 28 29 30 data10 gnd data11 data12 data13 gnd data14 data15 d7_0_oen data9 data8 vdd gnd 48 gnd 49 data6 50 data7 63 iorn 62 sense_8_16n 61 gnd 60 vdd 59 vdd 58 vdd 57 gnd 56 vdd 55 sw5 54 nc 53 mode 52 sw9 51 sw8 83 gnd 82 nrfdn 81 ndacn isa pin con?guration figure 4. tnt4882 isa pin con?guration table continued from page 3
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 5 isa pin description all input (i) and bidirectional (i/o) pins have an internal pull-up resistor between 50 k and 150 k . pins with names that end in n are active low signals C all others are active high. open-collector outputs are type oc. note: you can also see the hardware considerations chapter of the tnt programmer reference manual (p/n 320724-01) for more information. pin no.(s) name(s) type description 1 d7_0_oen o asserts when data7-0 bus is enabled for output C may be left unconnected 2,3,5,6,7,9,10,11 data15-8 i/o upper eight bits of bidirectional three-state data bus for transfer of commands, data, and status between tnt4882 and cpu C can connect directly to the at bus C data15 is the most signi?cant bit 14 bhen_n i enables access to upper eight bits of data bus when asserted 19-15 addr4-0 i determines which register will be accessed during an i/o access 31,30,29,28,26 addr9-5 i determines if an i/o address is within the range occupied by the tnt4882 C the chip is selected and an i/o access occurs when addr9-5 match sw9-5 and aen_n is asserted 20 d15_8_oen o asserts when data15:8 bus is enabled for output C may be left unconnected 21,54 nc o leave unconnected 52,51,23,22,55 sw9-5 i determines the base address of the tnt4882 32 drq o asserts to request a dma transfer cycle 33 dackn i enables fifo accesses during a dma transfer cycle 34 intr o asserts when one or more of the unmasked interrupt conditions becomes true 37 aen_n i enables i/o accesses to the tnt4882 38 iochrdy oc when the tnt4882 is not accessed, this open-collector signal is not driven, and a pull-up resistor on the system board keeps it pulled high C at the start of some tnt4882 accesses, the tnt4882 may drive it low, then pull it high again during the cycle to indicate that the tnt4882 is ready for the cpu to end that cycle 50,49,47,46,44, data7-0 i/o lower eight bits of bidirectional three-state data bus for transfer of commands, data, 43,42,39 and status between tnt4882 and cpu C can connect directly to the at bus C data7 is the most signi?cant bit 53 mode i forces the tnt4882 to 7210 (high) or 9914 (low) emulation mode on a hardware reset C may be left unconnected 62 sense_8_16n i pull this pin low to tell the tnt4882 that it is connected to a 16-bit bus C leave it unconnected if the tnt4882 is connected to an 8-bit bus 63 iorn i drives the contents of the register selected by addr4-0 on the data bus when the tnt4882 is selected 64 iown i the value on the data bus is latched into the register selected by addr4-0 on the rising edge of iown when you select the tnt4882 66 iocs16n oc driven low during an access to the upper data bus 67 reset i causes a hardware reset and holds the tnt4882 in its idle state while asserted 71,74,77,80,88, dio8-1n i/o 8-bit bidirectional ieee 488 data bus 89,91,92 70,73,76,79,81, renn, atnn, srqn, i/o ieee 488 control signals 82,84,85 ifcn, ndacn, nrfdn, davn, eoin 95 xtal0 o output of crystal circuit C use only for driving a quartz crystal 96 xtal1 i crystal oscillator input C drive with a 40 mhz cmos input level clock signal 98 keyclkn o strobes data to or from the ds1204 electronic key 99 keydq i/o transmits serial data between the tnt4882 and a ds1204 key 100 keyrstn o resets a ds1204 key 4,8,13,25,27,35,41, gnd C ground pins C 0 v 45,48,57,61,65,68,72, 75,78,83,86,90,93,97 12,24,36,40,56,58, vdd C power pins C +5 v (5%) 59,60,69,87,94
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 6 tnt4882 register map notes on register map 1. for complete register descriptions, see the tnt4882 programmer reference manual (320724-01) 2. some of the 7210 mode registers, such as the isr1, have the same names as some of the 9914 mode registers. the 7210 mode registers are not the same as their 9914 mode counterparts. be sure to refer to the appropriate bit map for the chip emulation mode you are using when programming these registers. 3. the shaded registers are paged-in registers. paged-in registers only exist in 9914 mode. writing to the address of the 9914 mode adsr normally does not access any registers. writing one of four page-in commands to the auxcr changes all subsequent writes to that address to that of the corresponding paged-in register. the two readable paged-in registers, the 9914 mode spsr and isr2, are both paged in whenever any one of the four writable paged-in registers is paged in. when you write the clear page-in command to the auxcr, all paged-in registers are paged out again and are no longer accessible. 4. there are several unused bytes in the address space of the tnt4882. these addresses are reserved for adding new features to the chip. you should not map any external hardware into these addresses or access them at any time, as this may cause compatibility problems with future versions of the tnt4882. nat4882 registers 7210 mode 9914 mode 9914 mode swapped addr4-0 hex offset read register write register read register write register read register write register 00000 0 dir cdor isr0 imr0 dir cdor 00010 2 isr1 imr1 isr1 imr1 cptr ppr 00100 4 isr2 imr2 adsr imr2 spsr spmr eosr bcr accr 00110 6 spsr spmr bsr auxcr isr2 adr 01000 8 adsr admr isr2 adr adsr imr2 eosr bcr accr 01010 a cptr auxmr spsr spmr bsr auxcr 01100 c adr0 adr cptr ppr isr0 imr0 01110 e adr1 eosr dir cdor isr1 imr1 10001 11 dsr sh_cnt C C C C 10011 13 C hier C C C C 10101 15 C misc C C C C 10111 17 csr keyreg C C C C 11011 1b sasr dcr C C C C 11101 1d isr0 imr0 C C C C 11111 1f bsr bcr C C C C turbo488 registers (same in all modes) addr4-0 hex offset read register write register 01001 9 cnt2 cnt2 01011 b cnt3 cnt3 01101 d C hssel 10000 10 sts1 cfg 10010 12 imr3 imr3 10100 14 cnt0 cnt0 10110 16 cnt1 cnt1 11000 18 fifob fifob 11001 19 fifoa fifoa 11010 1a isr3 ccr 11100 1c sts2 cmdr 11110 1e timer timer special registers only accessible in isa pin con?guration addr4-0 hex offset read register write register 00101 5 C accwr 00111 7 C intr
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 7 nc at(isa) bus connector tnt4882 dio7n dio1n gpib ndacn ifcn nc nc nc nc nc nc nc nc nc nc nc nc nc nc bale sa19-16 la23-17 smemr* smemw* memr* memw* memcs16* nows* refresh* master16* iochk* bclk osc tc connect dackn, drq, and intr to one of the available lines on the at bus. sd15-0 sa9-0 sbhe* aen iochrdy reset iow* ior* iocs16* dack*7-5 drq7-5 irq (3-7,9,10-12,14,15) data15-0 addr9-0 bhen_n aen_n iochrdy reset iown iorn iocs16n dackn drq intr sense_8_16n nc nc nc nc nc nc d15_8_oen d7_0_oen mode keyrstn keydq keyclkn dio8n dio2n dio3n dio4n dio5n dio6n renn nrfdn davn eoin atnn srqn 40 mhz cmos oscillator xtal0 xtal1 sw9 sw8 sw7 sw6 sw5 nc nc nc nc } the tnt4882 is selected when the binary value on these pins matches that on addr9-5. connecting them to ground causes the corresponding address lines to be compared to zero; leaving them unconnected causes those address lines to be compared to one. (base i/o address 2c0 hex shown.) nc pc/xt bus connector tnt4882 dio7n dio1n gpib ndacn ifcn nc nc nc nc nc nc nc nc nc nc nc bale sa19-16 la23-17 smemr* smemw* memr* memw* refresh* iochk* bclk osc tc connect dackn, drq, and intr to one of the available lines on the pc bus. sd7-0 sa9-0 aen iochrdy reset iow* ior* dack*3-1 drq3-1 irq7-2 data7-0 addr9-0 aen_n iochrdy reset iown iorn dackn drq intr sense_8_16n nc nc nc nc nc nc d15_8_oen d7_0_oen mode keyrstn keydq keyclkn dio8n dio2n dio3n dio4n dio5n dio6n renn nrfdn davn eoin atnn srqn 40 mhz cmos oscillator xtal0 xtal1 sw9 sw8 sw7 sw6 sw5 nc nc nc nc } the tnt4882 is selected when the binary value on these pins matches that on addr9-5. connecting them to ground causes the corresponding address lines to be compared to zero; leaving them unconnected causes those address lines to be compared to one. (base i/o address 2c0 hex shown.) nc nc data15-8 figure 5. pc/xt and at (isa) bus to isa mode tnt4882 hardware interfacing C isa mode tnt4882
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 8 sense_8_16n bhen_n addr4-0 iorn iown data15-8 data7-0 0 0 11000 0 1 fifoa fifob 0 0 11000 1 0 fifoa fifob 0 0 xxxx1 0 1 read not driven 0 0 xxxx1 1 0 written ignored 0 1 xxxx0 0 1 not driven read 0 1 xxxx0 1 0 ignored written 1 1 xxxx0 0 1 not driven read 1 1 xxxx0 1 0 ignored written 1 1 xxxx1 0 1 not driven read 1 1 xxxx1 1 0 ignored written isa pin con?guration byte lane table this table shows which byte lane accesses the tnt4882 internal registers during an i/o access when you use the isa pin configuration. all combinations of addr4-1, sense_8_16n, and bhen_n not shown in this table are illegal. you should not apply these combinations to the tnt4882 while the chip is selected. the accessed register is determined only by addr4-0, not sense_8_16n or bhen_n.
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 9 generic pin con?guration byte lane table this table shows which byte lanes will access tnt4882 registers during i/o accesses. figure 6. intel cpu to generic mode tnt4882 74245 cpu (80186) tnt4882-aq (generic) gpib 74573 nc nc nc nc nc nc 40 mhz cmos oscillator nc nc nc nc dio8n dio7n dio6n dio5n dio4n dio3n dio2n dio1n renn ndacn nrfdn davn eoin atnn srqn ifcn xtal0 xtal1 keyrstn keydq keyclkn tadcs ladcs rem trig dcas abus_oen bbus_oen nc nc nc nc nc nc ad0 drq wrn dackn data7-0 resetn bbusn addr4-0 abusn intr csn cpuacc paged swapn burst_rdn fifo_rdy mode rrn rdy1 data15-8 drq0 ardy rd bhe int0 ale den ad15-0 wr reset dt/r 73245 decode hardware interfacing C generic mode tnt4882 abusn bbusn addr4-0 d15-8 d7-0 0 1 11000 fifob unused 1 0 11000 unused fifob 0 0 11000 fifoa fifob 0 1 xxxxx* used unused 1 0 xxxxx* unused used *any address except 11000
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 10 generic mode dc characteristics parameter symbol min max unit notes supply voltage v dd 4.75 5.25 v voltage input low v il -0.5 0.8 v voltage input high v ih 2.0 v cc v voltage output low v ol 0.0 0.4 v voltage output high v oh 2.4 v dd v supply current i dd 90 ma 50 ma, typical output current low i ol 24 ma v ol = 0.4 v data15-0, ladcs, drq, intr, rdy1 output current low i ol 8ma v ol = 0.4 v bbus_oen, abus_oen, tadcs, cpuacc, rem, trig, dcas, cic fifo_rdy i ol 4ma v ol = 0.4 v output current low i ol 2ma v ol = 0.4 v keydq, keyrstn, keyclkn dio8-1n, ifcn, srqn, eoin, atnn, i ol 48 ma v ol = 0.4 v renn, davn, nrfdn, ndacn output current high i oh -12 ma v oh = v dd -0.5 v data15-0, ladcs, drq, intr, rdy1 -24 ma v oh = 2.4 v output current high i oh -4 ma v oh = v dd -0.5 v bbus_oen, abus_oen, tadcs, cpuacc, rem, trig, dcas -8 ma v oh = 2.4 v fifo_rdy i oh -2 ma v oh = v dd -0.5 v -4 v oh = 2.4 v output current high i oh -1 ma v oh = v dd -0.5 v keydq, keyrstn, keyclkn -2 ma v oh = 2.4 v dio8-1n, ifcn, srqn, eoin, atnn, i oh 16 ma v oh = 2.4 v renn, davn, nrfdn, ndacn input leakage current C all pins i ih 10 m a v dd = 5.5 v output leakage current C all pins i oz 10 m a v dd = 5.5 v generic mode capacitance parameter symbol min typ max unit notes pin capacitance c 50 pf dio8-1n, renn, atnn, ifcn, srqn, davn, eoin, ndacn, nrfdn pin capacitance all other pins c 3.6 pf generic mode ac characteristics commercial industrial parameter symbol min max min max unit address setup to rdn = 0, wrn = 0 t as 24 27 ns data delay from rdn = 0, csn = 0 (one-chip mode access) t rd 71 78 ns data ?oat from rdn = 1 t df 40 44 ns rdn pulsewidth (i/0 access) t rw 71 78 ns rdn recovery width t rr 40 44 ns address hold from rdn = 1, wrn = 1 t ah 00ns drq unassertion t du 78 86 ns data delay from rdn = 0, dackn = 0 t dr 40 44 ns data setup to wrn = 1 t ws 14 16 ns data hold from wrn = 1 t wh 00ns csn setup to rdn or wrn t cs 00ns csn hold from rdn or wrn t ch 00ns dackn setup to rdn or wrn t ds 00ns dackn hold from rdn or wrn t dh 00ns rdn or wrn to cpuacc (two-chip mode nat4882 access only) t cpu 26 29 ns rdn or wrn to rdy1 assert t ardy two-chip mode nat4882 access 10 10 clock periods other accesses 25 28 ns rdn or wrn to rdy1 unassert t urdy 22 25 ns wrn pulse width (dma access) t wp 40 44 ns rdn pulse width (dma access) t rp 40 44 ns
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 11 figure 8. dma read figure 7. cpu read figure 9. cpu write generic mode ac characteristics waveforms waveforms continued on page 12 data wrn csn abusn, bbusn, addr4-0 t as t cs t wh t ch t ah t ws t wp t cpu t urdy t ardy t cpu rdy1 cpuacc ?? ?? cpuacc asserts during two-chip mode nat4882 accesses only drq dackn rdn data15-0 t du t dr t ds t dh t df rdy1 t rdyq t urdy t rp abusn, bbusn, addr4-0 t as t ah csn t cs t ch rdn data t df t rd t urdy t cpu t ardy t rw t cpu rdy1 cpuacc ?? ?? cpuacc asserts during two-chip mode nat4882 accesses only
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 12 wrn drq dackn data15-0 t ws t wh t du t ds t dh figure 10. dma write waveforms continued from page 11 isa mode dc characteristics parameter symbol min max unit notes supply voltage v dd 4.75 5.25 v voltage input low v il -0.5 0.8 v voltage input high v ih 2.0 v cc v voltage output low v ol 0.0 0.4 v voltage output high v oh 2.4 v dd v supply current i dd 90 ma 50 ma, typical output current low i ol 24 ma v ol = 0.4 v data15-0 drq, intr, iocs16, iochrdy output current low i ol 16 ma v ol = 0.4 v d7_0_oen output current low i ol 8ma v ol = 0.4 v d15_8_oen, tp_intwtn output current low i ol 2ma v ol = 0.4 v keydq, keyrstn, keyclkn output current low dio8-1n, renn, atnn, ifcn, srqn, i ol 48 ma v ol = 0.4 v davn, eoin, ndacn, nrfdn output current high i oh -12 ma v oh = v dd -0.5 v data15-0 drq, intr -24 ma v oh = 2.4 v output current high i oh -8 ma v oh = v dd -0.5 v d7_0_oen -16 ma v oh = 2.4 v output current high i oh -4 ma v oh = v dd -0.5 v d15_8_oen, tp_intwtn -8 ma v oh = 2.4 v output current high i oh -1 ma v oh = v dd -0.5 v keydq, keyrstn, keyclkn -2 ma v oh = 2.4 v output current high dio8-1n, renn, atnn, ifcn, srqn, i oh -16 ma v oh = 2.4 v davn, eoin, ndacn, nrfdn input leakage current C all pins i ih 10 ma v dd = 5.5 v output leakage current C all pins i oz 10 ma v dd = 5.5 v
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 13 figure 11. i/o read access waveforms continued on page 14 isa mode capacitance parameter symbol min typ max unit notes pin capacitance c 3.6 pf data15-0, drq, intr, iocs16n, iochrdy, addr6 pin capacitance c 3.0 pf d7_0_oen, d15_8_oen, tp_intwtn, keydq, keyrstn, keyclkn, addr4, addr8, addr9 pin capacitance c 3.5 pf bhen_n, addr3-0, addr5, addr7, dackn, aen_n, mode, testmode, pwbsel2-0, sw9, sense_8_16n, iorn, iown, reset pin capacitance c 50 pf dio8-1n, renn, atnn, ifcn, srqn, davn, eoin, ndacn, nrfdn parameter symbol min max unit notes addr9-0 setup to iorn, iown t as 30 ns addr9-0 hold from iorn, iown t ah 0ns dackn setup to iorn, iown t ds 0ns dackn hold from iorn, iown t dh 20 ns data setup time to iown rising t su 22 ns data hold time from iown rising t wh 0ns iorn low pulse width t rpwl 100 ns iorn high pulse width t rpwh 42 ns iown low pulse width t wpwl 100 ns iown high pulse width t wpwh 100 ns iorn or iown held from iochrdy t td 20 ns drq unassertion time t du 73 ns due to fifo full/empty drq unassertion time t du 48 ns due to byte count reached data access time from iorn falling, dma t dacc 80 ns data access time from iorn falling, i/o t acc 80 ns data hold time from iorn rising t rh 0ns data ?oat time from iorn rising t df 30 ns iocs16n assertion after valid address t dec 30 ns iocs16n negation after invalid address t decn 20 ns iochrdy negation from iorn or iown t rdyn 40 ns iochrdy release after iorn or iown t rdy 350 ns isa mode ac characteristics addr9-0, aen_n iorn data15-0 iocs16n iochrdy t ah t rh t df t decn t td t rdy t rdyn t acc t dec t as t rpwl t rpwh isa mode ac characteristics waveforms
tnt4882 single-chip ieee 488.2 talker/listener asic national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 14 waveforms continued from page 13 figure 13. dma read access figure 14. dma write access figure 12. i/o write access addr9-0, aen_n iown data15-0 iocs16n iochrdy t ah t decn t td t rdy t rdyn t dec t as t wpwl t wpwh t wh t su iorn drq dackn data15-0 t df t rh t du t ds t dh t rpwh t dacc t rpwl iown drq dackn data15-0 t wh t du t ds t dh t wpwh t wpwl t su
national instruments phone: (512) 794-0100 ? fax: (512) 683-9300 ? info@natinst.com ? www.natinst.com 15 tnt4882 single-chip ieee 488.2 talker/listener asic figure 16. mechanical data figure 17. recommended land pattern (not to scale) absolute maximum ratings property range units supply voltage, v dd - 0.5 to + 7.0 v input voltage, v in - 0.5 to v cc + 0.5 v output voltage, v out - 0.5 to v cc + 0.5 v storage temperature, t stg - 55 to 150 ? c 18.85 pin 1 index front view side view pin 1 pin 30 pin 31 pin 51 pin 50 pin 80 pin 81 pin 100 20.00 0.10 23.90 0.25 0.65 0.22 (min) 0.38 (max) 12.35 14.00 0.10 17.90 0.25 3.40 (max.) 2.80 0.25 0.23 0.13 see detail a detail a 0.15 +0.08 ?.02 0 ? 0.80 0.15 notes: 1. all dimensions are shown in millimeters. 2. unless otherwise specified, all dimensions are nominal. 3. when converting from millimeters to inches, four significant digits to the right of the decimal point are necessary. note: 20 x 30 lead pattern land pattern .075 1.90 .013 .330 .745 18.9 .0256 0.65 .980 24.9 pin 1
tnt4882 single-chip ieee 488.2 talker/listener asic technical support national instruments strives to provide you with quality technical assistance worldwide. we currently offer electronic technical support along with our technical support centers staffed by applications engineers. access information from our web site at www.natinst.com our ftp site is dedicated to 24-hour support, with a collection of ?les and documents to answer your questions. log on to our internet host at ftp.natinst.com you can fax questions to our applications engineers anytime at (800) 328-2203 or (512) 683-5678. or, you can call from 8:00 a.m. to 6:00 p.m. (central time) at (512) 795-8248. internationally, contact your local of?ce. national instruments sponsors a wide variety of group activities, such as user group meetings at trade shows and at large industrial sites. our users also receive our quarterly instrumentation newsletter ? with the latest information on new products, product updates, application tips, and current events. in addition, sign up for ni news , our electronic news service at www.natinst.com/news warranty all national instruments data acquisition, computer-based instrument, vxibus, and mxibus products are covered by a one- year warranty. gpib hardware products are covered by a two-year warranty from the date of shipment. the warranty covers board failures, components, cables, connectors, and switches, but does not cover faults caused by misuse. the owner may return a failed assembly to national instruments for repair during the warranty period. extended warranties are available at an additional charge. information furnished by national instruments is believed to be accurate and reliable. national instruments reserves the right to change product speci?cations without notice. seminars/training free and fee-paid seminars are presented several times a year in cities around the world. comprehensive, fee-paid training courses are available at national instruments offices or at customer sites. call for training schedules. for more information contact national instruments for application notes such as: using the tnt4882 in a mc68340 system factors to consider when clocking the tnt4882 at frequencies less than 40 mhz porting a 9914 gpib design to use the tnt4882 ordering information TNT4882-BQ tnt4882 developer kit..........................................776866-01 includes 2 tnt4882 asics, pc at evaluation board, esp-488tl source code software, and documentation. tnt4882 programmer reference manual ..............320724-01 part number legend abcde tnt 4882 b q a. family name tnt = single-chip, high-speed, gpib talker/listener interface b. device-number 4882 = ieee 488.2 compatible c. reserved d. revision e. package type q = quad ?at pack u.s. corporate headquarters fax (512) 683-9300 ? info@natinst.com branch of?ces: australia 03 9879 5166 ? austria 0662 45 79 90 0 ? belgium 02 757 00 20 ? brazil 000 811 781 0559 ? canada 905 785 0085 china 86 21 6555 7838 ? denmark 45 76 26 00 ? finland 09 725 725 11 ? france 01 48 14 24 24 ? germany 089 741 31 30 ? hong kong 2645 3186 india 91805275406 ? israel 03 6120092 ? italy 02 413091 ? japan 03 5472 2970 ? korea 02 596 7456 ? mexico 001 800 010 0793 netherlands 0348 433466 ? new zealand 09 914 0488 ? norway 32 27 73 00 ? singapore 2265886 ? spain 91 640 0085 ? sweden 08 587 895 00 switzerland 056 200 51 51 ? taiwan 02 2377 1200 ? u.k . 01635 523545 ? copyright 1999 national instruments corporation. all rights reserved. product and company names listed are trademarks or trad e names of their respective companies. 0305599 www.natinst.com (512) 794-0100 *000000a-01* 340570d-01

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