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sunplus technology reserves the right to change this documentation wi thout prior notice. information provided by sunplus technology is believed to be accurate and reliable. however, sunplus technology makes no warranty for any errors which may appear in this document. contact sunplus technology to obtain the lates t version of device specifications before placing your order. no responsibility is assumed by sunplus technology for any infringement of patent or other rights of third parties which may result from its use. in addition, sunplus products are not authoriz ed for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of su nplus. feb . 15 , 200 5 version 1. 7 s s p p l l c c 7 7 8 8 2 2 a a 1 1 6 6 c c o o m m / / 8 8 0 0 s s e e g g c c o o n n t t r r o o l l l l e e r r / / d d r r i i v v e e r r
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 2 feb. 15 , 2005 version: 1.7 table of contents page 1. general description ................................ ................................ ................................ ................................ ................................ .......... 4 2. features ................................ ................................ ................................ ................................ ................................ ................................ .. 4 3. block diagram ................................ ................................ ................................ ................................ ................................ ...................... 4 4. signal descriptions ................................ ................................ ................................ ................................ ................................ ............ 5 5. functional descriptions ................................ ................................ ................................ ................................ ................................ .. 6 5.1. o scillator ................................ ................................ ................................ ................................ ................................ .......................... 6 5.2. c ontrol and d isplay i nstructions ................................ ................................ ................................ ................................ ................... 6 5.3. i nstruction t able ................................ ................................ ................................ ................................ ................................ ............... 8 5.4. 8 - b it o peration and 16 - d igit 1 - l ine d isplay (u sing i nternal r eset ) ................................ ................................ .............................. 9 5.5. 4 - b it o peration and 16 - d igit 1 - l ine d isplay (u sing i nternal r eset ) ................................ ................................ ............................ 10 5.6. 8 - b it o peration and 16 - d igit 2 - l ine d isplay (u sing i nternal r eset ) ................................ ................................ ............................ 10 5.7. r eset f unction ................................ ................................ ................................ ................................ ................................ ................. 11 5.8. d isplay d ata ram (dd ram) ................................ ................................ ................................ ................................ ............................ 13 5.9. t iming g eneration c ircuit ................................ ................................ ................................ ................................ ............................... 13 5.10. lcd d r iver c ircuit ................................ ................................ ................................ ................................ ................................ ....... 13 5.11. c haracter g enerator rom (cg rom) ................................ ................................ ................................ ................................ ....... 13 5.12. c haracter g enerator ram (cg ram) ................................ ................................ ................................ ................................ ........ 13 5.13. c ursor /b link c ontrol c ircuit ................................ ................................ ................................ ................................ .................... 17 5.14. i nterfacing to mpu ................................ ................................ ................................ ................................ ................................ ....... 18 5.15. s upply v oltage for lcd d rive ................................ ................................ ................................ ................................ ..................... 20 5.16. r egister --- ir (i nstruction r egister ) and dr (d ata r egister ) ................................ ................................ ................................ 22 5.17. b usy f lag (bf) ................................ ................................ ................................ ................................ ................................ ............... 22 5.18. a ddress c ounter (ac) ................................ ................................ ................................ ................................ ................................ .. 22 5.19. s egment d ata d irection ................................ ................................ ................................ ................................ ............................... 22 5.20. c ommon d ata d irection ................................ ................................ ................................ ................................ ................................ 22 5.21. i/o p ort c onfiguration ................................ ................................ ................................ ................................ ................................ 22 6. electrical specifications ................................ ................................ ................................ ................................ ............................. 24 6.1. a bsolute m axi mum r atings ................................ ................................ ................................ ................................ ............................. 24 6.2. dc c haracteristics (vdd = 2.4v to 4.5v, t a = - 20 to +75 ) ................................ ................................ ................................ .... 24 6.3. dc c haracteristics (vdd = 4.5v to 5.5v, t a = - 20 to +75 ) ................................ ................................ ................................ .... 25 6.4. ac c haracteristics (vdd = 4.5v to 5.5v, t a = - 20 to +75 ) ................................ ................................ ................................ .... 25 6.5. ac c haracteristics (vdd = 2.4v to 4.5v, t a = - 20 to +75 ) ................................ ................................ ................................ .... 26 6.6. w rite m ode t iming d iagram (w riting d ata from mpu to SPLC782A) ................................ ................................ .......................... 27 6.7. r ead m ode t iming d iagram (r eading d ata from SPLC782A to mpu) ................................ ................................ ........................... 27 6.8. t he f ollowing g raps s how the r elationship b etween f osc and t emperature ................................ ................................ ......... 27 7. application circuits ................................ ................................ ................................ ................................ ................................ ......... 28 7.1. i nterface to mpu ................................ ................................ ................................ ................................ ................................ ............. 28 7.2. a pplications for lcd ................................ ................................ ................................ ................................ ................................ ...... 29 8. character gen erator rom ................................ ................................ ................................ ................................ ........................... 35 8.1. SPLC782A - 016 ................................ ................................ ................................ ................................ ................................ ................ 35 8.2. SPLC782A - 022 ................................ ................................ ................................ ................................ ................................ ................ 36 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 3 feb. 15 , 2005 version: 1.7 9. packag e/pad locations ................................ ................................ ................................ ................................ ................................ ... 37 9.1. pad a ssignment and l ocations ................................ ................................ ................................ ................................ ....................... 37 9.2. o rdering i nformation ................................ ................................ ................................ ................................ ................................ ..... 37 10. disclaimer ................................ ................................ ................................ ................................ ................................ ............................. 38 11. revision history ................................ ................................ ................................ ................................ ................................ ................. 39 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 4 feb. 15 , 2005 version: 1.7 16com/80seg controller/driver 1. general description the SPLC782A, a dot - matrix lcd controller and drive r, is a low - power cmos integrated circuit. the SPLC782A is capable of connecting with mpu for lcd application and easily to be used for designing the low - cost products. 2. features ? character generator rom: 10880 bits g character font 5 x 8 dots: 1 92 characters g character font 5 x 10 dots: 64 characters ? 4 type cgrom mode, max. 256 characters can be used. ? character generator ram: 512 bits g character font 5 x 8 dots: 8 characters g character font 5 x 10 dots: 4 characters ? provide connecting to 4 - bit or 8 - bit mpu ? direct driver for lcd: 16 coms x 80 segs ? 80 - channel bi - direction segment driver ? 16 - channel bi - direction common driver ? duty factor (selected by program): g 1/8 duty: 1 line of 5 x 8 dots g 1/11 duty: 1 line of 5 x 10 dots g 1/16 duty: 2 lines of 5 x 8 dots / line ? lcd type - a, type - b waveform can be selected. ? built - in power on automatic reset circuit ? built - in oscillator circuit (with internal resistor) ? built - in b ias resistor ? support external clock operation ? package form: au bump chip 3. block diagram figure 3 - 1 : block diagram com1- com16 seg1- seg80 osc1 i / o buffer timing generation circuit 80 segments x 16 commons lcd driver character generator rom 80-bit bi-direction shift register latch circuit 16-bit shift register parallel to serial data conversion circuit cursor blink control circuit character generator ram display data ram 80 bytes address counter instruction register data register busy flag instruction decorder 5 5 8 8 8 8 7 7 7 8 7 8 80 16 80 cl2 e rs r / w db0-db3 db4-db7 vss v2 v3 vpp shl d vdd mod1 mod0 type dirc sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 5 feb. 15 , 2005 version: 1.7 4. signal descriptions mnemonic pin no. type description vdd 19, 20, 28 i logic power input vss 11, 12, 37 i ground v pp 23, 24 i lcd voltage; v lcd = vpp - vss v2 v3 22 21 i lcd bias voltage control. open for 1/5 bias, short for 1/4 bias e 27 i it is a start signal to read data or write data. r / w 26 i it i s a signal to select read or write. 1: read, 0: write. rs 25 i it is a signal to select register. 1: data register (for read and write) 0: instruction register (for write), busy flag -- address counter (for read). db3 - db0 32 - 29 i/o low - order 4 data b its db7 - db4 36 - 33 i/o high - order 4 data bits seg 8 0 - seg1 46 - 125 o segment signals for lcd. com16 - com 9 45 - 38 o common signals for lcd. com 8 - com1 1 - 8 o common signals for lcd. type 14 i lcd alternate signals. type = 0: type - a type = 1: ty pe - b dirc 15 i common scan direction dirc = 0: com1 ? com2 ? ? com15 ? com16 dirc = 1: com16 ? com15 ? ? com2 ? com1 shl 16 i segment shift direction shl = 0: seg1 ? seg2 ? ? seg79 ? seg80 shl = 1: seg80 ? seg79 ? ? seg2 ? seg1 m od1 mod0 18 17 i cgrom / cgram mode select mod1 mod0 function 1 1 1 1 0 0 0 0 $00 - $0f as cgram $00 - $07 as cgram, $08 - $0f as cgrom $00 - $03 as cgram, $04 - $0f as cgrom $00 - $0f as cgrom osc1 13 for internal clock operation, leave this pin open. for external clock operation, the clock is input to osc1. cl2 10 o te s t m o d e clock output ; open for normally use. d 9 o t est mode data output ; open for normally use. sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 6 feb. 15 , 2005 version: 1.7 5. function al description s 5.1. oscillator the built - in rc oscillator generates suitable clock for SPLC782A operation. 5.2. control a nd display instructions control and display instructions is shown as follows: 5.2.1. clear d isplay figure 5 - 1 : clear display instruction code it clears the whole display and sets display data ram ? s address 0 in address counter. 5.2.2. return h ome figure 5 - 2 : return home instruction code x: do not care (0 or 1) it sets display data ram ? s address 0 in address counter and display returns to its original position. the cursor or blink goes to the left edge of the display (to the 1st line if 2 lines are disp layed). the content of the display data ram does not change. 5.2.3. entry m ode s et during writing and reading data, it sets cursor move direction and shifts the display. figure 5 - 3 : en try mode instruction code i / d = 1: increment, i / d = 0: decrement. s = 1: the display shift, s = 0: the display does not shift. s = 1 i / d = 1 it shifts the display to the left s = 1 i / d = 0 it shifts the display to the right figure 5 - 4 : shift direction patterns according to s and i/d bits 5.2.4. display o n /o ff c ontrol figure 5 - 5 : display on/off control instruction code d = 1: display on, d = 0: displa y off c = 1: cursor on, c = 0: cursor off b = 1: blinks on, b = 0: blinks off cursor 5 x 8 dot character font 5 x 10 dot character font 8th line 11th line blink display alternately figure 5 - 6 : cursor and blinking 5.2.5. cursor or d isplay s hift without changing dd ram ? s data, it can m ove cursor and shift display. figure 5 - 7 : cursor or display shift instruction code s/c r/l description address counter 0 0 shift cursor to the left ac = ac - 1 0 1 shift curs or to the right ac = ac + 1 1 0 shift display to the left. cursor follows the display shift ac = ac 1 1 shift display to the right. cursor follows the display shift ac = ac figure 5 - 8 : shift pattern s according to s/c and r/l bits db7 code rs r/w 1 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 db7 code rs r/w x db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 db7 code rs r/w s db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d db7 code rs r/w b db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c db7 code rs r/w x db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l x sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 7 feb. 15 , 2005 version: 1.7 5.2.6. function s et figure 5 - 9 : function set instruction code x: do not care (0 or 1) dl: it sets interface data length. dl = 1: datas are transferre d with 8 - bit lengths (db 0 - db7 ). dl = 0: datas are transferred with 4 - bit lengths (db 4 - db7). (it requires two times to transfer data) n: it sets the number of the display line. n = 0: one - line display. n = 1: two - line display. f: it sets the cha racter font. f = 0: 5 x 8 dots character font. f = 1: 5 x 10 dots character font. n f no. of display lines character font duty factor 0 0 1 5 x 8 dots 1 / 8 0 1 1 5 x 10 dots 1 / 11 1 x 2 5 x 8 dots 1 / 16 figure 5 - 10 : function set description it cannot display two lines with 5 x 10 dot character font. 5.2.7. set c haracter g enerator ram a ddres s figure 5 - 11 : set cgram address instruction code it sets character generator ram address (aaaaaa) 2 to the address counter. character generator ram data can read or write after this setting. 5.2.8. set d isplay d ata ram a ddress figure 5 - 12 : set ddram address instruction code it sets display data ram address (aaaaaaa) 2 to the address counter. display data ram can read or write after this setting. in one - line display (n = 0), (aaaaaaa) 2: (00) 16 - (4f) 16. in two - line display (n = 1), (aaaaaaa) 2 : (00) 16 - (27) 16 for the first line, (aaaaaaa) 2: (40) 16 - (67) 16 for the second line. 5.2.9. read b usy f lag and a ddress figure 5 - 13 : read busy flag and address instruc tion code when (bf = 1) indicates that the system is busy now; it will not accept any instruction until no busy (bf = 0). at the same time, the address counter contents (aaaaaaa) 2 is read out. 5.2.10. write data to character generator ram or d isplay d ata ram figure 5 - 14 : write data to cgram/ddram instruction code it writes data (dddddddd) 2 to character generator ram or display data ram. 5.2.11. read data from character generator ram or display data ram figure 5 - 15 : read data from cgram/ddram instruction code it reads data (dddddddd) 2 from character generator ram or display data ram. to g e t t h e c o r r e c t d a ta r e a d o u t i s s h o w n b e l o w s : 1). set the add ress of the character generator ram or display data ram or shift the cursor instruction. 2). send the read instruction. db7 code rs r/w x db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n f x db7 code rs r/w a db6 db5 db4 db3 db2 db1 db0 0 0 0 1 a a a a a db7 code rs r/w a db6 db5 db4 db3 db2 db1 db0 0 0 1 a a a a a a db7 code rs r/w db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 db7 code rs r/w d db6 db5 db4 db3 db2 db1 db0 1 0 d d d d d d d db7 code rs r/w d db6 db5 db4 db3 db2 db1 db0 1 1 d d d d d d d sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 8 feb. 15 , 2005 version: 1.7 5.3. instruction table instruction code instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description max. execution time (temp = - 2 0 ~ + 75 ) clear display 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram and set ddram address to "00h" from ac 4.1ms return home 0 0 0 0 0 0 0 0 1 - set ddram address to "00h" from ac and return cursor to its original p osition if shifted. the contents of ddram are not changed. 4.1ms entry mode set 0 0 0 0 0 0 0 1 i/d s assign cursor moving direction and enable the shift of entire display 100 ? s display on/ off control 0 0 0 0 0 0 1 d c b set display (d), cursor(c), and blinking of cursor(b) on/off control bit. 100 ? s cursor or display shift 0 0 0 0 0 1 s/c r/l - - set cursor moving and display shift control bit, and the direction, without changing of ddram data. 100 ? s function set 0 0 0 0 1 dl n f - - set interface dat a length (dl: 8 - bit/4 - bit), numbers of display line (n: 2 - line/1 - line) and, display font type (f:5x10 dots/5x8 dots) 100 ? s set cgram address 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 100 ? s set ddram address 0 0 1 ac6 ac5 ac4 a c3 ac2 ac1 ac0 set ddram address in address counter 100 ? s read busy flag and address counter 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 whether during internal operation or not can be known by reading bf. the contents of address counter can also be read. 0 ? s wr ite data to ram 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram). 100 ? s read data from ram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram). 100 ? s figure 5 - 16 : ins truction table note: - dont care sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 9 feb. 15 , 2005 version: 1.7 5.4. 8 - bit operation a nd 16 - digit 1 - line display (using internal reset) no. instruction display operation 1 power on. (SPLC782A starts initializing) power on reset. no display. 2 function set db7 rs r/w db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 x x 0 0 set to 8 - bit operation and select 1 - line display line and character font. 3 display on / off control 0 0 0 0 1 1 1 0 0 0 _ display on. cursor appear. 4 entry mode set 0 0 0 0 0 1 1 0 0 0 _ increase address by one. it will shift the c ursor to the right when writing to the dd ram/cg ram. now the display has no shift. 5 write data to cg ram / dd ram 0 1 0 1 0 1 1 1 1 0 w _ write " w ". the cursor is incremented by one and shifted to the right. 6 write data to cg ram / dd ram 0 1 0 0 0 1 0 1 1 0 we _ write " e ". the cursor is incremented by one and shifted to the right. 7 : : 8 write data to cg ram / dd ram 0 1 0 0 0 1 0 1 1 0 welcome _ write " e ". the cursor is incremented by one and shifted to the right. 9 entry mode set 0 0 0 0 0 1 1 1 0 0 welcome _ set mode for disp lay shift when writing 10 write data to cg ram / dd ram 0 0 1 0 0 0 0 0 1 0 elcome _ write " "(space). the cursor is incremented by one and shifted to the right. 11 write data to cg ram / dd ram 0 1 0 0 0 0 1 1 1 0 lcome c _ write " c ". the cursor is incremented by one and shifted to the right. 12 : : 13 write data to cg ram / dd ram 0 1 0 1 1 0 0 1 1 0 compamy _ write " y ". the cursor is incremented by one and shifted to the right. 14 cursor or display shift 0 0 0 1 0 0 x x 0 0 compamy _ only shift the cursor's positi on to the left (y). 15 cursor or display shift 0 0 0 1 0 0 x x 0 0 compamy _ only shift the cursor's position to the left (m). 16 write data to cg ram / dd ram 0 1 0 0 1 1 1 0 1 0 company _ write " n ". the display moves to the left. 17 cursor or display shift 0 0 0 1 1 1 x x 0 0 company _ shift the display and the cursor's position to the right. 18 cursor or display shift 0 0 0 1 0 1 x x 0 0 company _ shift the display and the cursor's position to the right. 19 write data to cg ram / dd ram 0 1 0 0 0 0 0 0 1 0 company _ write " " (space). the cursor is incremented by one and shifted to the right. 20 : : 21 retu rn home 0 0 0 0 0 0 1 0 0 0 welcome both the display and the cursor return to the original position (address 0). figure 5 - 17 : 8 - bit operation a nd 16 - digit 1 - line display sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 10 feb. 15 , 2005 version: 1.7 5.5. 4 - bit operation a nd 16 - digit 1 - lin e display (using internal reset) no. instruction display operation 1 power on. (SPLC782A starts initializing) power on reset. no display. 2 function set db7 rs r/w db6 db5 0 0 1 0 0 0 db4 set to 4 - bit operation. 3 function set 0 0 1 0 0 0 0 0 x x 0 0 set to 4 - bit operation and select 1 - line display line and character font. 4 display on / off control 0 0 0 0 0 0 1 1 1 0 0 0 _ display on. cursor appears. 5 entry mode set 0 0 0 0 0 0 0 1 1 0 0 0 _ increase address by one. it will shift the cursor to the right when writing to the dd ram/cg ram. now the display has no shift. 6 write data to cg ram / dd ram 0 1 0 1 1 0 0 1 1 1 1 0 w _ write " w ". the cursor is incremented by one and shifted to the right. figure 5 - 18 : 4 - bit operation a nd 16 - digit 1 - line display 5.6. 8 - bit ope ration a nd 16 - digit 2 - line display (using internal reset) no. instruction display operation 1 power on. (SPLC782A starts initializing) power on reset. no display. 2 function set db7 rs r/w db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 x x 0 0 set to 8 - bit operation and select 2 - line display line and 5 x 7 dot character font. 3 display on / off control 0 0 0 0 1 1 1 0 0 0 _ display on. cursor appear. 4 entry mode set 0 0 0 0 0 1 1 0 0 0 _ increase address by one. it will shift the cursor to the right when writing to the dd ram/cg ram. now the display has no shift. 5 write data to cg ram / dd ram 0 1 0 1 0 1 1 1 1 0 w_ write " w ". the cursor is incremented by one and shifted to the right. 6 : : 7 write data to cg ram / dd ram 0 1 0 0 0 1 0 1 1 0 welcome_ write " e ". the cursor is incremented by one and shifted to the right. 8 set dd ram address 1 1 0 0 0 0 0 0 0 0 welcome _ it sets dd ram's address. the cursor is moved to the beginning position of the 2nd line. 9 write data to cg ram / dd ram 0 1 0 1 0 1 0 0 1 0 welcome t_ write " t ". the c ursor is incremented by one and shifted to the right. 10 : : 1 1 write data to cg ram / dd ram 0 1 0 1 0 1 0 0 1 0 welcome to part_ write " t ". the cursor is incremented by one and shifted to the right. sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 11 feb. 15 , 2005 version: 1.7 no. instruction display operation 1 2 write data to cg ram / dd ram 0 1 0 1 0 1 0 0 1 0 welcome to part_ write " t ". the cursor is incremented by one and shifted to the right. 1 3 entry mode set 0 0 0 0 0 1 1 1 0 0 welcome to part_ when writing, it sets mode for the display s hift. 1 4 write data to cg ram / dd ram 0 1 0 1 1 0 0 1 1 0 elcome o party_ write " y ". the cursor is incremented by one and shifted to the right. 1 5 : : 1 6 return home 0 0 0 0 0 0 1 0 0 0 welcome to party bot h the display and the cursor return to the original position (address 0). figure 5 - 19 : 8 - bit operation a nd 16 - digit 2 - line display 5.7. reset function at power on, it starts the inte rnal auto - reset circuit and executes the initial instructions. there are the initial procedures shown as b elows: figure 5 - 20 : reset function (8 - bit interface) power on wait time > 15 ms after vdd > 4.5v rs r/w db7 db6 db5 db4 db3 db3 db1 db0 0 0 0 0 1 1 x x x x wait time > 4.1 ms rs r/w db7 db6 db5 db4 db3 db3 db1 db0 0 0 0 0 1 1 x x x x wait time > 100 us rs r/w db7 db6 db5 db4 db3 db3 db1 db0 0 0 0 0 1 1 x x x x rs r/w db7 db6 db5 db4 db3 db3 db1 db0 0 0 0 0 1 1 n f x x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 i/d s initialization ends bf cannot be checked before this instruction . function set ( interface is 8 bits length . ) bf cannot be checked before this instruction . function set ( interface is 8 bits length . ) bf cannot be checked before this instruction . function set ( interface is 8 bits length . ) bf can be checked after the following instructions . function set ( interface is 8 bits length . specify the number of display lines and character font . ) the number of display lines and character font cannot be changed afterwards . display off display clear entry mode set [ 8-bit interface ] wait time > 40ms after vdd > 2.7v sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 12 feb. 15 , 2005 version: 1.7 figure 5 - 21 : reset function (4 - bit interface) power on wait time > 15 ms after vdd > 4.5v rs r/w db7 db6 db5 db4 0 0 0 0 1 1 wait time > 4.1 ms wait time > 100 us bf cannot be checked before this instruction . function set ( interface is 8 bits length . ) bf cannot be checked before this instruction . function set ( interface is 8 bits length . ) bf cannot be checked before this instruction . function set ( interface is 8 bits length . ) bf can be checked after the following instructions . function set ( set interface to be 4 bits length) interface is 8 bits length . the number of display lines and character font cannot be changed afterwards . display off display clear entry mode set [ 4-bit interface ] function set ( interface is 4 bits length . specify the number of the display lines and character font . ) rs r/w db7 db6 db5 db4 0 0 0 0 1 1 rs r/w db7 db6 db5 db4 0 0 0 0 1 1 rs r/w db7 db6 db5 db4 0 0 0 0 1 0 0 0 0 0 1 0 0 0 n f x x 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 i/d s initialization ends wait time > 40ms after vdd > 2.7v 0 0 1 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 13 feb. 15 , 2005 version: 1.7 5.8. display data ram (dd ram) the dd ram stores display data and its ram size is 80 bytes. the area in dd ram that is not used for display can be used as a general data ram. its ad dress is set in the address counter. there are the relations between the display data ram ? s address and the lcd ? s position shown belows. figure 5 - 22 : relations between display data ram s address and t he lcd s position 5.9. timing generation circuit the timing generation circuit can generate needed timing signals to the internal circuits. to prevent the internal timing interface, the mpu access timing and the ram access timing are separately generated. 5.10. l cd driver circuit there are 16 commons x 80 segments signal drivers in the lcd driver circuit. when a program specifies the character fonts and line numbers, the corresponding common signals will output drive waveforms and the others still output unselect ed waveforms. 5.11. c haracter generator rom (cg rom) using 8 - bit character code, the character generator rom generates 5 x 8 dot or 5 x 10 dot character patterns. it also can generate 192 5 x 8 dot character patterns and 64 5 x 10 dot character patterns. 5.12. cha racter generator ram (cg ram) using the programs, users can easily change the character patterns in the character generator ram. it can be written with 5 x 8 dots, 8 character patterns or written with 5 x 10 dots, 4 character patterns. when the display shift operation is performed , the display data ram's address moves as : ( i ) left shift 01 02 03 04 05 06 06 07 ( ii ) right shift 08 4f 00 01 02 03 04 05 06 00 01 02 03 04 05 06 07 ( example ) 1-line display , 8 display characters display position 3 1 2 4 5 6 7 8 display data ram address 00 01 02 03 04 05 1-line display , 80 display characters 3 1 2 4 5 6 4e 4f display position 79 80 display data ram address sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 14 feb. 15 , 2005 version: 1.7 here are the SPLC782A ? s character patterns shown as belows: correspondence between character codes and character patterns . figure 5 - 23 : character code and character patterns sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 15 feb. 15 , 2005 version: 1.7 the relations between character generator r am addresses, character generator ram data (character patterns) and character codes are shown as belows: 5.12.1. 5 x 8 dot character patterns figure 5 - 24 : 5 x 8 d ot c haracter p atterns n ote1: it means that the bit0~2 of the character code correspond to the bit3~5 of the cg ram address. note2: these areas are not used for display, but can be used for the general data ram. note3: whe n all of the bit4 - 7 of the character code are 0, cg ram character patterns are selected. note4: " 1 ": selected, " 0 " : no selected , " x " : do not care (0 or 1). note5: for example (1), set character code (b2 = b1 = b0 = 0, b3 = 0 or 1, b7 - b4 = 0) to di splay t . that means character code (00) 16,and (08) 16 can display t character. note6: the bits 0 - 2 of the character code ram is the character pattern line position. the 8th line is the cursor position and display is formed by logical or with the cursor. b6 b5 b4 b3 b2 b1 b0 b7 b5 b4 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0 b7 character code ( dd ram data ) cg ram address character patterns ( cg ram data ) 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 x x x x 1 1 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 1 0 0 0 0 x x x x 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 character pattern example (1) cursor position character pattern example (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 16 feb. 15 , 2005 version: 1.7 5.12.2. 5 x 10 dot character patterns b6 b5 b4 b3 b2 b1 b0 b7 b5 b4 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0 b7 character code ( dd ram data ) cg ram address character patterns ( cg ram data ) 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 x x x x 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 x x x 1 1 0 0 0 1 character pattern example (1) cursor position x 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x x x x x 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 figure 5 - 25 : 5 x 10 d ot c haracter p atterns note1 : i t means that the bit1~2 of the character code correspond t o the bit4~5 of the cg ram address. note2: these areas are not used for display, but can be used for the general data ram. note3: when all of the bit4 - 7 of the character code are 0, cg ram character patterns are selected . note4 : " 1 : selected, " 0 : no selected, " x : do not care (0 or 1). note5: for example (1), set character code (b2 = b1 = 0, b3 = b0 = 0 or 1, b7 - b4 = 0) to display u . that means all of the character codes (00) 16, (01) 16, (08) 16,and (09) 16 can dis play u character. note6: the bits 0 - 3 of the character code ram is the character pattern line position. the 11th line is the cursor position and display is formed by logical or with the cursor. sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 17 feb. 15 , 2005 version: 1.7 5.13. cursor/blink control circuit it can generate the cursor or blink in the cursor / blink control circuit. the cursor or the blink appears in the digit at the display data ram address set in the address counter. when the address counter is (07) 16, the cursors position is shown as follows: in a 1-line display in a 2-line display 00 01 02 03 04 05 06 07 08 09 1 2 3 4 5 6 7 8 9 10 digit the cursor position 40 41 42 43 44 45 46 47 48 49 1st line 2nd line 00 01 02 03 04 05 06 07 08 09 1 2 3 4 5 6 7 8 9 10 digit display position display data ram address ( hexadecimal ) the cursor position 0 0 0 0 1 1 1 ac b6 b5 b4 b3 b2 b1 b0 display position display data ram address ( hexadecimal ) figure 5 - 26 : cursor/blink control sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 18 feb. 15 , 2005 version: 1.7 5.14. i nterfacing to mpu there are two types of data operations: 4 - bit operation and 8 - bit operation. using 4 - bit mpu, the interfacing 4 - bit data is transferred by 4 bu s lines ( for 8 - bit operation, db7 to db4 ). the bus lines of db 0 - db3 are not used. using 4 - bit mpu to interface 8 - bit data needs two times. first, the higher 4 - bit data is transferred by 4 - busline ( for 8 - bit operation, db7 to db4 ). secondly, the lower 4 - bit data is transferred by 4 bus lines ( for 8 - bit operation, db3 to db0 ). using 8 - bit mpu, the interfacing 8 - bit data is transferred by 8 bus lines ( db0 - db7 ). ir7 ir3 busy ac3 not busy ac3 d7 d3 ir6 ir2 ac6 ac2 ac6 ac2 d6 d2 ir5 ir1 ac5 ac1 ac5 ac1 d5 d1 ir4 ir0 ac4 ac0 ac4 ac0 d4 d0 instruction write busy flag check busy flag check data write rs e internal operation db7 r/w db6 db5 db4 functioning figure 5 - 27 : example of 4 - bit data transfer timing sequence sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 19 feb. 15 , 2005 version: 1.7 ir7 rs e internal operation db7 r/w busy busy not busy d7 ir6 ac6 d6 ir5 ac5 d5 ir4 ac4 d4 ir3 ac3 d3 ir2 ac2 d2 ir1 ac1 d1 ir0 ac0 d0 ac6 ac5 ac4 ac3 ac2 ac1 ac0 ac6 ac5 ac4 ac3 ac2 ac1 ac0 instruction write busy flag check busy flag check busy flag check data write db6 db5 db4 db3 db2 db1 db0 functioning figure 5 - 28 : example of 8 - b i t data transfer timing sequence sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 20 feb. 15 , 2005 version: 1.7 5.15. supply voltage f or l cd drive lcd bias can be selected by open/short v2 and v3 pins. 1/8, 1/11 1/16 duty factor supply voltage 1/4 1/5 v2 , v3 short open SPLC782A v2 v3 short v2 v3 open SPLC782A 1/5 bias (1/16 duty) 1/4 bias (1/8, 1/11 duty) figure 5 - 29 : supply voltage for lcd drive 5.15.1. the relations between lcd frame ? s freque ncy and oscillator ? s frequency (assume the oscillation frequency is 250khz, 1 clock cycle time = 4 .0 ? s) 5.15.2. 1/8 duty, type - a waveform figure 5 - 30 : 1/8 duty type - a waveform 5.15.3. 1/11 duty , type - a waveform figure 5 - 31 : 1/11 duty type - a waveform 1 frame = 4 ( ? s) x 400 x 8 = 12800 ( ? s) = 12.8 ms frame frequency = 1 12.8 (ms) = 78.1 (hz) com1 1 frame 1 2 3 4 8 1 2 400 clocks vpp v1 v2(v3) v4 vss 1 frame = 4 ( ? s) x 400 x 11 = 17600 ( ? s) = 17.6 ms frame frequency = 1 17.6 (ms) = 56.8 (hz) vpp v1 v2(v3) v4 vss com1 1 frame 1 2 3 4 400 clocks 11 1 2 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 21 feb. 15 , 2005 version: 1.7 5.15.4. 1/16 duty, type - a waveform figure 5 - 32 : 1/16 duty type - a waveform 5.15.5. 1/8 duty, type - b waveform figure 5 - 33 : 1/8 duty type - b waveform 5.15.6. 1/11 duty, type - b waveform figure 5 - 34 : 1/11 duty type - b waveform com1 1 frame = 4 ( ? s) x 200 x 16 = 12800 ( ? s) = 12.8 ms frame frequency = 1 12.8 (ms) = 78.1 (hz) 1 frame 1 2 3 4 16 1 2 200 clocks vpp v1 v3 v4 v2 vss 1 2 7 8 1 2 7 8 1 2 7 8 1 2 7 8 400 clocks com1 2 1 frame 1 frame 1 frame = 4( ? s) x 400 x 8 = 12800( ? s) = 12.8ms 78.1(hz) 12.8(ms) 1 ency framefrequ ? ? vpp v1 v4 vss v2(v3) 1 2 10 11 1 2 400 clocks 2 1 frame 1 frame 10 11 1 2 1 frame = 4( ? s) x 400 x 11 = 17600( ? s) = 17.6ms (hz) 5 17.6(ms) 1 ency framefrequ 8 . 6 ? ? com1 vpp v1 v4 vss v2(v3) sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 22 feb. 15 , 2005 version: 1.7 5.15.7. 1/16 duty, type - b waveform figure 5 - 35 : 1/16 duty type - b waveform 5.16. register --- ir (instruction register) and dr (data register ) SPLC782A has two 8 - bit registers - ir (instruction register) and dr (data register). in the followings, we can use the combinations of the rs pin and the r/w pin to select the ir and dr. rs r/w operation 0 0 ir write (display clear, etc.) 0 1 read bu sy flag (db7) and address counter ( db0 - db6 ) 1 0 dr write (dr to display data ram or character generator ram) 1 1 dr read (display data ram or character generator ram to dr) 5.17. busy flag (bf) when rs = 0 and r/w = 1, the busy flag is output to db7. as t he busy flag = 1, SPLC782A is in busy state and does not accept any instructions until the busy flag = 0. 5.18. address counter (ac) the address counter assigns addresses to display data ram and character generator ram. when an instruction for address is writt en in ir, the address information is sent from ir to ac. after writing into (or reading from)display data ram or character generator ram, ac is automatically incremented by +1 (or decremented by - 1). ac contents are output to db 0 - db6 when rs = 0 and r/ w = 1. 5.19. segment data direction shl is the segment data shift direction control pin. lcd data is shifted from seg1 to seg80 by connecting shl to vss, and is reversed by connecting shl to vdd. 5.20. common data direction dirc is the common data shift direction c ontrol pin. lcd common scan sequence from com1 to com16 by connecting dirc to vss, and is reversed by connecting dirc to vdd. 5.21. i /o port configuration 5.21.1. input port: e figure 5 - 36 : in put port: e configuration 5.21.2. input port: r/w, rs figure 5 - 37 : input port: rw, rs configuration 1 2 15 16 1 2 200 clocks vpp v1 v4 vss com1 2 1 frame 1 frame 15 16 1 2 1 frame = 4( ? s) x 200 x 16 = 12800( ? s) = 12.8ms 78.1(hz) 12.8(ms) 1 ency framefrequ ? ? v3 v2 pmos nmos vdd pmos nmos pmos vdd vdd sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 23 feb. 15 , 2005 version: 1.7 5.21.3. output port: cl2, d pmos nmos vdd figure 5 - 38 : output port: cl2, d configuration 5.21.4. input / output port: db0 - db7 pmos nmos vdd pmos data enable vdd vdd figure 5 - 39 : input/output port: db0 - db7 configuration sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 24 feb. 15 , 2005 version: 1.7 6. electrical specifications 6.1. absol ute maximum ratings characteristics symbol ratings operating voltage vdd - 0.3v to +7.0v driver supply voltage v pp - 0.3 v to + 7.0 v input voltage range v in - 0.3v to vdd +0.3v operating temperature t a - 20 to + 75 storage temperature t sto - 55 to +125 note: stresses beyond those given in the absolute maximum rating table may cause operational errors or damage to the device. for normal operational conditions see ac/dc electrical characteristics. 6.2. dc characteristics (vdd = 2.4v to 4.5 v , t a = - 2 0 to +7 5 ) limit characteristics symbol min. typ. max. unit test condition operating voltage vdd 2. 4 - 4 .5 v i dd 1 - 0.1 5 0. 25 m a no access from mpu (note1) operating current i dd2 - 0. 1 8 0. 48 ma access operation from mpu (f cyc = 500khz) (note 1 ) input high voltage v ih1 0.7vdd - vdd v input low voltage v il1 - 0.3 - 0.55 v pins:(e, rs, r/w, db0 - db7 ) input high current i ih - - 2.0 ? a input low current i il - 5.0 - 30 - 100 ? a pins: (rs, r/w, db0 - db7 ) o utput high voltage v oh1 0.75vdd - vdd v i oh = - 0.1ma , pins: db0 - db7 output low voltage v ol1 - - 0.2vdd v i ol = 0.1ma , pins: db0 - db7 v dcom - - 1.0 v i o = 0.1ma , pins: com1 - com16 voltage drop v dseg - - 1.0 v i o = 0.1ma , pins: seg1 - seg80 operat ing current i pp - 0.3 5 0.4 5 ma v pp = 6.0v (note2) lcd voltage v pp 4.0 - 6.0 v 1/4 bias or 1/5 bias note 1 : typ . condition vdd = 3.0v @ 25 , max. condition vdd = 4.5v @ - 20 note2: typ. condition vpp = 6.0v @ 25 , max. condition vpp = 6.0v @ - 20 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 25 feb. 15 , 2005 version: 1.7 6.3. dc characteristics (vdd = 4.5v to 5.5 v , t a = - 2 0 to +7 5 ) limit characteristics symbol min. typ. max. unit test condition operating voltag e vdd 4.5 - 5.5 v i dd 1 - 0.2 5 0.35 m a no access from mpu (note 1 ) operating current i dd2 - 0.4 5 0.7 ma access operation from mpu (f cyc = 500khz) (note1) input high voltage v ih1 0.7vdd - vdd v input low voltage v il1 - 0.3 - 0.6 v pins:(e, rs, r/w, db0 - db7 ) input high current i ih - - 2.0 ? a input low current i il - 30 - 80 - 150 ? a pins: (rs, r/w, db0 - db7 ) output high voltage (ttl) v oh1 2. 4 - vdd v i oh = - 0.1ma , pins: db0 - db7 output low voltage (ttl) v ol1 - - 0.4 v i ol = 0.1ma , pins: db0 - db7 v dcom - - 1.0 v i o = 0.1ma , pins: com1 - com16 voltage drop v dseg - - 1.0 v i o = 0.1ma , pins: seg1 - seg80 operating current i pp - 0.35 0.4 5 ma v pp = 6.0v (note2) lcd voltage v pp 4.0 - 6.0 v 1/4 bias or 1/5 bias note 1 : typ. condition vdd = 5.0v @ 25 , max. condition vdd = 5.5v @ - 20 note 2 : typ. condition vpp = 6.0v @ 25 , max. condition vpp = 6.0v @ - 20 6.4. ac characteristics (vdd = 4.5 v to 5.5v, t a = - 2 0 to +7 5 ) 6.4.1. internal clock operation ( t a = 25 , the oscillator frequency chart can be reference on figure 6 - 3) limit characteristics symbol min. typ. max. unit osc frequency f osc1 190 270 350 khz 6.4.2. l cd bias resistor ( t a = 25 ) limit characteristics symbol min. typ. max. unit bias resistor r1 - r5 3.0 5.0 7.0 k - ohm 6.4.3. write mode (writing d ata from mpu to SPLC782A) limit characteristics sym bol min. typ. max. unit test condition e cycle time t c 500 - - ns pin e e pulse width t pw 230 - - ns pin e e rise/fall time t r , t f - - 20 ns pin e address setup time t sp1 40 - - ns pins: rs, r/w, e address hold time t hd1 10 - - ns pins: rs, r/w, e data setup time t sp2 80 - - ns pins: db0 - db7 data hold time t hd2 10 - - ns pins: db0 - db7 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 26 feb. 15 , 2005 version: 1.7 6.4.4. read mode (reading d ata from SPLC782A to mpu) limit characteristics symbol min. typ. max. unit test condition e cycle time t c 500 - - ns pin e e pulse width t w 230 - - ns pin e e rise/fall time t r , t f - - 2 0 ns pin e address setup time t sp1 40 - - ns pins: rs, r/w, e address hold time t hd1 10 - - ns pins: rs, r/w, e data output delay time t d - - 160 ns pins: db0 - db7 data hold time t hd2 5.0 - - ns pin s: db0 - db7 6.5. ac characteristics (vdd = 2.4 v to 4.5v, t a = - 2 0 to +7 5 ) 6.5.1. internal clock operation ( t a = 25 , the oscillator frequency chart can be reference on figure 6 - 3) limit characteristics symbol min. typ. max. unit osc frequency f osc1 190 270 350 khz 6.5.2. lcd bias resistor ( t a = 25 ) limit characteristics symbol min. typ. max. unit bias resistor r1 - r5 3.0 5.0 7.0 k - ohm 6.5.3. write mode (writing d ata from mpu to SPLC782A) limit characteristics symbol min. typ. max. unit test condition e cycle time t c 1250 - - ns pin e e pulse width t pw 600 - - ns pi n e e rise/fall time t r , t f - - 25 ns pin e address setup time t sp1 60 - - ns pins: rs, r/w, e address hold time t hd1 20 - - ns pins: rs, r/w, e data setup time t sp2 195 - - ns pins: db0 - db7 data hold time t hd2 10 - - ns pins: db0 - db7 6.5.4. read mode (reading d ata from SPLC782A to mpu) limit characteristics symbol min. typ. max. unit test condition e cycle time t c 1250 - - ns pin e e pulse width t w 600 - - ns pin e e rise/fall time t r , t f - - 2 5 ns pin e address setup time t sp1 60 - - ns pins: rs, r/w, e address hold time t hd1 20 - - ns pins: rs, r/w, e data output delay time t d - - 360 ns pins: db0 - db7 data hold time t hd2 5.0 - - ns pin db0 - db7 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 27 feb. 15 , 2005 version: 1.7 6.6. write mode timing diagram (writing d ata f rom mpu t o SPLC782A) figure 6 - 1 : write mode timing diagram 6.7. read mode timing diagram (reading d ata f rom SPLC782A t o mpu) figure 6 - 2 : read mode timing di agram 6.8. the following graps show the relationship between f osc and temperature SPLC782A fosc frequency (vdd = 2.4v ~ 5.5v) 100 150 200 250 300 350 400 450 500 550 -20 -10 0 10 20 30 40 50 60 70 80 temp khz min. typ. max. f osc (max.) = 515khz @ vdd = 5.5v, temp = - 20 f osc (min.) = 114khz @ vdd = 2.4v, temp = 80 figure 6 - 3 : the relationship between fosc and temperature rs r / w e db0 - db7 v ih1 v il1 v ih1 v il1 v il1 t sp1 t c valid data v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v il1 t hd1 t hd1 t f t p w t hd2 t sp2 t r v il1 rs r / w e db0 - db7 v ih1 v il1 v ih1 v il1 t sp1 t c valid data v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 t hd1 t hd1 t f t p w t hd2 t r v il1 v ih1 v ih1 t d sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 28 feb. 15 , 2005 version: 1.7 7. application circuits 7.1. interface to mpu 7.1.1. interface to 8 - bit mpu (6805) fig ure 7 - 1 : interface to 8 - bit mpu (6805) 7.1.2. interface to 8 - bit mpu (z80) figure 7 - 2 : interface to 8 - bit mpu (z80) pa0 | pa7 pb0 pb1 pb2 8 e rs r / w SPLC782A 16 80 lcd panel 16 commons x 80 segments 6805 db0 | db7 com1 | com16 seg1 | seg80 d0 | d7 8 e rs r / w SPLC782A 16 80 lcd panel 16 commons x 80 segments z80 a1 | a7 a0 iorq wr 7 db0 | db7 com1 | com16 seg1 | seg80 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 29 feb. 15 , 2005 version: 1.7 7.2. applications f or lc d 7.2.1. chip bottom & lower view (dirc = "0", shl = "0") figure 7 - 3 : chip bottom & lower view (example 1) figure 7 - 4 : chip bottom & lower view (example 2) ] com8 com1 seg1 seg80 SPLC782A bottom view shl v2 v3 lcd panel 16 characters x 1 line ( example 1 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 8 duty ] dirc lcd panel 16 characters x 1 line ( example 2 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 11 duty ] seg1 seg80 SPLC782A bottom view com11 com9 com8 com1 shl v2 v3 dirc sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 30 feb. 15 , 2005 version: 1.7 figure 7 - 5 : chip bottom & lower view (example 3) 7.2.2. chip bottom & upper view (dirc = "1", shl = "1") figure 7 - 6 : chip bottom & upper view (example 4) ( example 3 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 bias , 1 / 16 duty ] seg1 seg80 SPLC782A bottom view shl v2 v3 dirc com8 com1 com16 com9 lcd panel 16 characters x 2 line ( example 4 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 8 duty ] com8 com1 seg1 seg80 SPLC782A bottom view shl v2 v3 lcd panel 16 characters x 1 line dirc vdd vdd sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 31 feb. 15 , 2005 version: 1.7 figure 7 - 7 : chip bottom & upper view (example 5) figure 7 - 8 : chip bottom & upper view (example 6) ( example 5 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 11 duty ] lcd panel 16 characters x 1 line seg1 seg80 vdd v2 v3 dirc SPLC782A bottom view com8 com1 com11 com9 shl vdd ( example 6 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 bias , 1 / 16 duty ] seg1 seg80 SPLC782A bottom view shl v2 v3 dirc com8 com1 com16 com9 vdd vdd lcd panel 16 characters x 2 line sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 32 feb. 15 , 2005 version: 1.7 7.2.3. chip top & lower view (dirc = "0", shl = "1") figure 7 - 9 : chip to p & l o w e r vi e w ( e x a m p l e 7 ) figure 7 - 10 : chip top & low e r view (example 8) ( example 7 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 8 duty ] com8 com1 seg1 seg80 SPLC782A top view shl v2 v3 lcd panel 16 characters x 1 line dirc vdd ( example 8 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 11 duty ] seg1 seg80 SPLC782A top view com11 com9 com8 com1 shl v2 v3 dirc vdd lcd panel 16 characters x 1 line sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 33 feb. 15 , 2005 version: 1.7 figure 7 - 11 : chip top & lower view (example 9) 7.2.4. chip top & upper view (dirc = "1", shl = "0") figure 7 - 12 : chip top & upper view (example 10) ( example 9 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 bias , 1 / 16 duty ] seg1 seg80 SPLC782A top view vdd v2 v3 dirc com8 com1 com16 com9 lcd panel 16 characters x 2 line ( example 10 ) : 5 x 8 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 8 duty ] com8 com1 seg1 seg80 SPLC782A top view shl v2 v3 lcd panel 16 characters x 1 line dirc vdd sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 34 feb. 15 , 2005 version: 1.7 figure 7 - 13 : chip top & upper view (example 11) figure 7 - 14 : chip top & upper view (example 12) ( example 11 ) : 5 x 10 dots , 16 characters x 1 line [ 1 / 4 bias , 1 / 11 duty ] lcd panel 16 characters x 1 line seg1 seg80 v2 v3 dirc SPLC782A top view com11 com9 shl vdd com8 com1 ( example 12 ) : 5 x 8 dots , 16 characters x 2 lines [ 1 / 5 bias , 1 / 16 duty ] seg1 seg80 SPLC782A top view shl v2 v3 dirc com8 com1 com16 com9 vdd lcd panel 16 characters x 2 line sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 35 feb. 15 , 2005 version: 1.7 8. character generator rom 8.1. splc 782a - 016 figure 8 - 1 : cgrom (SPLC782A - 016) sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 36 feb. 15 , 2005 version: 1.7 8.2. splc 782a - 022 figure 8 - 2 : cgrom (SPLC782A - 022) sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 37 feb. 15 , 2005 version: 1.7 9. package/pad locations 9.1. pad assignment and locations please contact sunplus sales representatives fo r more information. 9.2. ordering information product number package type SPLC782A - n n nnv - c chip form with gold bump note1: code number is assigned for customer. note2: code number ( n = a - z or 0 - 9, n nn = 0 00 - 9 99); version ( v = a - z). sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 38 feb. 15 , 2005 version: 1.7 10. disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by sunplus technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. sunplus makes no warranty, expres s, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, sunplus makes no warranty of merchantability or fitness for any purpose. sunplus res erves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. product s described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additi onal processing by sunplus for such applications. please note that application circuits illustrated in this document are for reference purposes only. sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 39 feb. 15 , 2005 version: 1.7 11. revision history date revision # description page feb . 15 , 2005 1.7 1. modify from type to dirc in se ction 5.20 common data direction 2. add description (t a =25 ) in section 6.5.1 and 6.5.2 3. correct the description of figure 5 - 4 4. correct the code of 5.2.9 read busy flag and address 5. modify the execution time of 5.3 instruction table 6. remove the note of figure 5 - 16 7. correct the display of 14~21 of figur e 5 - 17 8. insert the display of 10 of figure 5 - 19 9. modify the driver supply voltage of 6.1 absolute maximum ratings 10. modify the operation current of idd1 and idd2 of 6.2 dc characteristics and 6.3 dc characteristics 11. add the operation current of ip p of of 6.2 dc characteristics and 6.3 dc characteristics 12. add the description of max. and min. of fosc of figure 6 - 3 22 2 6 6 7 8 8 9 10 24 24 - 25 24 - 25 27 dec. 24, 2004 1.6 1. add figure number for all figure 2. modify 6.2 iil max. value to - 100ua 3. modify 6.3 iil max. value to - 150ua 4. modify 6.3 vih1 min. value to 0.7vdd 5. modify ta of all dc/ac characteristics to ta= - 2 0 to +7 5 6. modify 6.5.3 and 6.5.4 e cycle time to 1250ns 7. modify 6.5.3 and 6.5.4 e pulse width to 600ns 24 24 24 24 - 26 26 26 apr. 23, 2004 1.5 1. modify description: execution time to execution time (temp = 25 ) 2. modify note2 : from 2.3ms to 4.1ms 8 8 apr. 01, 2004 1.4 1. add min. and max. value in instruction table 2. add 8 - bit/4 - bit data transfer timing sequence exa mple 3. add 6.8 the following graps show the relationship between fosc and temperature 4. add note2 in instruction table 8 18 - 19 27 8 jun. 20, 2003 1.3 1. add 8.3 splc 782a - 22 2. remove 9. package/pad locations 33 34 may. 09, 2002 1.2 1. correct pin no. error v2 pin: 21 to 22 v3 pin: 22 to 21 r/w pin: 25 to 26 rs pin: 26 to 25 mod1 pin: 17 to 18 mod0 pin: 18 to 17 2. correct rom size: 160 5*8 dot - > 192 5*8 dot character patterns 32 5*10 dot - > 64 5*10 dot character patterns 5 13 nov. 26, 2001 1.1 1. modify mode1 to mod1 , mode2 to mod0 in the 4. signal descriptions 2. modify pins cl2 and d description : normal mode to normally use in the 4. signal descriptions 3. modify pin osc1 descripti on in the 4. signal descriptions 4. modify dc characteristics in the 6. electrical specifications 5 5 5 21 sunplus confidential for partminer use only
SPLC782A ? sunplus technology co., ltd. proprietary & confidential 40 feb. 15 , 2005 version: 1.7 date revision # description page jul. 27, 2001 1.0 1. delete preliminary 2. add with gold bump in the 9.3 ordering information 3. renew to a new document format 33 may. 04, 2001 0.1 original sunplus confidential for partminer use only

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