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1. general description the SC68C2550B is a two channel universal asynchronous receiver and transmitter (uart) used for serial data communications. its principal function is to convert parallel data into serial data and vice versa. the uart can handle serial data rates up to 5 mbit/s. the SC68C2550B provides enhanced uart functions with 16-byte fifos, modem control interface, dma mode data transfer. the dma mode data transfer is controlled by the fifo trigger levels and the txrd y and rxrd y signals. on-board status registers provide the user with error indications and operational status. system interrupts and modem control features may be tailored by software to meet speci?c user requirements. an internal loop-back capability allows on-board diagnostics. independent programmable baud rate generators are provided to select transmit and receive baud rates. the SC68C2550B operates at 5 v, 3.3 v and 2.5 v and the industrial temperature range, and is available in a plastic lqfp48 package. 2. features n 2 channel uart with motorola m p interface n 5 v, 3.3 v and 2.5 v operation n industrial temperature range n up to 5 mbit/s data rate at 5 v and 3.3 v, and 3 mbit/s at 2.5 v n 16-byte transmit fifo to reduce the bandwidth requirement of the external cpu n 16-byte receive fifo with error ?ags to reduce the bandwidth requirement of the external cpu n independent transmit and receive uart control n four selectable receive fifo interrupt trigger levels n software selectable baud rate generator n standard asynchronous error and framing bits (start, stop, and parity overrun break) n transmit, receive, line status, and data set interrupts independently controlled n fully programmable character formatting: u 5, 6, 7, or 8-bit characters u even, odd, or no-parity formats u 1, 1 1 2 , or 2-stop bit u baud generation (dc to 5 mbit/s) n false start-bit detection n complete status reporting capabilities n 3-state output ttl drive capabilities for bi-directional data bus and control bus SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos and motorola m p interface rev. 02 28 april 2005 product data sheet
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 2 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos n line break generation and detection n internal diagnostic capabilities: u loop-back controls for communications link fault isolation n prioritized interrupt system controls n modem control functions ( cts, r ts, dsr, dtr, ri, cd) 3. ordering information table 1: ordering information type number package name description version SC68C2550Bib48 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 3 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 4. block diagram fig 1. block diagram of SC68C2550B txa, txb rxa, rxb SC68C2550B xtal2 xtal1 d0 to d7 r/w reset 002aab334 data b u s and control logic register select logic a0 to a3 cs interrupt control logic irq txrdya, txrdyb rxrdya, rxrdyb clock and baud rate generator interconnect bus lines and control signals modem control logic dtra, dtrb rtsa, rtsb op2a, op2b ctsa, ctsb ria, rib cda, cdb dsra, dsrb receive shift register receive fifo register transmit shift register transmit fifo register
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 4 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 5. pinning information 5.1 pinning 5.2 pin description fig 2. pin con?guration for lqfp48 SC68C2550Bib48 d5 reset d6 dtrb d7 dtra rxb rtsa rxa op2a txrdyb rxrdya txa irq txb n.c. op2b a0 cs a1 a3 a2 n.c. n.c. xtal1 d4 xtal2 d3 r/w d2 cdb d1 gnd d0 rxrdyb txrdya v cc v cc dsrb ria rib cda rtsb dsra ctsb gnd ctsa n.c. 002aab335 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 table 2: pin description symbol pin type description a0 28 i address 0 select bit. internal register address selection. a1 27 i address 1 select bit. internal register address selection. a2 26 i address 2 select bit. internal register address selection. a3 11 i address 3. a3 is used to select channel a or channel b. a logic low selects channel a, and a logic high selects channel b. (see t ab le 3 .) cs 10 i chip select (active low). this pin enables data transfers between the user cpu and the SC68C2550B for the channel(s) addressed. individual uart sections (a, b) are addressed by a3. see t ab le 3 . d0 to d7 44, 45, 46, 47, 48, 1, 2, 3 i/o data bus (bi-directional). these pins are the 8-bit, 3-state data bus for transferring information to or from the controlling cpu. d0 is the least signi?cant bit and the ?rst data bit in a transmit or receive serial data stream. gnd 17, 24 i signal and power ground. irq 30 o interrupt request. interrupts from uart channels a-b are wire-ored internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by addressing each channel through its associated internal register, using cs and a3. an external pull-up resistor must be connected between this pin and v cc .
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 5 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos r/ w 15 i a logic low on this pin will transfer the contents of the data bus (d[0:7]) from an external cpu to an internal register that is de?ned by address bits a[0:2]. a logic high on this pin will load the contents of an internal register de?ned by address bits a[0:2] on the SC68C2550B data bus (d[0:7]) for access by an external cpu. op2a, op2b 32, 9 o output 2 (user-de?ned). this function is associated with individual channels a and b. the state of these pins is de?ned by the user through the software settings of mcr[3]. op2a/ op2b is a logic 0 when mcr[3] is set to a logic 1. op2a/ op2b is a logic 1 when mcr[3] is set to a logic 0. the output of these two pins is high after reset. reset 36 i reset (active low). a logic 0 on this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. (see section 7.10 SC68C2550B e xter nal reset condition for initialization details.) rxrd y a, rxrd yb 31, 18 o receive ready a, b (active low). this function is associated with plcc44 and lqfp48 packages only. this function provides the rx fifo/rhr status for individual receive channels (a-b). rxrd yn is primarily intended for monitoring dma mode 1 transfers for the receive data fifos. a logic 0 indicates there is a receive data to read/upload, that is, receive ready status with one or more rx characters available in the fifo/rhr. this pin is a logic 1 when the fifo/rhr is empty or when the programmed trigger level has not been reached. this signal can also be used for single mode transfers (dma mode 0). txrd y a, txrd yb 43, 6 o transmit ready a, b (active low). this function is associated with plcc44 and lqfp48 packages only. these outputs provide the tx fifo/thr status for individual transmit channels (a-b). txrd yn is primarily intended for monitoring dma mode 1 transfers for the transmit data fifos. an individual channels txrd y a, txrd yb buffer ready status is indicated by logic 0, that is, at lease one location is empty and available in the fifo or thr. this pin goes to a logic 1 (dma mode 1) when there are no more empty locations in the fifo or thr. this signal can also be used for single mode transfers (dma mode 0). v cc 19, 42 i power supply input xtal1 13 i crystal or external clock input. functions as a crystal input or as an external clock input. a crystal can be connected between this pin and xtal2 to form an internal oscillator circuit. alternatively, an external clock can be connected to this pin to provide custom data rates. (see section 6.5 prog r ammab le baud r ate gener ator .) see figure 3 . xtal2 14 o output of the crystal oscillator or buffered clock. (see also xtal1.) crystal oscillator output or buffered clock output. should be left open if an external clock is connected to xtal1. for extended frequency operation, this pin should be tied to v cc via a 2 k w resistor. cd a, cdb 40, 16 i carrier detect (active low). these inputs are associated with individual uart channels a through b. a logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. ctsa, ctsb 38, 23 i clear to send (active low). these inputs are associated with individual uart channels, a through b. a logic 0 on the cts pin indicates the modem or data set is ready to accept transmit data from the SC68C2550B. status can be tested by reading msr[4]. this pin has no effect on the uarts transmit or receive operation. dsra, dsrb 39, 20 i data set ready (active low). these inputs are associated with individual uart channels, a through b. a logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the uart. this pin has no effect on the uarts transmit or receive operation. table 2: pin description continued symbol pin type description
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 6 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos dtra, dtrb 34, 35 o data terminal ready (active low). these outputs are associated with individual uart channels, a through b. a logic 0 on this pin indicates that the SC68C2550B is powered-on and ready. this pin can be controlled via the modem control register. writing a logic 1 to mcr[0] will set the dtr output to logic 0, enabling the modem. this pin will be a logic 1 after writing a logic 0 to mcr[0], or after a reset. this pin has no effect on the uarts transmit or receive operation. ria, rib 41, 21 i ring indicator (active low). these inputs are associated with individual uart channels, a through b. a logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate an interrupt. r tsa, r tsb 33, 22 o request to send (active low). these outputs are associated with individual uart channels, a through b. a logic 0 on the r ts pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register mcr[1] will set this pin to a logic 0, indicating data is available. after a reset this pin will be set to a logic 1. this pin has no effect on the uarts transmit or receive operation. rxa, rxb 5, 4 i receive data a, b. these inputs are associated with individual serial channel data to the SC68C2550B receive input circuits, a-b. the rx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the rx input pin is disabled and tx data is connected to the uart rx input, internally. txa, txb 7, 8 o transmit data a, b. these outputs are associated with individual serial transmit channel data from the SC68C2550B. the tx signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. during the local loop-back mode, the tx output pin is disabled and tx data is internally connected to the uart rx input. n.c. 12, 25, 29, 37 - not connected table 2: pin description continued symbol pin type description
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 7 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 6. functional description the SC68C2550B provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character (character orientated protocol). data integrity is insured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. the SC68C2550B represents such an integration with greatly enhanced features. the SC68C2550B is fabricated with an advanced cmos process. the SC68C2550B is an upward solution that provides a dual uart capability with 16 bytes of transmit and receive fifo memory. the SC68C2550B is designed to work with high speed modems and shared network environments that require fast data processing time. increased performance is realized in the SC68C2550B by the transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. for example, the st16c2450 without a receive fifo, will require unloading of the rhr in 93 microseconds (this example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s). this means the external cpu will have to service the receive fifo less than every 100 microseconds. however, with the 16-byte fifo in the SC68C2550B, the data buffer will not require unloading/loading for 1.53 ms. this increases the service interval, giving the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. in addition, the four selectable receive fifo trigger interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. the fifo memory greatly reduces the bandwidth requirement of the external controlling cpu, increases performance, and reduces power consumption. the SC68C2550B is capable of operation up to 5 mbit/s with a 80 mhz clock. with a crystal or external clock input of 7.3728 mhz, the user can select data rates up to 460.8 kbit/s. the rich feature set of the SC68C2550B is available through internal registers. selectable receive fifo trigger levels, selectable tx and rx baud rates, and modem interface controls are all standard features. 6.1 uart a-b functions the uart provides the user with the capability to bi-directionally transfer information between an external cpu, the SC68C2550B package, and an external serial device. a logic 0 on chip select pin cs and a3 (low or high) allows the user to con?gure, send data, and/or receive data via uart channels a and b. individual channel select functions are shown in t ab le 3 . table 3: channel selection using cs pin cs a3 uart select 1 - none 0 0 channel a 0 1 channel b
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 8 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 6.2 internal registers the SC68C2550B provides two sets of internal registers (a and b) consisting of 12 registers each for monitoring and controlling the functions of each channel of the uart. these registers are shown in t ab le 4 . the uart registers function as data holding registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control register (fcr), line status and control registers (lcr/lsr), modem status and control registers (mcr/msr), programmable data rate (clock) control registers (dll/dlm), and a user accessible scratchpad register (spr). [1] these registers are accessible only when lcr[7] is a logic 0. [2] these registers are accessible only when lcr[7] is a logic 1. 6.3 fifo operation the 16 byte transmit and receive data fifos are enabled by the fifo control register (fcr) bit 0. the user can set the receive trigger level via fcr[7:6], but not the transmit trigger level. the receiver fifo section includes a time-out function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (rhr) has not been read following the loading of a character or the receive trigger level has not been reached. table 4: internal registers decoding a2 a1 a0 read mode write mode general register set (thr/rhr, ier/isr, mcr/msr, fcr, lsr, spr) [1] 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register n/a 1 1 0 modem status register n/a 1 1 1 scratchpad register scratchpad register baud rate register set (dll/dlm) [2] 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 1 msb of divisor latch msb of divisor latch table 5: flow control mechanism selected trigger level (characters) irq pin activation 11 44 88 14 14
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 9 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 6.4 hardware/software and time-out interrupts the interrupts are enabled by ier[0-3]. care must be taken when handling these interrupts. following a reset, if interrupt enable register (ier) bi t1=1,the SC68C2550B will issue a transmit holding register interrupt. this interrupt must be serviced prior to continuing operations. the isr register provides the current singular highest priority interrupt only. a condition can exist where a higher priority interrupt may mask the lower priority interrupt(s). only after servicing the higher pending interrupt will the lower priority interrupt(s) be re?ected in the status register. servicing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. receive data ready and receive time-out have the same interrupt priority (when enabled by ier[0]). the receiver issues an interrupt after the number of characters have reached the programmed trigger level. in this case, the SC68C2550B fifo may hold more characters than the programmed trigger level. following the removal of a data byte, the user should re-check lsr[0] for additional characters. a receive time-out will not occur if the receive fifo is empty. the time-out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time-out value is 4 character time, including data information length, start bit, parity bit, and the size of stop bit, that is, 1 , 1.5 , or 2 bit times. 6.5 programmable baud rate generator the SC68C2550B supports high speed modem technologies that have increased input data rates by employing data compression schemes. for example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. a 128.0 kbit/s isdn modem that supports data compression may need an input data rate of 460.8 kbit/s. the SC68C2550B can support a standard data rate of 921.6 kbit/s. a single baud rate generator is provided for the transmitter and receiver, allowing independent tx/rx channel control. the programmable baud rate generator (brg) is capable of operating with a frequency of up to 80 mhz. to obtain maximum data rate, it is necessary to use full rail swing on the clock input. the SC68C2550B can be con?gured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the xtal1 and xtal2 pins. alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates (see t ab le 6 ). the generator divides the input 16 clock by any divisor from 1 to (2 16 - 1). the SC68C2550B divides the basic external clock by 16. the basic 16 clock provides table rates to support standard and custom applications using the same system design. the rate table is con?gured via the dll and dlm internal register functions. customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides a user capability for selecting the desired ?nal baud rate. the example in t ab le 6 shows the selectable baud rate table available when using a 1.8432 mhz external clock input.
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 10 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 6.6 dma operation the SC68C2550B fifo trigger level provides additional ?exibility to the user for block mode operation. lsr[6:5] provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifos in the dma mode (fcr[3]). when the transmit and receive fifos are enabled and the dma mode is de-activated (dma mode 0), the SC68C2550B activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode 1), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the receive trigger level and the transmit fifo. in this mode, the SC68C2550B sets the txrdy (or rxrdy) output pin when characters in the transmit fifo is below 16, or the characters in the receive fifos are above the receive trigger level. fig 3. crystal oscillator connection table 6: baud rate generator programming table using a 1.8432 mhz clock output baud rate output 16 clock divisor (decimal) output 16 clock divisor (hex) dlm program value (hex) dll program value (hex) 50 2304 900 09 00 75 1536 600 06 00 110 1047 417 04 17 150 768 300 03 00 300 384 180 01 80 600 192 c0 00 c0 1200 96 60 00 60 2400 48 30 00 30 3600 32 20 00 20 4800 24 18 00 18 7200 16 10 00 10 9600 12 0c 00 0c 19.2 k 6 06 00 06 38.4 k 3 03 00 03 57.6 k 2 02 00 02 115.2 k 1 01 00 01 002aab325 c2 33 pf xtal1 xtal2 x1 1.8432 mhz c1 22 pf
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 11 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 6.7 loop-back mode the internal loop-back capability allows on-board diagnostics. in the loop-back mode, the normal modem interface pins are disconnected and recon?gured for loop-back internally (see figure 4 ). mcr[3:0] register bits are used for controlling loop-back diagnostic testing. in the loop-back mode, the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally. the cts, dsr, cd, and ri are disconnected from their normal modem control inputs pins, and instead are connected internally to r ts, dtr, mcr[3] ( op2) and mcr[2] ( op1). loop-back test data is entered into the transmit holding register via the user data bus interface, d0 to d7. the transmit uart serializes the data and passes the serial data to the receive uart via the internal loop-back connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface d0 to d7. the user optionally compares the received data to the initial transmitted data for verifying error-free operation of the uart tx/rx circuits. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational.
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 12 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos fig 4. internal loop-back mode diagram ctsa, ctsb transmit fifo registers txa, txb receive shift register receive fifo registers rxa, rxb interconnect bus lines and control signals SC68C2550B transmit shift register xtal2 xtal1 002aab336 data b u s and control logic register select logic interrupt control logic clock and baud rate generator modem control logic rtsa, rtsb dsra, dsrb dtra, dtrb ria, rib (op1a, op1b) cda, cdb (op2a, op2b) mcr[4] = 1 d0 to d7 r/w reset a0 to a3 cs irq txrdya, txrdyb rxrdya, rxrdyb
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 13 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7. register descriptions t ab le 7 details the assigned bit functions for the SC68C2550B internal registers. the assigned bit functions are more fully de?ned in section 7.1 through section 7.10 . [1] the value shown in represents the registers initialized hex value; x = n/a. [2] accessible only when lcr[7] is logic 0. [3] baud rate registers accessible only when lcr[7] is logic 1. 7.1 transmit (thr) and receive (rhr) holding registers the serial transmitter section consists of an 8-bit transmit hold register (thr) and transmit shift register (tsr). the status of the thr is provided in the line status register (lsr). writing to the thr transfers the contents of the data bus (d7 to d0) to the tsr and uart via the thr, providing that the thr is empty. the thr empty ?ag in the lsr register will be set to a logic 1 when the transmitter is empty or when data is transferred to the tsr. note that a write operation can be performed when the thr empty ?ag is set (logi c 0 = at least one byte in fifo/thr, logic 1 = fifo/thr empty). the serial receive section also contains an 8-bit receive holding register (rhr) and a receive serial shift register (rsr). receive data is removed from the SC68C2550B and receive fifo by reading the rhr register. the receive section provides a mechanism to table 7: SC68C2550B internal registers a2 a1 a0 register default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general register set [2] 0 0 0 rhr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 thr xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 ier 00 0 0 0 0 modem status interrupt receive line status interrupt transmit holding register interrupt receive holding register 0 1 0 fcr 00 rcvr trigger (msb) rcvr trigger (lsb) reserved 0 reserved 0 dma mode select xmit fifo reset rcvr fifo reset fifos enable 0 1 0 isr 01 fifos enabled fifos enabled 0 0 int priority bit 2 int priority bit 1 int priority bit 0 int status 0 1 1 lcr 00 divisor latch enable set break set parity even parity parity enable stop bits word length bit 1 word length bit 0 1 0 0 mcr 00 0 0 0 loop back op2 control ( op1) r ts dtr 1 0 1 lsr 60 fifo data error thr and tsr empty thr empty break interrupt framing error parity error overrun error receive data ready 1 1 0 msr x0 cd ri dsr cts d cd d ri d dsr d cts 1 1 1 spr ff bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 special register set [3] 0 0 0 dll xx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 dlm xx bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 14 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos prevent false starts. on the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate. after 7 1 2 clocks, the start bit time should be shifted to the center of the start bit. at this time the start bit is sampled, and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. receiver status codes will be posted in the lsr. 7.2 interrupt enable register (ier) the interrupt enable register (ier) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. these interrupts would normally be seen on the irq output pin. table 8: interrupt enable register bits description bit symbol description 7:4 ier[7:4] not used 3 ier[3] modem status interrupt. this interrupt will be issued whenever there is a modem status change as re?ected in msr[3:0]. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 ier[2] receive line status interrupt. this interrupt will be issued whenever a receive data error condition exists as re?ected in lsr[4:1]. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 ier[1] transmit holding register interrupt. in the 16c450 mode, this interrupt will be issued whenever the thr is empty, and is associated with lsr[5]. in the fifo modes, this interrupt will be issued whenever the fifo is empty. logic 0 = disable the transmit holding register empty (txrdy) interrupt (normal default condition) logic 1 = enable the txrdy (isr level 3) interrupt 0 ier[0] receive holding register. in the 68c450 mode, this interrupt will be issued when the rhr has data, or is cleared when the rhr is empty. in the fifo mode, this interrupt will be issued when the fifo has reached the programmed trigger level or is cleared when the fifo drops below the trigger level. logic 0 = disable the receiver ready (isr level 2, rxrdy) interrupt (normal default condition) logic 1 = enable the rxrdy (isr level 2) interrupt
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 15 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.2.1 ier versus transmit/receive fifo interrupt mode operation when the receive fifo (fcr[0] = logic 1), and receive interrupts (ier[0] = logic 1) are enabled, the receive interrupts and register status will re?ect the following: ? the receive rxrdy interrupt (level 2 isr interrupt) is issued to the external cpu when the receive fifo has reached the programmed trigger level. it will be cleared when the receive fifo drops below the programmed trigger level. ? receive fifo status will also be re?ected in the user accessible isr register when the receive fifo trigger level is reached. both the isr register receive status bit and the interrupt will be cleared when the fifo drops below the trigger level. ? the receive data ready bit (lsr[0]) is set as soon as a character is transferred from the shift register (rsr) to the receive fifo. it is reset when the fifo is empty. ? when the transmit fifo and interrupts are enabled, an interrupt is generated when the transmit fifo is empty due to the unloading of the data by the tsr and uart for transmission via the transmission media. the interrupt is cleared either by reading the isr register, or by loading the thr with new data characters. 7.2.2 ier versus receive/transmit fifo polled mode operation when fcr[0] = logic 1, resetting ier[3:0] enables the SC68C2550B in the fifo polled mode of operation. in this mode, interrupts are not generated and the user must poll the lsr register for tx and/or rx data status. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ? lsr[0] will be a logic 1 as long as there is one byte in the receive fifo. ? lsr[4:1] will provide the type of receive errors, or a receive break, if encountered. ? lsr[5] will indicate when the transmit fifo is empty. ? lsr[6] will indicate when both the transmit fifo and transmit shift register are empty. ? lsr[7] will show if any fifo data errors occurred. 7.3 fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the receive fifo trigger levels, and select the dma mode. 7.3.1 dma mode 7.3.1.1 mode 0 (fcr bit 3 = 0) set and enable the interrupt for each single transmit or receive operation, and is similar to the 68c450 mode. transmit ready ( txrd y) will go to a logic 0 whenever the fifo (thr, if fifo is not enabled) is empty. receive ready ( rxrd y) will go to a logic 0 whenever the receive holding register (rhr) is loaded with a character. 7.3.1.2 mode 1 (fcr bit 3 = 1) set and enable the interrupt in a block mode operation. the transmit interrupt is set when the transmit fifo is empty. txrd y remains a logic 0 as long as one empty fifo location is available. the receive interrupt is set when the receive fifo ?lls to the programmed
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 16 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos trigger level. however, the fifo continues to ?ll regardless of the programmed level until the fifo is full. rxrd y packages transitions low when the fifo reaches the trigger level, and transitions high when the fifo empties. 7.3.2 fifo mode table 9: fifo control register bits description bit symbol description 7:6 fcr[7:6] rcvr trigger. these bits are used to set the trigger level for the receive fifo interrupt. logic 0 (or cleared) = normal default condition logic 1 = rx trigger level an interrupt is generated when the number of characters in the fifo equals the programmed trigger level. however, the fifo will continue to be loaded until it is full. refer to t ab le 10 . 5:4 fcr[5:4] not used; initialized to logic 0 3 fcr[3] dma mode select logic 0 = set dma mode 0 logic 1 = set dma mode 1 transmit operation in mode 0: when the SC68C2550B is in the 68c450 mode (fifos disabled; fcr[0] = logic 0) or in the fifo mode (fifos enabled; fcr[0] = logic 1; fcr[3] = logic 0), and when there are no characters in the transmit fifo or transmit holding register, the txrd y pin will be a logic 0. once active, the txrd y pin will go to a logic 1 after the ?rst character is loaded into the transmit holding register. receive operation in mode 0: when the SC68C2550B is in mode 0 (fcr[0] = logic 0), or in the fifo mode (fcr[3] = logic 0) and there is at least one character in the receive fifo, the rxrd y pin will be a logic 0. once active, the rxrd y pin will go to a logic 1 when there are no more characters in the receiver. transmit operation in mode 1: when the SC68C2550B is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1), the txrd y pin will be a logic 1 when the transmit fifo is completely full. it will be a logic 0 if one or more fifo locations are empty. receive operation in mode 1: when the SC68C2550B is in fifo mode (fcr[0] = logic 1; fcr[3] = logic 1) and the trigger level has been reached, or a receive time-out has occurred, the rxrd y pin will go to a logic 0. once activated, it will go to a logic 1 after there are no more characters in the fifo. 2 fcr[2] xmit fifo reset logic 0 = transmit fifo not reset (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] rcvr fifo reset logic 0 = receive fifo not reset (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo.
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 17 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.4 interrupt status register (isr) the SC68C2550B provides four levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with four interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. a lower level interrupt may be seen after servicing the higher level interrupt and re-reading the interrupt status bits. t ab le 11 shows the data values (bit 0 to bit 3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. 0 fcr[0] fifos enabled logic 0 = disable the transmit and receive fifo (normal default condition). logic 1 = enable the transmit and receive fifo. this bit must be a 1 when other fcr bits are written to, or they will not be programmed. table 10: rcvr trigger levels fcr[7] fcr[6] rx fifo trigger level 0001 0104 1008 1114 table 9: fifo control register bits description continued bit symbol description table 11: interrupt source priority level isr[3] isr[2] isr[1] isr[0] source of the interrupt 1 0 1 1 0 lsr (receiver line status register) 2 0 1 0 0 rxrdy (received data ready) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 0 1 0 txrdy (transmitter holding register empty) 4 0 0 0 0 msr (modem status register) table 12: interrupt status register bits description bit symbol description 7:6 isr[7:6] fifos enabled. these bits are set to a logic 0 when the fifos are not being used in the 68c450 mode. they are set to a logic 1 when the fifos are enabled in the SC68C2550B mode. logic 0 or cleared = default condition 5:4 isr[5:4] not used 3:1 isr[3:1] int priority bits 2 to 0. these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see t ab le 11 ). logic 0 or cleared = default condition 0 isr[0] int status logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine logic 1 = no interrupt pending (normal default condition)
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 18 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.5 line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. table 13: line control register bits description bit symbol description 7 lcr[7] divisor latch enable. the internal baud rate counter latch and enhanced feature mode enable. logic 0 = divisor latch disabled (normal default condition). logic 1 = divisor latch enabled. 6 lcr[6] set break. when enabled, the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no tx break condition (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition 5:3 lcr[5:3] programs the parity conditions (see t ab le 14 ) 2 lcr[2] stop bits. the length of stop bit is speci?ed by this bit in conjunction with the programmed word length (see t ab le 15 ). logic 0 or cleared = default condition 1:0 lcr[1:0] word length bits 1, 0. these two bits specify the word length to be transmitted or received (see t ab le 16 ). logic 0 or cleared = default condition table 14: lcr[5:3] parity selection lcr[5] lcr[4] lcr[3] parity selection x x 0 no parity x 0 1 odd parity 011even parity 001f orced parity 1 111f orced parity 0 table 15: lcr[2] stop bit length lcr[2] word length stop bit length (bit times) 0 5, 6, 7, 8 1 15 1 1 2 1 6, 7, 8 2 table 16: lcr[1:0] word length lcr[1] lcr[0] word length 005 016 107 118
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 19 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.6 modem control register (mcr) this register controls the interface with the modem or a peripheral device. table 17: modem control register bits description bit symbol description 7:5 mcr[7:5] reserved; set to 0 4 mcr[4] loop-back. enable the local loop-back mode (diagnostics). in this mode the transmitter output (tx) and the receiver input (rx), cts, dsr, cd, and ri are disconnected from the SC68C2550B i/o pins. internally the modem data and control pins are connected into a loop-back data con?guration (see figure 4 ). in this mode, the receiver and transmitter interrupts remain fully operational. the modem control interrupts are also operational, but the interrupts sources are switched to the lower four bits of the modem control. interrupts continue to be controlled by the ier register. logic 0 = disable loop-back mode (normal default condition) logic 1 = enable local loop-back mode (diagnostics) 3 mcr[3] op2 control logic 0 = forces op2 output to high state logic 1 = forces op2 output to low state. in loop-back mode, controls msr[7]. 2 mcr[2] ( op1). op1a/ op1b are not available as an external signal in the SC68C2550B. this bit is instead used in the loop-back mode only. in the loop-back mode, this bit is used to write the state of the modem ri interface signal. 1 mcr[1] r ts logic 0 = force r ts output to a logic 1 (normal default condition) logic 1 = force r ts output to a logic 0 0 mcr[0] dtr logic 0 = force dtr output to a logic 1 (normal default condition) logic 1 = force dtr output to a logic 0
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 20 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.7 line status register (lsr) this register provides the status of data transfers between the SC68C2550B and the cpu. table 18: line status register bits description bit symbol description 7 lsr[7] fifo data error logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when there are no remaining error ?ags associated with the remaining data in the fifo. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode, this bit is set to 1 whenever the transmit fifo and transmit shift register are both empty. 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmit shift register. the bit is reset to a logic 0 concurrently with the loading of the transmit holding register by the cpu. in the fifo mode, this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. 4 lsr[4] break interrupt logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. 3 lsr[3] framing error logic 0 = no framing error (normal default condition) logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode, this error is associated with the character at the top of the fifo. 2 lsr[2] parity error logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. 1 lsr[1] overrun error logic 0 = no overrun error (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case, the previous data in the shift register is overwritten. note that under this condition, the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. 0 lsr[0] receive data ready logic 0 = no data in receive holding register or fifo (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 21 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.8 modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC68C2550B is connected. four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register. [1] whenever any msr bit 0 to bit 3 is set to logic 1, a modem status interrupt will be generated. table 19: modem status register bits description bit symbol description 7 msr[7] cd. during normal operation, this bit is the complement of the cd input. reading this bit in the loop-back mode produces the state of mcr[3] ( op2). 6 msr[6] ri. during normal operation, this bit is the complement of the ri input. reading this bit in the loop-back mode produces the state of mcr[2] ( op1). 5 msr[5] dsr. during normal operation, this bit is the complement of the dsr input. during the loop-back mode, this bit is equivalent to mcr[0] ( dtr). 4 msr[4] cts. during normal operation, this bit is the complement of the cts input. during the loop-back mode, this bit is equivalent to mcr[1] ( r ts). 3 msr[3] d cd [1] logic 0 = no cd change (normal default condition) logic 1 = the cd input to the SC68C2550B has changed state since the last time it was read. a modem status interrupt will be generated. 2 msr[2] d ri [1] logic 0 = no ri change (normal default condition) logic 1 = the ri input to the SC68C2550B has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. 1 msr[1] d dsr [1] logic 0 = no dsr change (normal default condition) logic 1 = the dsr input to the SC68C2550B has changed state since the last time it was read. a modem status interrupt will be generated. 0 msr[0] d cts [1] logic 0 = no cts change (normal default condition) logic 1 = the cts input to the SC68C2550B has changed state since the last time it was read. a modem status interrupt will be generated.
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 22 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 7.9 scratchpad register (spr) the SC68C2550B provides a temporary data register to store 8 bits of user information. 7.10 SC68C2550B external reset condition 8. limiting values table 20: reset state for registers register reset state ier ier[7:0] = 0 fcr fcr[7:0] = 0 isr isr[7:1] = 0; isr[0] = 1 lcr lcr[7:0] = 0 mcr mcr[7:0] = 0 lsr lsr[7] = 0; lsr[6:5] = 1; lsr[4:0] = 0 msr msr[7:4] = input signals; msr[3:0] = 0 spr sfr[7:0] = 1 dll dll[7:0] = x dlm dlm[7:0] = x table 21: reset state for outputs output reset state txa, txb logic 1 op2a, op2b logic 1 r tsa, r tsb logic 1 dtra, dtrb logic 1 irq 3-state condition table 22: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 7 v v n voltage at any pin gnd - 0.3 v cc + 0.3 v t amb operating temperature - 40 +85 c t stg storage temperature - 65 +150 c p tot(pack) total power dissipation per package - 500 mw
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 23 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 9. static characteristics [1] except xtal2, v ol = 1 v typical. table 23: static characteristics t amb = - 40 c to +85 c; v cc = 2.5 v, 3.3 v or 5.0 v 10 %, unless otherwise speci?ed. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v v cc = 5.0 v unit min max min max min max v il(ck) low-level clock input voltage - 0.3 0.45 - 0.3 0.6 - 0.5 0.6 v v ih(ck) high-level clock input voltage 1.8 v cc 2.4 v cc 3.0 v cc v v il low-level input voltage (except x1 clock) - 0.3 0.65 - 0.3 0.8 - 0.5 0.8 v v ih high-level input voltage (except x1 clock) 1.6 - 2.0 - 2.2 - v v ol low-level output voltage on all outputs [1] i ol =5ma (data bus) -----0.4v i ol =4ma (other outputs) ---0.4--v i ol =2ma (data bus) -0.4----v i ol = 1.6 ma (other outputs) -0.4----v v oh high-level output voltage i oh = - 5ma (data bus) ----2.4-v i oh = - 1ma (other outputs) --2.0---v i oh = - 800 m a (data bus) 1.85 -----v i oh = - 400 m a (other outputs) 1.85 -----v i lil low-level input leakage current - 10 - 10 - 10 m a i cl clock leakage - 30 - 30 - 30 m a i cc supply current f = 5 mhz - 3.5 - 4.5 - 4.5 ma c i input capacitance - 5 - 5 - 5 pf
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 24 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 10. dynamic characteristics [1] rclk is an internal signal derived from divisor latch lsb (dll) and divisor latch msb (dlm) divisor latches. [2] applies to external clock; crystal oscillator max 24 mhz. [3] table 24: dynamic characteristics t amb = - 40 c to +85 c; v cc = 2.5 v, 3.3 v 10 % or 5 v 10 %, unless speci?ed otherwise. symbol parameter conditions v cc = 2.5 v v cc = 3.3 v and 5 v unit min max min max t d1 r/ w to chip select 10 - 10 - ns t d2 read cycle delay 25 pf load 20 - 20 - ns t d3 delay from cs to data 25 pf load - 77 - 26 ns t d4 data disable time 25 pf load - 15 - 15 ns t d6 write cycle delay 25 - 25 - ns t d7 delay from write to output 25 pf load - 100 - 33 ns t d8 delay to set interrupt from modem input 25 pf load - 100 - 24 ns t d9 delay to reset interrupt from read 25 pf load - 100 - 24 ns t d10 delay from stop to set interrupt - 1t rclk [1] -1t rclk [1] ns t d11 delay from read to reset interrupt 25 pf load - 100 - 29 ns t d12 delay from start to set interrupt - 100 - 100 ns t d13 delay from write to transmit start 8t rclk [1] 24t rclk [1] 8t rclk [1] 24t rclk [1] ns t d14 delay from write to reset interrupt - 100 - 70 ns t d15 delay from stop to set rxrd y-1t rclk [1] -1t rclk [1] ns t d16 delay from read to reset rxrd y - 100 - 75 ns t d17 delay from write to set txrd y - 100 - 70 ns t d18 delay from start to reset txrd y - 16t rclk [1] - 16t rclk [1] ns t h2 r/ w hold time from cs 10 - 10 - ns t h3 data hold time 15 - 15 - ns t h4 address hold time 15 - 15 - ns t 1w , t 2w clock cycle period 10 - 6 - ns f xtal clock speed [2] [3] - 48 - 80 mhz t (reset) reset pulse width 200 - 200 - ns t su1 address setup time 10 - 10 - ns t su2 data setup time 16 - 16 - ns t w1 cs strobe width 77 - 30 - ns f xtal 1 t 3w ------- =
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 25 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 10.1 timing diagrams fig 5. general read timing 002aab087 t su1 a0 to a3 cs r/w d0 to d7 t w1 t h4 t d2 t d4 t d1 t d3 valid data valid data valid address valid address fig 6. general write timing 002aab088 a0 to a3 d0 to d7 cs r/w t d1 t su2 t h3 t h2 t d6 t h4 t w1 t su1 valid data valid data valid address valid address
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 26 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos (1) cs timing during a write cycle. see figure 6 . (2) cs timing during a read cycle. see figure 5 . fig 7. modem input/output timing t d7 change of state t d8 t d8 t d9 002aab089 t d8 change of state change of state change of state active active active active active active active change of state rtsa, rtsb dtra, dtrb cs (write) (1) cda, cdb ctsa, ctsb dsra, dsrb irq cs (read) (2) ria, rib fig 8. external clock timing external clock 002aaa112 t 3w t 2w t 1w f xtal 1 t 3w ------- =
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 27 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos fig 9. receive timing d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aab090 t d11 next data start bit stop bit parity bit start bit t d10 rxa, rxb irq cs (read) data bits (0 to 7) 5 data bits 6 data bits 7 data bits fig 10. receive ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab091 next data start bit stop bit parity bit t d15 rxa, rxb rxrdya, rxrdyb cs (read) active data ready start bit data bits (0 to 7) active t d16
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 28 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos fig 11. receive ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab092 first byte that reaches the trigger level stop bit parity bit t d15 rxa, rxb rxrdya, rxrdyb cs (read) active data ready start bit data bits (0 to 7) active t d16 fig 12. transmit timing d0 d1 d2 d3 d4 d5 d6 d7 active tx ready active 16 baud rate clock 002aab093 t d14 start bit t d12 txa, txb irq cs (write) data bits (0 to 7) active t d13 5 data bits 6 data bits 7 data bits parity bit stop bit next data start bit
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 29 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos fig 13. transmit ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab094 start bit t d17 txa, txb txrdya, txrdyb cs (write) data bits (0 to 7) active d0 to d7 byte #1 t d18 transmitter not ready active transmitter ready parity bit stop bit next data start bit fig 14. transmit ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab337 stop bit parity bit t d17 txa, txb cs (write) d0 to d7 start bit data bits (0 to 7) byte #16 txrdya, txrdyb t d18 trigger lead active 5 data bits 6 data bits 7 data bits
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 30 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 11. package outline fig 15. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 31 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 12. soldering 12.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 12.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 32 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 12.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 12.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 25: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 33 of 35 philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 13. abbreviations 14. revision history table 26: abbreviations acronym description cpu central processing unit dma direct memory access fifo first in/first out isdn integrated service digital network lsb least signi?cant bit msb most signi?cant bit ttl transistor-transistor logic uart universal asynchronous receiver and transmitter table 27: revision history document id release date data sheet status change notice doc. number supersedes SC68C2550B_2 20050428 product data sheet - 9397 750 14941 SC68C2550B_1 modi?cations: ? added and motorola m p interface to descriptive title on ?rst page. ? section 2 f eatures on page 1 , ?rst bullet: added with motorola m p interface ? added section 18 t r ademar ks on page 34 . SC68C2550B_1 20050329 product data sheet - 9397 750 14698 -
philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 9397 750 14941 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 28 april 2005 34 of 35 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 28 april 2005 document number: 9397 750 14941 published in the netherlands philips semiconductors SC68C2550B 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 16-byte fifos 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 7 6.1 uart a-b functions . . . . . . . . . . . . . . . . . . . . . 7 6.2 internal registers. . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 hardware/software and time-out interrupts. . . . 9 6.5 programmable baud rate generator . . . . . . . . . 9 6.6 dma operation . . . . . . . . . . . . . . . . . . . . . . . . 10 6.7 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 11 7 register descriptions . . . . . . . . . . . . . . . . . . . 13 7.1 transmit (thr) and receive (rhr) holding registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 interrupt enable register (ier) . . . . . . . . . . . 14 7.2.1 ier versus transmit/receive fifo interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.2 ier versus receive/transmit fifo polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 fifo control register (fcr) . . . . . . . . . . . . . 15 7.3.1 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.1.1 mode 0 (fcr bit 3 = 0) . . . . . . . . . . . . . . . . . . 15 7.3.1.2 mode 1 (fcr bit 3 = 1) . . . . . . . . . . . . . . . . . . 15 7.3.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 interrupt status register (isr) . . . . . . . . . . . . 17 7.5 line control register (lcr) . . . . . . . . . . . . . . 18 7.6 modem control register (mcr) . . . . . . . . . . . 19 7.7 line status register (lsr) . . . . . . . . . . . . . . . 20 7.8 modem status register (msr). . . . . . . . . . . . 21 7.9 scratchpad register (spr) . . . . . . . . . . . . . . 22 7.10 SC68C2550B external reset condition . . . . . . 22 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 9 static characteristics. . . . . . . . . . . . . . . . . . . . 23 10 dynamic characteristics . . . . . . . . . . . . . . . . . 24 10.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 25 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 12 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.1 introduction to soldering surface mount packages 31 12.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 12.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 12.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 32 12.5 package related soldering information . . . . . . 32 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 33 15 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 34 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 19 contact information . . . . . . . . . . . . . . . . . . . . 34

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