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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD73460 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 six-input channel analog front end features afe performance 6 16-bit a/d converters programmable input sample rate simultaneous sampling 72 db snr 64 ks/s maximum sample rate C 80 db crosstalk low group delay (25 s typ per adc channel) programmable input gain single supply operation on-chip reference dsp performance 19 ns instruction cycle time @ 3.3 v, 52 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 400 cycle recovery from power-down condition low power dissipation in idle mode functional block diagram serial port sport 2 ref adc3 analog front end section adc1 adc2 adc4 adc5 adc6 external address bus serial ports sport 0 shifter mac alu arithmetic units memory programmable i/o and flags byte dma controller timer adsp-2100 base architecture power-down control program sequencer dag 2 data address generators program memory address data memory address program memory data data memory data dag 1 16k dm (optional 8k) 16k pm (optional 8k) external databus full memory mode sport 1 AD73460 general description the AD73460 is a six-input channel analog front end processor f or general-purpose applications including industrial power m eter- in g or multichannel analog inputs. it features six 16-bit a/d conversion channels, each of which provides 72 db signal-to-noise ratio over a dc-to-2 khz signal bandwidth. each channel also features a programmable input gain amplifier (pga) with gain settings in eight stages from 0 db to 38 db. the AD73460 is particularly suitable for industrial power metering since each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. the AD73460 also features low group delay conversions on all channels. an on-chip reference voltage of 1.25 v is included. the sampling rate of the device is programmable with separate settings o ffering 64 khz, 32 khz, 16 khz, and 8 khz sampling rates (from a master clock of 16.384 mhz), while the serial port (sport2) allows easy expansion of the number of input channels by cas- cading an extra afe external to the AD73460. the AD73460 s dsp engine combines the adsp-2100 family base architecture (three computational units, data address gen- erators, and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the AD73460-80 integrates 80k bytes of on-chip memory c onfigured as 16k words (24-bit) of program ram and 16k (16-bit) of data ram. the AD73460-40 integrates 40k bytes of on-chip memory configured as 8k words (24-bit) of program ram and 8k (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. the AD73460 is available in a 119-ball pbga package.
rev. a AD73460 ?2? topic page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 timing characteristics . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pbga ball configuration . . . . . . . . . . . . . . . . . . . . 7 pin function descriptions . . . . . . . . . . . . . . . . . . 8 architecture overview . . . . . . . . . . . . . . . . . . . . 10 analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . 10 functional description ? afe . . . . . . . . . . . . . . . 11 encoder channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signal conditioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . 11 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 analog sigma-delta modulator . . . . . . . . . . . . . . . . . . . . 12 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 adc coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 afe serial port (sport2) . . . . . . . . . . . . . . . . . . . . . . . 13 sport2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 sport register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 master clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial clock rate divider . . . . . . . . . . . . . . . . . . . . . . . . . 14 decimation rate divider . . . . . . . . . . . . . . . . . . . . . . . . . 14 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 resetting the afe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 cascade operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 functional description ? dsp . . . . . . . . . . . . . . 20 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 dsp section pin descriptions . . . . . . . . . . . . . . . 21 memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 terminating unused pins . . . . . . . . . . . . . . . . . . . . . . . . 22 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 topic page low power operation . . . . . . . . . . . . . . . . . . . . . . . 23 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 slow idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 reset 2 modes of operation 2 s m m 2 p c 2 a c 2 memor architecture 2 program memor 2 p m f m m 2 p m h m 2 data memor 2 d m f m m 2 io s f m m 2 c m s cms 2 b m s bms d 2 b m 2 b m dma bdma f m m 2 i m dma p idma p h m m 2 b l b 2 idma p b 2 b r b g f m m 2 f io p 2 instruction set description 2 designing an eicecompatible sstem 2 t b c e ice p 0 t m i 0 pm dm bm iom cm 0 t s i s 0 analog front end afe interfacing 0 dsp sport to afe interfacing 0 cascade operation 1 i afe a i 1 d i 2 outline dimensions 2 reision histor 2 table of contents
rev. a AD73460 ? specifications AD73460b parameter min typ max unit test conditions/comments 1 reference refcap absolute voltage, v refcap 1.125 1.25 1.375 v refcap tc 50 ppm/ c 0.1 f capacitor required from refcap to agnd2 refout typical output impedance 130 ? absolute voltage, v refout 1.125 1.25 1.375 v unloaded minimum load resistance 1 k ? maximum load capacitance 100 pf adc specifications maximum input range at vin 2, 3 1.644 v p-p measured differentially C 2.85 dbm nominal reference level at vin 1.1413 v p-p measured differentially (0 dbm0) C 6.02 dbm absolute gain pga = 0 db C 1.2 +0.6 db 1.0 khz signal to (noise + distortion) pga = 0 db 71 db 0 hz to 4 khz; f s = 8 khz; f in = 60 hz pga = 0 db 70 72 db 0 hz to 2 khz; f s = 8 khz; f in = 60 hz total harmonic distortion pga = 0 db C 77 C 72 db intermodulation distortion C 76 db pga = 0 db idle channel noise C 70 db pga = 0 db crosstalk adc-to-adc C 83 db adc1 input at idle adc2 to adc6 input signal: 1.0 khz C 95 db adc1 input at idle adc2 to adc6 input signal: 60 hz dc offset C 30 +10 +45 mv pga = 0 db power supply rejection C 55 db input signal level at avdd and dvdd pins 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s 64 khz output sample rate 50 s 32 khz output sample rate 95 s 16 khz output sample rate 190 s8 khz output sample rate input resistance at vin 2, 4 25 k ? 6 dmclk = 16.384 mhz phase mismatch 0.15 degrees f in = 1 khz 0.01 degrees f in = 60 hz frequency response (adc) 7 typical output frequency (normalized to f s ) 00db 0.03125 C 0.1 db 0.0625 C 0.25 db 0.125 C 0.6 db 0.1875 C 1.4 db 0.25 C 2.8 db 0.3125 C 4.5 db 0.375 C 7.0 db 0.4375 C 9.5 db > 0.5 < C 12.5 db (avdd = 3.0 v to 3.6 v; dvdd = 3.0 v to 3.6 v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f sclk = 8.192 mhz, f s = 8 khz; t a = t min to t max , unless otherwise noted.)
rev. a ?4? AD73460 C C + + +
rev. a AD73460 ? parameter test conditions min typ max unit dsp section v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min, i oh = C 0.5 ma 2.4 v @ v dd = min, i oh = C 100 a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min, i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max, v in = v dd max 10 a i il lo-level input current 3 @ v dd = max, v in = 0 v 10 a i ozh three-state leakage current 7 @ v dd = max, v in = v dd max 8 10 a i ozl three-state leakage current 7 @ v dd = max, v in = 0 v 8 10 a i dd supply current (idle) 9 @ v dd = 3.3 v t ck = 19 ns 10 14 ma t ck = 25 ns 10 12 ma t ck = 30 ns 10 10 ma i dd supply current (dynamic) 11 @ v dd = 3.3 v, t amb = 25 c t ck = 19 ns 10 54 ma t ck = 25 ns 10 43 ma t ck = 30 ns 10 37 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = 25 c8pf notes 1 bidirectional pins: d0 C d23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1 C a13, pf0 C pf7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack , a0, dt0, dt1, clkout, fl2 C 0, bgh . 5 although specified for ttl outputs, all AD73460 outputs are cmos compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0 C a13, d0 C d23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0 C pf7. 8 0 v on br . 9 idle refers to AD73460 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 11 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 applies to pbga package type. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. specifications (avdd = 3.0 v to 3.6 v; dvdd = 3.0 v to 3.6 v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted.)
rev. a AD73460 ?6? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD73460 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * (t a = 25 + + + + + + + + C C adsp-2100 family user? manual, third edition. specifications subject to change without notice. (avdd = 3 v to 3.6 v; dvdd = 3 v to 3.6 v; agnd = dgnd = 0 v; t a = t mln to t max , unless otherwise noted.)
rev. a AD73460 ?7? pbga ball configurations pbga ball pbga ball pbga ball pbga ball number name number name number name number name a1 irqe pf4 e3 rfs0 j5 d22 n7 d13 a2 dms e aiad2 d21 p1 ebr a ddint e a2iad1 d20 p2 d0iad1 a clkin e a1iad0 k1 elout p ddd a a11iad10 e a0 k2 elin p dgnd a aiad f1 dr0 k eint p areset a aiad f2 sclk0 k d1 p sclk2 b1 irql0 pf5 f3 dt1 k5 d18 p7 mclk b2 pms f pwdack k d1 r1 sdo b wr f bgh k d1 r2 sdofs b tal f m a pf0 l1 bg r sdifs b a12iad11 f m b pf1 l2 d3/ iack r sdi b aiad g1 tfs1 l dial r se b aiad g2 rfs1 l d r refcap c1 irql1 pf6 g3 dr1 l5 d9 r7 refout c2 ioms g gnd l d12 t1 inn2 c rd g pwd l d1 t2 inp2 c ddet g ddet m1 ebg t inn1 c a1iad12 g m c pf2 m2 d2/iad15 t4 vinp1 c6 a9/iad8 h1 sclk1 m3 d4/ is t inn c gnd h2 ereset m d iwr t inp d1 irq2 pf7 h3 reset m ddet t inn d2 cms h pf m d11 u1 agnd d bms h fl0 m d1 u2 add d clkout h fl1 n1 br u inp d gnd h fl2 n2 d1iad1 u inn d a10iad 1 ems n ddint u inp d aiad 2 ee n d ird u inn e1 dt0 eclk n gnd u inp e2 tfs0 d2 n d10 pbga ball configuration a b c d e f g h k l m n p r t u 12 a b c d e f g h k l m n p r t u 12
rev. a AD73460 ?8? pin function descriptions 1 mnemonic function vinp1 analog input to the positive terminal of input channel 1 vinn1 analog input to the negative terminal of input channel 1 vinp2 analog input to the positive terminal of input channel 2 vinn2 analog input to the negative terminal of input channel 2 vinp3 analog input to the positive terminal of input channel 3 vinn3 analog input to the negative terminal of input channel 3 vinp4 analog input to the positive terminal of input channel 4 vinn4 analog input to the negative terminal of input channel 4 vinp5 analog input to the positive terminal of input channel 5 vinn5 analog input to the negative terminal of input channel 5 vinp6 analog input to the positive terminal of input channel 6 vinn6 analog input to the negative terminal of input channel 6 refout buffered reference output, which has a nominal value of 1.25 v refcap a bypass capacitor to agnd2 of 0.1 areset a l r s t ad0 sclk2 o s c r d s t r afe i sport2 t sclk mclk mclk m c i a f e mclk sdo s d o ad0 b sclk2 sdo se sdofs f s o sdo s t t sclk msb sdofs sclk2 sdofs se sdifs f s i sdi s t t sclk msb sdifs sclk2 se sdi s d i ad0 b sclk2 sdi se se sport e a sport w se dsp sport sclk2 w se sport se reset i p r i br i b r i bg o b g o bgh o b g h o dms o d m s o pms o p m s o ioms o m s o bms o b m s o cms o c m s o rd o m r e o
rev. a AD73460 ?9? pin function descriptions 1 (continued) mnemonic function wr o m w e o irq2 i e ls i pf7 (input/output) request. 2 programmable i/o pin irql0 i ls i r 2 pf6 (input/output) programmable i/o pin irql1 i ls i r 2 pf5 (input/output) programmable i/o pin irqe i es i r 2 pf4 (input/output) programmable i/o pin mode d/ (input) mode select input ? checked only during reset pf3 (input/output) programmable i/o pin during normal operation mode c/ (input) mode select input ? checked only during reset pf2 (input/output) programmable i/o pin during normal operation mode b/ (input) mode select input ? checked only during reset pf1 (input/output) programmable i/o pin during normal operation mode a/ (input) mode select input ? checked only during reset pf0 (input/output) programmable i/o pin during normal operation clkin, (inputs) clock or quartz crystal input xtal clkout (output) processor clock output sport0 (inputs/outputs) serial port i/o pins sport1 (inputs/outputs) serial port i/o pins irq1 0 i e ls i fi i f i fo o f o pwd i pd c i pwdack o pd c o fl0 fl1 o o f fl2 a1 a0 o a o p p d b io s d2 d0 io d io p p d b io s dd p g gnd eice p io f e u ereset ems ee eclk elout elin eint ebr ebg notes 1 r adsp21l dsp 2 if i imask dsp sport dsp s c r s
rev. a AD73460 ?10? architecture overview the AD73460 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instruc- ti ons. every instruction can be executed in a single processor cycle. the AD73460 assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of devel- opment tools supports program development. serial port sport 2 ref adc3 analog front end section adc1 adc2 adc4 adc5 adc6 external address bus serial ports sport 0 shifter mac alu arithmetic units memory programmable i/o and flags byte dma controller timer power-down control program sequencer dag 2 data address generators program memory address data memory address program memory data data memory data dag 1 16k dm (optional 8k) 16k pm (optional 8k) external databus full memory mode sport 1 AD73460 adsp-2100 base architecture figure 1. functional block diagram figure 1 is an overall block diagram of the AD73460. the pro- cessor section contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provi- s ions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primi- tives are also supported. the mac performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, n ormalization, denormalization, and d erive exponent operations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address genera tors ensure efficient de livery of operands to these compu- tational units. the sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. with internal loop counters and loop stacks, the AD73460 executes looped c ode with zero overhead; no explicit jump instructions are r equired to maintain loops. t wo data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two databuses (pmd and dmd) share a single external databus. byte memory space and i/o memory space also share the external buses. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the AD73460 can respond to 11 interrupts. there can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port, and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. analog front end the analog front end (afe) of the AD73460 is configured as a separate block that is normally connected to either sport0 or sport1 of the dsp section. as it is not hardwired to either sport, users have total flexibility in how they wish to allocate s ystem resources to support the afe. it is also possible to f urther expand the number of analog input channels connected to the sport by cascading an ad73360 device external to the AD73460. the afe is configured as six input channels. it comprises six independent encoder channels, each featuring signal condition ing, programmable gain amplifier, sigma-delta a/d converter, and decimator sections. each of these sections is described in further detail later in this data sheet. all channels share a common internal reference whose nominal value is 1.25 v. figure 2 shows a block diagram of the afe section of the AD73460. it shows six input channels along with a common reference. communication to all channels is handled by the sport2 block, which interfaces to either sp ort0 or sport1 of the dsp section.
rev. a AD73460 ?11? vinn1 vinp1 analog - modulator sdi sdifs sclk2 refcap refout se areset sdos sdo amclk i2 ip2 i ip i ip i ip i ip aesectio sigal coditioig 0b pga decimator serial io port sigal coditioig 0b pga decimator sigal coditioig 0b pga decimator sigal coditioig 0b pga decimator sigal coditioig 0b pga decimator sigal coditioig 0b pga decimator reerece aalog - modulator analog - modulator analog - modulator analog - modulator analog - modulator AD73460 figure 2. functional block diagram of analog front end table ii. pga settings for the encoder channel ixgs2 ixgs1 ixgs0 gain (db) 000 0 001 6 010 12 011 18 100 20 101 26 110 32 111 38 adc each channel has its own adc consisting of an analog sigma- delta modulator and a digital antialiasing decimation filter. the sigma-delta modulator noise-shapes the signal and produces 1- bit samples at a dmclk/8 rate. this bit stream, representing the analog input signal, is input to the antialiasing decimation f ilter. the decimation filter reduces the sample rate and increases the resolution. functional description
rev. a AD73460 ?12? analog sigma-delta modulator the AD73460 input channels employ a sigma-delta conversion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. s igm a-delta converters employ a technique known as over- sampling, w here the sampling rate is many times the highest frequency of interest. in the case of the AD73460, the initial sampling rate of the sigma-delta modulator is dmclk/8. the main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to f s /2 = dmclk/16 (figure 3a). this means that the noise in the band of interest is much reduced. another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. this technique has the effect of pushing the noise from the band of interest to an out-of-band position (figure 3b). the combina- tion of these techniques, followed by the application of a digital filter, reduces the noise in-band sufficiently to ensure good dynamic performance from the part (figure 3c). band of interest f s /2 dmclk/16 a. f s /2 dmclk/16 noise-shaping b. band of interest f s /2 dmclk/16 digital filter band of interest c. figure 3. sigma-delta noise reduction figure 4 shows the various stages of filtering that are employed in a typical AD73460 application. in figure 4a we see the trans- fer function of the external analog antialias filter. even though it is a single rc pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (dmclk /8) that it takes c are of any signals that could be aliased by the sampling frequency. t his also shows the major difference between the initial over- sa mpling rate and the bandwidth of interest. in figure 4b, the signal and noise-shaping responses of the sigma-delta modulator are shown. the signal response provides further rejection of any high frequency signals while the noise-shaping will push the inher- ent quantization noise to an out-of-band position. the detail of figure 4c shows the response of the digital decimation filter ( sinc-cubed response) with nulls every multiple of dmclk /256, which is the decimation filter update rate. the final detail in figure 4d shows the application of a final antialias filter in the dsp engine. this has the advantage of being implemented ac cord- ing to the user ? s requirements and available mips. the filtering in figures 4a through 4c is implemented in the ad73 460. f b = 4khz f sinit = dmclk/8 a. analog antialias filter transfer function f b = 4khz f sinit = dmclk/8 noise transfer function signal transfer function b. analog sigma-delta modulator transfer function f b = 4khz f sinter = dmclk/256 c. digital decimator transfer function f b = 4khz f sinter = dmclk/256 f sfinal = 8khz d. final filter lpf (hpf) transfer function figure 4. dc frequency responses decimation filter the digital filter used in the AD73460 carries out two important f unctions. firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator, and secondly, it deci- mates the high frequency bit stream to a lower rate 15-bit word. the antialiasing decimation filter is a sinc-cubed digital filter t hat reduces the sampling rate from dmclk/8 to dmclk/256, and increases the resolution from a single bit to 15 bits. its z transform is given as: [(1 ? z ? 32 )/(1 ? z ? 1 )] 3 . this ensures a mini- mal group delay of 25
rev. a AD73460 ?13? adc coding the adc coding scheme is in two ? s complement format (see f igure 5). the output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the final output of the adc block. in 16-bit data mode, this value is left shifted with the lsb being set to 0. for input values equal to or greater than positive full scale however, the output word is set at 0x7 fff , which has the lsb set to 1. in mixed control/data mode, the resolution is fixed at 15 bits, with the msb of the 16- bit transfer being used as a flag bit to indicate either control or data in the frame. v ref + (v ref 0.32875) v ref v ref e (v ref 0.32875) 10...00 00...00 01...11 adc code differential analog input v inn v inp v ref + (v ref 0.6575) v ref e (v ref 0.6575) 10...00 00...00 01...11 adc code single-ended analog input v inp v inn figure 5. adc transfer function voltage reference the AD73460 contains an internal band gap reference that provides a low noise, temperature-compensated reference to the adcs. the reference has a nominal value of 1.25 v and is available on the refcap pin. a buffered version of the refer ence is available on the refout pin and can be used to bias external analog circuitry if required. the reference output (refout) can be enabled by setting the ru bit (crc:6) in control register c. it is possible to overdrive the internal reference by connect ing an external reference to the refcap pin. this may be required when a different value of reference or better temperature coeffi cient is required. the current sink and source capabilities of the refcap pin must be taken into consideration when overdriving the refer- ence. when a lower value of external reference is required, it must have sufficient current sink capability to override the current source capabilities of the refcap pin. when a higher value of external reference is required, it can usually be connected directly to the refcap pin as the pin can typically only sink 0.25 ma before its value changes. figure 6 shows a plot of refcap voltage versus current. note that the negative values indicate that the external reference is sinking current to provide the required reference voltage. afe serial port (sport2) the afe section communicates with dsp via the bidirectional synchronous serial port (sport2), which interfaces to either sport0 or sport1 of the dsp section. sport2 is used to tr ansmit and receive digital data and control information. an refcap e v e4.5 1.00 current e ma e4.0 e3.5 e3.0 e2.5 e2.0 e1.5 e1.0 e0.5 0.0 0.5 1.10 1.20 1.30 1.40 1.50 figure 6. refcap voltage vs. current additional external afe can be cascaded to the internal afe (u p to a limit of seven) to provide additional input channels if required. in both transmit and receive modes, data is transferred at the serial clock (sclk2) rate with the msb being transferred first. communication between the afe section and dsp section must always be initiated by the afe section (afe is in master mode, dsp is in slave mode). this ensures that there is no collision between input data and output samples. sport2 overview s port2 is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow an additional afe to be connected in cascade to the dsp section. it has a very flexible architecture that can be configured by programming two of the internal control registers in each afe block. sport2 has three distinct modes of operat ion: control mode, data mode, and mixed control/data mode. note: as each afe has its own sport section, the register settings in each must be programmed. the registers that control sport and sample rate operation (cra and crb) must be programmed with the same values to ensure correct operation. in control mode (cra:0 = 0), the device ? s internal configura- tion can be programmed by writing to the eight internal control registers. in this mode, control information can be written to or re ad from the afe. in data mode (cra:0 = 1), any information that is sent to the afe is ignored, while the encoder section (adc) data is read from the device. in this mode, only adc data is read from the device. mixed mode (cra:0 = 1 and cra:1 = 1) allows the user to send control information and receive either control information or adc data. this is achieved by using the msb of the 16-bit frame as a flag bit. mixed mode reduces the resolution to 15 bits with the msb being used to indicate whether the information in the 16-bit frame is control information or adc data. sport2 features a single 16-bit serial register that is used for both input and output data transfers. as the input and output data must share the same register, some precautions must be observed. the primary precaution is that no information must be written to sport2 without reference to an output sample event, which is when the serial register will be overwritten with the latest adc sample word. once sport2 starts to output the latest adc word, it is safe for the dsp to write new control
rev. a AD73460 ?14? words to the afe. in certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial register ? see section on interfacing devices. the s erial clock rate (crb:2 ? 3) defines how many 16-bit words c an be written to a device before the next output sample event will happen. the sport2 block diagram, shown in figure 7, details the blocks associated with afe including the eight control registers (a ? h), external amclk to internal dmclk divider and serial clock divider. the divider rates are controlled by the setting of control register b. the afe features a master clock divider that allows users the flexibility of dividing externally available high frequency dsp clocks to generate a lower frequency master clock internally in the afe, which may be more suitable for either serial transfer or sampling rate requirements. the master clock divider has five divider options ( areset sdis sdi serialport sport serialregister sclk2 cotrol register b cotrol register c cotrol register d cotrol register e cotrol register a 2 dmclk iteral sdos sdo cotrol register cotrol register g cotrol register h sclk diider sportbd sport2sclk dmclkdmclk2dmclkdmclk dmclk cm cscsr ae sportrm tae tiae tcracrb sport2t i aecracrb tcrccrh r pcadc pgai crccrhae c sclk2 mcd tae amclk12 dmclk t crb tiii t tiii dmclkirds mcd2 mcd1 mcd0 dmclkr 000amclk 0 01 amclk2 0 10 amclk 0 11 amclk 1 00 amclk 101amclk 110amclk 111amclk scrd tae sclk2 dsptsclk2dmclk dmclk2dmclk dmclktdmclksclk2 t crb2 ti ti sclkrds scd1 scd0 sclk2r 00 dmclk 01 dmclk 10 dmclk2 11 dmclk drd tae ae adc dspt dmclk2 dmclk12dmclk102dmclk20t dmclk20 t crb0 1 t t drds dr1 dr0 sr 00 dmclk20 01 dmclk102 10 dmclk12 11 dmclk2
rev. a AD73460 ?15? table vi. control register map address (binary) name description type width reset setting (hex) 000 cra control register a r/ w 000 001 crb c r b r w 000 010 crc c r c r w 000 011 crd c r d r w 000 100 cre c r e r w 000 101 crf c r f r w 000 110 crg c r g r w 000 111 crh c r h r w 000 t ii c w d 1 1 1 12 11 10 210 c d r w data w p m pd m w p m b 1 read write w w b 1 11 deice address t o i b 10 register address t ad0 b 0 register data t control register a t iii c r a d b n d 0 data pgm o m 0 p 1 d m 1m mm m 0 off 1 e 2r m b p 0 slb sport lb m 0 off 1 e dc0 d c b 0 dc1 d c b 1 dc2 d c b 2 reset s r 0 off 1 i r 21 0 reset dc dc dc sb res mm dt pgm
rev. a AD73460 ?16? table ix. control register b description 76543210 cee mcd2 mcd1 mcd0 scd1 scd0 dr1 dr0 bit name description 0 dr0 decimation rate (bit 0) 1 dr1 decimation rate (bit 1) 2 scd0 serial clock divider (bit 0) 3 scd1 serial clock divider (bit 1) 4m cd0 master clock divider (bit 0) 5m cd1 master clock divider (bit 1) 6m cd2 master clock divider (bit 2) 7 cee control echo enable (0 = off; 1 = enabled) table x. control register c description 76543210 res ru puref res res res res gpu bit name description 0 gpu global power-up device (0 = power down; 1 = power up) 1r eserved must be programmed to zero (0) 2r eserved must be programmed to zero (0) 3r eserved must be programmed to zero (0) 4r eserved must be programmed to zero (0) 5 puref ref power (0 = power down; 1 = power up) 6r ur e fout use (0 = disable refout; 1 = en able refout) 7r eserved must be programmed to zero (0) table xi. control register d description 76543210 pui2 i2gs2 i2gs1 i2gs0 pui1 i1gs2 i1gs1 i1gs0 bit name description 0 i1gs0 adc1: input gain select (bit 0) 1 i1gs1 adc1: input gain select (bit 1) 2 i1gs2 adc1: input gain select (bit 2) 3 pui1 power control (adc1): 1 = on, 0 = off 4 i2gs0 adc2: input gain select (bit 0) 5 i2gs1 adc2: input gain select (bit 1) 6 i2gs2 adc2: input gain select (bit 2) 7 pui2 power control (adc2): 1 = on, 0 = off control register b control register c control register d
rev. a AD73460 ?17? table xii. control register e description 76543210 pui4 i4gs2 i4gs1 i4gs0 pui3 i3gs2 i3gs1 i3gs0 bit name description 0 i3gs0 adc3: input gain select (bit 0) 1 i3gs1 adc3: input gain select (bit 1) 2 i3gs2 adc3: input gain select (bit 2) 3 pui3 power control (adc3): 1 = on, 0 = off 4 i4gs0 adc4: input gain select (bit 0) 5 i4gs1 adc4: input gain select (bit 1) 6 i4gs2 adc4: input gain select (bit 2) 7 pui4 power control (adc4): 1 = on, 0 = off table xiii. control register f description 76543210 pui6 i6gs2 i6gs1 i6gs0 pui5 i5gs2 i5gs1 i5gs0 bit name description 0 i5gs0 adc5: input gain select (bit 0) 1 i5gs1 adc5: input gain select (bit 1) 2 i5gs2 adc5: input gain select (bit 2) 3 pui5 power control (adc5): 1 = on, 0 = off 4 i6gs0 adc6: input gain select (bit 0) 5 i6gs1 adc6: input gain select (bit 1) 6 i6gs2 adc6: input gain select (bit 2) 7 pui6 power control (adc6): 1 = on, 0 = off table xiv. control register g description 76543210 seen rmod ch6 ch5 ch4 ch3 ch2 ch1 bit name description 0 ch1 channel 1 select 1 ch2 channel 2 select 2 ch3 channel 3 select 3 ch4 channel 4 select 4 ch5 channel 5 select 5 ch6 channel 6 select 6 rmod reset analog modulator 7 seen enable single-ended input mode control register e control register f control register g
rev. a AD73460 ?18? operation resetting the afe the areset a afe sclk2 dmclk dmclk20 a afe areset reset cra c r a b dmclk o data pgm cra0 0 c m t f sdofs 20 0 amclk areset t c m p m t afe crc t p m dsp i t u crc t crc0 r t i crc crd crf o m t afe t c p m d m m c d m t p m pd m i 1 t dsp sport 1 control mode in control mode, cra:0 = 0, the user writes to the control registers to set up the device for desired operation ? sport2 operation, cascade length, power management, input/output gain, an d so on . in this mode, the 16-bit information packet sent to the device by the dsp is interpreted as a control word whose format is shown in table vii. in this mode, the user must address the device to be programmed using the address field of the control word. this field is read by the device and if it is zero (000 bin), the device recognizes the word as being addressed to it. if the address field is not zero, it is then decremented and the control word is passed out of the device ? either to the next device in a cascade or back to the dsp. this 3-bit address format allows th e us er to uni qu ely address any device in a cascade. if the afe is used in a standalone configuration connected to the dsp, the device address corresponds to 0. following reset, when the se pin is enabled, the afe responds by raising the sdofs pin to indicate that an output sample event has occurred. control words can be written to the device to coincide with the data being sent out of sport2, as shown in f igure 9 (directly coupled), or they can lag the output words by a time interval that should not exceed the sample interval (indirectly coupled). refer to the digital interface section for more information. after reset, output frame sync pulses will occur at a slower default sample rate, which is dmclk/2048, u ntil control register b is programmed, after which the sdofs will be pulsed at the selected rate. while the afe is in control mode, the data output by the device is random and should not be interpreted as adc data. table xv. control register h description 76543210 inv tme ch6 ch5 ch4 ch3 ch2 ch1 bit name description 0 ch1 channel 1 select 1 ch2 channel 2 select 2 ch3 channel 3 select 3 ch4 channel 4 select 4 ch5 channel 5 select 5 ch6 channel 6 select 6 tme test mode enable 7i nv enable invert channel mode control register h
rev. a AD73460 ?19? data mode once the device has been configured by programming the cor- rect settings to the various control registers, the device may exit program mode and enter data mode. this is done by program- ming the data/ pgm cra0 1 mm cra1 0 o d m w d m mixed program/data mode this mode allows the user to send control words to the device while receiving adc words. this permits adaptive control of the device whereby control of the input gains can be affected by reprogramming the control registers. the standard data frame remains 16 bits, but now the msb is used as a flag bit to indicate that the remaining 15 bits of the frame represent control information. mixed mode is enabled by setting the mm bit (cra:1) to 1 and the data/ pgm cra0 1 i n adc msb c s t adc ad0 pui crd crf i ad0 m dc m i d m ad0 p m ad0 i adc c 1 interfacing t afe sport sport2 sport0 sport1 dsp b 1 t sclk afe dsp t r t f dsp t t r r ad0 s di sdifs sdo sdofs t w dsp r dsp t dsp t dsp afe t t f dsp t r afe sdi sdo dsp t r ad0 sdifs sdofs i afe afe t dsp t r afe sdofs t d m n afe afe t tfs01 dt01 sclk01 dr01 rfs01 dsp section afe section sdifs sdi sclk sdo sofs f i c n s lb c tfs01 dt01 sclk01 dr01 rfs01 dsp section afe section sdifs sdi sclk sdo sdofs f d c f s lb c c o t ad0 afe sport0 sp ort1 t sport2 t a t t t f 16 11617 f device count sclk s ?+
rev. a AD73460 ?20? in cascade mode, both devices must know the number of devices in t he cascade to be able to output data at the correct time. control register a contains a 3-bit field (dc0 ? 2) that is pro- grammed by the dsp during the programming phase. the d efault condition is that the field contains 000b, which is equiva- le nt to a single device in cascade (see table xvi). however, for cascade operation this field must contain a binary value that is o ne less than the number of devices in the cascade. with a cascade, each device takes a turn to send an adc result to the dsp. for example, in a cascade of two devices the data will be output as device 2-channel 1, device 1-channel 1, device 2-channel 2, device 1-channel 2 and so on. when the first device in the cascade has transmitted its channel data, there is an additional sclk period during which the last device asserts its sdofs as it begins its transmission of the next channel. this will not cause a problem for most dsps as they count clock edges after a frame sync and therefore the extra bit will be ignored. when two devices are connected in cascade, there are also restrictions concerning which adc channels can be powered u p. in all cases the cascaded devices must all have the same channels powered up (i.e., for a cascade requiring channels 1 and 2 on device 1 and channel 5 on device 2, c hannels 1, 2, and 5 must be powered up on both devices to ensure correct operation). table xvi. device count settings dc2 dc1 dc0 cascade length 00 01 00 12 01 03 01 14 10 05 10 16 11 07 11 18 functional description
rev. a AD73460 ?21? (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? ? ? ? ? reset t e t ad0 1 t sport1 i a a 1 tcount n pro- cessor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the AD73460 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the AD73460 sports. for additional information on serial ports, refer to the adsp- 2100 family user? manual , third edition. ? ? ? ? ? ? ? ? reset f i s p f d m i p t ad0 f m m bdma io h m idma t m c reset s f m m p h m p
rev. a AD73460 ?2 full memory mode pins (mode c = 0) pin # of input/ name(s) pins output function a13:0 14 o address output pins for program, data, byte, and i/o spaces d23:0 24 i/o d ata i/o pins for program, data, byte, and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) pin # of input/ name(s) pins output function iad15:0 16 i/o idma port address/databus a0 1 o address pin for external i/o, pro- gram, data, or byte access d23:8 16 i/o data i/o pins for program, data byte, and i/o spaces iwr 1i idma write enable ird 1i idma read enable ial 1 i idma address latch pin is 1i idma select iack 1o id ma port acknowledge configur- able in m ode d; open source in h ost mode, external peripheral addresses can be decoded using the a0, cms , pms , dms , and ioms signals terminating unused pins the following table shows the recommendations for terminating unused pins. pin terminations i/o hi-z * pin three- reset caused unused name state (z) state by configuration xtal i i float clkout o o float a13:1 or o (z) hi-z br , ebr float iad12:0 i/o (z) hi-z is float a0 o (z) hi-z br , ebr float d23:8 i/o (z) hi-z br , ebr float d7 or i/o (z) hi-z br , ebr float iwr ii high (inactive) d6 or i/o (z) hi-z br , ebr float ird ii br , ebr high (inactive) d5 or i/o (z) hi-z float ial i i low (inactive) d4 or i/o (z) hi-z br , ebr float is ii high (inactive) d3 or i/o (z) hi-z br , ebr float iack float d2:0 or i/o (z) hi-z br , ebr float iad15:13 i/o (z) hi-z is float pms o (z) o br , ebr float dms o (z) o br , ebr float bms o (z) o br , ebr float ioms o (z) o br , ebr float cms o (z) o br , ebr float rd o (z) o br , ebr float pin terminations (continued) i/o hi-z * pin three- reset caused unused name state (z) state by configuration wr o (z) o br , ebr float br ii high (inactive) bg o (z) o ee float bgh oo float irq2 / pf7 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql1 / pf6 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql0 / pf5 i/o (z) i input = high (inactive) or program as output, set to 1, let float irqe / pf4 i/o (z) i input = high (inactive) or program as output, set to 1, let float sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low tfs0 i/o o high or low dt0 o o float sclk1 i/o i input = high or low, output = float rfs1/ irq0 i/o i high or low dr1/ fl1 ii high or low tfs1/ irq1 i/o o high or low dt1/fo o o float ee i i ebr ii ebg oo ereset ii ems oo eint ii eclk i i elin i i elout oo notes * hi-z = high impedance. 1. if the clkout pin is not used, turn it off. 2. if the interrupt/programmable flag pins are not used, there are two options: option 1: when these pins are configured as inputs at reset and function as interrupts and input flag pins, pull the pins high (inactive). option 2: program the unused pins as outputs, set them to 1, and let them float. 3. all bidirectional pins have three-stated outputs. when the pin is configured as an output, the output is hi-z (high impedance) when inactive. 4. clkin, reset, and pf3:0 are not included in the table because these pins must be used.
rev. a AD73460 ?23? interrupts the interrupt controller allows the processor to respond to the 11 possible interrupts and reset t ad0 irq2 irql0 irql1 irqe i sport1 irq0 irq1 flagin flagout t ad0 dma t t irq2 irq0 irq1 irql0 irql1 irqe t t ii t ii i p i a i s i a h reset pu pucr 1 0000 highest priority ) power-down (nonmaskable) 002c irq2 000 irql1 000 irql0 000c sport0 t 0010 sport0 r 001 irqe 001 bdma i 001c sport1 t irq1 0020 sport1 r irq0 002 t 002 lowest priority ) interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. inter rupts can be masked or unmasked with the imask register. indi vidual interrupt requests are logically anded with the bits in imask; the highest priority unmasked int errupt is then selected. the power-down interrupt is nonmaskable. the AD73460 masks all interrupts for one instruction cycle f ollowing the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, icntl, controls interrupt nesting and defines the irq0 irq1 irq2 t irqe t irql0 irql1 t ifc o t 12 t imask d dma ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the AD73460 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? ? ? adsp-2100 family user? manual , third edition, ? system interface ? chapter, for detailed information about the power-d own feature. ? ? ? ? pwd i t ? ? reset ? idle instruction on the AD73460 slows the processor ? s internal clock signal, further reducing power consumption. the reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is idle (n); where n = 16, 32, 64, or 128. this instruction keeps the proces- sor fully functional, but operating at the slower clock rate. while it is in this state, the processor ? s other internal clock signals, such as sclk, clkout, and timer clock, are reduced by the same ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction.
rev. a AD73460 ?4 when the idle (n) instruction is used, it effectively slows down the processor s internal clock and thus its response time to in coming interrupts. the one-cycle response time of the stan- dard idle state is increased by n , the clock divisor. when an enabled interrupt is rec eived, the AD73460 will remain in the idle st ate for up to a maximum of n processor cycles ( n = 16, 32, 64, or 128) before resuming normal operation. when the idle (n) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processor s reduced internal clock rate. under these conditions, interrupts must not be generated at a rate faster than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 11 shows a typical basic system configuration with the a d73460, two serial devices, a byte-wide eprom, and optional external program and data overlay memories (mode selectable). programmable wait state generation allows the pro- cessor to easily connect to slow peripheral devices. the AD73460 also provides four external interrupts and two serial ports or six external interrupts and one serial port. host memory mode allows access to the full external databus, but limits addressing to a single address bit (a0). additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals. clock signals the AD73460 can be clocked by either a crystal or a ttl compatible clock signal. the clkin input cannot be halted, changed during operation, or operated below the specified frequency during normal operation. th e on ly ex cep ti on is wh ile the processor is in the power-down state. for additional information, refer to chapter 9, adsp- 2100 family user? manual, third edition , for detailed information on this power-down feature. if an external clock is used, it should be a ttl compatible signal running at half the instruction rate. the signal is con nected to the processor s clkin input. when an external clock is used, the xtal input must be left unconnected. the AD73460 uses an input clock with a frequency equal to half the instruction rate; a 26.00 mhz input clock yields a 19 ns processor cycle (which is equivalent to 52 mhz). normally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the AD73460 includes an on-chip oscillator circuit, an e xternal crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors con nected as s hown in figure 12. capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. a clock output (clkout) signal is generated by the processor at the processor s cycle rate. this can be enabled and disabled by the clk0dis bit in the sport0 autobuffer control register. sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 a0-a21 data cs byte memory i/o space (peripherals) cs data addr data addr 2048 locations overlay memory two 8k pm segments two 8k dm segments a 13? d 23? a 10? d 15? d 23?6 a 13? 14 24 fl0? pf3 clkin xtal addr13? data23? bms ioms pms dms cms br bg bgh pwd pwdack AD73460 system interface or controller 16 1 16 fl0? pf3 clkin xtal a0 data23? bms ioms AD73460 irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf1 mode a/pf0 host memory mode irq2 /pf7 irqe /pf4 irql0 /pf5 irql1 /pf6 mode c/pf2 mode b/pf1 mode a/pf0 full memory mode wr rd wr rd 1/2x clock or crystal afe * section or serial device afe * section or serial device d 23? 1/2x clock or crystal sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 afe * section or serial device afe * section or serial device pms dms cms br bg bgh pwd pwdack idma port ird /d6 iwr /d7 is /d4 ial/d5 iack /d3 iad15? * afe section can be connected to either sport0 or sport1 figure 11. basic system configuration clkin xtal clkout figure 12. external crystal connections
rev. a AD73460 ?25? reset t reset ad0 t reset reset i reset t dd pll a 2000 clkin pll d reset o reset rsp t reset rc reset s t mstat w reset t 00000 modes of operation t iii ad0 s m m m m ad0 m c t dsp pf2 t m c p c m c t pf2 dsp 100 ? reset 2 w m c 0 f m w m c 1 h m m w m b 0 a b w m b 1 a b w m a 0 bdma w m a 1 idma c u
rev. a AD73460 ?26? program memory (host mode) allows access to all internal me mory. external overlay access is limited by a single external address line (a0). external program execution is not available in host mode due to a rest ricted databus that is only 16 bits w ide. table xix. pmovlay bits pmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external 0 13 lsbs of address overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of address overlay 2 between 0x2000 and 0x3fff accessible when pmovlay = 2 0x2000e 0x3fff 2 external memory accessible when pmovlay = 1 0x2000e 0x3fff 2 always accessible at address 0x0000 e 0x1fff accessible when pmovlay = 0 3 pm (mode b = 0) internal memory 0x2000e 0x3fff 8k internal pmovlay = 0 3 or 8k external pmovlay = 1 or 2 0x3fff 0x2000 0x1fff 8k internal 0x0000 program memory mode b = 0 address 8k internal pmovlay = 0 3 8k external program memory mode b = 1 address 0x3fff 0x2000 0x1fff 0x0000 accessible when pmovlay = 0 internal memory external memory 0x2000e 0x3fff 0x0000e 0x1fff 2 pm (mode b = 1) 1 reserved accessible when pmovlay = 0 3 reserved notes 1 when mode b = 1, pmovlay must be set to 0 2 see table iii for pmovlay bits 3 not accessible on ad73422-40 figure 13. program memory map data memory data memory (full memory mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. the AD73460-80 has 16k words on data memory ram on-chip (the AD73460-40 has 8k words on data memory ram on-chip), consisting of 16,352 user-accessible locations in the case of the AD73460-80 (8,160 user-accessible l ocations in the case of the AD73460-40) and 32 memory-m apped registers. support also exists for up to two 8k external memory overlay spaces through the external databus. all internal accesses com plete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. accessible when dmovlay = 2 accessible when dmovlay = 1 always accessible at address 0x2000 e 0x3fff accessible when dmovlay = 0 internal memory external memory 0x0000e 0x1fff 0x0000e 0x1fff 0x0000e 0x1fff data memory 32 memory mapped registers 0x3fff 0x2000 0x1fff internal 8160 words 0x0000 data memory address 8k internal dmovlay = 0 or external 8k dmovlay = 1, 2 0x3fe0 0x3fdf figure 14. data memory map data memory (host mode) allows ac cess to all inte rnal memory. external overlay access is limited by a single external address line (a0). the dmovlay bits are defined in table xx. table xx. dmovlay bits dmovlay memory a13 a12:0 0 internal not applicable not applicable 1 external 0 13 lsbs of address overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of address overlay 2 between 0x2000 and 0x3fff i/o space (full memory mode) the AD73460 supports an additional external memory space called i/o space. this space is designed to support simple con nections to peripherals (such as data converters and external registers) or to bus interface asic data registers. i/o space supports 2048 locations of 16-bit-wide data. the lower 11 bits of the external address bus are used; the upper three bits are undefined. two instructions were added to the core adsp-2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated 3-bit wait state registers, iowait0-3, that specify up to seven wait states to be automati cally generated for each of four regions. the wait states act on ad dress ranges as shown in table xxi. table xxi. wait states address range wait state register 0x000 ? 0x1ff iowait0 0x200 ? 0x3ff iowait1 0x400 ? 0x5ff iowait2 0x600 ? 0x7ff iowait3 composite memory select ( cms td t cms pms dms bms ioms e cmssel cms f 2k pms dms cmssel cms dms pms
rev. a AD73460 ?27? the cms a 1 cms a 1 bms b m s bms d td bdm cms bdma bms t bms b s c r 1 t s c r f 1 sstem control register pwait program memor wait states 0000010000000111 1 1 1 12 11 10 210 dm 0fff bms enable 0 enabled 1 disabled sport0 enable 1 enabled 0 disabled sport1 enable 1 enabled 0 disabled sport1 configure 1 serial port 0 f i fo irq0 irq1 sclk f 1 s c r b m t b bdma t bdma c r f 1 t 2 1k
rev. a AD73460 ?28? dsp with only one dsp cycle per word overhead. the idma port cannot be used, however, to write to the dsp ? s memory- mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer. 2. host checks iack dsp h is ial dma idmaa pmdm ola dsp idma iad1 0 h is ird iwr dsp pm dm h iack dsp idma h idma t idma 1 2 t idma ad0 t dsp idma a t idma p t idma a l w 1 1 t dm pm t idmaa o ad0 a is ird iwr ad0 i t o t idmaa dsp dma a idma is ial ad0 iad0 1 idma c r i iad1 0 idma t idmaa dm 0fe0 n idmaa t id ma ola dm 0fe s f 1 idma dma idma control u undefined at reset dm0fe0 idmaa address idmad destination memor tpe 0 pm 1 dm uuuuuuuuuuuuuuu 1 1 1 12 11 10 210 f 1 idma cola r b l b t ad0 t m a b c w bdma ad0 bdma t bdma bdma bdir bmpage biad bead 0 btpe 0 2 bwcount 2 t 2 t 2 bdma t bcr 1 2 e 0 t adsp2100 f d s r 02 bdma t idle bdma f bdma h m ad0 t a0 idma p b t ad0 i dma i m c 1 m b 0 m a 1 ad0 idma idma p 0 b r b g f m m t ad0 w br i ad0 br ? pms dms bms cms ioms rd wr ? bg ?
rev. a AD73460 ?9 if the AD73460 is performing an external memory access when the external device asserts the br signal, it will not three-state the memory interfaces nor assert the bg signal until the proces- sor cycle after the access completes. the instruction does not n eed to be completed when the bus is granted. if a single in struction requires two external memory accesses, the bus will be granted between the two accesses. when the br signal is released, the processor releases the bg signal, re-enables the output drivers, and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the AD73460 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. the other device can release the bus by deasserting the bus request. once the bus is released, the AD73460 deasserts bg and bgh and executes the external memory access. flag i/o pins the AD73460 has eight general-purpose programmable input/ output flag pins. they are controlled by two memory-mapped registers. the pftype register determines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin config- ured as an input is synchronized to the AD73460 s clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, the AD73460 has five f ixed-mode flags, flag_in, flag_out, fl0, fl1, and fl2. fl0 C fl2 are dedicated output flags. flag_in and flag_out are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2, and pf3 are also used for device configuration during reset. instruction set description t he AD73460 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. the assembly language, which takes full advantage of the processor s unique architecture, offers the following benefits: ? the algebraic syntax eliminates the need to remember cryp- tic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly language and is completely source and object code compatible with other family members. programs may need to be reloc ated to utilize on-chip memory and conform to the AD73460 s inter rupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, c all, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruc- tion cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice compatible system the AD73460 has on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin con- nector to accept the ez-ice s in-circuit probe, a 14-pin plug. see the adsp-2100 family ez-tools data sheet for complete information on ice products. issuing the chip reset command during emulation causes the dsp to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emulator user in terface. if you are using a passive method of maintaining mode information (as discussed in setting memory modes) then it does not matter that the mode information is latched by an emulator reset. however, if you are using the reset pin as a method of setting the value of the mode pins, then you have to take into consideration the effects of an emulator reset. one method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in figure 18. this circuit forces the value located on the mode a pin to logic high; regardless if it latched via the reset or ereset pin. reset ereset AD73460 mode a /pfo programmable i/o 1k figure 18. mode a pin/ez-ice circuit the ice-port interface consists of the following AD73460 pins: ebr ebg ereset ems eint eclk elin elout ee these AD73460 pins must be connected only to the ez-ice connector in the target system. these pins have no function e xcept during emulation, and do not require pull-up or pull-down r esistors. the traces for these signals between the a d73460 and the connector must be kept as short as possible, no longer than three inches. the following pins are also used by the ez-ice: br bg reset gnd
rev. a AD73460 ?0 th e ez-ice uses the ee (emulator enable) signal to take con trol of the AD73460 in the target system. this causes the processor to use its ereset , ebr , and ebg pins instead of t he reset , br , and bg pins. the bg output is thre e-stated. these signals do not need to be jumper-isolated in your system. the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the ribbon cable is 10 inches in length with one end fixed to the ez-ice. the female plug is plugged o nto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 19. this connector must be added to the target board design in order to use the ez-ice. be sure to allow enough room in the system to fit the ez-ice probe onto the 14-pin connector. 12 34 56 78 9 10 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr el out ee eint elin eclk ems ereset figure 19. target board connector for ez-ice the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tion ? pin 7 must be removed from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spac- ing should be 0.1 0.1 inches. the pin strip header must have at least 0.15-inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mc kenzie, and samtec. target memory interface f or the target system to be compatible with the ez-ice emu- lator, it must comply with the memory interface guidelines listed below. pm, dm, bm, iom, and cm design program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom), and composite memory (cm) external interfaces to comply with worst-case device timing requirements and switching characteristics as specified in the dsp ? s data sheet. the performance of the ez-ice may approach published worst-case specification for some memory access timing requirements and switching characteristics. note: if the target does not meet the worst-case chip specifica- tion for memory access parameters, user may not be able to emulate the circuitry at the desired clkin frequency. depending on the severity of the specification violation, it may create a problem manufacturing the system as dsp components statistically vary in switching characteristic and timing require- ments within published limits. restriction: all memory strobe signals on the AD73460 ( rd , wr , pms , dms , bms , cms , and ioms ) used in the target system must have 10 k pull-up resistors connected when the e z-ice is being used. the pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed at the user ? s option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals changes. design the system to be compatible with the following system interface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay b etween the target circuitry and the dsp on the reset signal. ? e z-ice emulation introduces an 8 ns propagation delay be tween the target circuitry and the dsp on the br signal. ? ez-ice emulation ignores reset and br when single- stepping. ? ez-ice emulation ignores reset and br when in emulator space (dsp halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the dsp ? s external memory bus only if bus grant ( bg ) is asserted by the ez-ice board ? s dsp. analog front end (afe) interfacing the afe section of the AD73460 features six input channels, each with 16-bit linear resolution. connectivity to the afe section from the dsp is uncommitted, thus allowing the user the flexibility of connecting in the mode or configuration of their choice. this section will detail several configurations ? with no extra afe channels configured and with an extra afe section configured (using an external ad73360 afe). dsp sport to afe interfacing t he sc lk , s do, sdofs, sdi, and sdifs must be connected to the sclk, dr, rfs, dt, and tfs pins of the dsp respec- tively. the se pin may be controlled from a parallel output pin or flag pin such as fl0 ? 2 or, where sport power-down is not required, it can be permanently strapped high using a suitable pull-up resistor. for consistent performance, the se pin should be synchronized to the rising edge of the amclk using a cir- cuit similar to that of figure 23. the areset pin may be connected to the system hardware reset structure or it may also be controlled using a dedicated control line. in the event of tying it to the global system reset, it is necessary to operate the device in mixed mode, which allows a software reset. otherwise there is no convenient way of resetting the device.
rev. a AD73460 ?31? tfs dt sclk dr rfs dsp section afe section sdifs sdi sclk sdo sdofs fl0 fl1 areset se 20 dspad0aec cascadeoperatio w ad0 ad0ae 22i se areset a d amclk f 21 12 hc clk dq dsp control to se amclk se signal snchronied to amclk 12 hc clk dq dsp control to areset amclk areset signal synchronized to amclk figure 21. se and areset s t t t 16 11617 f device count sclk s ?+ areset amclk f 21 t sclk dsp sclk sclk tfs dt dr rfs afe sdifs sdi sclk sdo sdofs sclk deice 1 amclk se areset additioal ad0 ae hc q0 q1 d1 d0 l0 l1 dsp sectio clk sdis sdi sclk sdo sdos deice2 mclk se reset ad0 22cad0c ad0 iae
rev. a ?32? c01040?0?10/02(a) printed in u.s.a. AD73460 figure 24 details the dc-coupled input circuits for single-ended operation respectively. vin vinpx vinnx refout refcap voltage reference 100 0.047 f 0.1 f figure 24. example circuit for single-ended input (dc coupling) digital interface as there are a number of variations of sample rate and clock speeds that can be used with the AD73460 in a particular application, it is important to select the best combination to achieve the desired performance. high speed serial clocks will read the data from the AD73460 in a shorter time, giving more time for pro cessing at the expense of injecting some digital noise into the circuit. digital noise can also be reduced by connecting resistors (t yp <50 ?

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