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utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? features pc100 compliant functionality and performance. jedec standard 3.3 v 10% power supply. lvttl compatible inputs and outputs. all inputs are sampled on positive edge of system clock. dual banks for hidden row access/precharge. internal pipeline operation, column addresses can be changed every cycle. dqm for masking. mrs cycle with address key programmability for: - cas latency ( 2 , 3 ) - burst length ( 1 , 2 , 4 , 8 or full page) - burst type ( sequential & interleave ) auto precharge and auto refresh modes. self refresh mode. 64ms , 4096 cycle refresh ( 15.6 us/row ) 50?pin 400 mil plastic tsop (type ii) package. general description the UT52L1616 is a high-speed cmos dynamic random-a ccess memory containing 16,777,216 bits. it is internally configured as a dual memory array (512k x 16) with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the two internal banks is organized with 2,048 rows and with either 256 columns by 16 bits. read and write accesses to the sdram ar e burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an activate command which will then be followed by a read or write command. the address bits registered coincident with the activate command are used to sele ct the bank and row to be accessed (a11 selects the bank, a0-10 selects the row). the address bits coincident with the read or write command are used to select the starting column location for the burst access. the UT52L1616 uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2n rule of prefet ch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high speed, fully random a ccess. precharging one bank while accessing the alternate bank will hide the precharge cycles and provides s eamless high-speed random a ccess operation. the UT52L1616 is designed to comply with the intel pc ( 66mhz) and intel pc/100 ( 100mhz) specifications. the UT52L1616 is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided along with a power saving power-down m ode. all inputs and outputs are lvttl-compatible. sdrams offer substantial advances in dram operating performance, includi ng the ability to synchronously burst data at a high data rate with automat ic column-address generation, the abilit y to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. product family part no. max freq. cl tac organization interface package UT52L1616mc-7 143mhz 3 5.5ns UT52L1616mc-8 125mhz 3 6ns UT52L1616mc-10 100mhz 3 7ns 2 banks512k bits16 lvttl 400 mil 50pin tsop ii
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? pin assignment UT52L1616 50 pin tsop ii package v cc dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cas ce we ras dqml a10 a11 a0 a1 a2 a3 v cc v ssq v ccq v ssq v ccq 10 11 12 13 14 15 16 17 18 19 20 25 24 23 22 21 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 50 49 48 47 46 45 44 43 42 41 vss dq15 dq14 dq13 dq12 dqmu dq11 dq10 dq9 dq8 nc clk cke nc a7 a6 a5 a4 vss a9 a8 v ssq v ccq v ssq v ccq pin description pin name function a0 to a11 address input row address a0 to a10 column address a0 to a7 bank select address a11 dq0 to dq15 data-input/output ce chip select cas column address strobe command ras row address strobe command we write enable command dqmu dqml upper byte input/output mask lower byte input/output mask clk clock input cke clock enable v cc power for internal circuit vss ground for internal circuit vccq power for i/o circuit vssq ground for i/o circuit nc no connection
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? function block diagram block diagram vcc vss vpp vbb reg clk clock buffer cke ce ras cas we dqmu dqml a11 a10 bank 0 row control circuit a [0 : 9] cell array bank 0 512k x 16 bit row decoder column decoder 16 pairs cell array bank 1 512k x 16 bit row decoder sense amp & write in circuit 16 pairs input & output buffer bank 1 row control circuit 16 dq [0,15] burst counter address buffer refresh counter row address command buffer control circuit column address & pre - decoder sense amp & write in circuit
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? pin functions clk (input pin): clk is the master clock input to this pin. the other input signals are referred at clk rising edge. ce (input pin ): when ce is low, the command input cycle becomes valid. when ce is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. ras , cas , and we (input pins): although these pin names are the sa me as those of conventional drams, they function in a different way. these pins define operation commands (r ead, write, etc.) depending on the combination of their voltage levels. for det ails, refer to the command operation section. a0 to a10 (input pins): row address (ax0 to ax10) is determined by a0 to a10 level at the bank active command cycle clk rising edge. column address (ay0 to ay7) is determined by a0 to a7 level at the read or write command cycle clk rising edge. and this column addr ess becomes burst access st art address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, both banks are precharged. but when a10 = low at the precharge command cy cle, only the bank that is sele cted by a11 (bs) is precharged. a11 (input pin): a11 is a bank select signal (bs). the memory array of the UT52L1616 is divided into bank 0 and bank 1, both which contain 512 k x 16 bits. if a11 is low, bank 0 is select ed, and if a11 is high, bank 1 is selected. cke (input pin): this pin determines whether or not the next clk is valid. if c ke is high, the next clk rising edge is valid. if cke is low, the next clk rising edge is invalid. this pin is used for power down and clock suspend modes. dqmu/dqml (input pins): dqmu controls upper byte and dqml cont rols lower byte input/output buffers. read operation: if dqmu/dqml is high, the output buffer becom es high-z. if the dqmu/dqml is low, the output buffer becomes low-z. write operation: if dqmu/dqml is high, the previous data is held (the new data is not written).if dqmu/dqml is low, the data is written. dq0 to dq15 (i/o pins): data is input to and output fr om these pins. these pins ar e the same as those of a conventional dram. vcc and vccq (power supply pins): 3.3v is applied. (vcc is for the in ternal circuit and vccq is for the output buffer.) vss and vssq (power supply pins): ground is connected. (vss is for the in ternal circuit and vssq is for the output buffer.)
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? command operation command truth table the synchronous dram recognizes the fo llowing commands specified by the ce , cas , ras , we and address pins. function symbol cke n-1 cke n ce ras cas we a11 a10 a0 to a9 ignore command desl h x h x x x x x x mode register set mrs h x l l l l v v v refresh ref/self h v l l l h x x x precharge select bank pre h x l l h l v l x precharge all bank pall h x l l h l x h x bank active act h x l l h h v v v column address and write command writ h x l h l l v l v write with auto-precharge writa h x l h l l v h v column address and read command read h x l h l h v l v read with auto-precharge reada h x l h l h v h v burst stop in full page bst h x l h h l x x x no operation nop h x l h h h x x x note: h: v ih . l: v il . x: v ih or v il . v: valid address input. ignore command [desl]: when this command is set ( ce is high), the synchronous dram ignore command input at the clock. however, the internal status is held. mode register set [mrs]: synchronous dram has a mode register t hat defines how it operates. the mode register is specified by the address pins (a0 to a11) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register ar e undefined, execute the mode register set command to set up the mode register. refresh [ref/self]: this command starts the refresh operation. t here are two types of refresh operation, the one is auto refresh, and the other is self refresh. for details, refer to the cke truth table section. precharge selected bank [pre]: this command starts precharge operati on for the bank selected by a11. if a11 is low, bank 0 is selected. if a11 is high, bank 1 is selected. precharge all banks [pall]: this command starts a prec harge operation for all banks. row address strobe and bank activate [act]: this command activates the bank that is selected by a11 (bs) and determines the row address (ax0 to ax10). when a11 is low, bank 0 is acti vated. when a11 is high, bank 1 is activated. column address strobe and write command [writ]: this command starts a wr ite operation. when the burst write mode is select ed, the column address (ay0 to ay7) and the bank select addre ss (a11) become the burst write start address. when the single write mode is sele cted, data is only written to the location specified by the column address (ay0 to ay7) and the bank select address (a11). write with auto precharge [writ a]: this command automatically perfo rms a precharge operation after a burst write with a lengt h of 1, 2, 4 or 8. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is det ermined by the column address (ay0 to ay7) and the bank select address (bs). after the read operation, t he output buffer becomes high-z.
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? read with auto precharge [read a]: this command automatically perfo rms a precharge operation after a burst read with a burst l ength of 1, 2, 4 or 8. burst stop command [bst]: this command stops the cu rrent burst operation. no operation [nop]: this command is not an execution command. ho wever, the internal operations continue. dqm truth table cke cke function symbol n - 1 n dqmu dqml upper byte write enable/output enable enbu h x l x lower byte write enable/output enable enbl h x x l upper byte write inhibit/output disable masku h x h x lower byte write inhibit/output disable maskl h x x h note: h: v ih . l: v il . x: v ih or v il . the UT52L1616 can mask input/output dat a by means of dqmu and dqml . dqmu masks the upper byte and dqml masks the lower byte. during reading, the output buffer is set to low-z by setting dqmu/dqml to low, enabling data output. on the other hand, when dqmu/dqml is set to high, the out put buffer becomes high-z, disabling data output. during writing, data is written by setting dqmu/dqml to low. when dqmu/dqml is set to high, the previous data is held (the new data is not wri tten). desired data can be masked during burst read or burst write by setting dqmu/dqml. for details, refer to the dqm cont rol section of the UT52L1616 operating instructions.
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? cke truth table current state function cke n-1 cke n ce ras cas we address active clock suspend mode entry h l h x x x x any clock suspend l l x x x x x l h l h h h x clock suspend clock suspend mode exit l h h x x x x idle auto-refresh command ref h h l l l h x idle self-refresh entry self h l l l l h x h l l h h h x idle power down entry h l h x x x x l h l h h h x self refresh self refresh exit selfx l h h x x x x l h l h h h x power down power down exit l h h x x x x note: h: v ih . l: v il . x: v ih or v il . clock suspend mode entry: the synchronous dram enters clock su spend mode from active mode by setting cke to low. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the nex t clock by internally maintaining the bank active status. read suspend and read a suspend: the data being output is held ( and continues to be output). write suspend and writ a suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend mode exit: the synchronous dram exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not sele cted, and completed precharge operation. auto refresh command [ref ]: when this command is input from t he idle state, the synchronous dram starts auto-refresh operation, (the auto-refresh is the same as the re f refresh of conventional drams.) during the auto-refresh operation, refres h address and bank select address are generated inside the synchronous dram. for every auto-refresh cycle, the in ternal address counter is updated. acco rdingly, 2048 times are required to refresh the entire memory. before exec uting the auto-refresh command, all t he banks must be in the idle state. in addition, since the precharge for all banks is autom atically performed after auto-refresh, no precharge command is required after auto refresh. self refresh entry [self]: when this command is input during the id le state, the sync hronous dram starts self refresh operation. after the execution of this command, self refresh continues while cke is low. since self refresh is performed internally and automatically , external refresh operations are unnecessary. power down mode entry : when this command is executed during t he idle state, the synchronous dram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self refresh exit: when this command is executed during self re fresh mode, the sync hronous dram can exit from self refresh mode. after exiting from self re fresh mode, the synchronous dra m enters the idle state.
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? function truth table the following table shows the operati ons that are performed when each comm and is issued in each mode of the synchronous dram. current state ce ras cas we address command operation precharge h x x x x desl enter idle after t rp l h h h x nop enter idle after t rp l h h l x bst illegal l h l h ba,ca,a10 read/read a illegal l h l l ba,ca,a10 writ/writ a illegal l l h h ba,ra act illegal l l h l ba,a10 pre,pall illegal l l l h x ref,self illegal l l l l mode mrs illegal idle h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba,ca,a10 read/read a illegal l h l l ba,ca,a10 writ/writ a illegal l l h h ba,ra act bank and row active l l h l ba,a10 pre,pall nop l l l h x ref,self refresh l l l l mode mrs mode register set row active h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba,ca,a10 read/read a begin read l h l l ba,ca,a10 writ/writ a begin write l l h h ba,ra act other bank active; illegal on same bank*3 l l h l ba,a10 pre,pall precharge l l l h x ref,self illegal l l l l mode mrs illegal read h x x x x desl continue burst to end l h h h x nop continue burst to end l h h l x bst burst stop to full page l h l h ba,ca,a10 read/read a continue burst read to cas latency and new read l h l l ba,ca,a10 writ/writ a term burst read/start write l l h h ba,ra act other bank active; illegal on same bank*3 l l h l ba,a10 pre,pall term burst read and precharge l l l h x ref,self illegal l l l l mode mrs illegal write h x x x x desl continue burst to end l h h h x nop continue burst to end l h h l x bst burst stop on full page l h l h ba,ca,a10 read/read a term burst and new read l h l l ba,ca,a10 writ/writ a term burst and new read l l h h ba,ra act other bank active; illegal on same bank*3 l l h l ba,a10 pre,pall term burst write and precharge*2 l l l h x ref,self illegal l l l l mode mrs illegal
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? current state ce ras cas we address command operation write with auto h x x x x desl continue burst to end and precharge precharge l h h h x nop continue burst to end and precharge l h h l x bst illegal l h l h ba,ca,a10 read/read a illegal l h l l ba,ca,a10 writ/writ a illegal l l h h ba,ra act other bank active; illegal on same bank*3 l l h l ba,a10 pre,pall illegal l l l h x ref,self illegal l l l l mode mrs illegal refresh h x x x x desl enter idle after t rc (auto refresh) l h h h x nop enter idle after t rc l h h l x bst enter idle after t rc l h l h ba,ca,a10 read/read a illegal l h l l ba,ca,a10 writ/writ a illegal l l h h ba,ra act illegal l l h l ba,a10 pre,pall illegal l l l h x ref,self illegal l l l l mode mrs illegal notes h: v ih . l: v il . x:v ih or v il . 1. the other combinations are inhibit. 2. an interval of t rwl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, other bank active command is illegal.
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? simplified state diagram sr entey sr exit refresh mrs cke cke active cke cke precharge power applied cke cke write withap automatic transition after completion of command. transition resulting from command input. cke cke self refresh idle power down idle row active active clock suspend reada reada suspend read suspend writea suspend write suspend writea precharge power on write cke cke read withap cke cke read precharge precharge read write write read read with ap write with ap read with ap write with ap write read bst (on tull page) bst auto refresh mode register set (on tull page) precharge
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? device operation power up sequence apply power and start clock, attempt to maintain cke= ?h?, dqm= ?h?. ot her pins are nop condition at their inputs. maintain stable power, stable clock and no p input condition for a minimum of 200us . initialization sequence after the following initialization sequence, t he device is ready for full functionality: precharge both banks. issue 2 or more auto refresh (ref) commands to the device. issue a mode register set (mrs) command to set the device mode of operation. after t mrd0 (3 clocks) is met. the device is ready for operation. ** step 2 and 3 are interchangeable. precharge select bank (pre) the precharge operation will be perfo rmed on the active bank when the precharge selected bank command is issued. when the precharge command is issued with address a10 low, a11 se lects the bank to be precharged. at the end of the precharge sele cted bank command the selected bank will be in idle state after the minimum t rp is met. precharge all (pall) both banks are precharged at the same time when th is command is issued. w hen the precharge command is issued with address a10 high then all banks will be prec harged. at the end of the precharge all command both banks will be in idle state after the minimum t rp is met. auto precharge auto precharge is a feature wh ich performs the same individual- bank precharge function described above, but without requiri ng an explicit command. this is acco mplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is autom atically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabl ed or disabled for each individual read or write command. auto precharge ensures t hat the precharge is in itiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operat ion section of this data sheet. burst terminate the burst terminate command is used to truncate either fixed-length or full-page bur sts. the most recently registered read or weite command prior to the b urst terminate command will be truncated as shown in the operation secti on of this data sheet . nop and device deselect (nop, desl) the device is deselected by deactivating the ce signal. in this mode the device ignores all the control inputs. the sdrams are put in nop mode when ce is active and by deactivating, ras , cas and we . for both deselect and nop the device will finish the cu rrent operation when this command is issued.
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? row activate (act) this command is used to select a row in a specif ied bank of the device. read and write operation can only be initiated on this activated bank after the minimum t rcd time has elapsed from the activate command. read bank (read) this command is issued after the row activate command to initiate the burst read of data. the read command is initiated by activating ce , cas and deasserting we at the same clock sampling (rising) edge as described in the command truth table. the length of the burst and the cas latency time will be determined by the values programmed during the mrs command. write bank (writ) this command is used after the row activate command to in itiate the burst write of data. the write command is initiated by activating ce , cas and we at the same clock sampling (rising) edge as described in the command truth table. the l ength of the burst will be determined by the values programmed during the mrs command. functionality of sdram device: the following operations ar e supported by sdram: burst read burst write multi bank ping-pong access burst read with autoprecharge burst write with autoprecharge burst read terminated with precharge burst write terminated with precharge burst read terminated with another burst read/write burst write terminated with another burst write/read dqm masking fastest command to command delay of 1 clock precharge all command auto refresh cl=2,3 burst length 1,2,4, 8 and full page (256) self refresh command power down terminating a read burst terminating a write burst
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 13 ? mode register set (mrs) this command is used to program the sdram for the desired operating mode. this command is normally used after power up as defined in the power up sequence before the act ual operation of the sdra m is initiated. the functionality of the sdram dev ice can be altered by re-programming the mode register through the execution of mode register set command. both banks must be prechar ged (i.e. in idle state) before the mrs command can be issued. mode register definition the mode register is set by the input to the address pins (a0 to a11) dur ing mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. a11, a10, a9, a8 : (op mode): the synchronous dram has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specifi ed burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified dur ing the write cycle, regardl ess of the burst length. a6, a5, a4: (cas latency): these pins specify the cas latency. a3: (bt): a burst type is specified. when full-page burst is performed, only "sequent ial" can be selected. a2, a1, a0: (burst length): these pins specify the burst length.
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 14 ? mode register configuration the mode register is set by the input to the address pins (a0 to a11) during mode register set cycles. the mode register consists of five secti ons, each of which is assigned to address pins. f.p.= full page(256) r is reserved (inhibit) .= 0 or 1 a11 a10 a9 a8 write mode 0 0 0 0 burst read and burst write xx0 1r 0 0 1 0 burst read and single wirte xx1 1r a6 a5 a4 cas latency 000 r 001 1 010 2 011 3 1-- r burst length a2 a1 a0 bt=0 bt=1 000 1 1 001 2 2 010 4 4 011 8 8 100 r r 101 r r 110 r r 1 1 1 f.p. r a3 burst type 0 sequential 1 interleave a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl burst length = 2 starting ad. addressing (decimal) a0 0 1 sequence 0, 1, interleave 0, 1, burst length = 4 starting ad. addressing (decimal) a1 0 0 1 1 sequence 0, 1, 2, 3, interleave a0 0 1 0 1 burst length = 8 starting ad. addressing (decimal) a2 sequence a1 a0 1, 0, 0, 1, 2, 3, 1, 2, 3, 0, 1, 0, 3, 2, 2, 3, 0, 1, 2, 3, 0, 1, 3, 0, 1, 2, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 4, 5, 2, 3, 0, 1, interleave 0 0 0 00 0 0 1 1 11 1 1 1 1 1 1 1 1 0 0 0 0 0 0, 1,
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 15 ? multi-bank ping pong access two-bank ping-pong accesses are described in the followi ng diagram. another bank c an be activated while the first bank is being accessed as shown. ras to ras delay t rrd must be met while activating another bank. read and write with autoprecharge burst reads and writes with auto prec harge commands are initiated with aut oprecharge if a10 is at a high state while the read or write commands are issued. precharge termination of burst burst reads and writes without au toprecharge can be terminat ed prematurely by a pr echarge command. if the burst read or write command was issued in auto precharge mode then the commands may not be terminated prematurely for that bank. precharge command after a burst read the earliest a precharge command can be issued after a r ead command without the loss of data is cl + bl ? 2 clocks. the precharge command c an be issued as soon as the t ras time is met. the earliest time that precharge can be issued is shown for the cas latency = 3 device. precharge termination of a burst read burst read (with no autoprecharge) can be terminated earlier using a prec harge command along with the dqm . it allows starting the precharge early. the remaining dat a is undefined. dqm should be used to mask the invalid data. precharge termination of a burst write to terminate burst write early with precharge command t he dqm signal must be used as shown. data sampled t rdl clocks before precharge command will be written correct ly. data sampled afterward and before the precharge command is undefined. dqm must be used to prevent the location from bei ng corrupted. dqm must be asserted active to prevent location (a3 and a4 in this case) fr om being corrupted. dq(a2) w ill be written correctly as t rdl is met. read terminated by read a read command will terminate the previous read command and the data will be available after cas latency for the new command. fastest command to command delay is determined by t ccd (1 clock as shown). write terminated by write a write command will terminate the prev ious write command and the new burst write command will start with the new command as shown. fastest command to command delay is determined by t ccd (1 clock as shown). read terminated by write a write command terminates the prev ious read command and the new burst write will start . the minimum command delay for valid operation (i.e. read-modified-write) = cas latency + 2. the dqm must be held active for 3 clocks to keep the output buffer in hi-z as shown to prevent an internal io buffer conflict between the read data (in pipe) and the write data driven on the input pins. sdram commands to two banks in consecutive clocks given command1 detected by sdram component (to bank(i)), it will handl e correctly command2 (to bank(j)) that is detected in the nex t clock or later clock. also, note that command1 (or command2) can be: pr echarge-bank, internally -scheduled_auto-precharge, activate, read or write. command1/2 cannot be a precharge-all. next co mmand to same bank after precharge
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 16 ? write terminated by read a read command terminates the previous write command and the new burst read w ill start as shown. in case of t ccd =1, cl=3, and t dqz =2, there is no loss of data bandwidth even if dqm is activated to mask the write data . the burst stop command is defined by having ras and cas high with, cas and we low at the rising edge of the clock. when using the burst stop command during a burst read cycle, it should be issued x cycles before the clock edge at which the last des ired data element is valid, where x equals the cas latency minus one. when using the burst stop command during a burst write cycle, the input dat a applied coincident with the burst stop command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst stop command. precharge-bank if a precharge-bank command (to bank(k )) is detected by sdram component in clk(n), then there can be no commands presented to this bank until clk(n+t rp ). precharge-all if a precharge-all command is detected by sdram co mponent in clk(n), then there can be no commands presented to this component until clk(n+t rp ). read-auto precharge if a read with auto-precharge command (to bank(k)) is det ected by sdram component in clk(n), then there can be no commands presented to this bank until clk(n+cl+bl-2+t rp ). write-auto precharge if a write with auto-precharge command (to bank(k)) is det ected by sdram component in clk(n), then there can be no commands presented to this bank until clk(n+bl+t dal -1). back to back command with auto precharge read or write burst initiated with auto precharge (a10=high during read or wr ite) will execute the read or write normally with the exception that afte r the burst operation is over the acce ssed bank will start precharge. to access the bank again the user must reacti vate with an active bank command. the commands initiated with auto- precharge cannot be terminated with any other commands for that bank. auto refresh (ref) command an auto refresh (ref) refreshes the sdram array. re fresh addresses are generated in ternally by the sdram device and incremented after each auto re fresh automatically. no commands (i ncluding another auto refresh) can be issued until a minimum t rc is satisfied. self refresh entry/exit the self refresh mode is entered by holding ce , cas , ras ,cke low and we high at the rising edge of the clock. once the sdram enters the se lf refresh mode, all i nputs except cke will be in a don?t care state and outputs will be tri-stated. the external clock may be halted while the devic e is in self refresh mode, however, the clock must be restarted 200 cycles befor e cke is high. the self refresh comm and is exited by asserting cke high. a new command may be given t rc clocks after cke is high. multi-bank operation the following table specifies some of the timi ng parameters used for the timing diagrams. cl, t rcd and t rp can all have values of 2 or 3. cl cas latency 3 clocks bl burst length 4 t rp ras precharge 3 clocks t ras ras active time 5 clocks t rcd ras to cas delay 3 clocks
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 17 ? absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in ,v out -1.0~4.6 v voltage on v cc supply relative to v ss v cc, v ccq -1.0~4.6 v storage temperature t stg -55~+150 power dissipation p d 1 w short circuit current i os 50 ma notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shoul d be restricted to recommended operation condition. exposurc to higher than reco mmended voltage for extended periods of time could affect device reliability. dc operating conditions (t a =0 ~+70 ) parameter symbol min typ max unit note supply voltage v cc, v ccq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v cc +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2+ma output logic low voltage v ol - - 0.4 v i ol = 2+ma input leakage current i il -5 - 5 ua 3 output leakage current i ol -5 - 5 ua 4 notes: 1. v ih (max) =4.6 v ac for pulse width 10 ns acceptable. 2. v il (min) = -1.5 v ac for pulse width 10 ns acceptable 3.any input 0v v in v cc + 0.3v. all other pins are not under test=0v. 4.dout is disabled. 0v vout v cc capacitance (v cc =3.3v , t a = 25c, f = 1mhz) pin symbol min max unit clock c clk 2.5 4.0 pf ras cas we ce cke, ldqm,udqm c in 2.5 5.0 pf address c add 2.5 5.0 pf dq0~dq15 c out 4.0 6.5 pf
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 18 ? dc characteristics (recommended operating conditi on unless otherwise noted,t a = 0 to 70oc, v ih (min)/ v il (max) = 2.0v/0.8v) version parameter symbol test condition cas latency -7 -8 -10 unit note operating current (one bank active) icc1 burst length =1 t rc t rc (min),t ck t ck (min),i ol =0ma 100 80 70 ma 1 i cc2 p cke= v il (max), t ck=min 3 ma precharge standby current in power-down mode i cc2 ps cke= v il (max), clk v il (max), t ck= 2 ma i cc2 n cke v ih (min), ce v ih (max),t ck =15ns input signals are changed one time during 30ns 50 ma precharge standby current in non power- down mode i cc2 ns cke v ih (min),clk v il (max), t ck = input signals are stable 30 ma i cc3 p cke = v il (max), t ck=min 5 ma active standby current in power-down mode i cc3 ps cke = v il (max), clk v il (max), t ck= 3 ma i cc3 n cke v ih (min), ce v ih (max),t ck =15ns input signals are changed one time during 30ns 65 ma active standby current in non power-down mode (one bank active) i cc3 ns cke v ih (min),clk v il (max),t ck = input signals are stable 25 ma 160 150 140 ma operating current (burst mode) i cc4 i ol= 0ma, page burst all band activated. t ck =t ck (min) bl=4 160 150 140 ma 1 refresh current i cc5 t rc t rc (min) 160 150 140 ma 2 self refresh current i cc6 cke 0.2v 2 ma notes 1.measured with outputs open. addresses are changed only one time during t ck (min). 2.refresh period is 32ms. addresses are changed only time during t ck (min). ac operaating test conditions (v cc =3.3v 0.3v,t a =0 to 70 ) parameter value unit input levels(vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr / tf=1/1 ns output timing measurement reference level 1.4 v output load condition see fig.1 2.8 v t t t t input vss 80% 20% t t t t output i/o 50 30p +1.4 v fig.1
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 19 ? ac timeing characteristics (t a =0 ~+70 , vcc=3v~3.6v) -7 -8 -10 parameter symbol min max min max min max unit note cl=3 7 8 10 ns ck cycle time cl=2 t ck 12 12 - 12 - ns - ck high level width t ch 3 - 3 - 3 - ns - ck low level width t cl 3 - 3 - 3 - ns - input setup time t ss 2 - 2 - 2 - ns - input hold time t sh 1 - 1 - 1 - ns - cl=3 5.5 6 7 ns output valid from clock cl=2 t ac - 6 6 - 9 ns - output hold from clock t oh 2 - 2 - 2 - ns - cas to cas delay t ccd 1 - 1 - 1 - clk - ras to ras bank active delay t rrd 2 - 2 - 2 - clk - dqm to input data delay t dqd 0 - 0 - 0 - clk - write command to data-in delay t dwd 0 - 0 - 0 - clk - mrs to active delay t mrd 2 - 2 - 2 - clk - precharge to o/p in high z t roh cl - cl - cl - clk 1 dqm to data in high z for read t dqz 2 - 2 - 2 - clk - dqm to data mask for write t dqm 0 - 0 - 0 - clk - data-in to prechange command t rdl 2 - 2 - 2 - clk - power down mode entry t sb - 1 - 1 - 1 clk - self refresh exit time t srx 1 - 1 - 1 - clk - power down exit time t pde 1 - 1 - 1 - clk 1 note: 1. cl=cas latency frequency vs ac parameters UT52L1616-7 frequency cl t rc t ras t rp t rcd 143mhz(7ns) 3 10 7 3 3 125mhz(8ns) 3 9 6 3 3 100mhz(10ns) 3 7 5 2 2 83mhz(12ns) 2 6 4 2 2 UT52L1616-8 frequency cl t rc t ras t rp t rcd 125mhz(8ns) 3 9 6 3 3 100mhz(10ns) 3 7 5 2 2 83mhz(12ns) 2 6 4 2 2 UT52L1616-10 frequency cl t rc t ras t rp t rcd 125mhz(8ns) 3 9 6 3 3 100mhz(10ns) 3 7 5 2 2 83mhz(12ns) 2 6 4 2 2
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 20 ? timeing waveform power up initialization sequence 012345678910111213141516171819 power up input stable for 200us precharge all bank row active (a-bank) mrs high-z auto refresh : don't care clk cke ce ras add a11 a10 dq we dqm trp trc trc key raa raa high level is necessary auto refresh high level is necessary cas
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 21 ? active / prechange power down mode (cl=2 , bl=4) ra ca ra qa0 qa1 qa2 0 1 2 3 4 5 6 7 8 9 10111213141516171819 precharge power-down exit precharge power-down exit precharge read active power-down exit active power-down entry row active : don't care clk cke ce ras add a11 a10 dq we dqm tss tss tss t shz
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 22 ? mode register set cycle auto refresh cycle mrs clk cke ce ras add dq we dqm cas 012345678910 high-z auto refresh : don't care trc 0123456 hi-z new command high new command high high-z key ra
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 23 ? self refresh entry exit cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 self refresh entry auto refresh self refresh exit : don't care clk cke ce ras add a11 a10 dq we dqm tss trc cas hi-z
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 24 ? single bit read-write-read cycle at same page ( cl=3 , bl=1 ) ra ca qa 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 precharge read : don't care clk cke ce ras add a11 a10 dq we dqm t slz tcc t rc cas cb cc rb bs bs bs bs bs bs ra rb db qc row active read write row active high tc h t cl t ras t rcd t rp t ccd t sh tss tss t sh t rac t sac t oh tss t sh
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 25 ? read write cycle at same bank ( bl=4 ) ra ca0 qa1 012345678910111213141516171819 precharge : don't care clk cke ce ras add a11 a10 dq we dqm t rc cas cb0 rb ra rb qa3 db0 row active read write row active high t rcd t rac t sac t oh t sac t shz qa2 db1 db2 db3 qa0 qa1 qa3 db0 qa2 db1 db2 db3 qa0 t rdl t rdl t oh t rac t shz cl=2 cl=3 precharge ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank )
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 26 ? read write cycle with random row at different bank ( bl=4 ) raa caa qaa1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 precharge : don't care clk cke ce ras add a11 a10 dq we dqm cas rac cbb raa rac qaa3 dbb0 row active read write row active high qaa2 dbb1 dbb2 dbb3 qaa0 qaa1 qaa3 dbb0 qaa2 dbb1 dbb2 dbb3 qaa0 t cdl cl=2 cl=3 read ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) rbb qac0 qac1 qac0 row active ( a-bank ) cac rbb
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 27 ? page read cycle at different bank ( bl=4 ) raa caa qaa1 012345678910111213141516171819 precharge : don't care clk cke ce ras add a11 a10 dq we dqm cas cac cbb raa qaa3 qbb0 row active read high qaa2 qbb1 qbb2 qbb3 qaa0 qaa1 qaa3 qbb0 qaa2 qbb1 qbb2 qbb3 qaa0 cl=2 cl=3 read ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) rbb qac0 qac1 row active ( a-bank ) cbd qac0 qac1 rbb qbd1 qae1 qae0 qbd0 qbd1 qae1 qae0 qbd0 cae read read ( a-bank ) read
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 28 ? page write cycle at different bank ( bl=4 ) raa ca0 daa1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 precharge : don't care clk cke ce ras add a11 a10 dq we dqm cas cac cbb raa daa3 dbb0 row active write high daa2 dbb1 dbb2 dbb3 daa0 ( a-bank ) ( a-bank ) ( b-bank ) ( b-bank ) ( both-bank ) rbb dac0 dac1 row active ( b-bank ) cbd dbd1 dbd0 write ( a-bank ) rbb write write t rdl t rdl
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 29 ? page read write cycle at same bank ( cl=2 , bl=4 ) ra ca0 012345678910111213141516171819 precharge : don't care clk cke ce ras add a11 a10 dq we dqm cas cc0 cb0 ra qa1 qb0 row active read high qa0 qb1 qb2 ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) ( a-bank ) dc0 dc1 cd0 dd1 dd0 read ( a-bank ) write write t cdl t rdl qa1 qb0 qa0 qb1 dc0 dc1 dd1 dd0 t rcd cl=2 cl=3
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 30 ? read interruption by precharge command read burst stop cycle (bl= full page ) qaa1 012345678910111213141516171819 precharge : don't care clk cke ce ras add a11 a10 dq we dqm cas qaa3 qaa4 row active read high qaa2 qab0 qaa0 qaa1 qaa3 qaa4 qaa2 qaa0 cl=2 cl=3 ( a-bank ) ( a-bank ) qab1 qab2 ( a-bank ) qab0 qab1 qab4 qab5 qab3 qab3 qab5 qab4 qab2 burst stop ( a-bank ) read raa raa caa cab
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 31 ? write interruption by precharge command read burst stop cycle (bl= full page ) raa caa qaa1 012345678910111213141516171819 precharge : don't care clk cke ce ras add a11 a10 dq we dqm cas raa qaa3 qaa4 row active write high qaa2 qab0 qab1 qaa0 ( a-bank ) ( a-bank ) qab2 qab3 cab qab5 qab4 ( a-bank ) write burst stop t bdl t rdl ( a-bank )
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 32 ? clock suspension dqm operation cycle ( cl=2 , bl=4 ) ra ca qa1 0 1 2 3 4 5 6 7 8 9 10111213141516171819 write dqm : don't care clk cke ce ras add a11 a10 dq we dqm cas ra qa3 row active read high qb0 qb1 qa0 dc0 cb dc2 read t shz cc qa2 t shz clock suspension read dqm write clock suspension write dqm
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 33 ? package outline dimention 50 pin 400mil package outline dimention symbol dimension(inch) dimension(mm) min. nom max min nom max a - - 0.047 - - 1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.037 0.040 0.042 0.95 1.00 1.05 a3 - 0.010 - - 0.025 - b 0.012 0.014 0.017 0.30 0.36 0.42 c 0.004 0.005 0.006 0.11 0.13 0.15 d 0.820 0.825 0.830 20.82 20.95 21.08 e 0.395 0.400 0.405 10.03 10.16 10.29 e - 0.032 - - 0.80 - he 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.020 0.024 0.40 0.50 0.60 y - - 0.004 - - 0.10 z - - 0.040 - - 1.0 0 - 5 0 - 5
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 34 ? ordering information part no. access time package UT52L1616mc-7 5.5 ns 50 pin tsop ii UT52L1616mc-8 6 ns 50 pin tsop ii UT52L1616mc-10 7 ns 50 pin tsop ii
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 35 ? revision history revision description date preliminary rev.0.9 original. feb 12, 2001 preliminary rev.0.91 a new version. dec. 13, 2001
utron UT52L1616 preliminary rev. 0.91 1m x 16 bit sdram utron technology inc. p90004 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 36 ? this page is left blank intentionally.

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