View CXD2931R-9_1873239.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1 ? e01z12-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2931R-9/ga-9 CXD2931R-9 144 pin lqfp (plastic) cxd2931ga-9 144 pin lflga (plastic) 1 chip gps lsi description the CXD2931R-9/ga-9 is a dedicated lsi for the gps (global positioning system) satellite-based position measurement system. this lsi contains a 32-bit risc cpu, 2m-bit mask rom, ram, uart, timer, and others. this lsi, used together with the rf lsi (cxa1951aq), enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. features ? 16-channel gps receiver capable of simultaneously receiving 16 satellites supports differential gps ? comforms to rtcm sc-104 ver. 2.1 ? supports darc all-in-view measurement 2-satellite measurement timer supporting gps time high performance 32-bit risc cpu 256k-byte program rom 36k-byte ram 3-channel uart ? baud rate generator ? supports 1.2k, 2.4k, 4.8k, 9.6k, 19.2k and 38.4k baud ? supports 1/2/4-byte buffer mode 23-bit general-purpose i/o port capable of defining input/output independently for each bit 8-bit successive approximation system a/d converter structure silicon gate cmos ic absolute maximum ratings supply voltage v dd v ss ? 0.5 to 4.6 v input voltage v i v ss ? 0.5 to v dd + 0.5 v output voltage v o v ss ? 0.5 to v dd + 0.5 v operating temperature topr ?40 to +85 c storage temperature tstg ?50 to +150 c recommended operating conditions supply voltage v dd 3.0 to 3.6 v operating temperature topr ?40 to +85 c input/output pin capacitance input capacitance c in 9 (max.) pf output capacitance c out 11 (max.) pf i/o capacitance c i/o 11 (max.) pf
? 2 ? CXD2931R-9/ga-9 performance 16-channel gps receiver high performance 32-bit risc cpu receiver frequency: 1575.42mhz (l1 band, ca code) reception sensitivity tracking sensitivity: ?145dbm (typ.) when using the antenna of 25dbi, nf = 2db and the rf amplifier with the 25db gain ? reference data using the sony's reference board. this value is not guaranteed, depending on the conditions. time to first fix (time until initial measurement after power-on) cold start (without both ephemeris and almanac): 27 to 58s warm start (without ephemeris with almanac): 23 to 45s hot start (with both ephemeris and almanac): 6 to 17s ? reference data with elevation angle of 5 or more and no interception environment on nov., 2001. positioning time with 90% possibility. these values are not guaranteed, depending on the conditions. positioning accuracy 2drms: approx. 12m ? reference data with elevation angle of 5 or more and no interception environment. this value is not guaranteed, depending on the conditions. measurement data update time 1s interfece format nmea0183 (4800bps) sony binary (9600bps) communication method start-stop synchronization all-in-view gps receiver system block diagram using the CXD2931R-9 cxa1951aq rf converter CXD2931R-9 16ch gps processor 1575.42mhz if 1.023mhz rxd txd tcxo 18.414mhz lna
? 3 ? CXD2931R-9/ga-9 block diagram ics0, 1 iadr (1:18) ib (0:15) ird iwr xcs0 dcs0 to dcs5/port (16:21) dadr (0:15) db (0:7) drd dwr port (0:15) test0, 1 icst0, 1 xromw exrs pwrst v dd 10 v ss 10 avd avs vrt vrb clks clki clko clkout tcxos nmi hold rxd0 to rxd2 pmi txd0 to txd2 holda iodbk sint/port (22) run avin otcxo tcxo xtcxo ccki ccko if0 if0o 36k-byte sram uart (baud rate generator) 3 timer 3 16ch gps dsp biu 32-bit risc 256k-byte rom 8-bit adc
? 4 ? CXD2931R-9/ga-9 pin configuration (CXD2931R-9) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 133 134 135 136 137 138 139 140 141 142 143 144 121 122 123 124 125 126 127 128 129 130 131 132 109 110 111 112 113 114 115 116 117 118 119 120 db6 db7 sint/port22 dcs0/port21 v dd dcs1/port20 dcs2/port19 dcs3/port18 dcs4/port17 dcs5/port16 port15 port14 v ss port13 port12 port11 port10 port9 port8 port7 v dd port6 port5 port4 port3 port2 port1 port0 v ss txd2 rxd2 txd1 rxd1 txd0 rxd0 v dd ib8 ib7 v ss ib6 ib5 ib4 ib3 ib2 ib1 v dd ib0 iadr18 iadr17 iadr16 iadr15 iadr14 iadr13 v ss iadr12 iadr11 iadr10 iadr9 iadr8 iadr7 iadr6 v dd iadr5 iadr4 iadr3 iadr2 iadr1 xromw ics1 v ss ics0 ird avd avin vrt vrb avs v ss tcxo xtcxo v dd otcxo test0 test1 ccki ccko v ss icst0 icst1 if0 if0o tcxos v dd hold nmi pmi holda iodbk exrs pwrst v ss clki clko clks clkout v dd run iwr 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 96 97 98 99 100 101 102 103 104 105 106 107 108 91 92 93 94 95 db5 db4 db3 db2 v ss db1 db0 dadr15 dadr14 dadr13 dadr12 dadr11 dadr10 v dd dadr9 dadr8 dadr7 dadr6 dadr5 dadr4 dadr3 dadr2 v ss dadr1 dadr0 xcs0 dwr drd ib15 ib14 ib13 ib12 ib11 v dd ib10 ib9
? 5 ? CXD2931R-9/ga-9 pin configuration (cxd2931ga-9) 7 5 2 62 ib0 66 ib3 69 ib6 109 db6 113 v dd 117 64 ib1 68 ib5 72 ib8 73 ib9 76 ib11 80 ib15 84 dadr0 88 dadr3 93 dadr8 97 dadr11 101 dadr15 105 db2 108 db5 110 db7 114 54 iadr12 53 iadr11 52 iadr10 124 port11 125 port10 126 port9 55 v ss 56 iadr13 57 iadr14 120 port14 121 v ss 123 port12 58 iadr15 60 iadr17 61 iadr18 116 118 122 port13 59 iadr16 63 v dd 65 ib2 112 115 119 port15 47 v dd 43 iadr2 40 ics1 137 v ss 135 port1 131 port5 50 iadr8 46 iadr5 44 iadr3 133 port3 132 port4 130 port6 51 iadr9 49 iadr7 48 iadr6 129 v dd 128 port7 127 port8 45 iadr4 41 xromw 37 ird 141 rxd1 138 txd2 134 port2 39 v ss 35 run 32 clks 30 clki 27 exrs 24 pmi 20 tcxos 17 icst1 13 ccki 10 otcxo tcxo avs avin 143 rxd0 139 rxd2 70 v ss 75 v dd 78 ib13 81 drd 83 xcs0 86 v ss 87 dadr2 90 dadr5 91 dadr6 94 dadr9 95 v dd 98 dadr12 100 dadr14 103 db1 106 db3 67 ib4 71 ib7 74 ib10 77 ib12 79 ib14 82 dwr 85 dadr1 89 dadr4 92 dadr7 96 dadr10 99 dadr13 102 db0 104 v ss 107 db4 111 42 iadr1 38 ics0 36 iwr 33 clkout 29 v ss 25 holda 21 v dd 16 icst0 12 test1 8 xtcxo 4 vrb 1 avd 144 v dd 140 txd1 136 port0 34 v dd 31 clko 28 pwrst 26 iodbk 23 nmi 22 hold 19 if0o 18 if0 15 v ss 14 ccko 11 test0 9 v dd 6 v ss 3 vrt 142 txd0 8 9 10 11 12 13 14 5 6 742 15 31 r p n m l k j h g f e d c b a dcs0/ port21 dcs1/ port20 sint/ port22 dcs4/ port17 dcs2/ port19 dcs3/ port18 dcs5/ port16
? 6 ? CXD2931R-9/ga-9 pin configuration pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 symbol avd avin vrt vrb avs vss tcxo xtcxo v dd otcxo test0 test1 ccki ccko vss icst0 icst1 if0 if0o tcxos v dd hold nmi pmi holda iodbk exrs pwrst vss clki clko clks clkout v dd run iwr ird i/o ? i i i ? ? i o ? o i i i o ? i i i o i ? i i i o o i i ? i o i o ? o o o description a/d converter power supply. analog input. reference input. a/d converter gnd. gnd tcxo binary conversion circuit/crystal oscillator. power supply. tcxo clock output. test. (low level fixed) timer oscillation. (32.768khz ?100ppm) gnd test. (low level fixed) if signal binary conversion circuit. tcxo select. (low: tcxo/2, high: tcxo through) power supply. hold input signal. (high: hold) non maskable interrupt. program maskable interrupt. hold acknowledge signal. break signal for debugging. reset input signal. connect to main power supply. leave open during backup. gnd cpu clock oscillation circuit. cpu clock select signal. (low: tcxo, high: clki) cpu clock output. power supply. signal indicating cpu operating status. write signal for external expansion memory. read signal for external expansion memory.
? 7 ? CXD2931R-9/ga-9 pin no. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 symbol ics0 vss ics1 xromw iadr1 iadr2 iadr3 iadr4 iadr5 v dd iadr6 iadr7 iadr8 iadr9 iadr10 iadr11 iadr12 vss iadr13 iadr14 iadr15 iadr16 iadr17 iadr18 ib0 v dd ib1 ib2 ib3 ib4 ib5 ib6 vss ib7 ib8 ib9 ib10 i/o o ? o i i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o description chip select 0 for external expansion memory. gnd chip select 1 for external expansion memory. wait signal for external expansion memory. (high: wait) (lsb) address signal for external expansion memory. power supply. address signal for external expansion memory. gnd address signal for external expansion memory. (msb) (lsb) data bus i/o for external expansion memory. power supply. data bus i/o for external expansion memory. gnd data bus i/o for external expansion memory.
? 8 ? CXD2931R-9/ga-9 pin no. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 symbol v dd ib11 ib12 ib13 ib14 ib15 drd dwr xcs0 dadr0 dadr1 vss dadr2 dadr3 dadr4 dadr5 dadr6 dadr7 dadr8 dadr9 v dd dadr10 dadr11 dadr12 dadr13 dadr14 dadr15 db0 db1 vss db2 db3 db4 db5 db6 db7 i/o ? i/o i/o i/o i/o i/o o o o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o description power supply. data bus i/o for external expansion memory. (msb) read signal for external expansion data memory. write signal for external expansion data memory. chip select signal for external expansion data memory. (lsb) address signal for external expansion data memory. gnd address signal for external expansion data memory. power supply. address signal for external expansion data memory. (msb) (lsb) data bus i/o for external expansion data memory. gnd data bus i/o for external expansion data memory. (msb)
? 9 ? CXD2931R-9/ga-9 pin no. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 symbol sint/port22 dcs0/port21 v dd dcs1/port20 dcs2/port19 dcs3/port18 dcs4/port17 dcs5/port16 port15 port14 vss port13 port12 port11 port10 port9 port8 port7 v dd port6 port5 port4 port3 port2 port1 port0 vss txd2 rxd2 txd1 rxd1 txd0 rxd0 v dd i/o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o i/o ? o i o i o i ? description external interrupt input signal/general-purpose i/o port. this pin can be used as a general-purpose i/o port according to the internal registers. chip select for external expansion data memory/general-purpose i/o port. this pin can be used as a general-purpose i/o port according to the internal registers. power supply. chip select for external expansion data memory/general-purpose i/o port. these pins can be used as a general-purpose i/o port according to the internal registers. general-purpose i/o port. gnd general-purpose i/o port. power supply. general-purpose i/o port. gnd uart transmission data output. (channel 2) uart reception data input. (channel 2) uart transmission data output. (channel 1) uart reception data input. (channel 1) uart transmission data output. (channel 0) uart reception data input. (channel 0) power supply.
? 10 ? CXD2931R-9/ga-9 a/d converter characteristics (0 < vrb < vin < vrt < avd = 3.0 to 3.6v, topr = ? 40 to +85 c) item resolution differential linearity error (dle) integral linearity error (ile) sampling time conversion time current consumption pin condition avd = 3.0v f = 18.414mhz avd = 3.0v min. ? 0.5 ? 2.5 648 864 ty p. 2.0 max. 8 +0.5 +2.5 unit bit lsb lsb ns ns ma electrical characteristics dc characteristics (v dd = 3.0 to 3.6v, topr = ? 40 to +85 c) item high level low level high level low level high level low level high level low level high level low level input voltage (1) (cmos level) input voltage (2) (5v interface) output voltage (1) output voltage (2) output voltage (3) current consumption in standby mode (using external timer, +85 c) supply current v ih (1) v il (1) v ih (2) v il (2) v oh (1) v ol (1) v oh (2) v ol (2) v oh (3) v ol (3) istb i dd i oh = ? 4.0ma i ol = 4.0ma i oh = ? 2.0ma i ol = 4.0ma i oh = ? 2.0ma i ol = 8.0ma v dd = 3.0v v dd = 1.8v f = 18.414mhz 0.7 v dd 0.7 v dd v dd ? 0.4 v dd ? 0.8 v dd ? 0.8 v dd 0.2 v dd 5.5 0.2 v dd 0.4 0.4 0.4 70 50 20 4 55 v v v v v v v v v v ? ma ? 1 ? 2 ? 3 ? 4 ? 5 ? ? symbol condition min. typ. max. unit applicable pins applicable pins ? 1 pins 11, 12, 16, 17, 20, 28, 32, 41 ? 2 pins 22 to 24, 27, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122, 128, 130 to 136, 139, 141, 143 ? 3 pins 10, 25, 26, 33, 35 ? 4 pins 38, 40, 82, 83, 138, 140, 142 ? 5 pins 36, 37, 42 to 46, 48 to 54, 56 to 62, 64 to 69, 71 to 74, 76 to 81, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136
? 11 ? CXD2931R-9/ga-9 battery backup mode the battery backup mode is activated when the power for the gps receiver is turned off and power-on reset goes to low level. the timer clock continues to operate even when power-on reset goes low, but all other clock are fixed high and the lsi is set to the low power consumption mode. at this time, the ram data is held and the registers are initialized. battery backup mode is canceled by setting power-on reset to high. normal outputs txd0 to 2, otcxo, holda inputs rxd0 to rxd2, if0, hold, nmi, pmi tri-state outputs iodbk, run, clkout hi-z hi-z fixed low fixed low fixed low fixed low 10 clocks 100ms or more pwrst power-on reset exrs timer clocks ccki, ccko other clocks tcxo, xtcxo, clki, clko tri-state outputs ics0, ics1, iadr[18:1], ird, iwr, drd, dwr, xcs0 bidirectional sint, ib[15:0], dcs0 to dcs5, dadr[15:0], db[7:0], port[22:0] (input) (outut)
? 12 ? CXD2931R-9/ga-9 CXD2931R-9/ga-9 initialization CXD2931R-9/ga-9 initialization is started by setting the reset input signal exrs (pin 27) to low level. the timing should satisfy the conditions noted below. 1. during power-on (power-on reset) (v dd = 3.0 to 3.6v, topr = ? 40 to +85 c) the pwrst (pin 28) signal should rise simultaneously with the power supply. the exrs (pin 27) signal should rise 100ms or more after the power supply and the pwrst signal have risen. note that the pwrst signal should be left open during battery backup. 2. initialization during operation (v dd = 3.0 to 3.6v, topr = ? 40 to +85 c) the internal registers can be initialized during operation by setting the exrs (pin 27) signal to low level for 100? or more. keep the pwrst (pin 28) signal at high level at this time. v dd [v] v dd gnd exrs (pin 27) power supply, pwrst (pin 28) v dd /2 100ms or more v dd [v] v dd gnd exrs (pin 27) power supply, pwrst (pin 28) v dd /2 100? or more
? 13 ? CXD2931R-9/ga-9 external command fetch timing (xromw = 0) no. (a) (b) (c) (d) (e) (f) (g) (h) item read cycle time (fex: @20mhz) address delay time chip select fall delay time chip select rise delay time read signal fall delay time read signal rise delay time read data setup time read data hold time min. ? ? 2 2 0 0 11 0 ty p . 100 ? ? ? ? ? ? ? max. ? 12 10 10 3 5 ? ? unit ns ns ns ns ns ns ns ns ? the load capacitance = 30pf. external command fetch timing (xromw = 1) clkout (g) (b) (c) (d) (e) (f) (h) iadr ics0, ics1 ird ib (a) (16) (16) iadr clkout ics0, ics1 ird ib
? 14 ? CXD2931R-9/ga-9 external data access timing (ics0, ics1/xromw = 0) (1) read (half-word access/xromw = 0) (2) write (half-word access/xromw = 0) no. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) item read/write cycle time (fex: @20mhz) address delay time chip select fall delay time chip select rise delay time read signal fall delay time read signal rise delay time read data setup time read data hold time write signal fall delay time write signal rise delay time write data established time write data hold time min. ? ? 2 2 0 0 11 0 0 0 ? 5 ty p . 100 ? ? ? ? ? ? ? ? ? ? ? max. ? 12 10 10 3 5 ? ? 1 2 5 ? unit ns ns ns ns ns ns ns ns ns ns ns ns ? the load capacitance = 30pf. clkout (g) (b) (c) (d) (e) (f) (h) iadr ics0, ics1 ird ib (a) (16) clkout (k) (b) (c) (d) (i) (j) (l) iadr ics0, ics1 iwr ib (a) (16)
? 15 ? CXD2931R-9/ga-9 (3) read (word access/xromw = 0) (4) write (word access/xromw = 0) h (16) l (16) iadr clkout ics0, ics1 ird ib l (16) h (16) iadr clkout ics0, ics1 iwr ib
? 16 ? CXD2931R-9/ga-9 external data access timing (ics0, ics1/xromw = 1) (1) read (half-word access/xromw = 1) (2) write (half-word access/xromw = 1) (3) read (word access/xromw = 1) (4) write (word access/xromw = 1) (16) iadr clkout ics0, ics1 ird ib (16) iadr clkout ics0, ics1 iwr ib iadr clkout ics0, ics1 ird ib h (16) l (16) iadr clkout ics0, ics1 iwr ib l (16) h (16)
? 17 ? CXD2931R-9/ga-9 external data access timing (xcs0, dcs0 to dcs5/no data wait) (1) read (byte access/no data wait) (2) write (byte access/no data wait) no. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) item read/write cycle time (fex: @20mhz) address delay time chip select fall delay time chip select rise delay time read signal fall delay time read signal rise delay time read data setup time read data hold time write signal fall delay time write signal rise delay time write data established time write data hold time min. ? ? 3 3 2 2 16 0 0 0 ? 5 ty p . 100 ? ? ? ? ? ? ? ? ? ? ? max. ? 12 13 13 8 10 ? ? 2 3 12 ? unit ns ns ns ns ns ns ns ns ns ns ns ns ? the load capacitance = 30pf. clkout (h) (b) (c) (d) (e) (f) (g) dadr xcs0, dcs0 to dcs5 drd db (a) (8) clkout (l) (b) (c) (d) (i) (j) (k) dadr xcs0, dcs0 to dcs5 dwr db (a) (8)
? 18 ? CXD2931R-9/ga-9 (3) read (half-word access/no data wait) (4) write (half-word access/no data wait) (5) read (word access/no data wait) (6) write (word access/no data wait) h (8) h (8) dadr clkout xcs0, dcs0 to dcs5 drd db l (8) h (8) dadr clkout xcs0, dcs0 to dcs5 dwr db hh (8) dadr clkout xcs0, dcs0 to dcs5 drd db hl (8) lh (8) ll (8) ll (8) dadr clkout xcs0, dcs0 to dcs5 dwr db lh (8) hl (8) hh (8)
? 19 ? CXD2931R-9/ga-9 external data access timing (xcs0, dcs0 to dcs5/data wait = 1) (1) read (byte access/data wait = 1) (2) write (byte access/data wait = 1) (3) read (half-word access/data wait = 1) (4) write (half-word access/data wait = 1) dadr clkout xcs0, dcs0 to dcs5 drd db (8) dadr clkout xcs0, dcs0 to dcs5 dwr db (8) h (8) dadr clkout xcs0, dcs0 to dcs5 drd db l (8) l (8) dadr clkout xcs0, dcs0 to dcs5 dwr db h (8)
? 20 ? CXD2931R-9/ga-9 external data access timing (xcs0, dcs0 to dcs5/data wait = 2) (1) read (byte access/data wait = 2) (5) read (word access/data wait = 1) (6) write (word access/data wait = 1) (2) write (byte access/data wait = 2) dadr clkout xcs0, dcs0 to dcs5 drd db hh (8) hl (8) lh (8) ll (8) dadr clkout xcs0, dcs0 to dcs5 dwr db ll (8) lh (8) hl (8) hh (8) (8) dadr clkout xcs0, dcs0 to dcs5 drd db (8) dadr clkout xcs0, dcs0 to dcs5 dwr db
? 21 ? CXD2931R-9/ga-9 (3) read (half-word access/data wait = 2) (4) write (half-word access/data wait = 2) (5) read (word access/data wait = 2) (6) write (word access/data wait = 2) h (8) dadr clkout xcs0, dcs0 to dcs5 drd db l (8) l (8) dadr clkout xcs0, dcs0 to dcs5 dwr db h (8) hh (16) dadr clkout xcs0, dcs0 to dcs5 drd db hl (16) lh (16) ll (16) ll (16) dadr clkout xcs0, dcs0 to dcs5 dwr db lh (16) hl (16) hh (16)
? 22 ? CXD2931R-9/ga-9 application notes the constants shown in the circuits below are the examples, and do not quarantee the circuit operation. 1. tcxo input (1) when inputting the binary-converted signal the tcxo (pin 7) input signal should be 18.414mhz ?3ppm. (2) when performing the self-oscillation with the tcxo and xtcxo pins (pins 7 and 8) the tcxo (pin 7) input signal should be 18.414mhz ?3ppm. 2. cpu clock generation pin 32 is used to select that tcxo is used or that the self-oscillation is performed with the mcki and mcko pins (pins 30 and 31). (1) tcxo solution (tcxo is used for cpu clock) set pin 32 to low. pin 30: low pin 31: open (2) when performing the self-oscillation with the mcki and mcko pins (pins 30 and 31) set pin 32 to high. the crystal frequency should be less than 20mhz. the following circuit is just a reference, and is not guaranteed. 7 8 input open 7 8 0.01? 1m ? tcxo 30 31 20pf 20pf 10m ? 20mhz max.
? 23 ? CXD2931R-9/ga-9 (3) using internal clock set port5 (pin 131) to high. connect the external parts as follows when performing the self-oscillation with the ccki and ccko pins (pins 13 and 14). (4) input if signal 13 14 220pf 220pf 10m ? 32.768khz ?00ppm 18 19 0.01? 1m ?
? 24 ? CXD2931R-9/ga-9 description of application circuit see the application circuit when using the CXD2931R-9/ga-9 to configure a gps receiver. points for caution are as follows. 1. unused pins software processing is performed to prevent undesired current from flowing to unused pins in the circuit diagram, so leave these pins open. 2. tcxo input the tcxo frequency is 18.414mhz ?3ppm. signals that have not been binary-converted should be input via a dc filter capacitor (c19 in the circuit diagram). input binary-converted signals directly to pin 7 (tcxo) without passing through c19 or r1 in the circuit diagram. make sure the input level at this time satisfies the electrical characteristics. 3. if input the CXD2931R-9/ga-9 interface is 1.023mhz, and does not accept other frequencies. signals that have not been binary-converted should be input via a dc filter capacitor (c20). input binary-converted signals directly to pin 18 (if0) without passing through c20 or r3 in the circuit diagram. make sure the input level at this time satisfies the electrical characteristics. 4. txd (sio output) the txd amplitude low level is 0.4v or less, and the high level is v dd ? 0.4v (v dd = 3.0 to 3.6v) or more. when the lsi, etc., connected to txd operates at 5v and has a cmos input level, perform 3 to 5v conversion before inputting the signal. 5. real-time clock the current software version uses an external real-time clock. consult your sony representative beforehand when using the internal real-time clock. when using an external real-time clock, connect pin 13 (ccki) to gnd.
? 25 ? CXD2931R-9/ga-9 application circuit recommended components ic1: CXD2931R-9/ga-9 ic2: real-time clock made by ricoh (rs5c313) ic3: voltage regulator (for step-down transformation) made by seiko instruments (s81218sg, steps down 3v to 1.8v) tcxo: made by tokyo denpa oscillator frequency: 18.414mhz ?3ppm note) set port5 to low when using an external timer, and set port5 to high when using an internal timer. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 142 143 144 121 122 123 124 125 126 127 128 129 130 131 132 109 110 111 112 113 114 115 116 117 118 119 120 avd avin vrt vrb avs v ss tcxo xtcxo v dd otcxo test0 test1 ccki ccko v ss icst0 icst1 if0 if0o tcxos v dd hold nmi pmi holda iodbk exrs pwrst v ss clki iadr18 iadr17 iadr16 iadr15 iadr14 ib3 ib2 ib1 v dd ib0 ib5 ib4 ib8 ib7 v ss ib6 iadr13 v ss iadr12 iadr11 iadr10 iadr9 iadr8 iadr7 iadr6 v dd iadr5 iadr4 iadr3 iadr2 iadr1 xromw ics1 v ss ics0 ird port14 v ss port13 port12 port11 91 92 93 94 95 dcs2/port19 dcs3/port18 dcs4/port17 dcs5/port16 port15 dcs1/port20 db6 db7 sint/port22 dcs0/port21 v dd port10 ic1 CXD2931R-9/ga-9 port9 port8 port7 v dd port6 port5 port4 port3 port2 port1 port0 v ss txd2 rxd2 txd1 rxd1 txd0 rxd0 v dd db5 db4 db3 db2 v ss db1 db0 dadr15 dadr14 dadr13 dadr12 dadr11 dadr10 v dd dadr9 dadr8 dadr7 dadr6 dadr5 dadr4 dadr3 dadr2 v ss dadr1 dadr0 xcs0 dwr drd ib15 ib14 clko clks clkout v dd run iwr ib13 ib12 ib11 v dd ib10 ib9 ic2 rs5c313 1 2 3 4 8 7 6 5 v ss sio scl ce int osco osci v dd ic3 5812185g 1 2 3 4 5 vout vin nc nc gnd r1 1m c14 0.1 c10 0.1 v dd v dd v ss v ss v dd v ss 47k 47k v dd v dd v dd v ss v ss v ss r3 1m r2 10m x2 32.768k c13 0.1 c19 0.01 tcxo v ss v dd rxd0 txd0 if reset c15 220p c16 220p c20 0.01 c17 0.1 c18 0.1 c2 0.1 c1 0.1 x1 32.768k c6 10p c9 10p bt1 3.0v d1 rb400d-t146 c5 0.1 c3 0.1 c7 0.1 c4 0.1 c11 3.3 d2 rb400d-t146 cn1 gnd reset if (1.023mhz) tcxo (18.414mhz) rxd txd 3.6v ? 1 2 3 4 5 6 7 47k 47k 47k 47k 47k 47k when using the internal timer when using an external timer ? input 3.6v in consideration of voltage step-down by diode (d2).
? 26 ? CXD2931R-9/ga-9 package outline unit: mm CXD2931R-9 sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin copper alloy lqfp-144p-l01 lqfp144-p-2020 1.3 g 144pin lqfp (plastic) 0.1 0.05 (21.0) 0.5 0.15 0? to 10? detail a 1 36 37 72 73 108 109 144 b 0.5 m 0.08 1.7 max 1.4 0.1 a b 0.1 s s 22.0 0.2 20.0 0.1 s detail b 0.125 0.04 b = 0.20 0.03 palladium plating
?27 CXD2931R-9/ga-9 sony corporation package outline unit: mm cxd2931ga-9 sony code eiaj code jedec code package mass package structure lflga-144p-01 organic substrate 0.5g package material terminal treatment terminal material 144pin lflga p-lflga144-13x13-0.8 detail x 1.4max s s 0.20 s 0.10 0.01 x 0.15 x4 13.0 13.0 0.2 a s 0.2 b s pin 1 index 0.08 m sab a b 0.9 144 0.40 0.05 0.8 0.9 3 0.50 0.55 0.55 0.55 0.55 0.5 0.5 0.8 a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 101112131415 nickel & gold plating copper

▲Up To Search▲

Price & Availability of CXD2931R-9

	To Download CXD2931R-9 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .