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preliminary rev. 0.71 5/02 copyright ? 2002 by silicon laboratories SI5310-EVB-071 SI5310-EVB e valuation b oard for si5310 p recision c lock m ultiplier /r egenerator ic description the si5310 evaluation board provides a platform for testing and characterizing the silicon laboratories si5310 precision clock multiplier/regenerator ic. all high-speed i/os are ac coupled to ease interfacing to industry standard test equipment. features single 2.5 v power supply differential i/os ac coupled simple jumper configuration function block diagram refclk + ? z c = 50 ? z c = 50 ? z c = 50 ? z c = 50 ? clkin + ? clkout + ? multout + ? z c = 50 ? z c = 50 ? z c = 50 ? z c = 50 ? pulse generator freq. synth. spectrum analyzer scope spectrum analyzer si5310 lol rext multsel pwrdn/cal 10 k ? jumpers SI5310-EVB rev c test point
SI5310-EVB 2 preliminary rev. 0.71 functional description the evaluation board simplifies characterization of the si5310 precision clock multiplier/regenerator ic by providing access to all of the si5310 i/os. device performance can be evaluated by following the ?test configuration? section. specific performance metrics include jitter tolerance, jitter generation, and jitter transfer. power supply the evaluation board requires one 2.5 v supply. supply filtering is placed on the board to filter typical system noise components; however, initial performance testing should use a linear supply capable of supplying 2.5 v 5% dc. caution : the evaluation board is designed so that the body of the sma jacks and gnd are shorted. care must be taken when powering the pcb at potentials other than gnd at 0.0 v and vdd at 2.5 v relative to chassis gnd. self-calibration the si5310 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal dspll tm . self-calibration is initiated by a high-to-low transition of the pwrdn/cal signal while a valid reference clock is supplied to the refclk input. on the si5310- evb board, a voltage detector ic is utilized to initiate self-calibration. the voltage detector drives the pwrdn/cal signal low after the supply voltage has reached a specific voltage level. this circuit is described in silicon laboratories application note an42. on the SI5310-EVB, the pwrdn/cal signal is also accessible via a jumper located in the lower left- hand corner of the evaluation board. pwrdn/cal is wired to the center post (signal post) between 2.5 v and gnd. device power down the si5310 device can be powered down via the pwrdn/cal signal. when pwrdn/cal is driven high (2.5 v) the evaluation board will draw minimal current. on the SI5310-EVB board, the pwrdn/cal signal may be controlled via a jumper located in the lower left-hand corner of the evaluation board. pwrdn/cal is wired to the center post (signal post) between 2.5 v and gnd. clkin, clkout, multout these high-speed i/os are wired to the board perimeter on 30 mil (0.030 inch) 50 ? microstrip lines to the end- launch sma jacks as labeled on the pcb. these i/os are ac coupled to simplify direct connection to a wide array of standard test hardware. because each of these signals are differential both the positive (+) and negative (?) terminals must be terminated to 50 ? . terminating only one side will degrade the performance of the si5310 device. the clkin inputs are terminated on the die with 50 ? resistors. note: the 50 ? termination is for each terminal/side of a dif- ferential signal, thus the differential termination is actu- ally 50 ? +50 ? = 100 ? . refclk refclk is used to center the frequency of the si5310 dspll so that the device can lock to the clkin signal. for a given clkin rate, there are five choices for the refclk frequency. these five options are all multiples of the clkin frequency, as indicated in table 1. the refclk frequency is automatically detected by the si5310 device, so no digital control inputs are needed for refclk frequency selection. refclk may be synchronous or asynchronous with respect to clkin. however, refclk must be within 100 ppm of the target clkin frequency multiple. refclk is ac coupled to the sma jacks located on the top side of the evaluation board. the refclk inputs are terminated on the die with 50 ? resistors. note: the 50 ? termination is for each terminal/side of a dif- ferential signal, thus the differential termination is actu- ally 50 ? +50 ? = 100 ? . multsel multsel is a binary input to the si5310 device that selects the frequency range for the multout clock output. the multout output frequency is a multiple of the clkin input frequency. the frequency for multout will be in either the 150?167 mhz frequency range or the 600?668 mhz frequency range depending on the state of the multsel signal as indicated in table 1. on the si5310 evaluation board, multsel is controlled via a jumper located in the lower left-hand corner of the board. multsel is wired to the center post (signal post) between 2.5 v and gnd. the jumper configurations for multsel are indicated in figure 1.
SI5310-EVB preliminary rev. 0.71 3 figure 1. multsel jumper configurations loss-of-lock (lol) lol is an indicator of the relative frequency between the refclk input, which is nominally a multiple of clkin, and an internally generated multiple of clkin. lol will assert when the frequency difference is greater than 600 ppm. in order to prevent lol from de- asserting prematurely, there is hysterisis in returning from the out of lock condi tion. lol will be de-asserted (indicating a lock condition) when the frequency difference is less than 300 ppm. lol is wired to a test point which is located on the upper right-hand side of the evaluation board. test configuration the characterization of clock sources typically involves measuring the output jitter or phase noise of the source. the overall output jitter is a function of the input jitter (jitter transfer) and the jitter generated (output jitter) by the internal pll. jitter can be measured using several different techniques and hardware. an oscilloscope, a spectrum analyzer, and a phase-noise analyzer are three such instruments capable of measuring output jitter. a spectrum analyzer is the best choice for measuring jitter transfer. output jitter output jitter is a measure of the output clock short-term stability. in figure 2, either position a or b can be used when measuring this parameter. oscilloscope an oscilloscope can measure jitter from the clock edges within the trigger-to-capture bandwidth. typically the jitter measured is expressed in picoseconds (peak-to- peak and rms) relative to the average edge position. a histogram can be used to capture the jitter distribution. table 1. clkin, clkout, multout, refclk operating ranges multsel clkin range (mhz) refclk = 2 n x clkin 100 ppm (see note 2) clkout multout 0 (multout = 600?668 mhz) 37.500?41.750 n = ?2, ?1, 0, 1, or 2 1xclkin 16xclkin 75.000?83.500 n = ?3, ?2, ?1, 0, or 1 1xclkin 8xclkin 150.000?167.000 n = ?4, ?3, ?2, ?1, or 0 1xclkin 4xclkin 300.000?334.000 n = ?5, ?4, ?3, ?2, or ?1 1xclkin 2xclkin 600.000?668.000 n = ?6, ?5, ?4, ?3, or ?2 see note 1 1xclkin 1 (multout = 150?167 mhz) 9.375?10.438 n = 0, 1, 2, 3, or 4 1xclkin 16xclkin 18.750?20.875 n = ?1, 0, 1, 2, or 3 1xclkin 8xclkin 37.500?41.750 n = ?2, ?1, 0, 1, or 2 1xclkin 4xclkin 75.000?83.500 n = ?3, ?2, ?1, 0, or 1 1xclkin 2xclkin 150.000?167.000 n = ?4, ?3, ?2, ?1, or 0 see note 1 1xclkin note: 1. the clkout output is not valid for multout:clkin ratios of 1:1 (multout = 1 x clkin.) 2. the refclk input can be set to any one of the five clkin multiples indicated. the refclk input can be asynchronous to the clkin input, but must be within 100 ppm of the stated clkin multiple. gnd 2.5 v multsel low range 150?167 mhz gnd 2.5 v multsel high range 600?668 mhz multsel pwrdn/ cal multsel pwrdn/ cal
SI5310-EVB 4 preliminary rev. 0.71 spectrum analyzer a spectrum analyzer measures the power of the carrier source and its associated phase noise. analysis of the offset power distribution provides the data from which jitter can be derived. simple integration of the offset power distribution over the desired offset range and filtered amplitudes provides a rms jitter value. phase-noise analyzer a phase-noise analyzer behaves similarly to a spectrum analyzer, but only provides details regarding the power offset from the carrier. simple integration of the offset power distribution over the desired offset range and filtered amplitudes provides a rms jitter value. jitter transfer jitter transfer is the ratio of the input jitter spectrum to the output jitter spectrum. comparing the power levels from the input jitter spectrum with the output jitter spectrum provides the jitter transfer details. to characterize this parameter, a modulation source is added to the synthesizer. the fm modulation frequency is the jitter frequency, and its relative amplitude on the output verses the input describes the amount transferred. in figure 2, position a should be used when measuring this parameter. figure 2. test configuration for jitter tolerance, transfer, and generation pulse generator synthesizer signal source sampling scope 2.5 v refclk clkin multout clkout SI5310-EVB ? + + ? + ? + ? + ? spectrum analyzer phase noise analyzer pulse generator a b modulation signal source fm reference frequency
SI5310-EVB preliminary rev. 0.71 5 c16 0603 100pf j8 jc 142-0701-801 1 2 sig body vdd vdd j1 jc 142-0701-801 1 2 sig body j6 jc 142-0701-801 1 2 sig body l1 1206 blm31a601s c13 0603 100pf j4 jc 142-0701-801 1 2 sig body c1 0603 0.1uf r2 0603 2.5k c9 0805 do not install vdd v? u4 max6376xr23-t 3 1 2 vcc gnd out c7 0603 0.1uf vdd c12 tantalum 10uf c5 0603 0.1uf u5 si5310 6 12 13 16 17 20 19 15 9 10 4 5 1 2 7 11 3 8 18 14 lol clkout- clkout+ multout- multout+ nc multsel pwrdn/cal clkin+ clkin- refclk+ refclk- rext vdda vddb vddc gnda gndb gndc vddd jp1 c3 0603 0.1uf j9 mkdsn 2,5/3-5,08 1 2 pos1 pos2 j7 jc 142-0701-801 1 2 sig body j3 jc 142-0701-801 1 2 sig body jp4 2.5v c15 0603 100pf c2 0603 0.1uf jp2 r1 0603 10k c6 0603 0.1uf c8 0603 0.1uf j5 jc 142-0701-801 1 2 sig body vdd c4 0603 0.1uf j2 jc 142-0701-801 1 2 sig body figure 3. SI5310-EVB schematic
SI5310-EVB 6 preliminary rev. 0.71 bill of materials si5310evb assy rev c-01 bom reference part desc part number manufacturer c1,c2,c3,c4,c5,c6, c7,c8 cap, sm, 0.1uf, 0603 c0603x7r160-104kne venkel c12 cap, sm, 10 uf, tantalum, 3216 ta010tcm106kar venkel c13,c15,c16 cap, sm, 100 pf, 16v, 0603 c0603c0g500101kne venkel jp1,jp4 connector, header, 2x1 2340-6111tn or 2380-6121tn 3m jp2 connector, header, 3x1 2340-6111tn or 2380-6121tn 3m j1,j2,j3,j4,j5,j6,j7, j8 connector, sma, side mount 901-10003 amphenol j9 connector, power, 2 pos 1729018 phoenix contact l1 resistor, sm, 0 ohm, 1206 cr1206-8w-000t venkel r1 resistor, sm, 10k, 1%, 0603 cr0603-16w-1002ft venkel r2 resistor, sm, 2.55k, 1%, 0603 cr0603-16w-2551ft venkel u4 max6376xr23-t max6376xr23-t maxim u5 si5310 si5310-bm silicon laboratories pcb printed circuit board si 5310-evb pcb rev c silicon laboratories no load c9 spare,0805
SI5310-EVB preliminary rev. 0.71 7 figure 4. si5310 silkscreen
SI5310-EVB 8 preliminary rev. 0.71 figure 5. si5310 component side
SI5310-EVB preliminary rev. 0.71 9 figure 6. si5310 solder side
SI5310-EVB 10 preliminary rev. 0.71 document change list revision 0.7 to revision 0.71 added bill of materials. evaluation board assembly revision history assembly level pcb si5310 device assembly notes b-01 b b assemble per bom rev b-01. c-01 c c assemble per bom rev c-01.
SI5310-EVB preliminary rev. 0.71 11 notes:
SI5310-EVB 12 preliminary rev. 0.71 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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