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DM9102 10/100mbps single chip lan controller final 1 version: DM9102-ds-f03 august 30,2000 general description the davicom ? s DM9102 is a hig hly integrated single- chip fast ethernet controller. it fully integrated 100base- tx/10base-t fast ethernet mac, phy and pmd. it is fully compliant with pci spec. 2.1 and ieee802.3u. the DM9102 provides a direct interface to the pci local bus and direct c onnection to the network wire. as a controller, it provides the bus master capabil ity. the DM9102 also supports auto- negotiation function that enables it to detect s peed and duplex automatically. due to the well-controlled rising/falling time, it requires no external filter to transmit signal to the media. block diagram dma eeprom interface boot rom interface pci interface tx+/- rx+/- mii management control & mii register autonegotiation led driver rx machine rx fifo tx fifo tx machine mac mii nrz to nrzi nrzi to mlt3 parallel to serial scrambler 4b/5b encoding mlt3 to nrzi nrzi to nrz parallel to serial de- scrambler 4b/5b decoding aeq phyceiver
DM9102 10/100mbps single chip lan controller 2 final version: DM9102-ds-f03 august 30, 2000 table of contents general description ................................................1 block diagram ........................................................1 features .................................................................4 pin configuration: DM9102 qfp .............................5 pin description .......................................................6 - pci bus interface ................................................6 - boot rom and eeprom interface ......................7 multiplex mode ...................................................7 direct mode .........................................................8 - led pins .............................................................9 - network interface ..............................................10 - clock pins .........................................................10 - miscellaneous pins ............................................10 - power pins ........................................................11 register definition ................................................12 ? pci configuration registers ..............................12 key to default .......................................................13 identification id ..................................................14 command & status ............................................14 command register definition ............................16 revision id........................................................17 miscellaneous function .....................................17 i/o base address...............................................18 memory mapped base address .........................18 subsystem identification ....................................19 expansion rom base address ..........................19 capabilities pointer ............................................20 interrupt & latency configuration .......................20 device specific configuration register ..............20 ? control and status register (cr)......................22 key to default .......................................................22 1. system control register (cr0) .........................23 2. transmit descriptor poll demand (cr1)............24 3. receive descriptor poll demand (cr2) ............24 4. receive descriptor base address (cr3) ...........24 5. transmit descriptor base address (cr4) ..........25 6. network status report register (cr5) ..............25 7. network operation register (cr6)....................27 8. interrupt mask register (cr7)...........................29 9. statistical counter register (cr8) .....................30 10. prom & management access register (cr9) 31 11. programming rom address register (cr10) .32 12. general purpose timer register (cr11) .........32 13. phy status register (cr12)........................... 32 14. frame access register................................... 33 15. frame data register (cr14) .......................... 33 16. watching & jabber timer register (cr15) ..... 33 ? phy management register set ........................ 34 key to default ..................................................... 34 basic mode control register (bmcr) - register 0 .......................................................... 35 basic mode status register (bmsr) - register 1 .......................................................... 36 phy id identifier register #1 (phyidr1) - register 2 .......................................................... 37 phy id identifier register #2 (phyidr2) - register 3 .......................................................... 37 auto-negotiation advertisement register (anar) - register 4 .......................................................... 37 auto-negotiation link partner ability register (anlpar) - register 5 ......................................... 38 auto-negotiation expansion register (aner) - register 6 .......................................................... 39 davicom specified configuration register (dscr) - register 16......................................................... 39 davicom specified configuration and status register (dscsr) - register 17 ........................... 40 10base-t configuration/status (10btscrcsr) - register 18......................................................... 41 functional description .......................................... 42 ? system buffer management .............................. 42 1. overview .......................................................... 42 2. data structure and descriptor list .................... 42 3. buffer management: ring struc ture method ..... 42 4. buffer management: chain structure method ... 43 5. descriptor list: buffer descriptor format .......... 43 (a). receive descriptor format ............................. 43 (b). transmit descriptor format ............................ 45
DM9102 10/100mbps single chip lan controller final 3 version: DM9102-ds-f03 august 30,2000 initialization procedure ..........................................48 data buffer processing algorithm..........................48 1. receive data buffer processing ........................48 2. transmit data buffer processing .......................49 ? network function ..............................................50 1. overview...........................................................50 2. receive process and state machine .................50 3. transmit process and state machine ................50 4. physical layer overview ...................................50 ? serial management interface .............................51 configuration rom overview................................52 1. subsystem id block..........................................52 2. crom version..................................................53 3. controller count ................................................53 4. controller_x information ...................................53 5. controller information body pointed by controller_x info block offset item in controller information header ............................................53 absolute maximum ratings...................................55 dc electrical characteristics .................................55 ac electrical characteristics & timing waveforms 56 pci clock spec. timing.....................................56 other pci signals timing diagram ....................56 multiplex mode boot rom timing ......................57 direct mode boot rom timing ..........................57 eeprom timing ...............................................58 phyceiver .........................................................58 auto-negotiation and fast link pulse timing diagram ............................................................59 package information .............................................60 ordering information.............................................61 disclaimer ............................................................61 company overview ..............................................61 products ...............................................................61 contact windows ..................................................61 warning................................................................61 appendix a ...........................................................62 DM9102 srom format.....................................62
DM9102 10/100mbps single chip lan controller 4 final version: DM9102-ds-f03 august 30, 2000 features single chip lan controller integrated fast ethernet mac, phy and transceiver compliant with ieee 802.3u 100base-tx, ieee 802.3 10base-t and ansi x3t12 tp-pmd standard direct interface to the pci bus & fully compliant with pci specification 2.1 pci bus master architecture support pci bus burst mode data transfer with programmable burst size eeprom 93c46 interface to store configuration information and user defined message support up to 256k bytes boot rom interface two large independent receive fifo (4k) & transmit fifo (2k) with programmable fifo threshold and full packet burst processing support automatic packet deletion for runt packets and packet re-transmission with no fifo reload support full/half duplex operation physical, broadcast address recognition and 512-bit hash table algorithm for multicast address filtering compliant with ieee802.3u auto-negotiation protocol for automatic link type selection high performance 100mbps clock generator and data recovery circuit digital clock recovery circuit using advanced digital algorithm to reduce jitter adaptive equalization circuit and baseline wandering restoration circuit for 100mbps receiver provides loopback mode for easy system diagnostics 128 pin qfp with cmos process
DM9102 10/100mbps single chip lan controller final 5 version: DM9102-ds-f3 august 30, 2000 pin configuration 11 DM9102 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 55 54 53 52 51 61 81 82 83 84 85 86 87 88 89 int# rst# dvdd gnt# req# pclk ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 cbe3# dgnd nc idsel ad23 ad21 ad20 ad19 ad18 ad17 ad16 cbe2# ad22 dvdd dgnd frame# stop# irdy# trdy# devsel# perr# serr# cbe0# bggnd bgres oscvdd x1/osc x2 oscgnd ledtrf ledfdx led100m dgnd led10m bpa0 bpa1/test eedi eedo eeck eecs selrom test0 test1 test2 bpad4 bpad5 bpad6 bpad7 bpcs# bpad0 bpad1 bpad2 bpad3 ad0 ad1 ad2 ad6 ad7 dvdd ad5 ad3 dgnd ad4 ad9 ad10 dgnd ad11 dvdd ad13 ad14 ad15 ad12 ad8 cbe1# par (ma10/ledtrf) (ma11/ledfdx) (ma12/led100m) (ma13led10m) (md0/eedi) (md1) (md2) (md3) (md4) (md5) (md6) (md7) (romcs) (ma0) (ma1) (ma2) (ma3/eedo) (ma4/eeck) (ma5) (ma6/selrom) (ma7) (ma8) (ma9) dvdd dgnd dgnd dvdd dgnd dvdd dvdd dgnd dgnd dvdd 27 dvdd dvdd dgnd dvdd dgnd dgnd dvdd dgnd dgnd dvdd ma16 102 101 ma15 ma14 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 127 128 126 dgnd dvdd pwrin ravdd rxi- rxi+ ragnd tagnd txo- txo+ tavdd tagnd tagnd tagnd tavdd nc nc nc nc
DM9102 10/100mbps single chip lan controller 6 final version: DM9102-ds-f03 august 30, 2000 pin description i = input, o = output, i/o = input/output, o/d = open drain, p = power li = reset latch input, # = all pin name with # are asserted low pci bus interface pin no. pin name i/o description 1 pclk i pci system clock pci bus clock that provides timing for DM9102 related to pci bus transactions. the clock frequency range is up to 33mhz. 4 gnt# i bus grant this signal is asserted low to indicate that DM9102 has been granted ownership of the bus by the central arbiter. 5 req# o bus request the DM9102 will assert this signal low to request the ownership of the bus. 6 nc no connection 20 idsel i initialization device select this signal is asserted high during configuration space read and write access. 34 frame# i/o cycle frame this signal is driven low by the DM9102 master mode to indicate the beginning and duration of a bus transact ion. 37 irdy# i/o initiator ready this signal is driven low when the master is ready to complete the current data phase of the t ransaction. a data phase is completed on any clock both irdy# and trdy# are sampled asse rted. 38 trdy# i/o target ready this signal is driven low when the target is ready to complete the current data phase of the t ransaction. during a read, it indicates that valid data is asserted. during a write, it indicates the target is prepared to accept data. 40 devsel# i/o device select the DM9102 asserts the signal low when it recognizes its target address after frame# is asserted. as a bus master, the DM9102 will sample t his si gnal to insure that the destination address for the data transfer is recognized by a target. 41 stop# i/o stop this signal is asserted low by the target device to request the master device to stop the current transaction. 42 perr# i/o parity error the DM9102 as a master or slave will assert this signal low to indicate a parity error on any incoming data. 43 serr# i/o system error this signal is asserted low when an address parity is detected with pcics bit31 (detected parity error) is
DM9102 10/100mbps single chip lan controller final 7 version: DM9102-ds-f3 august 30, 2000 enabled. the system error asserts two clock cycles after the falling address if an address parity error is detected. 44 par i/o parity this signal indicates even parity across ad0~ad31 and c/be0#~c/be3# including the par pin. this signal is an output for the master and an input for the slave device. it is stable and valid one clock after the address phase. 19 33 45 60 c/be3# c/be2# c/be1# c/be0# i/o bus command/byte enable during the address phase, t hese signals def ine the bus command or the type of bus transaction that will take place. during the data phase these pins indicate which byte lanes contain valid data. c/be0# applies to bit7-0 and c/be3# applies to bit31-24. 9~12, 14~17, 22~25,27~30,47,48, 49,52,53,56,57,58,62, 63,64,67,68,71,72,73 ad31~ad0 i/o address & data these are multiple xed address and data bus signals. as a bus master, the DM9102 will drive address during the first bus phase. during subsequent phases, the DM9102 will either read or write data expecting the target to increment its address pointer. as a target, the DM9102 will decode each address on the bus and res pond if it is the target being addressed. 127 int# o/d interrupt request this signal will be asserted low when an interrupt condition as defined in cr5 is set, and the corresponding mask bit in cr7 is not set. 128 rst# i system reset when this signal is asserted low, DM9102 performs the internal system reset to its initial state. boot rom and eeprom interface (including multiplex mode or direct mode) : multiplex mode: pin no. pin name i/o description 75~82 bpad0~bpad7 i/o boot rom address and data bus boot rom address and data multiplexed lines bits 0~7. in two consecutive address cycles, these lines contain the boot rom address pins 7~2, out_enable and write_enable of boot rom in the fi rst cyc le; and these lines contain address pins 15~8 in second cycle. after the first two cycles, these lines contain data bit 7~0 in consective cycles. 83 bpcs# o boot rom chip select boot rom or external register chip select signal. 85 bpa0 o,li boot rom address line. low address bit0 interfacing to boot rom. 86 bpa1/test o boot rom address line. low address bit1 interfacing to boot rom. this bit is also set to enable test mode only in multiplex mode. (debug only)
DM9102 10/100mbps single chip lan controller 8 final version: DM9102-ds-f03 august 30, 2000 87 eedi i,li eeprom data in the DM9102 will read the contents of eeprom serially through this pin. 88 eedo o eeprom data out the DM9102 will use this pin to serially write op codes, addresses and data i nto the eeprom. 89 eeck o eeprom serial clock this pin provides the clock for the eeprom data transfer. 90 eecs o eeprom chip select this pin will enable the eeprom during loading of the configuration data. 92 test0 i test option control this pin are valid only test mode enabled. in normal operation when in mult iplex mode, this pin are pulled low. 93,94 test1,test2 i test option control these two pins are valid only test mode is enabled. in normal operation when in mult iplex mode, these two pins are pulled low. 99~101 nc in multiplex mode, these three pins are not connected. direct mode pin no. pin name i/o description 75 md0/eedi i boot rom data input/eedi data in this pin is multiplexed by eedi and md0. the DM9102 will read the contents of eeprom serially through this pin. 76~82 md1~md7 i boot rom data input bus 83 romcs o boot rom or eeprom chip selection. 85~87 ma0~ma2 o boot rom address output bus 88 ma3/eedo o boot rom address output/eeprom data out this pin is multiplexed with ma3 and eedo. the DM9102 will use this pin to serially write op codes, addresses and data i nto the eep rom. 89 ma4/eeck o boot rom address output/eeprom serial clock this pin is multiplexed with ma4 and eeck. this pin provides the clock for the eeprom data transfer. 90 ma5 o boot rom address output bus 91 ma6/selrom o/li boot rom address output bus/multiplex or direct mode selection it is also used as multiplex or direct m ode selection at power-up reset. 0 = multiplex mode, 1 = direct mode. 92~94 ma7~ma9 o boot rom address output bus 95~98 ma10/ledtrf o boot rom address output bus/active led when at the time of boot rom operation, the led maybe flash few seconds. led active low. when operates as led pin, if bit5 of phy
DM9102 10/100mbps single chip lan controller final 9 version: DM9102-ds-f3 august 30, 2000 management register16 is 0, it is the activity led and will flash when in transmitting or receiving. if bit5 of phy management register16 is 1, this pin is no use 96 ma11/ledfdx o boot rom address output/full-duplex led indicates full duplex mode operation. active low. when at the time of boot rom operation, the led maybe flash few seconds. 97 ma12/led100m o boot rom address output/100mbps led when at the time of boot rom operation, the led maybe flash few seconds. led active low. when operates as led pin, if bit5 of phy management register16 is 0, it indicates good link to 100mbps (default). if bit5 of phy management register16 is 1, it is link and activity led. 98 ma13/led10m o boot rom address output bus/10mbps led when at the time of boot rom operation, the led maybe flash few seconds. led active low. when operates as led pin, if bit5 of phy management register16 is 0, it indicates good link to 10mbps (default). if bit5 of phy management register16 is 1, it is link and activity led. 99~101 ma14~ma16 o boot rom address output bus led pins pin no. pin name i/o description 95 ledtrf o active led, active low if bit5 of phy management register16 is 0, it is the activity led and will flash when in transmitting or receiving. (default) if bit5 of phy management register16 is 1, this pin is no use. 96 ledfdx o full-duplex led, active low indicates full-duplex mode operation. 97 led100m o 100mbps led, active low indicates 100mbps mode operation. if bit5 of phy management register16 is 0, it indicates good link to 100mbps. (default) if bit5 of phy management register16 is 1, it is link and activity led. 98 led10m o 10mbps led, active low. indicates 10mbps mode operation. if bit5 of phy management register16 is 0, it indicates good link to 10mbps. (default) if bit5 of phy management register16 is 1, it is link and activity led.
DM9102 10/100mbps single chip lan controller 10 final version: DM9102-ds-f03 august 30, 2000 network interface pin no. pin name i/o description 107 108 rxi- rx+ i 100m/10mbps differential input pair. these two pins are differential receive input pair for 100base-tx and 10 base -t. they are capable of receiving 100base-tx mlt-3 or 10 base-t manchester encoded data. 112 113 txo- txo+ o 100m/10mbps differential output pair. these two pins are differential output pair for 100base-tx and 10 base -t. this output pair provides controlled rise and fall times des igned to filter the transmitter output. clock pins pin no. pin name i/o description 118 oscvdd p analog power 119 x1/osc i crystal or oscillator input. (25mhz 50ppm) 120 x2 o crystal feedback output pin used for crystal connection only. leave this pin open if oscillator is used. 121 oscgnd p analog ground miscellaneous pins pin no. pin name i/o description 91 selrom li multiplex mode/direct mode selection. this pin is ?reset latch input at power up? to select multiplex mode or direct mode. ?0? = multiplex mode (default), ?1? = direct mode. at direct mode, this is also a output pin which is used by ma6. 102 nc o no connection 104 bgres i band-gap voltage reference resistor . it connects to a 6200 , 1% error tolerance resistor between this pin and bggnd pin (pin 105) to provide an accurate current reference for dm 9102. 105 bggnd i ground for band-gap circuit 122 pwrin i vdd clamp this pin is used to identify the d3(cold) power state in a power management aware system. this pin should be connected to the pci power, while other dvdd pins should be connected to the auxiliary power, if any. in non-power m anagem ent aware systems, or there is no auxiliary power, the dvdd pins and the pwrin pins should be connected to the pci power
DM9102 10/100mbps single chip lan controller final 11 version: DM9102-ds-f3 august 30, 2000 power pins pin no. pin name i/o description 106 ravdd p analog power for receive 109 ragnd p analog ground for receive 114,115 tavdd p analog power for transmit 110,111,116,117 tagnd p analog ground for transmit 7,8,13,26,35,36,39,54 ,55,59,69,70,74,103, 125,126 dgnd p digital ground pins 2,3,18,21,31,32,46,50 ,51,61,65,66,84,123, 124 dvdd p digital power pins
DM9102 10/100mbps single chip lan controller 12 final version: DM9102-ds-f03 august 30, 2000 register definition pci configuration registers the definitions of pci conf iguration registers are based on the pci specification re vision 2.1 and provides the initialization and configuration information to operate the pci interface in the DM9102. all registers can be accessed with byte, word, or double word mode. as defined in pci specification 2.1, read accesses to reserve or unimplemented registers will return a value of ?0.? these registers are to be described in the following sections. pci configuration registers mapping : description identifier address offset value of reset identification pciid 00h 91021282h command & status pcics 04h 02900007h revision pcirv 08h 02000020h miscellaneous pcilt 0ch 00000000h i/o base address pciio 10h undefined memory base address pcimem 14h undefined reserved -------- 18h - 28h subsystem identification pcisid 2ch load from srom expansion rom base address pcirom 30h 00000000h capability pointer cap_ptr 34h 00000050h reserved -------- 38h interrupt & latency pciint 3ch 281401xxh device specific configuration register pciusr 40h 00000000h
DM9102 10/100mbps single chip lan controller final 13 version: DM9102-ds-f3 august 30, 2000 vendor id device id status (with bit 4 set to 1) c ommand revision latency timer cach line size class code = 020000h header type bist bass address register cbio bass address register cbma 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch reserved subsystem vendor id subsystem id expansion rom base address reserved reserved cap_ptr max_lat min_gnt interrupt pin = 1 interrupt line configuration register structure 40h 44h 48h 4ch reserved device specific configuration register key to default in the register description that follows, the default column takes the form where : 1 bit set to logic one 0 bit set to logic zero x no default value : ro = read only rw = read/write r/c : means read / write & write "1" for clear.
DM9102 10/100mbps single chip lan controller 14 final version: DM9102-ds-f03 august 30, 2000 identification id (xxxxxx00 - pciid) 31 16 15 0 dev_id vend_id device id vendor id bit default type description 16:31 9102h ro the field identifies the particular device. unique and fixed number for the DM9102 is 9102h . it is the product nu mber assigned by d avicom. 0:15 1282h ro this field identifies the manufacturer of the device. unique and fixed number for davicom is 1282h . it is a registered number from sig. command & status (xxxxxx04 - pcics) 31 16 15 0 status command status command status register definition: 31 30 29 28 27 26 25 24 23 22 21 20 16 0 0 1 1 0 0 19 1 detected parity error signal for system error master abort detected target abort detected devsel timing data parity error detected slave mode fast back to back new capability 66mhz capability user definable send target abort
DM9102 10/100mbps single chip lan controller final 15 version: DM9102-ds-f3 august 30, 2000 bit default type description 31 0b r/c detected parity error the DM9102 samples the ad[0:31], c/be[0:3]#, and the par signal to check parity and to set parity errors. in slave mode, the parity check falls on command phase and data va lid phase (irdy# and trdy# both active). while in master mode, the DM9102 will check during each data phase of a memory read cycle for a parity error during a memory write cycle, if an error occurs, the perr# signal will be driven by the target. this bit is set by the DM9102 and c leared by writing "1". there is no effect by writing "0". 30 0b r/c signal for system error this bit is set when the serr# signal is driven by the dm 9102. this system error occurs when an address parity is detected under the condition that bit 8 and bit 6 in command register below are set. 29 0b r/c master abort detected this bit is set when the DM9102 terminates a master cycle with the master-abort bus transaction. 28 0b r/c target abort detected this bit is set when the DM9102 terminates a master cycle due to a target-abort signal from other tar gets. 27 0b r/c send target abort (0 for no implementation) the DM9102 will never assert the target-abort sequence. 26:25 01b r/c devsel timing (01 select medium timing) medium timing of devsel# means the DM9102 will assert devsel# signal two clocks after frame# is sample ?asserted.? 24 0b r/c data parity error detected this bit will take effect only when operating as a master and when a parity error response bit in com mand configuration register is set. it is set under two c onditions: (i) perr# asserted by the dm 9102 in memory data r ead error, (ii) perr# sent from the target due to memory data write error. 23 1b r/c slave mode fast back-to-back capable (1 for good capability) this bit is always reads "1" to indicate that the DM9102 is capable of accepting fast back-to-back transaction as a slave mode device. 22 0b r/c user-definable-feature supported (0 for no support) 21 0b r/c 66 mhz capable (0 for no capability) 20 1b r/c new capabilities this bit indicates whether this function implements a list of extended capabilities such as pci power m anagement. when set this bit indicates the presence of new capabilities. a value of 0 means that this function does not i mplement new capabilities. 19:16 0000b ro reserved
DM9102 10/100mbps single chip lan controller 16 final version: DM9102-ds-f03 august 30, 2000 command register definition: 15 109876543 210 reserved r/w 0 r/w 00 r/w r/w r/w 0 0 parity error response enable/disable i/o space access enable/disable memory space access enable/disable master device capability enable/disable serr# driver enable/disable mast mode fast back-to-back address/data steeping vga palette snoop special cycle memory write and invalid bit default type description 15:10 000000b ro reserved 9 0b ro master mode fast back-to-back (0 for no support) the DM9102 does not support master mode fast back-to-back c apability and will not generate fast back-to-back cycles. 8 0b rw serr# driver enable/disable this bit controls the assertion of serr# signal o utput. the se rr# output will be asserted on detection of an address parity error and if both this bit and bit 6 are set. 7 0b ro address/data stepping (0 for no stepping) 6 0b rw parity error response enable/disable setting this bit will enable the DM9102 to assert perr# on the detection of a data parity error and to assert serr# for reporting address parity error. 5 0b ro vga palette snooping (0 for no support) 4 0b ro memory write and invalid (0 for no implementation) the DM9102 only generates memory write cycle. 3 0b ro special cycles (0 for no implem entation) 2 1b rw master device capability enable/disable when this bit is set, DM9102 has the ability of master mode opera tion. 1 1b rw memory space access enable/disable this bit controls the ability of memory space access. the memory access includes memory mapped i/o access and boot rom access. as the system boots up, this bit will be enabled by bios for boot rom memory access. while in normal operation using memory m apped i/o acc ess, this bit should be set by driver before memory access cycles. 0 1b rw i/o space access enable/disable this bit controls the ability of i/o space access. it will be set by bios after power on.
DM9102 10/100mbps single chip lan controller final 17 version: DM9102-ds-f3 august 30, 2000 revision id (xxxxxx08 - pcirv) 31 0 7 8 revision id class code class code revision major number revision minor number 31 0 7 8 revision id class code class code revision major number revision minor number bit default type description 31:8 020000h ro class code (020000h) this is the standard code for ethernet lan controller. 7:4 0010b ro revision major number this is the silicon-major revision num ber that will increase for the subsequent versions of the DM9102. 3:0 0000b ro revision minor number this is the silicon-minor revision num ber that will increase for the subsequent versions of the DM9102. miscellaneous function (xxxxxx0c - pcilt) 31 16 15 0 87 23 24 bist header type latency timer cache line size built-in self test header type latency timer for the bus master cache line size for memory read
DM9102 10/100mbps single chip lan controller 18 final version: DM9102-ds-f03 august 30, 2000 bit default type description 31:24 00h ro built-in-self test (=00h means no implementation) 23:16 00h ro header type (= 00h means single function with predefined header type ) 15:8 00h rw latency timer for the bus master. the latency timer is guaranteed by the system and measured by clock cycles. when the frame# asserted at the beginning of a master period by the DM9102, the value will be copied into a counter and start counting down. if the frame# is de-asserted prior to count expiration, this v alue is meaningless. when the count expires before gnt# is de-asserted, the master transaction will be terminated as soon as the gnt# is removed. while gnt# signal is removed and the counter is non-zero, the DM9102 will continue with its data transfers until the count expires. the system host will read min_gnt and max_lat registers to determine the latency requirement for the device and then initialize the latency timer with an appropriate value. 7:0 00h ro cache-line size for memory read mode selection (00h means no implementation for use) i/o base address (xxxxxx10 - pciio) 31 0 1 6 7 1 000000 i/o base address i/o base address pci i/o range indication i/o or memory space indicator bit default type description 31:7 undefined rw pci i/o base address this is the base address value for i/o access cycles. it will be compared to ad[31:7] in the address phase of bus command cycle for the i/o resource access. 6:1 000000b ro pci i/o range indication it indicates that the minimum i/o resource size is 80h. 0 1b ro i/o space or memory space base indicator determines that the register maps into the i/o space.(=1 indicates i/o base) memory mapped base address (xxxxxx14 - pcimem) 31 0 1 6 7 000000 memory mapped base 0 memory base address memory range indication i/o or memory space indicator
DM9102 10/100mbps single chip lan controller final 19 version: DM9102-ds-f3 august 30, 2000 bit default type description 31:7 undefined r/w pci memory base address this is the base address value for memory access cycles. it will be compared to ad[31:7] in the address phase of bus comm and cycle for the memory resource access. 6:1 000000b ro pci memory range indication it indicates that the minimum memory resource size is 80h. 0 0b ro i/o space or memory space base indicator determines that the register maps into the memory space(=0 indicates memory base) subsystem identification (xxxxxx2c - pcisid) 0 31 subsystem id subsystem vendor id subsystem id subsystem vendor id bit default type description 31:16 xxxx h ro subsystem id node number l oaded from eeprom word 1 and different from each card. 15:0 xxxx h ro subsystem vendor id unique number given by pci sig and l oaded from eeprom word 0. expansion rom base address (xxxxxx30 - pcirom) 31 0 1 rom base address r/w 11 10 reserved 18 17 0000000 rom base address 9 00000000 bit default type description 31:10 00h rw rom base address with 256k b oundary pcirom bit17~10 are hardwi red to 0, indicating rom size is up to 256k size 9:1 000000000b ro reserved bits read as 0 0 0b rw expansion rom decoder enable/disable if this bit and the memory space access bit are both set to 1, the DM9102 will responds to its expansion rom.
DM9102 10/100mbps single chip lan controller 20 final version: DM9102-ds-f03 august 30, 2000 capabilities pointer (xxxxxx34 - cap _ptr) 0 0 0000 11 cap_ptr offset 34h 0 7 bit default type description 31:8 000000h ro reserved 7:0 01010000b ro c apability pointer the cap_ptr provides an offset (default is 50h) into the function ? s pci configuration space for the location of the first term in the capab ilities l inked list. the cap_ptr offset is double word aligned so the two least significant bits significant bits are always ? 0 ? s interrupt & latency configuration (xxxxxx3c - pciint) 31 16 15 0 87 23 24 max_lat min_gnt int_pin int_line maximum latency timer minimum grant interrupt pin interrupt line bit default type description 31:24 28h ro maximum latency timer that can be sustained (read only and read as 28h ) 23:16 14h ro minimum grant minimum length of a burst period (read only and read as 14h ) 15:8 01h ro interrupt pin read as 01h to indic ate inta# 7:0 xxh ro interrupt line that is routed to the interrupt controller device specific configuration register (xxxxxx40 - pciusr) 31 30 29 16 15 8 0 reserved 27 26 28 7 25 24 23 device specific device specific
DM9102 10/100mbps single chip lan controller final 21 version: DM9102-ds-f3 august 30, 2000 bit default type description 31 0b rw device specific bit (sleep mode) 30 0b rw device specific bit (snooze mode) 29 0b ro when set enable link status change wake-up event 28 0b ro when set enable sample frame wake-up event 27 0b ro when set enable magic packet wake-up event 26 0b ro when set, indicates link change and link status change event occurred 25 0b ro when set, indicates the sample frame is received and sample frame event occurred 24 0b ro when set, indicates the magic packet is received and magic packet event occurred 23:16 00h ro reserved bits read as 0 15:8 00h rw device specific 7:0 00h ro reserved bits read as 0
DM9102 10/100mbps single chip lan controller 22 final version: DM9102-ds-f03 august 30, 2000 control and status registers (cr) the DM9102 implement 16 control and status register, which can be accessed by the host. these crs are double long word ali gned. all crs are set to their default values by a hardware or a software reset unless otherwise specified. all control and status registers with their definitions and offset from io or memory base address are shown below : register description offset from csr base address default cr0 system control register 00h ffc00000 cr1 transmit descriptor poll demand 08h ffffffff cr2 receive descriptor poll demand 10h ffffffff cr3 receive descriptor base address register 18h 00000000 cr4 transmit descriptor base address register 20h 00000000 cr5 network status report register 28h fc000000 cr6 network operation mode register 30h 02400040 cr7 interrupt mask register 38h fffe0000 cr8 statistical counter register 40h 00000000 cr9 external management access register 48h fff097ff cr10 programming rom address register 50h unpredictable cr11 general purpose timer register 58h fffe0000 cr12 phy status register 60h ffffffxx cr13 access register 68h xxxxxx00 cr14 data register 70h unpredictable cr15 watchdog and jabber timer register 78h fffffec8 key to default in the register description that follows, the default column takes the form: , where : 1 bit set to logic one 0 bit set to logic zero x no default value : ro = read only rw = read/write wo = write only
DM9102 10/100mbps single chip lan controller final 23 version: DM9102-ds-f3 august 30, 2000 1. system control register (cr0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 0 0 00 bit name default description 21 mrm 0b,rw memory read multiple when set, the DM9102 will use memory read multiple command (c/be3~0 = 1100) when it initialize the memory read burst transaction as a master device. when reset, it will use memory read command (c/be3 ~ 0 = 0110) for the same master operation. 20 reserved 0b,rw must be zero 19:17 txap 000b,rw transmit automatic polling interval time when set, the DM9102 will poll the transmit descriptor automatically when it is in the suspend state due to buffer una vailable. the polling interval time is programmable based on the table shown below: bit 19 bit 18 bit 17 time interval 0 0 0 no polling 0 0 1 200us 0 1 0 800us 0 1 1 1.6ms 1 0 0 12.8us 1 0 1 25.6us 1 1 0 51.2us 1 1 1 102.4us 16 reserved 0b,rw must be zero 15:14 aba 00b,rw address boundary alignment when set, the DM9102 will execute each bu rst cycles to stop at the p rogr ammed address boundary. the address boundary can be progr ammed to be 8, 16, or 32 double-word as shown below. bit 15 bit 14 alignment boundary 0 0 reserved 0 1 8-double word 1 0 16-double word 1 1 32-double word 13:8 bl 000000b, rw burst length when reset, the DM9102 ? s burst length in one dma transfer is limited by the amount of data in the receive fifo ( when receive ) or the amount of free space in the transmit fifo (when transmit ). when set, the dma ? s burst length is limited by the programmed value. the permissible va lues are 0, 1, 2, 4, 8, 16, or 32 doublewords. 7 reserved 0,rw must be zero 6:2 dgw 00000,rw descriptor gap width the value of this field defines the gap width ( count in double-word ) between two continuous descriptor. it is used in ring-type descriptor structure. 1 reserved 0,rw must be zero
DM9102 10/100mbps single chip lan controller 24 final version: DM9102-ds-f03 august 30, 2000 bit name default description 0sr 0,rw software reset when set, the DM9102 will make a internal reset cycle. all consequent action to DM9102 should wait at least 32 pci clock cycles to start and no necessary to reset this 2. transmit descriptor poll demand (cr1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 bit name default description 31:0 tdp ffffffff h ,wo transmit descriptor polling command writing any value to this port will force DM9102 to poll the transmit descriptor. if the acting descriptor is not available, t ransmit process will return to suspend state. if the descriptor shows buffer available, transmit process will begin the data tr ansfer. 3. receive descriptor poll demand (cr2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 bit name default description 31:0 rdp ffffffffh ,wo receive descriptor polling command writing any value to this port will force DM9102 to poll the receive descriptor. if the acting descriptor is not available, receive process will re turn to suspend state. if the descriptor shows buffer available, receive process will begin the data transfer. 4. receive descriptor base address (cr3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 0 0 bit name default description 31:0 rdba 00000000h ,rw receive descriptor base address this register defines base address of receive descriptor-chain ( or descriptor-ring ) and must be double- word aligned. the receive descriptor- polling command a fter cr3 is set will make DM9102 to fetch the descriptor at the base-address. in ring- type structure, the descriptor pointer will go back to the base-address after end- descriptor of ring. bit1,0 must be ? 00 ? for double word alignment.
DM9102 10/100mbps single chip lan controller final 25 version: DM9102-ds-f3 august 30, 2000 5. transmit descriptor base address (cr4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 0 0 bit name default description 31:0 tdba 00000000h ,rw transmit descriptor base address this register defines base address of transmit descriptor-chain ( or descript or-ring ) and must be double- word aligned. the transmit descript or- polling comm and after cr4 is set will make DM9102 to fetch the descriptor at the base-address. in ring-type structure, the descriptor pointer will go back to the base-address after end-descriptor of ring. bit1,0 must be ? 00 ? for double word alignment. 6. network status report register (cr5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 bit name default description 25:23 sbeb 000,ro system bus error bits these bits are r ead only and used to indicate the type of system bus fetal error. valid only when system bus error is set. the mapping bits are shown below. bit25 bit24 bit23 bus error type 0 0 0 parity error 0 0 1 master abort 0 1 0 slave abort 0 1 1 reserved 1 x x reserved 22:20 txps 000,ro transmit process state these bits are r ead only and used to indicate the state of transmit pro cess. the mapping table is shown below. bit22 bit21 bit20 process state 0 0 0 transmit process stopped 0 0 1 fetch transmit descriptor 0 1 0 move setup frame from the host memory 0 1 1 move data from host memory to transmit fifo 1 0 0 close descriptor by clearing owner bit of descriptor 1 0 1 waiting end of transmit 1 1 0 transmit end and close descriptor by writing status 1 1 1 transmit process suspend 19:17 rxps 000b,ro receive process state these bits are r ead only and used to indicate the state of receive proc ess. the mapping table is shown below. bit19 bit18 bit17 process state
DM9102 10/100mbps single chip lan controller 26 final version: DM9102-ds-f03 august 30, 2000 0 0 0 receive process stopped 0 0 1 fetch receive descriptor 0 1 0 waiting for receive packet under buffer available 0 1 1 move data from receive fifo to host memory 1 0 0 close descriptor by clearing owner bit of descriptor 1 0 1 close descriptor by writing status 1 1 0 receive process suspended due to buffer unavailable 1 1 1 purge the current frame from the receive fifo because of unava ilable receive buffer 16 nis 0b,rw normal interrupt summary normal interrupt includes any of the th ree con ditions : cr5<0> ? txci : transmit compl ete in terrupt cr5<2> ? txdu : transmit buffer unavailable cr5<6> ? rxci : receive complete interrupt 15 ais 0b,rw abnormal interrupt summary abnormal interrupt includes any interrupt condition as shown below excluding normal interrupt conditions. they are txps(bit1), txjt(bit3), txfu(bit5), rxdu(bit7), rxps(bit8), rxwt(bit9), txer(bit10), gpt(bit11), sbe(bit13). 13 sbe 0b,rw system bus error the pci system bus errors will set this bit. the type of system bus error is shown in cr5<25:23> . 11 gpt 0b,rw general-purpose timer expired this bit is set to indicate the general-purpose timer (described in cr11) has expired. 10 txer 0b,rw transmit early interrupt transmit early interrupt is set when the full packet data has been moved from host memory into transmit fifo. it will inform the host to process next step before the transmission end. transmit complete event cr5<0> will clear this bit automatically. 9 rxwt 0b,rw receive watchdog timer expired this bit is set to indicate receive watchdog timer has expired. 8 rxps 0b,rw receive process stopped this bit is set to indicate receive process enters the st opped state. 7 rxdu 0b,rw receive buffer unavailable this bit is set when the DM9102 fetches the next receive descriptor is still owned by the host. receive process will be suspended until a new frame enters or the re ceive polling command is set. 6 rxci 0b,rw receive complete interrupt this bit is set when a received f rame is fully moved into host memory and receive status has been written to descriptor. receive proc ess is still running and continues to fetch next descriptor. 5 txfu 0b,rw transmit fifo under-run this bit is set when the transmit fifo has a under-run condition during the pa cket transmission. it may happen due to the heavy load on bus, receive process dominate in full-duplex, or transmit buffer unavailable before end of packet. in this case, tran smit process is placed in the suspend state and under-run error tdes0<1> is set. 3 txjt 0b,rw transmit jabber timer expired this bit is set when the jabber timer expired with the transmitter is still active. transmit process will be aborted and placed in the stop state. it also c auses transmit jabber timeout tdes0<14> to assert. 2 txdu 0b,rw transmit buffer unavailable this bit is set when the DM9102 fetches the next transmit descriptor that is still owned by the host. the transmit process will be sus pended until the transmit
DM9102 10/100mbps single chip lan controller final 27 version: DM9102-ds-f3 august 30, 2000 polling command is set or auto-polling timer time-out. 1 txps 0b,rw transmit process stopped this bit is set to indicate transmit process enters the stopped state. 0 txci 0b,rw transmit complete interrupt this bit is set when a frame is fully transmitted and the transmit status has been writen to descriptor ( the tdes1<31> is also asserted). the transmit process is st ill r unning and continues to fetch next descriptor. note: bits 1~16 can be cleared by writing ?1? 7. network operation mode register (cr6) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 0 00 1 1 0 0 00 0 0 bit name default description 30 rxa 0b,rw receive all when set, all incoming packet will be received, regardless the destination address. the address match is checked according to thecr6<7>, cr6<6>, cr6<4>, cr6<2>, cr6<0>, and rdes0<30> will show this match. 28:26 reserved 000b,rw must be zero. 25 reserved 1b,rw must be one. 24:23 reserved 00b,rw must be zero. 22 txtm 1b,rw transmit threshold mode when set, the transmit threshold mode is 10mb/s. when reset, the threshold mode is 100mb/s. this bit is used together with cr6<15:14> to decide the exact threshold level. 21 sft 0b,rw store and forward transmit when set, the packet transmission from mac will be started after a full frame has been moved from the host memory to transmit fifo. when reset, the packet transmission ? s start will depend on the threshold value specified in cr6<15:14> 20 sti 0b,rw start transmission immediately when this bit is set, the packet transmission from mac will be started immediately after transmit fifo ? s threshold level reaches 16 bytes, regardless of the setting in cr6<22> and cr6<15:14>. this mode will make transmit fifo underrun condition to happen more easily. 18:19 mbo 00b,rw must always write ? 11 ? to these two bits. 17 reserved 0b,rw must be zero. 16 reserved 0b,rw must be zero.
DM9102 10/100mbps single chip lan controller 28 final version: DM9102-ds-f03 august 30, 2000 15:14 tsb 00b,rw threshold bits these bits are set together with cr6<22> (chose 10mb or 100mb) and will decide the exact fifo thres hold level. the packet transmiss ion will start after the data level exceeds the threshold value. bit15 bit14 threshold(100m ) threshold(10m) 0 0 128 72 0 1 256 96 1 0 512 128 1 1 reserved reserved 13 txsc 0b,rw transmit start/stop command when set, the transmit process will begin by fetching the transmit descriptor for available packet data to be transmitted (running state). if the fetched descriptor is owned by the host, the transmit process will enter the suspend state and tran smit buffer unavailable (cr5<2>) is set. otherwise it will begin to move data from host to fifo and transmit out after reaching threshold level. when reset, the transmit process is placed in the stopped state after completing the transmission of the current frame. 12 fcm 0b,rw force collision mode when set, the transmission proc ess is for ced to be the collision status. meaningful only in the internal loopback mode. 11:10 lbm 00b,rw loopback mode these bits decide two loopback modes besides normal operation. external loopback mode expects transmitted data back to receive path and makes no c ollision detection. bit11 bit10 loopback mode 0 0 normal 0 1 internal loopback 1 x external loopback 9 fdm 0b,rw full-duplex mode when auto- negotia tion is di sabled, this bit is set to make dm 9102 operate in the full-duplex mode. transmit and receive processes can work simultaneously. there is no collision detection needed during this m ode operat ion. 7 pam 0b,rw pass all multicast when set, any packet with a multicast destination address is received by DM9102. the packet with a physical address will also be filte red based on the cr6<0> filter mode setting. 6 pm 1b,rw promiscuous mode when set, any incoming valid frame is received by DM9102, and no matter what the destination address. the dm 9102 is initialized to this m ode after reset operation. 5 reserved 0b,rw must be zero. 4 iafm 0b,ro inverse address filtering mode it is set to indicate the DM9102 operate in a inverse filtering m ode. this is a read only bit and mapped from the setup frame together with cr6<2>, cr6<0> setting. that is it is valid only during perfect filtering mode. 3 pbf 0b,rw pass bad frame when set, the DM9102 is indicated to receive the bad frames including runt packets, truncated frames caused by the fifo overflow. the bad f rame also has to pass the address filtering if the DM9102 is not set in promiscuous m ode.
DM9102 10/100mbps single chip lan controller final 29 version: DM9102-ds-f3 august 30, 2000 2 hofm 0b,ro hash-only filter mode this is a read-only bit and mapped from the set-up frame together with bit4,0 of cr6. it is set to indicate the DM9102 operate in a hash-only filtering m ode. 1 rxrc 0b,rw receive start/stop command when set, the receive process will begin by fetching the receive descrip tor for available buffer to store the new-coming packet (placed in the running state). if the fetched descriptor is owned by the host (no desc riptor is ow ned by the DM9102), the receive process will enter the suspend state and receive buffer unavailable cr5<7> sets. otherwise it runs to wait for the packet ? s income. when reset, the receive process is placed in the stopped state after completing the reception of the current frame. 0 hpfm 0b,ro hash/perfect filter mode this is a read only bit and mapped from the setup frame together with cr6<4>, cr6<2>. when reset, the DM9102 does a perfect address filter of incoming frames according to the addresses spe cified in the s etup f rame. when set, the dm 9102 does a imperfect address filtering for the incoming frame with a multicast address according to the hash t able speci fied in the setup frame. the filter ing mode (perfect/imperfect) for the frame with a physical address will depend on cr6<2>. 8. interrupt mask register (cr7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 bit name default description 16 nise 0b,rw normal interrupt summary enable this bit is set to enable the interrupt for normal interrupt summary. normal interrupt includes three conditions : cr5<0> ? txci : transmit compl ete in terrupt cr5<2> ? txdu : transmit buffer unavailable cr5<6> ? rxci : receive complete interrupt 15 aise 0b,rw abnormal interrupt summary enable this bit is set to enable the interrupt for abnormal interrupt summary. abnormal interrupt includes all interrupt condition as shown below excluding normal interrupt conditions. they are txps(bit1), txjt(bit3), txfu(bit5), rxdu(bit7), rxps(bit8), rxwt(bit9), txer(bit10), gpt(bit11), sbe(bit13). 13 sbee 0b,rw system bus error enable when set together with cr7<15>, cr5<13>, it enables the interrupt for system bus error. the type of system bus error is shown in cr5<24:23>. 11 gpte 0b,rw general-purpose timer expired enable this bit is set together with cr7<15>, cr5<11> then it will enable the interrupt for the condition of the general-purpose timer (descri bed in cr11) expired. 10 txere 0b,rw transmit early interrupt enable this bit is set together with cr7<16>, cr5<10> then it enables the interrupt of the early transmit event. 9 rxwte 0b,rw receive watchdog timer expired enable when this bit and cr7<15>, (cr5<9> are set together, it enable the in terrupt of the condition of the receive watchdog timer expired.
DM9102 10/100mbps single chip lan controller 30 final version: DM9102-ds-f03 august 30, 2000 8 rxpse 0b,rw receive process stopped enable when set together with cr7<15> and cr 5<8>. this bit is set to enable the interrupt of receive process stopped condition. 7 rxdue 0b,rw receive buffer unavailable enable when this bit and cr7<15>, cr5<7> are set together, it will enable the interrupt of receive buffer unavailable condition. 6 rxcie 0b,rw receive complete interrupt enable when this bit and cr7<16>, cr5<6> are set together, it will enable the interrupt of receive process completed condition. 5 txfue 0b,rw transmit fifo under-run enable when set together with cr7<15>, cr 5<5>, it will enable the in terrupt of the transmit fifo under-run condition. 3 txjte 0b,rw transmit jabber timer expired enable when this bit and cr7<15>, cr5<3> are set together, it enables the interrupt of transmit jabber timer expired condition. 2 txdue 0b,rw transmit buffer unavailable enable when this bit and cr7<16>, cr5<2> are set together, the transmit buffer unavailable interrupt is enabled. 1 txpse 0b,rw transmit process stopped enable when this bit is set together with cr7<15> and cr5<1>, it will enable the interrupt of the transmit process stopped 0 txcie 0b,rw transmit complete interrupt enable when this bit and cr7<16>, cr5<0> are set, transmit interrupt is enabled. 9. statistical counter register (cr8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 bit name default description 31 rxfu 0b,ro receive overflow counter overflow this bit is set when the purged packet counter (rxdu) has an overflow condition. it is a read only register bit. 30:17 rxdu 0000h,ro receive purged packet counter this is a statistic counter to indicate the purged received packet count upon fifo overflow. 16 rxps 0b,ro receive missed counter overflow this bit is set when the receive missed frame counter (rxci) has an overflow condition. it is a r ead only register bit. 15:0 rxci 0000h,ro receive missed frame counter this is a statistic counter to indicate the receive missed frame count when there is a host buffer unava ilable condit ion for receive proc ess. note : cr8 is cleared after read
DM9102 10/100mbps single chip lan controller final 31 version: DM9102-ds-f3 august 30, 2000 10. prom & management access register (cr9) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10 15 9 8 bit name default description 19 mdin 0b,ro mii management data_in this is read only bit to indicate the mdio input data. 18 mrw 0b,rw mii management read/write mode selection this bit defines the read/write mode for mii m anagement interface for phy access. 17 mdout 0b,rw mii management data_out this bit is used to gener ate the output data signal for the mdio pin. 16 mdclk 0b,rw mii management clock this bit is used to gener ate the output clock signal for the mdc pin. 14 mrc 0b,rw memory read control this bit is set to perform the read operation for the boot prom or eeprom access. 13 ewc 0b,rw memory write control this bit is set to perform the write operation for the boot prom (m ultiplex mode) or eeprom access. 12 brs 1b,rw boot rom selected this bit is set to select the boot rom access for memory interface. 11 ers 0b,rw eeprom selected this bit is set to select the eeprom access for memory interface. 10 xrs 0b,rw external register selected this bit is set to select an external register. 7:0 data ffh,rw data input/output of boot rom this field contains the data read from or write to the boot rom when the boot rom mode is selected. (cr9<12> = 1) if eeprom is selected (cr9<11> = 1), then cr9<3:0> are connected the serial rom control pins. 3 crdout 1b,ro data_out from eeprom this bit is set to reflect the signal status of eedi pin when eeprom m ode is selected. 2 crdin 0b,rw data_in to eeprom this bit is set to generate the o utput signal to eedo pin when eeprom mode is selected. 1 crclk 0b,rw clock to eeprom this bit is set to generate the o utput clock to ee clk pin when eeprom m ode is selected. 0 crcs 0b,rw chip_select to eeprom this bit is set to generate the o utput signal to eecs pin when eeprom m ode is selected.
DM9102 10/100mbps single chip lan controller 32 final version: DM9102-ds-f03 august 30, 2000 11. programming rom address register (cr10) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 bit name default description 17:0 badr unpredictable boot rom address this field contains the address pointer for boot rom when the mode of programming by register is selected. 12. general purpose timer register (cr11) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 bit name default description 16 tcon 0b,rw continuous mode of timer when this bit is set, the timer will conti nuously re-initiated upon the set time is up. when reset, the timer will be one-shot response after bclk value is programmed. 15:0 mbclk 0000h,rw multiple of base clock this field set the iteration number of base clock. the base clock duration is defined to be 81.92us --- for mii port/ 100m is selected 2us --- for mii port/10m is selected 13. phy status register (cr12) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 bit name default description 8 gepc x b, rw gepd bits control when in initialization, this bit is set and the uni que ? 80h ? must be written to the gepd(7:0). after initialization, this bit is reset and it controls the functional mode of gepd in bit0~7. 7 gepd(7) x b, rw general phy reset control it must be set to ? 1 ? if cr12<8> is set. when cr12<8> is reset, write ? 1 ? to this bit will reset the phy of the DM9102.
DM9102 10/100mbps single chip lan controller final 33 version: DM9102-ds-f3 august 30, 2000 6:0 gepd(6:0) xxxxxxx b ,rw general phy status when cr12<8> is set at initialization, it operates the only write operation and write the unique ?0000000? to these seven bits. after initialization, cr12<8> is reset, write opera tion is mean ingless and read these seven b its to indicate the phy s tatus. these status bits are shown below. bit 6:utp-sig bit 5:signal detection bit 4:rx-lock bit 3:link status (the same as bit2 of phy register) bit 2:full-duplex bit 1:speed 100mbps link bit 0:speed 10mbps link 14. access register (cr13) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 54 3 2 1 0 register general definition bit8 ~ 3 r/w txfifo transmit fifo access port 32h r/w rxfifo receive fifo access port 35h r/w diagreset general reset for di agnostic pointer port 38h w 15. data register (cr14) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 16. watchdog and jabber timer register (cr15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 0 bit name default description 8 reserved 0b,rw must be zero. 5 twdr 0b,rw time interval of watchdog release this bit is used to select the time interval between receive watc hdog timer expiration until re-enabling of the receive channel. when this bit is set, the time interval is 40~48 bits time. when this bit is reset, it is 16~24 bits time. 4 twde 0b,rw watchdog timer disable when set, the watchdog timer is disabled. otherwise it is enabled.
DM9102 10/100mbps single chip lan controller 34 final version: DM9102-ds-f03 august 30, 2000 2 jc 0b,rw jabber clock when set, the transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted. when reset, transmiss ion for the 10mbps port is cut off after a r ange of 26ms to 33ms. when reset, transmiss ion for the 100mbps port is cut off after a range of 2.6ms to 3.3ms. 1 tunj 0b,rw transmit un-jabber interval this bit is used to select the time interval between the transmit jabber timer expiration until re-enabling of the transmit channel. when set, the transmit channel is released right after the jabber expiration. when reset, the time interval is 365~420ms for 10mb/s port and 36.5~42.0ms for 100mb/s. 0 tje 0b,rw transmit jabber disable when set, the transmit jabber timer is disabled. otherwise it is enabled. phy management register set register address register name description 0 bmcr basic mode control register 1 bmsr basic mode status register 2 phyidr1 phy identifier register #1 3 phyidr2 phy identifier register #2 4 anar auto-negotiation advertisement register 5 anlpar auto-negotiation link partner ability register 6 aner auto-negotiation expansion register 7-15 reserved reserved 16 dscr davicom specified configuration register 17 dscsr davicom specified configuration/status register 18 10btcsr 10base-t configuration/status register others reserved reserved for future use-do not read/write to these registers key to default in the register description that follows, the default column takes the form: , / where : 1 bit set to logic one 0 bit set to logic zero x no default value (pin#) value latched in from pin # at reset : ro = read only rw = read/write : sc = self clearing p = value permanently set ll = latching low lh = latching high
DM9102 10/100mbps single chip lan controller final 35 version: DM9102-ds-f3 august 30, 2000 basic mode control register (bmcr) - register 0 bit name default description 0.15 reset 0b, rw/sc reset: 1=software reset 0=normal operation this bit sets the status and controls the phy registers of DM9102 to their default states. this bit, which is self-clearing, will keep returning a value of one until the reset proc ess is comp leted 0.14 loopback 0b, rw loopback: loop-back control register 1=loop-back enabled 0=normal operation when in 100mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appear at the mii receive outputs 0.13 speed selection 1b, rw speed select: 1=100mbps 0=10mbps link speed may be selected either by this bit or by auto- negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected media type. 0.12 auto- negotiation enable 1b, rw auto-negotiation enable: 1= auto-negotiation enabled: bit 8 and 13 will be in auto- negotiation status 0= auto-negotiation disabled: bit 8 and 13 will determine the link speed and mode 0.11 power down 0b, rw power down: setting this bit will power down the whole chip except crystal oscillator circuit. 1=power down 0=normal operation 0.10 isolate (phyad=00000b) ,rw isolate: 1= isolates the DM9102 from the mii with the exception of the serial management. 0= normal operation 0.9 restart auto- negotiation 0b,rw/sc restart auto-negotiation: 1= restart auto-negotiation. re-initiates the auto-negotiation process. when auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning a value of 1 until auto-negotia tion is init iated by the DM9102. the operation of the auto-negotiation process will not be affected by the m anage ment e ntity that clears this bit 0= normal operation 0.8 duplex mode 1b,rw duplex mode: 1= full duplex operation. duplex selection is allowed when auto- negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bit refle cts the duplex capability selected by auto-negotiation 0= normal operation
DM9102 10/100mbps single chip lan controller 36 final version: DM9102-ds-f03 august 30, 2000 0.7 collision test 0b,rw collision test: 1= collision test enabled. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en 0= normal operation 0.6:0.0 reserved 0000000b,ro reserved: write as 0, ignore on read basic mode status register (bmsr) - register 1 bit name default description 1.15 100base-t4 0b,ro/p 100base-t4 capable: 1=DM9102 is able to perform in 100base-t4 mode 0=DM9102 is not able to perform in 100base-t4 mode 1.14 100base-tx full duplex 1b,ro/p 100base-tx full duplex capable: 1= DM9102 able to perform 100base-tx in full dup lex mode 0= DM9102 not able to perform 100 base-tx in full duplex mode 1.13 100base-tx half duplex 1b,ro/p 100base-tx half duplex capable: 1=DM9102 is able to perform 100 base-tx in half duplex mode 0=DM9102 is not able to perform 100base-tx in half duplex mode 1.12 10base-t full duplex 1b,ro/p 10base-t full duplex capable: 1=DM9102 is able to perform 10base-t in full duplex mode 0=DM9102 is not able to perform 10base-t in full duplex mode 1.11 10base-t half duplex 1b,ro/p 10base-t half duplex capable: 1=DM9102 is able to perform 10base-t in half duplex mode 0=DM9102 is not able to perform 10base-t in half duplex mode 1.10-1.7 reserved 0000b ,ro reserved: write as 0, ignore on read 1.6 mf preamble suppression 0b,ro mii frame preamble suppression: 1=phy will accept management frames with pr eamble suppressed 0=phy will not accept management frames with preamble suppressed 1.5 auto-negotiation complete 0b,ro auto-negotiation complete: 1=auto-negotiation process completed 0=auto-negotiation process not completed 1.4 remote fault 0b, ro/lh remote fault: 1= remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection met hod is d m9102 implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0= no remote fault condition detected 1.3 auto-negotiation ability 1b,ro/p auto configuration ability: 1=DM9102 able to perform auto- negotiation 0=DM9102 not able to perform auto-negotiation 1.2 link status 0b ,ro/ll link status: 1=valid link established (for either 10mbps or 100mbps operation) 0=link not established the link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain c leared until it is r ead via the manage ment interface 1.1 jabber detect 0b, jabber detect:
DM9102 10/100mbps single chip lan controller final 37 version: DM9102-ds-f3 august 30, 2000 ro/lh 1=jabber condition detected 0=no jabber this bit is implemented with a latching function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9102 reset. this bit works only in 10mbps mode 1.0 extended capability 1b,ro/p extended capability: 1=extended register capability 0=basic register capability only phy id identifier register #1 (phyidr1) - register 2 the phy identifier registers #1 and #2 work together in a single identifier of the d m9102. the i dentifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit name default description 2.15-2.0 oui_msb <0181h> oui most significant bits: this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the m ost significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) phy identifier register #2 (phyidr2) - register 3 bit name default description 3.15-3.10 oui_lsb <101110b> ,ro/p oui least significant bits: bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 3.9-3.4 vndr_mdl <000000b> ,ro/p vendor m odel number: six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0 mdl_rev <0000b>,ro/p model revision number: four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3) auto-negotiation advertisement register (anar) - register 4 this register contains the advertised abilities of this DM9102 device as they will be transmitted to its link partner during auto-negotiation. bit name default description 4.15 np 0b,ro/p next page indication: 0=no next page available 1=next page available the DM9102 has no next page, so this bit is perm anently set to 0 4.14 ack 0b,ro acknowledge: 1=link partner ability data reception acknowledged 0=not acknowledged the DM9102's auto-negotiation state machine will automatically control this bit in the outgoing flp bu rsts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 4.13 rf 0b, rw remote fault: 1=local device senses a fault condition
DM9102 10/100mbps single chip lan controller 38 final version: DM9102-ds-f03 august 30, 2000 0=no fault detected 4.12-4.11 reserved 00b, rw reserved: write as 0, ignore on read 4.10 fcs 0b, rw flow control support: 1=controller chip supports flow control ability 0=controller chip doesn?t support flow control ability 4.9 t4 0b, ro/p 100base-t4 support: 1=100base-t4 supported by the local device 0=100base-t4 not supported the DM9102 does not support 100base-t4 so this bit is permanently set to 0 4.8 tx_fdx 1b, rw 100base-tx full duplex support: 1=100base-tx full duplex supported by the local device 0=100base-tx full duplex not supported 4.7 tx_hdx 1b, rw 100base-tx support: 1=100base-tx supported by the local device 0=100base-tx not supported 4.6 10_fdx 1b, rw 10base-t full duplex support: 1=10base-t full duplex supported by the local device 0=10base-t full duplex not supported 4.5 10_hdx 1b, rw 10base-t support: 1=10base-t supported by the local device 0=10base-t not supported 4.4-4.0 selector <00001b>, rw protocol selection bits: these bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports ieee 802.3 csma/cd. auto-negotiation link partner ability register (anlpar) - reg ister 5 this register contains the advertised abilities of the link partner when received during auto- negotiation. bit name default description 5.15 np 0b, ro next page indication: 0= link partner, no next page avai lable 1= link partner, next page available 5.14 ack 0b, ro acknowledge: 1=link partner ability data reception acknowledged 0=not acknowledged the DM9102's auto-negotiation state machine will automatically control this bit from the incoming flp bursts. software should not attempt to write to this bit. 5.13 rf 0b, ro remote fault: 1=remote fault indicated by link partner 0=no remote fault indicated by link partner 5.12-5.10 reserved 000b, ro reserved: write as 0, ignore on read 5.9 t4 0b, ro 100base-t4 support: 1=100base-t4 supported by the link partner 0=100base-t4 not supported by the link partner 5.8 tx_fdx 0b, ro 100base-tx full duplex support:
DM9102 10/100mbps single chip lan controller final 39 version: DM9102-ds-f3 august 30, 2000 1=100base-tx full duplex supported by the link partner 0=100base-tx full duplex not supported by the link partner 5.7 tx_hdx 0b, ro 100base-tx support: 1=100base-tx half duplex supported by the link partner 0=100base-tx half duplex not supported by the link partner 5.6 10_fdx 0b, ro 10base-t full duplex support: 1=10base-t full duplex supported by the link partner 0=10base-t full duplex not supported by the link partner 5.5 10_hdx 0b, ro 10base-t support: 1=10base-t half duplex supported by the link partner 0=10base-t half duplex not supported by the link partner 5.4-5.0 selector <00000b>, ro protocol selection bits: link partner?s binary encoded protocol selector auto-negotiation expansion register (aner)-register 6 bit name default description 6.15-6.5 reserved 0b, ro reserved: write as 0, ignore on read 6.4 pdf 0b, ro/lh local device parallel detection fault: pdf=1: a fault detected via parallel detection function. pdf=0: no fault detected via parallel detection function 6.3 lp_np_able 0b, ro link partner next page able: lp_np_able=1: link partner, next page available lp_np_able=0: link partner, no next page 6.2 np_able 0b,ro/p local device next page able: np_able=1: DM9102, next page available np_able=0: DM9102, no next page DM9102 does not support this function, so this bit is always 0. 6.1 page_rx 0b, ro/lh new page received: a new link code word page received. this bit will be automatically cl eared when the register (register 6) is r ead by management 6.0 lp_an_able 0b, ro link partner auto-negotiation able: a ? 1 ? in this bit indicates that the link partner supports auto-negotiation. davicom specified configuration register (dscr) - register 16 bit name default description 16.15:16.13 reserved 0b, rw reserved 16.12 reserved 0b, rw this bit must set to be 0. 16.11 reserved 0b, rw this bit must set to be 0 16.10 tx 1b, rw this bit must set to be 1 16.9 utp 1b, rw utp cable control: 1=the media is a utp cable, 0=stp 16.8 reserved 0b, rw reserved 16.7 f_link_100 0b, rw force good link in 100mbps: 0=normal 100mbps operation 1=force 100mbps good link status this bit is useful for diagnostic purposes. 16.6 reserved 1b, rw this bit must forced to be 1.
DM9102 10/100mbps single chip lan controller 40 final version: DM9102-ds-f03 august 30, 2000 16.5 led_ctl 0b,rw led mode select: (control ledtrf, led100m, led10m) 0 = ledtrf is activity led, and led 100m indi cates good link to 100mbps, led10m indicates good link to 10mbps . 1 = ledtrf is no use, led100m, led10m indicate link and activity. when good links to 100mbps, led100m actives and flashes if any traffic exists. when good links to 10mbps, led10m actives and flashes if any traffic exists. 16.4 reserved 0b,rw this bit must forced to be 0 16.3 smrst 0b,rw reset state machine: when write 1 to this bit, all state machines of phy will be reset. this bit is self-clear after reset is compl eted. 16.2 mfpsc 0b,rw mf preamble suppression control: mii frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off 16.1 sleep 0b,rw sleep mode: writing a 1 to this bit will cause phy entering the sleep mode and power down all circuit except oscillator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset 16.0 rlout 0b,rw remote loop out control: when this bit is set to 1, the received data will l oop out to the transmit channel. this is useful for bit error rate testing davicom specified configuration and status register (dscsr) - register 17 bit name default description 17.15 100fdx 1b, ro 100m full duplex operation m ode: after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 m ode is a 100mbps full duplex mode. the software can read bit[15:12] to see which mode is selected after auto-negotiation. this bit is invalid w hen it is not in the auto-negotiation mode. 17.14 100hdx 1b, ro 100m half duplex operation mode: after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 m ode is a 100mbps half-duplex mode. the software can read bit[15:12] to see which mode is selected after auto-negotiation. this bit is invalid w hen it is not in the auto-negotiation mode. 17.13 10fdx 1b, ro 10m full duplex operation mode: after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10mbps full duplex mode. the software can read bit[15:12] to see which mode is selected after auto-negotiation. this bit is invalid w hen it is not in the auto-negotiation mode. 17.12 10hdx 1b, ro 10m half duplex operation mode: after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 m ode is a 10mbps half duplex mode. the software can read bit[15:12] to see which mode is selected after auto-negotiation. this bit is invalid w hen it is not in the auto-negotiation mode.
DM9102 10/100mbps single chip lan controller final 41 version: DM9102-ds-f3 august 30, 2000 17.11-17.9 reserved 000b, rw reserved: write as 0, ignore on read 17.8-17.4 phyad[4:0] 00001b, rw phy address bit 4:0: the first phy address bit transmitted or received is the msb of the address (bit 4). a stat ion management entity connected to multiple phy entities must know the appropriate address of each phy. a phy address of <00000> will cause the isolate bit of the bmcr (bit 10, register address 00) to be set. 17.3-17.0 anmb[3:0] 0000b, ro auto-negotiation monitor bits: these bits are for debug only. the auto- negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 i n i d l e s t a t e 0 0 0 0 ability match 0 0 1 0 a c k n o w l e d g e m a t c h 0011acknowledge match fail 0 1 0 0 c o n s i s t e n c y m a t c h 0101consistency match fail 0 1 1 0 p a r a l l e l d e t e c t s s i g n a l _ l i n k _ r e a d y 0 1 1 1 parallel detects signal_link_ready fail 1 0 0 0 a u t o - n e g o t i a t i o n c o m p l e t e d successfully 10base-t configuration/status (10btcsrcsr) - register 18 bit name default description 18.15 reserved 0b, ro reserved: write as 0, ignore on read 18.14 lp_en 1b, rw link pulse enable: 1=transmission of link pulses enabled 0=link pulses disabled, good link condition forced this bit is valid only in 10mbps operation. 18.13 hbe 1b,rw heartbeat enable: 1=heartbeat function enabled 0=heartbeat function disabled when the DM9102 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode). it must set to be 1. 18.12 reserved 0b, ro reserved: write as 0, ignore on read 18.11 jaben 1b, rw jabber enable: enables or disables the jabber function when the DM9102 is in 10base-t full duplex or 10base-t transceiver loopback mode 1= jabber function enabled 0= jabber function disabled 18.10 reserved 0b,rw reserved 18.9-18.1 reserved 0b, ro reserved 18.0 reserved 0b, ro reserved
DM9102 10/100mbps single chip lan controller 42 final version: DM9102-ds-f03 august 30, 2000 functional description system buffer management 1. overview the data buffers for reception and transmission which data reside in the host memory. they are directed with the descriptor li sts that are located in another region of the host memory. all actions for the buffer management are operated by the DM9102 in conjunction with the driver. the data structures and processing a lgorithms are des cribed in the following text. 2. data structure and descr iptor list there are two types of buffers that reside in the host memory, the transmit bu ffer and the receive buffer. the buffers are composed of many distributed regions in the host memory. they are linked together and controlled by the descriptor lists that reside in another region of the host memory. the content of each descriptor includes pointer to the buffer, count of the buffer, comm and and status for the packet to be transmitted or received. each descriptor list starts from the address setting of cr3 (receive descriptor base address) and cr4 (transmit descriptor base address). the descriptor lists have two types of structure, ring structure and chain structure. 3. buffer management: ring structure method as the ring structure depicted below, the descriptors are linked directly one after another. the first and last descriptor on the list has the necessary information for the DM9102 to return to the beginning of the list after the bottom descriptor is accessed. each descriptor poi nts to the two buffer regions and one packet may cross many descriptor boundaries. buffer 1 buffer 2 buffer 1 buffer 2 descriptor 1 descriptor n packet n control buffer address 1 buffer address 2 status own buffer 2 length buffer 1 length
DM9102 10/100mbps single chip lan controller final 43 version: DM9102-ds-f3 august 30, 2000 4. buffer management: chain structure method as the chain structure depicted below, each descriptor contains two pointers, one point to a single buffer and the other to the next descriptor chained. the first descriptor is chained with the last descriptor under host driver?s control. with this structure, a descriptor can be allocated anywhere in host memory and is chained to the next descriptor. the chain structure and the ring structure may be combined to make the buffer structure more flexible. buffer 1 buffer 1 descriptor 1 descriptor n packet n control buffer address 1 status own not valid next descriptor address buffer 1 length 5. descriptor list: buffer descriptor format (a). receive descriptor format each receive descriptor has four double-word entries and may be read or written by the host or the DM9102. the descriptor format is shown below with a detailed functional description. 31 0 own status control bits buffer address 1 buffer address 2 rdes0 rdes1 rdes2 rdes3 buffer 1 length buffer 2 length own receive descriptor format
DM9102 10/100mbps single chip lan controller 44 final version: DM9102-ds-f03 august 30, 2000 rdes0: owner bit with receive status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 own frame length ( fl ) aun own: 1=owned by DM9102, 0=owned by host this bit should be reset after packet reception is completed. it will be set by the host after received data are removed. fl: frame length indicating total byte count of received packet. aun: received address unmatched. 151413121110 9 8 7 6 5 4 3 2 1 0 es rf ce mf due lbom bd ed tlf lcs ft rwt ple ae foe efl this word-wide content includes status of received frame. they are loaded after the received buffer that belongs to the corresponding descriptor is full. all status bits are valid only when the last descriptor (end descriptor) bit is set. bit 15: es, error summary it is set for the following error conditions: descriptor unavailable error (due =1), runt frame (rf=1), excessive frame length (efl=1), late collision seen (lcs=1), crc error (ce=1), fifo overflow error (foe=1). valid only when ed is set. bit 14: due, descriptor unavailable error it is set when the frame is truncated due to the buffer unavailable. it is valid only when ed is set. bit 13,12: lbom, loopback operation mode these two bits show the received f rame is derived from 00 --- normal operation 01 --- internal loopback 10 --- external loopback 11 --- reserved bit 11: rf, runt frame it is set to indicate the received f rame has the size smaller than 64 bytes. valid only when ed is set and foe is reset. bit 10: mf, multicast frame it is set to indicate the received f rame has a multicast address. valid only when ed is set. bit 9: bd, begin descriptor this bit is set for the descriptor indicating start of a received frame. bit 8: ed, ending descriptor this bit is set for the descriptor indicates end of a received frame. bit 7: efl, excessive frame length it is set to indicate the received frame length exceeds 1518 bytes. valid only when ed is set. bit 6: lcs: late collision seen it is set to indicate a late collision found during the frame reception. valid only when ed is set. bit 5: ft, frame type it is set to indicate the received f rame is the ethernet-type. it is reset to indicate the received frame is the eee802.3- type. valid only when ed is set bit 4: rwt, receive watchdog timeout it is set to indicate receive watchdog time-out during the frame reception. cr5<9> will also be set. valid only when ed is set. bit 3: ple, physical layer error it is set to indicate a physical layer error found during the frame reception. bit 2: ae, alignment error it is set to indicate the received f rame ends with a non-byte boundary. bit 1: ce, crc error it is set to indicate the received f rame ends with a crc error. valid only when ed is set. bit 0: foe, fifo overflow error this bit is valid for ending descriptor is set. (ed = 1) it is set to indicate a fifo overflow error happens during the frame reception.
DM9102 10/100mbps single chip lan controller final 45 version: DM9102-ds-f3 august 30, 2000 rdes1: descriptor status and buffer size 31 30 29 28 27 26 25 24 23 22 21 ~ 11 10 ~ 0 eor ce buffer 2 length buffer 1 length bit 25: eor, end of ring set to indicate that the descriptor is located on the bottom of the descriptor list. bit 24: ce, chain enable set to indicate that the second address is the chained descriptor instead of the other buffer. used as the indication of the chain structure. bit 21-11: buffer 2 length indicates the size of the second buffer. it has no meaning in chain type descriptor. bit 10-0: buffer 1 length indicates the size of the first buffer in ring type structure and single buffer in chain type structure. rdes2: buffer 1 starting address indicates the physical starting address of buffer 1. 31 0 buffer address 1 rdes3: buffer 2 starting address indicates the physical starting address of buffer 2 under the ring structure and that of the chained descriptor under the chain descriptor structure. 31 0 buffer address 2 (b). transmit descriptor format each transmit descriptor has four doubleword content and may be read or written by the host or by the DM9102. the descriptor format is shown below with detailed description. 31 0 own status control bits buffer address 1 buffer address 2 tdes0 tdes1 tdes2 tdes3 buffer 2 length buffer 1 length transmit descriptor format
DM9102 10/100mbps single chip lan controller 46 final version: DM9102-ds-f03 august 30, 2000 tdes0: owner bit with transmit status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 own bit 31: own, 1=owned by DM9102, 0=owned by host, this bit should be set w hen the transmitting buffer is filled with data and r eady to be transmitted. it will be reset by DM9102 after transmitting the whole data buffer. 151413121110 9 8 7 6 5 4 3 2 1 0 es ec hf cc tx jt loc nc lc lf fue df this word wide content includes status of transmitted frame. they are loaded after the data buffer that belongs to the corresponding descriptor is transmitted. bit 15: es, error summary it is set for the following error conditions: transmit jabber time-out (txjt=1), loss of carrier (loc=1), no carrier (nc=1), late collision (lc=1), excessive collision (ec=1), fifo underrun error (fue=1). bit 14: txjt, transmit jabber time out it is set to indicate the transmitted frame is t runcated due to transmit jabber time out condition. the transmit jabber time out interrupt cr5<3> is set. bit 11: loc, loss of carrier it is set to indicate the loss of carr ier during the f rame transmission, not valid in internal loopback mode. bit 10: nc, no carrier it is set to indicate that no carrier si gnal from transceiver is found, not valid in internal loopback mode. bit 9: lc, late collision it is set to indicate a collision occurs after the collision window of 64 bytes. not valid if fue is set. bit 8: ec, excessive collision it is set to indicate the transmission is aborted due to 16 excessive collisions. bit 7: hf, heartbeat fail it is set to indicate the heartbeat check failed after complete transmission. not valid if fue is set. when tdes0<14> is set, this bit is not valid. bits 6-3: cc, collision count these bits show the number of collision before transmission. not valid if excessive collision bit is also set. bit 2: lf, link test fail it is set to indicate the link test fails before the frame transmission. bit 1: fue, fifo underrun error it is set to indicate the transmission aborted due to transmit fifo underrun condition. bit 0: df, deferred it is set to indicate the frame is de ferred before ready to transmit.
DM9102 10/100mbps single chip lan controller final 47 version: DM9102-ds-f3 august 30, 2000 tdes1: transmit buffer control and buffer size 31 30 29 28 27 26 25 24 23 22 21 ~ 11 10 ~ 0 ci ed bd fmb1 setf cad eor ce pd fmb0 buffer 2 length buffer 1 length bit 31: ci, completion interrupt it is set to enable transmit interrupt after the present f rame has been transmitted. it is valid only when tdes1<30> is set or when it is a setup frame. bit 30: ed, ending descriptor it is set to indicate the pointed buffer contains the last segment of a frame. bit 29: bd, begin descriptor it is set to indicate the pointed buffer contains the first segment of a frame. bit 28: fmb1, filtering mode bit 1 this bit is used with fmb0 to indicate the filtering type when the present frame is a setup frame. bit 27: setf, setup frame it is set to indicate the current frame is a setup frame. bit 26: cad, crc append disable it is set to disable the crc appending at the end of the transmitted frame. valid only when tdes1<29> is set. bit 25: eor, end of ring descriptor it is set to indicate the descriptor is located on the bottom of the descriptor list. bit 24: ce, chain enable this bit is set to indicate the second address (tdes3) is the chained descriptor instead of the other buffer. it is used as the indication of the chain structure. when reset, it indicates the ring structure. bit 23: pd, padding disable this bit is set to disable the padding field for a packet shorter than 64 bytes. bit 22: fmb0, filtering mode bit 0 this bit is used with fmb1 to indicate the filtering type when the present frame is a setup frame. fmb1 fmb0 filtering type 0 0 perfect filtering 0 1 hash filtering 1 0 inverse filtering 1 1 hash-only filtering bits 21-11: buffer 2 length indicates the size of second buffer. it has no meaning with chain structure descriptor type. bit 10-0: buffer 1 length indicates the size of the first buffer in ring type structure and single buffer in chain type structure. tdes2 : buffer 1 starting address indicates the physical starting address of buffer 1. ba1: 31 0 buffer address 1 tdes3 : buffer 2 starting address indicates the physical starting address of buffer 2 under the r ing structure. ba2: 31 0 buffer address 2
DM9102 10/100mbps single chip lan controller 48 final version: DM9102-ds-f03 august 30, 2000 initialization procedure after hardware or software reset, transmit and receive proc esses are placed in the stop state. the DM9102 can accept the host commands to start operation. the general procedure for initializa tion is described below: (1) read/write suitable values for the pci configuration registers. (2) write cr3 and cr4 to provide the starting address of each descriptor list. (3) write cr0 to set global host bus operation parameters. (4) write cr7 to mask unnecessary interrupt causes. (5) write cr6 to set global parameters and start both the receive and transmit proc esses. the receive and transmit processes will enter the running state and attempt to acquire descriptors from the respective descriptor li sts. (6) wait for any interrupt. data buffer processing algorithm the data buffer process a lgorithm is based on the cooperation of the host and the dm 9102. the host sets cr3 (receive descriptor base address) and cr4 (transmit descriptor base address) for the descriptor list initialization. the DM9102 will start the data buffer transfer after the descriptor polling and get the ownership. for detailed processing procedure, please see below. 1. receive data buffer processing the DM9102 always attem pts to acquire an extra descriptor in anticipation of the incoming frames. any incoming frame size covers a few buffer regions and descriptors. the following con ditions satisfy the descriptor acquisition attempt: when start/stop receive sets immediately after being placed in the running state. when the DM9102 begins w riting f rame data to a data buffer pointed to by the current descriptor and the buffer ends before the f rame ends. when the DM9102 completes the reception of a frame and the current receive descriptor is closed. when receive process is suspended due to no free buffer for the DM9102 and a new frame is received. when receive poll demand is issued. after acquiring the free descriptor, the DM9102 processes the incoming frame and places it in the acquired descriptor's data buffer. when the whole received frame data has been trans ferred, the DM9102 will write the status information to the last descriptor. the same process will repeat until it encounters a descriptor flagged as being owned by the host. if this occurs, receive process enters the suspen ded s tate and waits the host to service. stop state descriptor access datat transfer write status suspended start receive command or receive poll command buffer available ( own bit = 1 ) fifo threshold reached frame fully received buffer not full receive buffer unavailable new frame coming or receive poll command stop receive command or reset command buffer full receive buffer management state transition
DM9102 10/100mbps single chip lan controller final 49 version: DM9102-ds-f3 august 30, 2000 2. transmit data buffer processing when start/stop transmit command is set and the DM9102 is in running state, transmit process polls transmit descriptor list for frames requiring transmission. when it completes a frame transmission, the status related to the transmitted frame will be written into the transmit descriptor. if the DM9102 detects a descriptor flagged as owned by the host and no transmit buffers are available, transmit process will be susp ended. while in the running state, transmit process can simultaneously acquire two frames. as transmit process completes copying the first frame, it immediately polls the transmit descriptor list for the sec ond f rame. if the second frame is valid, transmit process copies the frame before w riting the status information of the first frame. both conditions below will make transmit process be suspended: (i) the DM9102 det ects a descriptor owned by the host. (ii) a frame transmission is aborted when a locally induced error is dete cted. under either condition, the host driver has to service the condition before the DM9102 can resume. stop state descriptor access data transfer write status suspended buffer available ( own bit = 1 ) frame fully transmited start transmit command or transmit poll command under fifo threshold buffer not empty buffer empty transmit buffer unavailable ( owned by host ) transmit poll command stop transmit command or reset command transmit buffer management state transition
DM9102 10/100mbps single chip lan controller 50 final version: DM9102-ds-f03 august 30, 2000 network function 1. overview this chapter will introduce the normal state machine operation and mac layer management like c ollision backoff algorithm. in transmit mode, the DM9102 initiates a dma cycle to access data from a transmit buffer. it prefaces the data with the preamble, the sfd pattern, and it appends a 32-bit crc. in receive mode, the data is de-serialized by receive mechanism and fed into the internal fifo. for detailed process, please see below. 2. receive process and state machine a. reception initiation as a preamble being detected on the receive data lines, the DM9102 synchronizes itself to the data stream during the preamble and waits for the sfd. the synchronization proc ess is based on byte boundary and the sfd byte is 10101011. if the DM9102 receives a 00 or a 11 after the first 8 preamble bits and before receiving the sfd, the reception process will be termi nated. b. address recognition after initial synchronization, the DM9102 will recognize the 6-byte destination address field. the first bit of the destination address signifies whether it is a physical address (=0) or a multicast address (=1). the DM9102 filters the frame based on the node address of receive address filter setting. if the frame passes the filter, the subs equent ser ial data will be delivered into the host memory. c. frame decapsulation the DM9102 checks the crc bytes of all received frames before releasing the frame along with the crc to the host processor. 3. transmit process and state m achine a. transmission initiation once the host processor prepares a transmit descriptor for the transmit buffer, the host processor signals the DM9102 to take it. after the DM9102 has been notified of this transmit list, the DM9102 will start to move the data bytes from the host memory to the internal transmit fifo. when transmit fifo is adequately filled to the programmed threshold level, or when there is a full frame buffered into the transmit fifo, the DM9102 begins to encapsulate the frame. the transmit encapsulation is performed by the transmit state machine, which delays the actual transmission onto the network until the network has been idle for a minimum interframe gap time. b. frame encapsulation the transmit data frame encapsulation stream consists of two parts: basic frame beginning and basic frame end. the former conta ins 56 preamble bits and sfd, the later, fcs. the basic frame read from the host memory includes the destination address, the source address, the type/length field, and the data field. if the data field is less than 46 bytes, the DM9102 will pad the frame with the pattern 00 up to 46 bytes. c. collision when concurrent transmissions from two or more nodes occur (termed; c ollision), the dm 9102 halts the transmission of data bytes and begins a jam pattern consisting of aaaaaaaa. at the end of the jam transmission, it begins the backoff wait time. if the collision was detected during the preamble transmission, the jam pattern is transmitted after completing the preamble. the backoff process is called truncated binary exponential backo ff. the delay is a random integer multiple of slot times. the number of slot times of delay before the n th retransmission attempt is chosen as a uniformly distributed random integer in the range: 0 r < 2 k k = min ( n, n ) and n=10 4. physical layer overview: the DM9102 provides 100m/10mbps dual port operation. it provides a direct interface either to unshielded twisted pair cable utp5 for 100base- tx fast ethernet, or utp5/utp3 cable for 10base-t ethernet. in physical level operation, it consists of the following blocks: pcs clock generator nre/nrei, mlt 3 encoder/decoder and driver manchester encoder/decoder 10base-t filter and driver
DM9102 10/100mbps single chip lan controller final 51 version: DM9102-ds-f03 august 30, 2000 serial management interface the serial management interface uses a simple, two- wired serial interface to obtain and control the status of phy management register set through an mdc and mdio. the management data clock (mdc) is equipped with a maximum clock rate of 2.5mhz, while management data input /output (mdio) works as a bi-directional, shared by up to 32 devices. in read/write operation, the management data frame is 64-bit long start with 32 conti guous logic one bits (preamble) synchronization clock cycles on mdc. the start of frame delimiter (sfd) is indicated by a <01> pattern followed by the operation c ode (op):<10> indicates read operation and <01> indicates write operation. for read operation, a 2-bit turnar ound (ta) filing between r esistor address field and data field is provided for mdio to avoid contention. ?z? stands for high impedance state. following turnaround time, a 16-bit data is read from or written onto management registers. management interface - r ead frame struc ture 32 "1"s 0110a4a3a0r4r3r0 z 0 idle preamble sfd op code phy address register address turn around data idle read write mdc mdio read d15 d14 d1 d0 // // management interface - write frame structure 32 "1"s 0 1 1 0 a4 a3 a0 r4 r3 r0 1 0 d15 d14 d1 d0 idle preamble sfd op code phy address register address turn around data idle write mdc mdio write
DM9102 10/100mbps single chip lan controller 52 final version: DM9102-ds-f03 august 30, 2000 configuration rom overview the purpose of configuration rom (eeprom) is to support the DM9102 information to the driver for the card. the crom must support 64 words or more space for configuration data. the format of the crom is as followed: the format of eeprom. field name offset size subsystem id block 0 18 crom version 18 1 controller count 19 1 controller_0 information 20 n controller_1 information 20+n m : (depends on controller count) : : crc checksum 126 2 1. subsystem id block every card must have a s ubsystem id to indi cate the system vendor information. the content will be transferred into the pci configuration space during a hardware reset function. (a) vendor id & device id can be set in eeprom content & auto-loaded to pci configuration register after reset. (default value = 1282, 9102) this function must be selectable for enable/disable by auto_load_control ( offset 08 of eeprom) setting to avoid damaging default value due to (b) incorrectly auto-load operation. crc check circuit of eeprom contents to decide the auto-load operation of v endor id & subsystem. subsystem vendor id subsystem id reserved reserved id_block_crc reserved reserved reserved pci device id pci vender id nce auto_load_control 0 2 4 6 8 10 12 14 17,16 byte offset. subsystem id block
DM9102 final 53 version: DM9102-ds-f03 august 30, 2000 byte offset (08): auto_load_control 0 3 4 7 bit3~0: ? 1010 ? to enable auto-l oad of pci v endor_id & device_id, ? 0 ? to disable. bit7~4: ? 1x1x ? to enable auto-l oad of nce, to pci configuration space. byte offset (09): new_capabilities_enable 0 1 7 bit0: directly mapping to bit20 (new capabilities) of the pcics byte offset (16): id_block_crc 0 7 this field is implemented to confirm the correct reading of the eeprom contents. 2. crom version current version number is 03. 3. controller count the configuration rom supports multiple controllers in one board. every controller has its uni que controller information block. controller count indicates the number of controllers put in the card. 4. controller_x information each controller has its information block to address its node id, gpr control, supported connect media types (media information block) and other application circuit information block. controller information header item offset size node address 0 6 controller_x number 6 1 controller_x info. block offset 7 1 5. controller information body pointed by controller_x info block offset item in controller information header: item offset size connection type selected 02 gpr control 2 1 block count 3 1 block_1 4 n : 4+n m * connect type selected indicates the default connect media type selected. * gpr control defines the input or output direction of gpr. there are three types of block: 1. phy information block (type=01) 2. media information block (type=00) 3. delay period block (type=80) phy information block (type=01) item offset size block length 0 1 block type(01) 1 1 phy number 2 1 gpr initial length(g_i) 3 1 gpr initial data 4 g_i reset sequence length(r_i) 4+g_i 1 reset data 5+g_i r_i media capabilities 5+g_i+r_i 2 nway advertisement 7+g_i+r_i 2 fdx bit map 9+g_i+r_i 2 ttm bit map 11+g_i+r_i 2 note 1: the definition of media capabilities and nway advertisement is the same with 802.3u in terms of auto-negotiation.
DM9102 10/100mbps single chip lan controller 54 final version: DM9102-ds-f03 august 30, 2000 media information block (type = 00) item offset size block length 0 1 block type(00) 1 1 media code 2 1 gpr data 3 1 command 4 2 note 1: media code: 10base_t half duplex 00 10 base_t full duplex 04 100 base_t half duplex 01 100 base_t full duplex 05 note 2: command format delay period block (type = 80) define the delay time unit in us. item offset size block length 0 1 block type(80) 1 1 time unit 2 2
DM9102 10/100mbps single chip lan controller final 55 version: DM9102-ds-f03 august 30, 2000 absolute maximum ratings* supply voltage (v cc ) ........................... -0.5v to 5.5v maximum dc input voltage (v in ) -0.5v to vcc+0.5v dc output voltage (v out ) .........-0.5v to vcc +0.5v storage temperature rang (tstg) .. -65 to +150 case temperature range?????..?0 to 85 infrared solder reflow peak temp. (10 to 20 sec.) .......................................................... 220 to 225 esd rating (rzap=1.5k, czap= 100pf) .......... 4000v stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating c onditi ons for extended periods may affect device reliability. dc electrical characteristics symbol parameter min. typ. max. unit conditions v cc supply voltage 4.75 - 5.25 v - t op operation temperature -20 - 70 c - v il input low voltage - - 0.8 v - v ih input high voltage 2.0 - - v - v ol output low voltage (iol = 8ma) - - 0.5 v - v oh output high voltage (ioh = -2ma) 2.4 - - v - i il input leakage current - - 10 ua - i dd operation supply current - 230 250 ma - i pd power down supply c urrent - t/d - ua - receiver symbol parameter min. typ. max. unit v icm rxi+/rxi- input common-mode voltage 1.5 2.0 2.5 v 100 ? termination across transmitter i td100 100txo+/- 100base-tx mode differential output current 19 21 ma absolute value i td10 10tx+/- 10base-t differential output current 44 50 56 ma absolute value * -: no defined value *t/d: to be determined
DM9102 10/100mbps single chip lan controller 56 final version: DM9102-ds-f03 august 30, 2000 ac electrical characteristics pci clock specifications timing t high 2.0v 0.8v t r t f t low t cycle symbol parameter min. typ. max. unit conditions t r pci_clk rising time 4 - - ns - t f pci_clk falling time 4 - - ns - t cycle cycle time 30 - - ns - t high pci_clk high time 12 - - ns - t low pci_clk low time 12 - - ns - other pci signals timing diagram t off t h t su input t on output c lk 2.5v t val (max) t val (min) symbol parameter min. typ. max. unit conditions t val clk-to-signal valid dealy 2 - 11 ns cload = 50 pf t on float-to-active delay from clk 2 - - ns - t off active-to-float dealy from clk - - 28 ns - t su input signal valid setup time before clk 7 - - ns - t h input signal hold time from clk 0 - - ns -
DM9102 10/100mbps single chip lan controller final 57 version: DM9102-ds-f03 august 30, 2000 multiplex mode boot rom timing t oh t ehqz t elqv tavav t elqx address=<7;2> oe=1,we=0 address <15;8> date<7;0> valld t ads t adh t ads t adh bpad <7;0> bpa1 bpcs# address<1> address<17> address<16> bpa0 address<0> symbol parameter min. type max. unit conditions t avav read cycle time - 31 - pci clock - t elqv bpcs# to output delay 0 - 7 pci clock - t ehqz bpcs# rising edge to output high impedance -1 - pci clock - t oh output hold from bpcs# 0 - - pci clock - t ads address setup to latch enable high 4 - - pci clock - t adh address hold from latch enable high 4 - - pci clock - direct mode boot rom timing frame# irdy# trdy# devsel# cbel[3:0] ad[31:0] md[7:0] ma[17:0] romcs tcbad t1adl t2adl t3adl t4adl tadtd trc
DM9102 10/100mbps single chip lan controller 58 final version: DM9102-ds-f03 august 30, 2000 symbol parameter min. type max. unit conditions t rc read cycle time - 50 - pci clock - t cbad bus command to first address delay - 18 - pci clock - t 1adl first address length - 8 - pci clock - t 2adl second address delay - 8 - pci clock - t 3adl third address delay - 8 - pci clock - t 4adl fourth address delay - 7 - pci clock - t adtd end of address to tardy active - 1 - pci clock - eeprom timing romcs eeck eedo tcskd teckc tedsp tecsc symbol parameter min. typ. max. unit conditions t eckc serial rom clock eeck period 64 - - pci clock - t ecsc read cycle time 1792 - - pci clock - t cskd delay from romcs high to eeck high 28 - - pci clock - t edsp setup time of eedo to eeck 24 - - pci clock - phyceiver : symbol parameter min. typ. max. unit conditions transmitter t tr/f 100txo+/- differential rise/fall time 3.0 5.0 ns t tm 100txo+/- differential rise/fall time mismatch -0.5 0.5 ns t tdc 100txo+/- differential output duty cycle distortion -0.5 0.5 ns t t/t 100txo+/- differential output peak-to- peak jitter 800 ps x ost 100txo+/- differential voltage overshoot 5 %
DM9102 10/100mbps single chip lan controller final 59 version: DM9102-ds-f03 august 30, 2000 auto-negotiation and fast link pulse timing diagram fast link pulses clock pulse data pulse clock pulse t 1 t 2 t 3 flp burst flp burst t 4 t 5 10tx0+/- fast link pulses clock pulse data pulse clock pulse t 1 t 2 t 3 flp burst flp burst t 4 t 5 10tx0+/- symbol parameter min. typ. max. unit conditions t 1 clock/data pulse width - 100 - ns t 2 clock pulse to data pulse period - 62.5 - us data = 1 t 3 clock pulse to clock pulse period - 125 - us t 4 flp burst width - 2 - ms t 5 flp burst to flp burst period - 13.93 - ms - clock/data pulses per burst 33 33 33 ea
DM9102 10/100mbps single chip lan controller 60 final version: DM9102-ds-f03 august 30, 2000 package information qfp 128l outline dimensions unit: inches/mm l l1 detail f seating plane see detail f d y 0.10 see detail a a a2 a 1 y b e 138 128 103 65 102 d d1 e1 e 64 39 with plating base metal detail a c b symbol dimension in inch dimension in mm a 0.134 max. 3.40 max. a1 0.010 min. 0.25 min. a2 0.112 0.005 2.85 0.12 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.145 0.055 d 0.913 0.007 23.20 0.20 d1 0.787 0.004 20.00 0.10 e 0.677 0.008 17.20 0.20 e1 0.551 0.004 14.00 0.10 e 0.020 bsc 0.5 bsc l 0.035 0.006 0.88 0.15 l1 0.063 bsc 1.60 bsc y 0.004 max. 0.10 max. 0 ~12 0 ~12 note: 1. dimension d1 and e1 do not include resin fins. 2. all dimensions are based on metric system. 3. general appearance spec. should base itself on final visual inspection spec.
DM9102 10/100mbps single chip lan controller final 61 version: DM9102-ds-f03 august 30, 2000 ordering information part number pin count package DM9102f 128 qfp disclaimer the information appea ring in this publica tion is believed to be accur ate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipu lated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. da vicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the r eader is cauti oned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliab ility requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor, inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic pr oducts that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compat ible with major hardware and software standards. our currently available and soon to be released pr oducts are ba sed on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about d avicom produc ts, contact the sales department at: headquarters hsin-chu office: 3f, no. 7-2, industry e. rd., ix, science-based park, hsin-chu city, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5798858 taipei sales & marketing office: 8f, no. 3, lane 235, bao-chiao rd., hsin-tien city, taipei, taiwan, r.o.c. tel: 886-2-29153030 fax: 886-2-29157575 email: sales@davicom.com.tw davicom usa sunnyvale, california 1135 kern ave., sunnyvale, ca94085, u.s.a. tel: 1-408-7368600 fax: 1-408-7368688 email: sales@davicom8.com warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structur e, performance and/or function.
DM9102 10/100mbps single chip lan controller 62 final version: DM9102-ds-f03 august 30, 2000 appendix a DM9102 srom format total size: 128 bytes field name offset (bytes) size (bytes) value (hex) commentary sub-vendor id 0 2 0291 id block sub-device id 2 2 8212 reserved1 4 4 00000000 auto_load_control 8 1 00 auto-load function definition: bit 3..0 = 1010 auto-load pci vendor id/device id enabled bit 7..4 = 1010 auto-load pmc/pmcsr enabled (p.s.: for DM9102 e7 and later bit 7..4 = 1x1x auto-load pmc/pmcsr enabled) new_capabilities_enable (nce) 9 1 00 please refer to DM9102 spec. pci vendor id 10 2 1282 pci device id 12 2 9102 if auto-load pci vendor id/device id function disabled, the pci vendor id/device id will use the default values ( 1282h , 9102h ). reserved 14 1 00 please refer to DM9102 spec. reserved 15 1 00 please refer to DM9102 spec. id_block_crc 16 1 - offset 0..15, 17 id crc reserved2 17 1 00 srom format version 18 1 03 version 3.0 controller count 19 1 01 ieee network address 20 6 - controller info header controller_0 dev number 26 1 00 controller_0 info leaf offset 27 2 001e offset 30 reserved3 29 1 00 selected connected type 30 2 0800 controller_0 info leaf block general purpose control 32 1 80 mac cr12 register block count 33 1 06 6 blocks f(1)+length 34 1 8e block 1 (phy info block) type 35 1 01 phy information block phy number 36 1 01 phy address gpr length 37 1 00 reset sequence length 38 1 02 reset sequence 39 2 0080 media capabilities 41 2 7800 nway advertisement 43 2 01e0 fdx bit map 45 2 5000 ttm bit map 47 2 1800
DM9102 10/100mbps single chip lan controller final 63 version: DM9102-ds-f03 august 30, 2000 field name offset (bytes) size (bytes) value (hex) commentary f(1)+length 49 1 85 block 2 (delay period block) type 50 1 80 delay period block delay sequence 51 4 40002000 microsecond f(1)+length 55 1 85 block 3 (media info block) type 56 1 00 media information block media code 57 1 00 10base-t half_duplex gpr data 58 1 00 command 59 2 0087 f(1)+length 61 1 85 block 4 (media info block) type 62 1 00 media information block media code 63 1 01 100base-tx half_duplex gpr data 64 1 00 command 65 2 0087 f(1)+length 67 1 85 block 5 (media info block) type 68 1 00 media information block media code 69 1 04 10base-t full_duplex gpr data 70 1 00 command 71 2 0087 f(1)+length 73 1 85 block 6 (media info block) type 74 1 00 media information block media code 75 1 05 100base-tx full_duplex gpr data 76 1 00 command 77 2 0087 srom_crc 126 2 - offset 0..125 srom crc

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