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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4811 fixed function multi-effects audio processor features l audio processor for embedded reverb/effects applications C proprietary 24-bit audio processing engine C on-chip ram (no external ram required) C on-chip 24-bit ds adc with 100 db dyn. range C on-chip 24-bit ds dac with 100 db dyn. range C automatically boots firmware from external serial eeprom l firmware available for guitar effects or mixer effects applications l single +5 v supply l 100-pin metric quad flat pack (mqfp) description the cs4811 is a complete audio effects processing system on a chip. this device integrates a proprietary 24- bit audio processing engine, large on-chip ram memories, and a high performance 24-bit audio codec. a serial control port allows the device to boot firmware from a compact and low cost spi or i 2 c serial eeprom. other features such as single +5 v operation simplify system design. firmware for the cs4811 is provided by cirrus logic. there are two different firmware codes available; one for guitar effects and one for audio mixers. the guitar effects firmware provides a host of electric guitar effects includ- ing spring reverb, delay, chorus, flange and tremolo. the mixer effects firmware provides a suite of effects such as digital reverb, delay and chorus which are suit- able for use in audio mixers, karaoke and acoustic instrument amplifiers. the cdb4811gtr and cdb4811mxr evaluation boards allow easy evaluation of the cs4811 device and the associated firmware. ordering info CS4811-KM -10 to +70c 100-pin mqfp cdb4811gtr-01 guitar effects evaluation board cdb4811mxr-01 mixer effects evaluation board i cmout cmfilt+ cmfilt- ain+ ain- xto xti clock manager aout+ 24-bit audio voltage reference pio3 pio2 pio1 pio0 digital filter dac analog lpf and output stage digital hpf serial control port (spi or i 2 c) adc spi /i 2 c scl/cclk sda/cdout ad1/cdin ad0/cs rst ovl aout- processing engine ram sep 00 ds486pp2
cs4811 2 ds486pp2 table of contents 1. characteristics and specifications ........................................................................ 4 adc characteristics ....................................................................................................... 4 dac characteristics ....................................................................................................... 5 switching characteristics .......................................................................................... 6 switching characteristics - control port - spi master.................................. 7 switching characteristics - control port - i 2 c master .................................. 8 recommended operating conditions ....................................................................... 9 digital characteristics ................................................................................................. 9 switching characteristics - programmable i/o................................................... 9 2. typical connection diagrams ................................................................................... 10 3. functional description ............................................................................................... 12 3.1 overview .................................................................................................................. ........ 12 3.2 analog inputs ............................................................................................................. ...... 12 3.2.1 line level inputs ................................................................................................. 12 3.2.2 digital high pass filter ........................................................................................ 12 3.3 analog outputs ............................................................................................................ .... 13 3.3.1 line level outputs .............................................................................................. 13 3.4 clock generation .......................................................................................................... ... 13 3.4.1 clock source ....................................................................................................... 13 3.5 serial control port ....................................................................................................... ..... 14 3.5.1 spi bus ............................................................................................................... 14 3.5.1.1 spi mode ................................................................................................ 14 3.5.2 i 2 c bus ................................................................................................................ 14 3.5.2.1 i 2 c mode ................................................................................................ 14 3.6 resets .................................................................................................................... .......... 15 4. power supply and grounding ................................................................................... 16 5. pin descriptions .......................................................................................................... .... 17 6. parameter definitions .................................................................................................. 21 7. package dimensions ..................................................................................................... 2 2 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or 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cs4811 ds486pp2 3 list of figures figure 1. spi control port timing ............................................................................. 7 figure 2. i 2 c control port timing .............................................................................. 8 figure 3. typical connection diagram, single-ended input .................................... 10 figure 4. typical connection diagram, i 2 c mode .................................................. 11 figure 5. typical connection diagram, spi mode .................................................. 11 figure 6. optional line input buffer ........................................................................ 12 figure 7. butterworth output filters ........................................................................ 13 figure 8. output mute circuit .................................................................................. 13 figure 9. control port timing, spi master mode self-boot ..................................... 14 figure 10.control port timing, i2c master mode self-boot ..................................... 15 figure 11.cs4811 suggested layout ...................................................................... 16 figure 12.pin assignments ...................................................................................... 17
cs4811 4 ds486pp2 1. characteristics and specifications adc characteristics (t a = 25 c; va, vd = + 5 v; -1 db full scale input sine wave, 997 hz; fs = 48 khz; xti = 12.2880 mhz; measurement bandwidth is 20 hz to 20 khz) notes: 1. referenced to typical full-scale differential input voltage (2 v rms ). 2. bench tested only. 3. filter characteristics scale with output sample rate. 4. measured using differential analog input circuit, see figure 6. 5. filter response is not tested but is guaranteed by design. parameters symbol min typ max units analog input characteristics adc conversion stereo audio channels 16 - 24 bits dynamic range (a weighted, note 4) (unweighted, note 4) 93 90 100 97 - - db db total harmonic distortion + noise (note 1,4) thd+n - -92 -87 db offset error (with internal high pass filter enabled) (note 5) - - 0 lsb full scale input voltage (differential) 1.9 2.0 2.1 v rms gain drift (note 2) - 100 - ppm/c input resistance 10 - - k w input capacitance - - 15 pf cmout output voltage - 2.3 - v common mode rejection ratio (note 2) cmrr 60 db high pass filter characteristics frequency response -3db (note 3) -0.14db (note 3) - - 3.7 20 - - hz hz phase deviation @ 20 hz (note 3) - 10 - degree passband ripple - - 0 db
cs4811 ds486pp2 5 dac characteristics (t a = 25 c; va, vd = + 5 v; full scale output sine wave, 997 hz; fs = 48 khz; xti = 12.288 mhz; measurement bandwidth is 20 hz to 20 khz) notes: 6. measured with dac calibration disabled. 7. measured with xti clock disabled. specifications are subject to change without notice. parameters symbol min typ max units analog output characteristics - minimum attenuation, 10 k w , 100 pf load; unless otherwise specified. dac resolution 16 - 24 bits dynamic range (dac not muted, a weighted) 95 100 - db total harmonic distortion + noise thd+n - -90 -85 db offset voltage (differential) (note 6) - -205 - mv offset voltage (v+/v- relative to cmout) (note 6) - -45/-28 - mv full scale output voltage (differential) 1.9 2.0 2.1 v rms gain drift (note 2) - 100 - ppm/c out of band energy (fs/2 to 2fs, note 2) - -60 - dbfs analog output load resistance capacitance 10 - - - - 100 k w pf analog loopback performance signal-to-noise ratio (ccir-2k weighted, -20 db input) ccir-2k - 74 - db power supply power supply current operating power down (note 7) - - 200 1 - - ma ma power supply rejection (1 khz, 10 mv rms, , note 2) - 50 - db
cs4811 6 ds486pp2 switching characteristics (t a = 25 c; va, vd = +5 v, outputs loaded with 30 pf) notes: 8. guaranteed by characterization but not tested. 9. on power-up, the cs4811 rst pin should be asserted until the power supplies have reached steady state. parameters symbol min typ max units adc & dac sample rate fs 30 - 50 khz xti frequency xti = 256fs 7.68 - 12.8 mhz xti duty cycle xti =256fs (note 8) 40 - 60 % xti jitter tolerance - 500 - ps rst low time (note 9) 500 - - ns
cs4811 ds486pp2 7 switching characteristics - control port - spi master (ta = 25 c, va, vd = 5 v; inputs: logic 0 = dgnd, logic 1 = vd, c l = 30 pf) notes: 10. measured with a 2.2 k w pullup resistor to vd. parameter symbol min typ max units spi master (self-boot) mode (spi /i2c = 0, scpm/s = 1) cclk clock frequency f sck -fs-khz cclk low time t scl -1/(2*fs)-ns cclk high time t sch -1/(2*fs)-ns cclk rise time (note 10) t r2 -12-ns cclk fall time (note 10) t f2 -12-ns rst rising to cs falling t srs -42- m s cs high time between transmissions t csh 37 - - m s cs falling to cclk edge t css 5- - m s cs falling to cdout valid t dv - - 50 ns cclk falling to cdout valid t pd --100ns cdin to cclk rising setup time t dsu 80 - - ns cclk rising to data hold time t dh 80 - - ns cclk falling to cs rising t clcs 40 - - ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t clcs t srs rst t pd cdout t dv figure 1. spi control port timing
cs4811 8 ds486pp2 switching characteristics - control port - i 2 c master (t a = 25 c; va, vd = 5 v; inputs: logic 0 = dgnd, logic 1 = vd, c l = 30 pf) notes: 11. use of the i 2 c bus interface requires a license from philips. i 2 c is a registered trademark of philips semiconductors. 12. data must be held for sufficient time to bridge the worst case fall time of 300 ns for cclk/scl. 13. for both sda transmitting and receiving. parameter symbol min typ max units i 2 c ? master (self-boot) mode (spi /i2c = 1, scpm/s = 1) (note 11) scl clock frequency f scl -fs-khz clock low time t low -1/(2*fs)- m s clock high time t high -1/(2*fs)- m s bus free time between transmissions t buf 4.7 - - m s rst rising to start condition t irs -22- m s start condition hold time t hdst 4.0 - - m s setup time for repeated start condition t sust 13.5 - - m s sda setup time to scl rising t sud 250 - - ns sda hold time from scl falling (note 12) t hdd 0--ns scl falling to sda output valid t cldv --1.5 m s scl and sda rise time (note 13) t r --1 m s scl and sda fall time (note 13) t f --300ns setup time for stop condition t susp 4.7 - - m s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst t cldv (output) figure 2. i 2 c control port timing
cs4811 ds486pp2 9 absolute maximum ratings (all voltages with respect to agnd = dgnd = 0 v.) notes: 14. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 15. the maximum over or under voltage is limited by the input current. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (all voltages with respect to agnd = dgnd = 0v.) digital characteristics (t a = 25 c; va, vd = 5 v) switching characteristics - programmable i/o (t a = 25 c; va, vd = 5 v 5%; inputs: logic 0 = dgnd, logic 1 = vd, c l = 30 pf) parameters symbol min typ max units power supplies digital analog vd va -0.3 -0.3 - - 6.0 6.0 v v input current (note 14) - - 10.0 ma analog input voltage (note 15) -0.7 - (va)+0.7 v digital input voltage (note 15) -0.7 - (vd)+0.7 v ambient temperature (power applied) -55 - +125 c storage temperature -65 - +150 c parameters symbol min typ max units power supplies digital |va - vd| < 0.4v analog vd va 4.75 4.75 5.0 5.0 5.25 5.25 v v operating ambient temperature t a -10 25 70 c parameters symbol min typ max units high-level input voltage (except xti) v ih 2.8 - (vd)+0.3 v low-level input voltage (except xti) v il -0.3 - 0.8 v high-level output voltage at i 0 = -2.0 ma (except xto) v oh (vd)-1.0 - - v low-level output voltage at i 0 = 2.0 ma (except xto) v ol --0.4v high-level input voltage (xti) v ih 2.8 - - v low-level input voltage (xti) v il --2.3v input leakage current (digital inputs) - - 10 a output leakage current (high-z digital outputs) - - 10 a parameters symbol min typ max units output rise time t rpo -200 - ns output fall time t fpo -200 - ns
cs4811 10 ds486pp2 2. typical connection diagrams d d a + 1 m f 0.1 m f agnd1..4 dgnd1..4 xto xti 46 45 caps, xtal, and resistor not needed with external clock input to xti. 44 7 aout + 63 62 68 67 scl/cclk sda/cdout ad0/cs ad1/cdin 92 1 m f cmout 86 to optional input and output buffers ain + 87 37 pio2 35 pio3 control/ monitor circuitry 72 69 spi/i2c mode/reset circuit all unused inputs should be tied to ground. cs4811 40 pio1 41 analog filter r=33 w s 150 w 2.2 nf 66 64 93 94 0.1 f 1 f + cmfilt+ cmfilt- rst pio0 8 aout - 2.2 k 2.2 k vd vd 13 89 19 42 11 39 pf 22 f + ain - 0.1 f 100 f + reset serial eeprom 1 m w 0.1 f 39 pf 39 ovl a a a a a a a d dd a va 1..3 88 18 12 + 1 m f 0.1 m f 43 65 vd 1..2 +5 v supply ferrite bead res-dgnd res-dgnd res-dgnd res-dgnd d res-dgnd res-dgnd 32, 36, 38, 48, 96, 82, 83 1, 2, 3, 4, 5, 6 31, 33, 49, 50, 51, 52, 53 24, 25, 26, 27, 28, 29, 30 78, 79, 80, 81, 84, 85, 98, 99, 100 54, 55, 56, 74, 75, 76, 77 res-nc res-nc 9, 10, 14, 15, 16, 17, 20 res-nc 21, 22, 23, 47, 57, 58, 59 60, 61, 71, 95, 97, 90, 91 res-vd 70, 73 vd figure 3. typical connection diagram, single-ended input
cs4811 ds486pp2 11 63 62 68 67 ic eeprom scl/cclk sda/cdout ad0/cs ad1/cdin 72 69 spi/i2c reset circuit rst cs4811 2 2.2 k 2.2 k vd vd a0 a1 a2 vd reset d d figure 4. typical connection diagram, i 2 c mode 63 62 68 67 spi eeprom scl/cclk sda/cdout ad0/cs ad1/cdin 72 69 spi/i2c reset circuit rst cs4811 reset 2.2 k 2.2 k vd vd d figure 5. typical connection diagram, spi mode
cs4811 12 ds486pp2 3. functional description 3.1 overview the cs4811 is a complete audio subsystem on a chip, integrating a proprietary 24-bit audio process- ing engine with large on chip ram memories and a single channel 24-bit audio codec. the delta-sigma adc includes linear phase digital anti-aliasing filters and only requires a single-pole external passive filter. the sigma-delta dac includes a switched-capaci- tor anti-image filter and requires an external 2nd or 3rd order active filter that can be easily integrated into the output differential-to-single-ended con- verter circuit. the serial control port is designed to accommodate i 2 c ? or spi interfaces for stand-alone operation with an external non-volatile memory. 3.2 analog inputs 3.2.1 line level inputs ain+ and ain- are the differential line level ana- log inputs (see figure 3). these pins are internally biased to the cmout voltage of 2.3 v. a dc blocking capacitor placed in series with the input pins allows signals centered around 0 v to be input to the cs4811. figure 3 shows operation with a single-ended input source. this source may be sup- plied to either the positive or negative input as long as the unused input is connected to ground through capacitors as shown. when operated with single- ended inputs, distortion will increase at input levels higher than -1 db full scale. if better performance is required, a single-ended-to-differential convert- er, shown in figure 6, may be used. this circuit provides unity gain, dc blocking on the input and anti-alias filtering. the ovl output pin asserts when the analog input is out-of-range. 3.2.2 digital high pass filter in dc coupled systems, a small dc offset may ex- ist between the input circuitry and the a/d con- verters. the cs4811 includes a high pass filter after the decimator to remove these dc compo- nents. the high pass filter response, given in high pass filter characteristics , scales linearly with sample rate. thus, the -3 db frequency at a 44.1 khz sample rate will be equal to 44.1/48 times that at a sample rate of 48 khz. + - 10 k + - 4.7 k ain - 10 m f + ain + 2.2 nf 150 150 10 k 10 k input signal + (2 vrms max) +5 v cmout from cs4811 + - 0.1 m f 10 m f gnd buffered cmout figure 6. optional line input buffer
cs4811 ds486pp2 13 3.3 analog outputs 3.3.1 line level outputs the cs4811 contains on-chip differential buffer amplifiers that produce line level outputs aout+ and aout-, which are capable of driving 10 k w loads. these amplifiers are internally biased to the cmout voltage of 2.3 v. the recommended off-chip analog filter is a 2nd order butterworth with a -3 db corner at fs. a third order butterworth filter with a -3 db corner at 0.75 fs can be used if greater out of band noise fil- tering is desired. these filters can be easily inte- grated into a differential-to-single-ended converter circuit as shown in the 2-pole and 3-pole butter- worth filters of figure 7. figure 8 shows the rec- ommended mute circuit referenced in figure 7. activating the mute circuit is recommended on power-up and power-down to avoid the output of undesirable audio signals. 3.4 clock generation the master clock to operate the cs4811 may be gen- erated by using the on-chip oscillator with an exter- nal crystal or may be input from an external clock source. 3.4.1 clock source the cs4811 requires a 256 fs master clock to run the internal logic. the two possible clock sources are the on-chip crystal oscillator or an external clock input to the xti pin. the master clock may be generated directly from the on-chip crystal oscillator circuit. when using the on-chip crystal oscillator, external loading ca- pacitors are required. (see figure 3) high frequen- cy crystals (>8 mhz) should be parallel resonant, fundamental mode and designed for 20 pf loading. (equivalent to 40 pf to ground on each leg) the master clock may also be generated directly from an external cmos clock input to the xti pin. 2-pole butterworth filter buffered cmout _ + example op-amp s are mc33078 a ou t- mute line out 14.0 k w 14.0 k w a out+ 3.24 k w 3.24 k w 1 0 00 pf 1000 pf 14.0 k w 220 pf 220 pf 14.0 k w gnd +5 v buffered cmout _ + mute line out a out+ a ou t- 220 pf 220 pf 2200 pf 2.8k w 2.8k w 2.8k w 2.8k w 11.0k w 11.0k w 14.0k w 14.0k w 2200 pf 2200 pf 2200 pf gnd +5 v 3-pole butterworth filter figure 7. butterworth output filters line out va from cs4811 pio mmbt3906 mmbt3904 mmbt3906 10 k w 10 k w 10 k w gnd 3.3 k w 10 m f 1 k w 10 m f + figure 8. output mute circuit
cs4811 14 ds486pp2 3.5 serial control port the serial control port is used for self-booting from an external eeprom and supports both the spi bus and the i 2 c ? bus interfaces. the desired inter- face is selected via the spi /i 2 c pin, which is sam- pled during de-assertion of the rst pin. 3.5.1 spi bus the spi bus interface consists of 4 digital signals, cclk, cdin, cdout and cs . cclk, the control port bit clock, is used to clock individual data bits. cdin, the control data input, is the serial data input line to the cs4811. cdout, the control data output, is the output data line from the cs4811. cs , the chip select signal, is asserted to enable an external spi port. data is clocked in on the rising edge of cclk and clocked out on the falling edge. 3.5.1.1 spi mode the spi master mode is designed for read-only op- eration during self-booting from a serial eeprom. a typical self-boot sequence with a xicor x25650 se- rial eeprom, or equivalent, is shown in figure 9. on exit from reset, the cs4811 asserts cs . the 8-bit read instruction (00000011) is sent to the eeprom fol- lowed by a pre-defined 16-bit start address. the cs4811 then automatically clocks out sequential bytes from the eeprom until the last byte has been received. these bytes include initialization and configuration data for the device along with the application firmware code. after the last byte is re- ceived, the cs4811 deasserts cs and begins program execution. at this point, the serial control port be- comes inactive and cannot be accessed. 3.5.2 i 2 c bus the i 2 c bus interface implemented on the cs4811 consists of 2 digital signals, scl and sda. scl or serial clock, is used to clock individual data bits. sda or serial data, is a bidirectional data line. two additional pins, ad1 and ad0, are inputs which determine the 2 lowest order bits of the 7-bit i 2 c device address and should be tied to ground. 3.5.2.1 i 2 c mode the i 2 c master mode is designed for read-only op- eration during self-booting from a serial eeprom. a typical self-boot sequence with a microchip x24256 serial eeprom, or equivalent, is shown in figure 10. on exit from reset, the cs4811 sends an initial write preamble to the eeprom which consists of a i 2 c start condition and the slave ad- 0 1 2 21 22 23 24 cs cdout read command 16-bit address = 0x0000 cdin data msb 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 clk 7 8 9 10 11 3 4 5 6 30 31 25 26 27 28 29 data + n 7 6 5 4 3 2 1 0 figure 9. control port timing, spi master mode self-boot
cs4811 ds486pp2 15 dress byte. the slave address consists of the 4 most significant bits set to 1010, the following 3 bits cor- responding to the device select bits, a2, a1 and a0 set to 000 and the last bit (r/ w ) set to 0. following this, a 2-byte eeprom starting address of 0x0000 is sent to the eeprom. the 2-byte eeprom starting address uses only the lowest 13 bits and sets the highest 3 bits to zero. to begin reading from the eeprom, the cs4811 sends another start condition followed by a read preamble. the read preamble is identical to the write preamble except for the state of the r/ w bit. the cs4811 then auto- matically clocks out sequential bytes from the ee- prom until the last byte has been received. these bytes include initialization and configuration data for the device along with the application firmware code. after the last byte, the cs4811 initiates a stop condition and begins program execution. at this point, the serial control port becomes inactive and cannot be accessed. 3.6 resets full chip reset can only be achieved by asserting the rst pin. with rst asserted, the chip enters low power mode during which the control port, codec and audio processor are reset, all registers are returned to their default values and the dac outputs are muted. the rst pin should be asserted during power-up until the power supplies have reached steady state. if the supply voltage drops below 4 volts, the co- dec is reset, the dac outputs are muted and the audio processor automatically executes a soft re- set. upon exit from a codec reset, the audio proces- sor restarts the application code and the codec performs the following procedure: ? the codec resynchronizes. ? the dac outputs unmute. 0 1 2 3 16 17 18 19 25 26 27 28 29 chip address (write) chip address (read) memory address data data +n start ack no start stop ack ack ack ack 1 0 1 0 a 2 a 1 a 0 0 0 0 0 0 0 0 1 0 1 0 a 2 a 1 a 0 1 7 0 7 0 scl sda 34 35 36 37 30 31 32 33 8 9 10 4 5 6 7 figure 10. control port timing, i 2 c master mode self-boot
cs4811 16 ds486pp2 4. power supply and grounding proper layout and grounding is critical to obtaining optimal audio performance in your system. the most important rule to remember is to not allow currents from digital circuitry to couple into sensi- tive analog circuitry. this is generally done by us- ing a separate or filtered power supply for the analog circuitry, physically separating the analog and digital components and traces in the pcb layout and using wide traces or planes for ground and power. one misplaced component or trace can se- verely degrade overall system performance. when using separate supplies, the analog and digi- tal power should be connected via a ferrite bead, positioned closer than 1" to the device (see figure 11). the cs4811 va pin should be derived from the quietest power source available. if only one supply is available, use the suggested arrange- ment in figure 3. a single solid ground plane is the simplest ground- ing scheme that works well in many cases. in this case, all analog and digital grounds shown in figure 3 are tied to the same ground plane. howev- er, if separate analog and digital grounds are used, they should be tied together at one point with the location of this point determined by the circuit lay- out. by considering where the digital ground cur- rents will return to their supply, the connection point can be chosen to keep those currents from flowing through sensitive analog circuit areas. decoupling capacitors should be placed as close as possible to the device with the lowest value capac- itor closest to the chip. any power and ground con- nection vias should be placed near their respective component pins and should be attached directly to the appropriate plane. if traces are used for the power supplies to the cs4811, they should be as wide as possible to maintain low impedance. it is recommended to solder the cs4811 directly to the printed circuit board. soldering improves per- formance and enhances reliability. for an example layout, please refer to the cdb4811 data sheet. digital power plane note that the cs4811 is oriented with its digital pins towards the digital end of the board. digital interface analog signals & components analog power plane 1/8" > cs4811 ferrite bead figure 11. cs4811 suggested layout
cs4811 ds486pp2 17 5. pin descriptions dgnd ad1/cdin ad0/cs spi /i2c res-vd res-nc rst res-vd nc nc nc nc nc nc nc nc res-dgnd res-dgnd nc nc ain+ ain- va agnd res-nc res-nc cmout cmfilt+ cmfilt- res-nc res-dgnd res-nc nc nc nc nc nc nc nc nc nc aout+ aout- res-nc res-nc agnd va agnd res-nc res-nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vd dgnd scl/cclk sda/cdout res-nc res-nc res-nc res-nc res-nc nc nc nc nc nc nc nc nc res-dgnd res-nc xto xti dgnd vd dgnd pio0 pio1 ovl res-dgnd pio2 res-dgnd pio3 res-dgnd nc res-dgnd nc nc nc nc nc nc nc nc res-nc res-nc res-nc res-nc agnd va res-nc res-nc cs4811 100-pin mqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vd dgnd scl/cclk sda/cdout res-nc res-nc res-nc res-nc res-nc nc nc nc nc nc nc nc nc res-dgnd res-nc xto xti dgnd vd dgnd pio0 pio1 ovl res-dgnd pio2 res-dgnd pio3 res-dgnd nc res-dgnd nc nc nc nc nc nc nc nc res-nc res-nc res-nc res-nc agnd va res-nc res-nc cs4811 100-pin mqfp figure 12. pin assignments
cs4811 18 ds486pp2 power supply va - analog power power: analog supply, +5 v. agnd - analog ground ground: analog ground. vd - digital power power: digital supply, +5 v. dgnd - digital ground ground: digital ground. analog input ain+/- - differential audio input inputs: these pins accept differential analog input signals and are biased to the internal reference voltage of approximately 2.3 v. the + and - input signals should be 180 out of phase resulting in a nominal differential input voltage of twice the input pin voltage. a single-ended signal may also be directly applied to either the + or - input with the other input ac coupled to ground through a capacitor. in general, differential input signals provide better performance. however, singled-ended inputs may result in reduced cost. inputs may be ac or dc coupled. dc coupled input signals must be biased at 2.3 v. any remaining dc offset is removed by an internal digital hpf. for best performance, a passive anti-aliasing filter is required. the typical connection diagram in figure 3. shows the recommended single-ended input circuit. figure 6 shows the recommended differential input circuit. ovl - adc overload indicator output: this pin is asserted when the adc is clipping. the pin does not latch and de-asserts when clipping stops. analog output aout+/- - differential audio output outputs: these pins output differential analog signals which are biased to the internal reference voltage of approximately 2.3 v. the + and - output signals are 180 out of phase resulting in a nominal differential output voltage of twice the output pin voltage. for best performance, an anti-imaging filter is required. figure 7 shows the recommended second and third order butterworth differential-to-single- ended output buffer circuits.
cs4811 ds486pp2 19 voltage reference cmout - common mode output output: this pin provides an internally generated reference of 2.3 v to be used for biasing external analog circuitry. the load on cmout must be dc only, with an impedance of not less than 50 kilohms. cmfilt+,cmfilt- - common mode filter connections inputs: these pins are connections for external filter components required by the internal common mode reference circuit. see the typical connection diagram in figure 3. for details. serial control port spi /i 2 c - serial control port format select input: this pin configures the control port for i 2 c format if tied to vd or spi format if tied to dgnd. scl/cclk - serial control port clock output: this pin clocks serial control port data into and out of sda in i 2 c mode. in spi mode, it clocks control port data into cdin and out of cdout. ad0/ cs - i 2 c address bit 0 / spi chip select input/output: in i 2 c ? mode, ad0 is an input and must be tied to ground. in spi mode, cs is an output and is used to select the boot eeprom. ad1/cdin - i 2 c address bit 1 / spi data input input: in i 2 c ? mode, ad1 is an input and must be tied to ground. in spi mode, cdin is the serial control port data input and is clocked in on the rising edge of cclk. sda/cdout - i 2 c data / spi data output bidirectional/output: in i 2 c ? mode, sda is the bidirectional data i/o line. in spi mode, cdout is the serial control port data output and is clocked out on the falling edge of cclk. clock and crystal xti, xto - crystal oscillator connections (master clock) input, output: these pins provide connections for an external parallel resonant quartz crystal. alternately, an external clock source may be applied to xti. the clock frequency must be 256xfs.
cs4811 20 ds486pp2 miscellaneous pio0:3 - general purpose inputs/outputs bidirectional: these pins are general-purpose digital i/o pins. the default state is input. the functionality of these pins after boot-up is determined by the application firmware. rst - reset input: this pin causes the device to enter a low power mode and forces all control port and i/o registers to be reset to their default values. the control port can not be accessed when reset is low. nc - no connect input: these pins are not internally connected and should be tied to ground for optimal performance. res-nc - reserved, no connect these pins are reserved and must be left unconnected for normal operation. res-vd - reserved, connect to vd these pins are reserved and must be tied to vd for normal operation. res-dgnd - reserved, connect to dgnd these pins are reserved and must be tied to digital ground for normal operation. res-agnd - reserved, connect to agnd these pins are reserved and must be tied to analog ground for normal operation.
cs4811 ds486pp2 21 6. parameter definitions dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 hz to 20 khz), including distortion components. expressed in decibels. adcs are measured at -1 dbfs as suggested in aes 17-1991 annex a. idle channel noise / signal-to-noise-ratio the ratio of the rms analog output level with 1 khz full scale digital input to the rms analog output level with all zeros into the digital input. measured a-weighted over a 10 hz to 20 khz bandwidth. units in decibels. this specification has been standardized by the audio engineering society, aes17-1991, and referred to as idle channel noise. this specification has also been standardized by the electronic industries association of japan, eiaj cp-307, and referred to as signal-to-noise-ratio. total harmonic distortion (thd) thd is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. units in decibels. interchannel isolation a measure of crosstalk between channels. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. frequency response a measure of the amplitude response variation from 20 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel gain mismatch for the adcs, the difference in input voltage that generates the full scale code for each channel. for the dacs, the difference in output voltages for each channel with a full scale digital input. units are in decibels. gain error the deviation from the nominal full scale output for a full scale input. gain drift the change in gain value with temperature. units in ppm/c. offset error for the adcs, the deviation in lsb's of the output from mid-scale with the selected input grounded. for the dac's, the deviation of the output from zero (relative to cmout) with mid-scale input code. units are in volts.
cs4811 22 ds486pp2 7. package dimensions inches millimeters dim min nom max min nom max a -- -- 0.134 -- -- 3.400 a1 0.010 0.012 0.014 0.250 0.30 0.350 b 0.009 0.012 0.015 0.220 0.30 0.380 d 0.667 0.677 0.687 16.950 17.20 17.450 d1 0.547 0.551 0.555 13.900 14.00 14.100 e 0.904 0.91 0.923 22.950 23.20 23.450 e1 0.783 0.79 0.791 19.900 20.0 20.100 e* 0.022 0.026 0.030 0.550 0.65 0.750 0.000 4.00 7.000 0.00 4.00 7.00 l 0.029 0.035 0.041 0.73 0.88 1.03 * nominal pin pitch is 0.65 mm = 0.65 bsc controlling dimension is mm. jedec designation: ms022 ase/spil 100l mqfp package drawing e1 e d1 d 1 e l b a1 a
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