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rev 1.1 7/12/00 characteristics subject to change without notice. 1 of 13 www.xicor.com recommend system management alternative: x5043 not recommended for new designs 2k x25020 256 x 8 bit spi serial eeprom with block lock protection features 2mhz clock rate spi modes (0,0 & 1,1) 256 x 8 bits 16-byte page mode low power cmos 10? standby current 3ma active write current 2.7v to 5.5v power supply block lock protection protect 1/4, 1/2 or all of eeprom array built-in inadvertent write protection power-up/power-down protection circuitry write latch write protect pin self-timed write cycle 5ms write cycle time (typical) high reliability endurance: 1,000,000 cycles per byte data retention: 100 years esd protection: 2000v on all pins 8-lead soic package description the x25020 is a cmos 2048-bit serial eeprom, internally organized as 256 x 8. the x25020 features a serial interface and software protocol, allowing opera- tion on a simple three-wire bus. the bus signals are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input, allowing any number of devices to share the same bus. the x25020 also features two additional inputs that provide the end user with added ?xibility. by asserting the hold input, the x25020 will ignore transitions on its inputs, thus allowing the host to service higher pri- ority interrupts. the wp input can be used as a hard- wire input to the x25020 (disabling all write attempts), thus providing a mechanism for limiting end user capa- bility of altering the memory. the x25020 utilizes xicors proprietary direct write cell, providing a minimum endurance of 1,000,000 cycles per byte and a minimum data retention of 100 years. block diagram command decode and control logic write control and timing logic write protect logic x decode logic 256 byte array 4 x 128 y decode data register 4 x 128 16 x 128 so si sck cs hold wp 4 4 16 status register 16 8 direct write and block lock protection is a trademark of xicor, inc.
x25020 characteristics subject to change without notice. 2 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs pin descriptions serial output (so) so is a push/pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select (cs ) when cs is high, the x25020 is deselected and the so pin is at high impedance; unless an internal write operation is underway, the x25020 will be in the standby power mode. cs low enables the x25020, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. write protect (wp ) when wp is low, nonvolatile writes to the x25020 are disabled, but the part otherwise functions normally. when wp is held high, all functions, including nonvol- atile writes operate normally. wp going low while cs is still low will interrupt a write to the x25020. if the internal write cycle has already been initiated, wp going low will have no affect on a write. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume com- munication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. pin configuration pin names principles of operation the x25020 is a 256 x 8 eeprom designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the x25020 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising sck. cs must be low and the hold and wp inputs must be high during the entire operation. table 1 contains a list of the instructions and their opcodes. all instructions, addresses and data are transferred msb ?st. data input is sampled on the ?st rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then resume operations. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input to place the x25020 into a ?ause condition. after releasing hold , the x25020 will resume operation from the point when hold was ?st asserted. symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage hold hold input soic cs so wp v ss v cc hold sck si x25020 1 2 3 4 8 7 6 5
x25020 characteristics subject to change without notice. 3 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs write enable latch the x25020 contains a ?rite enable latch. this latch must be set before a write operation will be com- pleted internally. the wren instruction will set the latch and the wrdi instruction will reset the latch. this latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status reg- ister write cycle. status register the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is format- ted as follows: bp0 and bp1 are set by the wrsr instruction. wel and wip are read-only and automatically set by other operations. the write-in-process (wip) bit indicates whether the x25020 is busy with a write operation. when set to a ?? a write is in progress, when set to a ?? no write is in progress. during a write, all other bits are set to ?? the write enable latch (wel) bit indicates the status of the ?rite enable latch. when set to a ?? the latch is set, when set to a ?? the latch is reset. the block protect (bp0 and bp1) bits are nonvolatile and allow the user to select one of four levels of protec- tion. the x25020 is divided into four 512-bit segments. one, two, or all four of the segments may be protected. that is, the user may read the segments but will be unable to alter (write) data within the selected seg- ments. the partitioning is controlled as illustrated below. 76543210 0 0 0 0 bp1 bp0 wel wip status register bits array addresses protected bp1 bp0 0 0 none 0 1 $c0?ff 1 0 $80?ff 1 1 $00?ff table 1. instruction set notes: *instructions are shown msb in leftmost position. instructions are transferred msb ?st. instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch (disable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address (1 to 32 bytes) clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the eeprom memory array, cs is ?st pulled low to select the device. the 8-bit read instruction is transmitted to the x25020, followed by the 8-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is auto- matically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached ($ff), the address counter rolls over to address $00, allowing the read cycle to be continued inde?itely. the read operation is terminated by taking cs high. refer to the read eeprom array operation sequence illustrated in figure 1.
x25020 characteristics subject to change without notice. 4 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs to read the status register cs line is ?st pulled low to select the device, followed by the 8-bit rdsr instruction. after the read status register opcode is sent, the contents of the status register are shifted out on the so line. figure 2 illustrates the read status reg- ister sequence. write sequence prior to any attempt to write data into the x25020, the ?rite enable latch must ?st be set by issuing the wren instruction (see figure 3). cs is ?st taken low, then the wren instruction is clocked into the x25020. after all eight bits of the instruction are trans- mitted, cs must then be taken high. if the user con- tinues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the eeprom memory array, the user issues the write instruction, followed by the address and then the data to be written. this is minimally a thirty-two clock operation. cs must go low and remain low for the duration of the operation. the host may continue to write up to 16 bytes of data to the x25020. the only restriction is that the 16 bytes must reside on the same page. if the address counter reaches the end of the page and the clock continues, the counter will ?oll over to the ?st address of the page and overwrite any data that may have been written. for the write operation (byte or page write) to be com- pleted, cs can only be brought high after bit 0 of data byte n is clocked in. if it is brought high at any other time, the write operation will not be completed. refer to figures 4 and 5 for a detailed illustration of the write sequences and time frames in which cs going high are valid. to write to the status register, the wrsr instruction is followed by the data to be written. data bits 0, 1, 4, 5, 6 and 7 must be ?? figure 6 illustrates this sequence. while the write is in progress following a status register or eeprom write sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. hold operation the hold input should be high (at v ih ) under normal operation. if a data transfer is to be interrupted, hold can be pulled low to suspend the transfer until it can be resumed. the only restriction is the sck input must be low when hold is ?st pulled low, and sck must also be low when hold is released. the hold input may be tied high either directly to v cc or tied to v cc through a resistor. operational notes the x25020 powers-up in the following state: the device is in the low power standby state. a high to low transition on cs is required to enter an active state and receive an instruction. so pin is high impedance. the ?rite enable latch is reset. data protection the following circuitry has been included to prevent inadvertent writes: the ?rite enable latch is reset upon power-up. a wren instruction must be issued to set the ?rite enable latch. ?s must come high at the proper clock count in order to start a write cycle.
x25020 characteristics subject to change without notice. 5 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs figure 1. read eeprom array operation sequence figure 2. read status register operation sequence figure 3. write enable latch sequence 10 11 12 13 14 15 16 17 18 19 20 21 22 data out cs sck si so msb high impedance instruction byte address 23456789 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 01234567 cs si sck high impedance so
x25020 characteristics subject to change without notice. 6 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs figure 4. byte write operation sequence figure 5. page write operation sequence 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs sck si so high impedance instruction byte address data byte 23456789 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 sck si cs 10 11 12 13 14 15 16 17 18 19 20 21 22 23 sck si instruction byte address data byte 1 cs 40 41 42 43 44 45 46 47 data byte 2 data byte 3 data byte 4 23456789 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
x25020 characteristics subject to change without notice. 7 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs figure 6. write status register operation sequence 0123456789 cs sck si so high impedance instruction data byte 76543210 10 11 12 13 14 15
x25020 characteristics subject to change without notice. 8 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs absolute maximum ratings temperature under bias ...................?5? to +135? storage temperature ........................?5? to +150? voltage on any pin with respect to v ss ....... ?v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds).........300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0? +70? industrial ?0? +85? supply voltage limits x25020-2.7 2.7 to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) power-up timing capacitance t a = +25?, f = 1mhz, v cc = 5v. notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. max. i cc v cc supply current (active) 3 ma sck = v cc x 0.1/v cc x 0.9 @ 1mhz, so = open i sb v cc supply current (standby) 10 ? cs = v cc , v in = v ss or v cc ?0.3v i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v il (1) input low voltage ?.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2ma v oh output high voltage v cc ?0.8 v i oh = ?ma symbol parameter min. max. unit t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms symbol test max. unit conditions c out (2) output capacitance (so) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp , hold ) 6 pf v in = 0v
x25020 characteristics subject to change without notice. 9 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs equivalent a.c. load circuit at 5v v cc a.c. test conditions 5v 2.16k ? 3.07k ? output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 a.c. characteristics (over recommended operating conditions, unless otherwise specified) data input timing data output timing notes: (3) parameter is tested on a sample basis only. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. symbol parameter min. max. unit f sck clock frequency 0 2 mhz t cyc cycle time 1000 ns t lead cs lead time 500 ns t lag cs lag time 500 ns t wh clock high time 400 ns t wl clock low time 400 ns t su data setup time 100 ns t h data hold time 100 ns t ri data in rise time 2 s t fi data in fall time 2 s t hd hold setup time 200 ns t cd hold hold time 200 ns t cs cs deselect time 500 ns t wc (4) write cycle time 10 ms symbol parameter min. max. unit f sck clock frequency 0 1 mhz t dis output disable time 500 ns t v output valid from clock low 360 ns t ho output hold time 0 ns t ro (3) output rise time 300 ns t fo (3) output fall time 300 ns t lz hold high to output in low z 100 ns t hz hold low to output in high z 100 ns
x25020 characteristics subject to change without notice. 10 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs serial output timing serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
x25020 characteristics subject to change without notice. 11 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs hold timing symbol table sck cs si so t hd t lz hold t cd t hz t cd t hd waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
x25020 characteristics subject to change without notice. 12 of 13 rev 1.1 7/12/00 www.xicor.com not recommended for new designs packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
not recommended for new designs x25020 characteristics subject to change without notice. 13 of 13 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.1 7/12/00 www.xicor.com ordering information part mark convention x25020 p -v device v cc limits 2.7v = 2.7v to 5.5v temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? package s = 8-lead soic t blank = 8-lead soic f = 2.7v to 5.5v, 0? to +70? g = 2.7v to 5.5v, ?0? to +85? x25020 x x

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