page 1 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7266r1 encoder to microprocessor interface chip chip the ls7266r1 is an lsi monolithic cmos building block useful in motion control applications. the two 24-bit multimode counters, registers, and logic enables a microprocessor to track the speed, direction, position, and index of one or two optical incremental encoders. in addition to an 8-bit data bus, programmable real-time inputs and outputs are provided for hardware based control functions and status indication. note: us digital has already designed the ic's on this data sheet into various products. please see the pc7266 , ad5 or ed2 . features: ? x4 or x1 resolution multiplication. ? two preloadable 24-bit up/down counters. ? choice of two 20-pin packages: soic surface mount or dip (600mil). ? x1 or x2 or x4 resolution multiplier. ? binary, bcd, divide-by-n, range limit, non-recycle & non-quadrature modes. ? 2-axis 24-bit comparators. ? independent mode programmability for each axis. ? 17 mhz in quadrature mode. ? 4 control registers. ? readable status flag register. ? digital filtering of the input quadrature clocks. ? programmable 8-bit separate filter clock prescalers for each axis. ? error flags for excess noise. ? 8-bit tri-state i/o bus. ? latched counter outputs. ? input/output ttl & cmos compatible. ? 5 volt operation. block diagram of counter & registers: ordering information: description: technical data, rev. 11.21.00, november 2000 all information subject to change without notice. dip package (600mil): LS7266R1-DIP surface mount package: ls7266r1-soic price: $16.55 / 1 $13.25 / 25 $10.60 / 100 $9.00 / 500 $7.65 / 1k
page 2 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7266r1 encoder to microprocessor interface chip chip either quadrature encoded clocks or non-quadrature clocks can be applied to a and b. in quadrature mode, a and b are digitally filtered and decoded for up/dn clock. in non-quadrature mode, the filter and decoder circuits are bypassed. also, in non- quadrature mode, a serves as the count input and b as the direction input, with b=1 selecting up count and b=0 selecting down count mode. the quadrature code will be decoded and used to clock and steer the 24-bit counter. it can be programmed to generat e one clock once per quadrature cycle, once per 1/2 cycle or once per 1/4 cycle (x1, x2 or x4 mode). maximum count frequency is 17 mhz in quadrature mode, and 30 mhz in non-quadrature mode. xa (pin 20) xb (pin 21) ya (pin 25) yb (pin 24) programmable input to operate either as direct load cntr or direct load ol or synchronous load cntr or synchronous load ol. the synchronous load mode is intended for interfacing with the encoder index output in quadrature clock mode. in direct load mode, a logic low level is the active level at this input. in synchronous load mode the active level can be programmed to be either a logic low or a logic high. both quarter cycle and half cycle index signals are supported by this input in the index ed load mode. the synchronous function must be disabled in non-quadrature count mode. programmable input to operate either as direct reset cntr or count enable/disable gate or synchronous reset cntr. the synchronous reset cntr mode is intended for interfacing with the encoder index output in quadrature clock mode. the synchronous reset cntr mode the active level can be programmed to be either a logic low or a logic high. in count enable/disabl e mode, a logic high at this input enables the counter and a logic low level disables the counter. both quarter cycle and half cy cle index signals are supported by this input in the indexed reset cntr mode. xflg1 (pin 22) yflg1 (pin 27) programmable output to operate either as carry (active low), or compare (generated when pr = cntr; active low), or idx (flag bit 6), or carry/borrow (active low). xflg2 (pin 23) yflg2 (pin 26) programmable output to operate as either borrow (active low), or u/d (flag bit 5), or e (flag bit 4). xlcntr/xlol (pin 19) ylcntr/ylol (pin 1) xrcntr/xabg (pin 18) yrcntr/yabg (pin 28) the ls7266 has two functionally equivalent halves, the x side and the y side, selected by a dedicated input pin xnot/y (pin 17). each hal f is a completely independent counting system. within each counting system there is a data channel and a control channel, selected by a dedicated input addressing pin c/ dnot (pin 13). reads of the data channel return one byte from the counting system output latch, and writes to the data channel store one byte in a preset latch. the 24-bit counter itself sits in between the preset latch and the output latch, and is not directly addressable. instead, comm ands to the control channel of a counting system transfer data from the preset latch into the counter, or from the counter to the output latch. the preset lat ch and the output latch are also three bytes wide; it takes three successive reads or writes to transfer a full count to or from the data channel. there is a hi dden byte pointer bp that controls which byte of the latches is being addressed via the data channel; this byte pointer cannot be directly written, but it can be reset via the control channel. bp auto-increments after every byte transfer to the data channel, and data is read out least-significant byte first. the control channel has different behavior depending on whether it is being read or written. when read, the control channel alw ays returns six bits of status information from the flag register. when writing to the control channel, data is sent to one of four different five-bit-wide co ntrol registers: reset/load decoder (rld), counter mode register (cmr), input/output control register (ior), and index control register (idr). bits d5 and d6 of th e data determine which register is addressed; bit d7 is a special bit that forces the write to occur in both the x and y counting systems when set. there is no provision for reading back the contents of any of the control channel write registers; the host software must keep a local copy of what was sent. one final wrinkle involves the prescale counter register. to load this register, host software must first write a single byte t o the lowest order byte of the preset latch; then the software must invoke a command to transfer data from this latch to the prescaler latch by writing a bit into th e rld register. functional descriptions: x & y axis inputs/outputs: common inputs/outputs: wr (pin 14) write input: control/data bytes are written at the trailing edge of low level pulse applied to this input. rd (pin 16) read input: a low level applied to this input enables the flags and ols to be read on the data bus. cs (pin 15) chip select input: a low level applied to this input enables the chip for read and write. c/d (pin 13) control/data input: this input selects between a control register or a data register for read/write. when low, a data register is selected. when high, a control register is selected. d0-d7 (pins 4-11) data bus input/output: the 8-bit three-state data bus is the i/o port through which all data transfers take place between the ls7266 and the host processor. fck (pin 2) filter clock input: the fck is divided down internally by two 8-bit programmable prescalers, one for each channel. x/y (pin 17) x/y select: x/y = 0 selects x-axis and x/y = 1 selects the y-axis. x/y is overridden by d7 = 1 in control write mode(c/d = 1). vdd (pin 3) +5vdc vss (pin 12) gnd
page 3 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7266r1 encoder to microprocessor interface chip chip the 24-bit preset register is the input port for the 24-bit counter and the filter clock prescaler (psc). the data is first written into the preset register in 3 write cycles (least significant byte 1st). the byte pointer is automatically incremented with each write cycle. you must reset the byte pointer (bp) before making the first write. the 24-bit counter value at any instant can be accessed by transferring its contents to the 24-bit output latch. note that only good stable data will be passed from the counter to the output latch even if the counter bits are in the midst of a transition. this chip will internally stretch the latch pulse if necessary until the counter has stabilized. the 3 bytes are then read from the output latch (least significant byte 1st). the byte pointer is automatically incremented with each read cycle. you must reset the byte pointer (bp) before making the first read. range limit: in range limit count mode, an upper and a lower limit is set, mimicking limit switches in the mechanical counterpart. the upper limit is set by the content of the pr and the lower limit is set to be 0. the cntr freezes as cntr = pr when counting up and at cntr = 0 when counting down. at either of these limits, the counting is resumed only when the count direction is reversed. non-recycle: in non-recycle count mode the cntr is disabled, whenever a count overflow or underflow takes place. the end of cycle is marked by the generation of a carry (in up count) or a borrow (in down count). the cntr is re-enabled when a reset or load operation is performed on the cntr. modulo-n: in modulo-n count mode, a count boundary is set between 0 and the content of the pr. when counting up, at cntr = pr, the cntr is reset to 0 and the up count is continued from that point. when counting down, at cntr = 0, the cntr is loaded with the content of pr and down count is continued from that point. the modulo-n is true bidirectional in that the divide-by-n output frequency is generated in both up and down direction of counting for same n and does not require the complement of n in the up instance. in frequency divider application the modulo-n output frequency can be obtained at either the compare (cy) or the bw output. modulo-n output frequency fn= (fi/ (n+1)) where fi = input count frequency and n = pr. output latch (read only, data): preset register (write only, data): counter mode register (cmr): each prescaler (psc) is an 8-bit programmable modulo-n down counter, driven by the filter clock input (fck). the factor n is loaded into a psc, from the preset register (pr) byte 0, in the rld register. this allows the ability to generate independent filter clock frequencies for each channel. final filter clock frequency = (fck / (psc +1)). filter clock prescalers (xpsc & ypsc): notes: 1) d7 is the most significant bit of the data bus. 2) x means "don't care". function disable chip write to xrld write to yrld write to both xrld and yrld write to xcmr write to ycmr write to both xcmr and ycmr write to xior write to yior write to both xior and yior write to xidr write to yidr write to both xidr and yidr write to x preset register, increment address counter write to y preset register, increment address counter read x output latch, increment address counter read y output latch, increment address counter read x flag register read y flag register d7 d6 d5 c/d rd wr x/y cs xxxxxxx 1 00011 0 0 00011 1 0 10011 x 0 00111 0 0 00111 1 0 10111 x 0 01011 0 0 01011 1 0 11011 x 0 01111 0 0 01111 1 0 11111 x 0 xxx01 0 0 xxx01 1 0 xxx0 10 0 xxx0 11 0 xxx1 10 0 xxx1 11 0 writing to 1 of the 4 control registers: set control/data high. bits 5 and 6 are used as address bits to select one of the 4 registers. bit 7 allows the data to apply to both x and y registers and overrides x/y input. only bits 0-4 are stored. chip access:
page 4 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7266r1 encoder to microprocessor interface chip chip the flag registers hold the status information of the cntrs and can be read out on the data bus when c\d = 1. e = 1 indicates excessive noise at the inputs but not a definite count error. once set, e can only be reset via the rld. bt: toggles every time cntr underflows ct: toggles every time cntr overflows cpt: toggles every time pr = cntr s: reset to 0 when cntr overflows e: set to 1 when excessive noise is present at the count inputs. u/d: set to 1 when counting up and reset to 0 when counting down. idx: set to 1 when index is valid. reset & load signal decorders (rld): status flag register (read only, control): control functions may be combined. the toggle flip flops are triggered by the trailing edges of the associated carry, borrow, or compare match. thus there is a 1-clock delay between the input and output of each flip flop. unless otherwise specified, assume the longest prop delay from any input to any output is <110ns. input/output control register (ior): parameter min. max. units voltage at any input -.5 vcc+.5 volts supply voltage (vcc) - 7 volts operating temperature -25 80 c storage temperature -65 150 c absolute maximum ratings: parameter min. max. units notes supply voltage 4.5 5.5 volts supply current 800 a all clocks off input logic low 0.8 volts input logic high 2.0 volts output low voltage 0.5 volts io utsink=5ma output high voltage vcc-.5 volts ioutsource=1ma input leakage current 30 n a output source current 1 ma v o = vcc-.5v output sink current 5 ma v o = 0.5v data bus leakage 60 na data bus off current dc electrical characteristics: either the lcntr/lol or the rcntr/abg inputs can be initialized to operate as an index input. when initialized as such, the index signal from the encoder, applied to one of these inputs performs either the reset cntr or the load cntr or the load ol operation synchronously with the quadrature clocks. note that only one of these inputs can be selected as the index at a time and hence only one type of indexing function can be performed in any given setup. the index function must be disabled in non-quadrature count mode. note 2 : rcntr/abg input must also be initialized as the reset cntr input via the ior register bit 2. note 1 : lcntr/lol input must also be initialized as the load cntr or the load ol input via the ior register bit 1. index control register (idr):
page 5 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7266r1 encoder to microprocessor interface chip chip parameter symbol min max unit wr pulse width t w 1 30 - ns cs setup time t w 2 30 - ns cs hold time t w 3 0 - ns c/d setup time t w 4 30 - ns c/d hold time t w 5 0 - ns x/y setup time t w 6 30 - ns x/y hold time t w 7 0 - ns data bus setup time t w 8 30 - ns data bus hold time t w 9 0 - ns back to back write delay tw10 60 - ns parameter symbol min max unit rd pulse width tr1 50 - ns cs setup time tr2 50 - ns cs hold time tr3 0 - ns c/d setup time tr4 50 - ns c/d hold time tr5 0 - ns x/y setup time tr6 50 - ns x/y hold time tr7 0 - ns data bus access time tr8 50 - ns data bus release time tr9 - 25 ns back to back read delay tr10 60 - ns read cycle: write cycle: filter clock fck & quadrature clocks a & b: write cycle timing: allow at least 30ns setup time after asserting both write and chip select for valid input data. read cycle timing: the data bus will become valid 50ns after asserting both read and chip select. release starts when either read or chip select is terminated. parameter symbol min max unit remarks fck high pulse width t1 14 - ns - fck low pulse width t2 14 - ns - fck frequency ffck - 35 mhz - mod-n filter clock (fckn) period t3 28 - ns t3 = (n+1)(t1+t2), where n = psc = 0 to ff(hex) fckn frequency ffckn - 35 mhz - quadrature separation t4 57 - ns - quadrature clock pulse width t5 115 - ns - quadrature clock frequency fqa, fqb - 4.3 mhz fqa = fqb = 1/8t3 note 4: fckn is the final modulo-n internal filter clock, arbitrarily shown here as modulo-1.
page 6 phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469 email: sales@usdigital.com l website: www.usdigital.com 11100 ne 34th circle l vancouver, washington 98682 usa ls7266r1 encoder to microprocessor interface chip chip note 8 : compare is generated when pr = cntr. in this timing diagram it is arbitrarily assumed that pr = 1. note 5 : shown here is positive index with solid line depicting 1/4 cycle index and dotted line depicting 1/2 cycle index. either lcntr/lol or rcntr/abg input can be used as the index input. note 6 : x1, x2 and x4 clocks are the final internal up/down count clocks derived from filtered and decoded quadrature clock inputs, a and b. note 7 : index0 is the synchronized internal "load ol" or "reset cntr" signal based on lcntr/lol or rcntr/abg input being selected as the index input, respectively. quadrature clock a, b & index input: carry, borrow, compare: ls7266r1 interface example a: ls7266r1 interface example b: paramemeter symbol min max unit remarks carry/borrow/compare/output width tq3 28 - ns tq3 = t3 parameter symbol min max unit remarks quadrature clock to count delay tq1 5t3 6t3 - - x1/x2/x4 count clock pulse width tq2 28 - ns tq2=t3 index input pulse width tidx 85 - ns tidx >= 3t3 index skew from a tai - 28 ns tai <= t3 carry, borrow, compare specifications: quadrature clock a, b & index input specifications:
|
