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copyright ? cirrus logic, inc. 2005 (all rights reserved) cirrus logic, inc. www.cirrus.com cs4271 24-bit, 192 khz stereo audio codec d/a features ! high performance ? 114 db dynamic range ? -100 db thd+n ! up to 192 khz sampling rates ! differential analog architecture ! volume control with soft ramp ? 1 db step size ? zero crossing click-free transitions ! selectable digital filters ? fast and slow roll off ! atapi mixing functions ! selectable serial a udio interface formats ? left justified up to 24-bit ?i 2 s up to 24-bit ? right justified 16-, 18-, 20-, and 24-bit ! control output fo r external muting ! selectable 50/15 s de-emphasis a/d features ! high performance ? 108 db dynamic range ? -98 db thd+n ! up to 192 khz sampling rates ! single-ended analog architecture ! multi-bit delta sigma conversion ! high-pass filter or dc offset calibration ! low-latency digital an ti-alias filtering ! automatic dithering of 16-bit data ! selectable serial audio interface formats ? left justified up to 24-bit ?i 2 s up to 24-bit system features ! direct interface with 5v to 2.5v logic levels ! internal digital loopback ! on-chip oscillator ! stand-alone or control port functionality 2.5 v to 5 v left and right mute controls ? modulator ? modulator low-latency anti-alias filter external mute control register / hardware configuration internal voltage reference internal oscillator volume control mixer selectable interpolation filter selectable interpolation filter reset left differential output right differential output switched capacitor dac and filter multibit oversampling adc multibit oversampling adc low-latency anti-alias filter high pass filter & dc offset calibration high pass filter & dc offset calibration pcm serial interface / loopback left input right input volume control level translator level translator serial audio input serial audio output 3.3 v to 5 v 5 v hardware or i 2 c/spi control data switched capacitor dac and filter august '05 ds592f1
cs4271 2 ds592f1 stand-alone mode feature set ! system features ? serial audio port master or slave operation ? internal oscillator for master clock ! d/a features ? auto-mute on static samples ? 44.1 khz 50/15 s de-emphasis available ? selectable serial audio interface formats " left justified up to 24-bit " i 2 s up to 24-bit ! a/d features ? automatic dithering for 16-bit data ? high-pass filter ? selectable serial audio interface formats " left justified up to 24-bit " i 2 s up to 24-bit software mode feature set ! system features ? serial audio port master or slave operation ? internal oscillator for master clock ? internal digital loopback available ! d/a features ? selectable auto-mute ? selectable interpolation filters ? selectable 32-, 44.1-, and 48-khz de-emphasis filters ? configurable atapi mixing functions ? configurable volume and muting controls ? selectable serial audio interface formats " left justified up to 24-bit " i 2 s up to 24-bit " right justified 16, 18, 20, and 24-bit ! a/d features ? selectable dithering for 16-bit data ? selectable high-pass filter or dc offset calibration ? selectable serial audio interface formats " left justified up to 24-bit " i 2 s up to 24-bit general description the cs4271 is a high-performance, integrated audio codec. the cs4271 performs stereo analog-to-digital (a/d) and digital-to-analog (d/a) conversion of up to 24-bit serial values at sample rates up to 192 khz. the d/a offers a volume control that operates with a 1 db step size. it incorporat es selectable soft ramp and zero crossing tran sition functions to eliminate clicks and pops. the d/a?s integrated digital mixing functions allow a va- riety of output configuratio ns ranging from a channel swap to a stereo-to-mono downmix. standard 50/15 s de-emphasis is available for sam- pling rates of 32, 44.1, an d 48 khz for compatibility with digital audio programs mastered using the 50/15 s pre- emphasis technique. integrated level translator s allow easy interfacing be- tween the cs4271 and other devices operating over a wide range of logic levels. an on-chip oscillator eliminat es the need for an external crystal oscillator circuit. this can reduce overall design cost and conserve circuit board space. the cs4271 au- tomatically uses the on-chip oscillator in the absence of an applied master clock, making this feature easy to use. independently addressable hi gh-pass filters are avail- able for the right and left ch annel of the a/d. this allows the a/d to be used in a wide variety of applications where one audio channel and one dc measurement channel is desired. the cs4271?s wide dynamic range, negligible distor- tion, and low noise make it id eal for applications such as a/v receivers, dvd-r, cd-r, digital mixing consoles, effects processors, set-top box systems, and automo- tive audio systems. ordering information product description package pb-free grade temp range container order # cs4271 24-bit, 192 khz stereo audio codec 28-pin tssop yes commercial -10 to +70 c tube cs4271-czz tape & reel cs4271-czzr automotive -40 to +85 c tube CS4271-DZZ tape & reel CS4271-DZZr cdb4271 cs4271 evaluation board no - - - cdb4271
cs4271 ds592f1 3 table of contents 1. pin descriptions - software mode ............................................................................. 5 2. pin descriptions - stand-alone mode ....................................................................... 7 3. characteristics and specifications ........................................................................ 9 specified operating conditions . .............. ................ ............. ............. ............. ........... 9 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 9 dac analog characteristics - commercial grade............................................ 10 dac analog characteristics - automotive grade ............................................ 11 dac combined interpolation & on-chip analog filter response................ 12 adc analog characteristics - commercial grade............................................ 14 adc analog characteristics - automotive grade ............................................ 15 adc digital filter characteristics......................................................................... 16 dc electrical characteristics ................................................................................ 17 digital characteristics............................................................................................... 17 switching characteristics - serial audio port................................................. 18 switching characteristics - i2c mode control port....................................... 21 switching characteristics - spi control port ................................................. 22 4. typical connection diagram ..................................................................................... 23 5. applications .............................................................................................................. ....... 24 5.1 stand-alone mode .......................................................................................................... .24 5.1.1 recommended powe r-up sequence ................................................................. 24 5.1.2 master/slave mode ............................. ................................................................ 24 5.1.3 system clocking ................................................................................................. 24 5.1.3.1 crystal applications (xti/xto) ........................................................... 24 5.1.3.2 clock ratio selection .......................................................................... 25 5.1.4 16-bit auto-dither ..... .......................................................................................... 26 5.1.5 auto-mute ........................................................................................................... 26 5.1.6 high pass filter ................................................................................................... 26 5.1.7 interpolation filter .............................................................................................. 26 5.1.8 mode selection & de-emphasis ......................................................................... 26 5.1.9 serial audio interface format selection .................... ......................................... 26 5.2 control port mode ......................................................................................................... .. 27 5.2.1 recommended power-up sequence - ac cess to control port mode ................ 27 5.2.2 master / slave mode selection ........................................................................... 27 5.2.3 system clocking ................................................................................................. 27 5.2.3.1 crystal applications (xti/xto) ........................................................... 27 5.2.3.2 clock ratio selection .......................................................................... 28 5.2.4 internal digital loopback .................................................................................... 30 5.2.5 dither for 16-bit data .......................................................................................... 30 5.2.6 auto-mute ........................................................................................................... 30 5.2.7 high pass filter and dc offset calibration ......................................................... 30 5.2.8 interpolation filter .............................................................................................. 31 5.2.9 de-emphasis ...................................................................................................... 31 5.2.10 oversampling modes ........................................................................................ 31 5.3 de-emphasis filter .......... .............................................................................................. .. 31 5.4 analog connections ........................................................................................................ 32 5.4.1 input connections ............................................................................................... 32 5.4.2 output connections ............................................................................................ 33 5.5 mute control .............................................................................................................. ...... 34 5.6 synchronization of multiple devices ................................................................................ 34 5.7 grounding and power supply decoupling ....................................................................... 34 6. control port interface .............................................................................................. 35
cs4271 4 ds592f1 6.1 spi mode .................................................................................................................. ....... 35 6.2 i2c mode .................................................................................................................. ........ 36 7. register quick reference .......................................................................................... 37 8. register description .................................................................................................... 38 8.1 mode control 1 - address 01h ......................................................................................... 38 8.1.1 functional mode (bits 7:6) .................................................................................. 38 8.1.2 ratio select (bits 5:4) ......................................................................................... 38 8.1.3 master / slave mode (bit 3) ................................................................................. 38 8.1.4 dac digital interface format (bits 2:0) ............................................................... 38 8.2 dac control - address 02h ............................................................................................. 39 8.2.1 auto-mute (bit 7) ................................................................................................. 39 8.2.2 interpolation filter sele ct (bit 6) .......................................................................... 39 8.2.3 de-emphasis control (bits 5:4) ........................................................................... 39 8.2.4 soft volume ramp-up af ter error (bit 3) ............................................................ 40 8.2.5 soft ramp-down before filter mode ch ange (bit 2) .......................................... 40 8.2.6 invert signal polarity (bits 1:0) ............................................................................ 40 8.3 dac volume & mixing control - address 03h ................................................................. 40 8.3.1 channel b volume = channel a volume (bit 6) ................................................. 40 8.3.2 soft ramp or zero cros s enable (bits 5:4) ......................................................... 40 8.3.3 atapi channel mixing and muting (bits 3:0) ...................................................... 41 8.4 dac channel a volume cont rol - address 04h .............................................................. 42 8.5 dac channel b volume cont rol - address 05h .............................................................. 42 8.5.1 mute (bit 7) .......................................................................................................... 42 8.5.2 volume control (bits 6:0) .................................................................................... 42 8.6 adc control - address 06h ............................................................................................. 43 8.6.1 dither for 16-bit data (bit 5) ................................................................................ 43 8.6.2 adc digital interface format (bit 4) .................................................................... 43 8.6.3 adc channel a & b mute (bits 3:2) .................................................................... 43 8.6.4 channel a & b high pass filter disable (bits 1:0) .............................................. 43 8.7 mode control 2 - address 07h ......................................................................................... 43 8.7.1 digital loopback (bit 4) ....................................................................................... 43 8.7.2 amutec = bmutec (bit 3) ............................................................................... 43 8.7.3 freeze (bit 2) ...................................................................................................... 44 8.7.4 control port enable (bit 1) ............... ................................................................... 44 8.7.5 power down (bit 0) ............................................................................................. 44 8.8 chip id - register 08h .................................................................................................... .44 8.8.1 chip id (bits 7:4) ................................................................................................. 44 8.8.2 chip revision (bits 3:0) ....................................................................................... 44 9. parameter definitions .................................................................................................. 45 10. package dimensions ..................................................................................................... 46 11. appendix ................................................................................................................. ........... 47
cs4271 ds592f1 5 1. pin descriptions - software mode xto bmutec xti aoutb- mclk aoutb+ lrck aouta+ sclk aouta- sdout amutec sdin filt+ dgnd agnd vd va vl vq3 scl/cclk ainb sda/cdin aina ad0/cs vq2 rst vq1 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 28-pin tssop
cs4271 6 ds592f1 pin name # pin description xto xti 1,2 crystal connections ( input/output ) - i/o pins for an external crystal which may be used to generate mclk. see ?crystal applications (xti/xto)? on pa ge 24 or ?crystal applications (xti/xto)? on page 27. mclk 3 master clock ( input/output ) -clock source for the delta-sigma modulators. see ?crystal applications (xti/xto)? on page 24 or ?crystal applications (xti/xto)? on page 27. lrck 4 left right clock (input/output ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 5 serial clock (input/output ) - serial clock for the serial audio interface. sdout 6 serial audio data output ( output ) - output for two?s complement serial audio data. sdin 7 serial audio data input ( input ) - input for two?s complement serial audio data. dgnd 8 digital ground ( input ) - ground reference for the internal digital section. vd 9 digital power ( input ) - positive power for the internal digital section. vl 10 logic power ( input ) - positive power for the digital input/output interface. scl/cclk 11 serial control port clock ( input ) - serial clock for the serial control port. sda/cdin 12 serial control data ( input / output ) - sda is a data i/o in i2c mode. cdin is the input data line for the control port interface in spi mode. ad0/cs 13 address bit 0 (i2c) / contro l port chip select (spi) (input) - ad0 is a chip address pin in i2c mode; cs is the chip select signal for spi format. rst 14 reset ( input ) - the device enters a low power mode when this pin is driven low. vq1 15 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. vq2 16 quiescent voltage ( input ) - connection for internal quiescent reference voltage. aina ainb 17, 18 analog input ( input ) - the full scale input level is specified in the adc analog characteristics specifica- tion table. vq3 19 quiescent voltage ( input ) - connection for internal quiescent reference voltage. va 20 analog power (input) - positive power for the internal analog section. agnd 21 analog ground ( input ) - ground reference for the internal analog section. filt+ 22 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. amutec 23 channel a mute control (output) - this pin is active during power-up initialization, reset, muting, when master clock to left/right clock freque ncy ratio is incorrect, or power-down. aouta- aouta+ aoutb+ aoutb- 24, 25, 26, 27 differential analog audio output ( output ) - the full scale differential output level is specified in the dac analog characteristics specification table. bmutec 28 channel b mute control (output) - this pin is active during power-up initialization, reset, muting, when master clock to left/right clock freque ncy ratio is incorrect, or power-down.
cs4271 ds592f1 7 2. pin descriptions - stand-alone mode xto bmutec xti aoutb- mclk aoutb+ lrck aouta+ sclk aouta- sdout (m/s )amutec sdin filt+ dgnd agnd vd va vl vq3 m0 ainb m1 aina i2s/lj vq2 rst vq1 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 28-pin tssop
cs4271 8 ds592f1 pin name # pin description xto xti 1,2 crystal connections ( input/output ) - i/o pins for an external crystal which may be used to generate the master clock. see ?crystal applications (xti/xto)? on page 24 or ?crystal applications (xti/xto)? on page 27. mclk 3 master clock ( input/output ) -clock source for the delta-sigma modulators. see ?crystal applications (xti/xto)? on page 24 or ?crystal applications (xti/xto)? on page 27. lrck 4 left right clock (input/output ) - determines which channel, left or right, is currently active on the serial audio data line. sclk 5 serial clock (input/output ) - serial clock for the serial audio interface. sdout (m/s ) 6 serial audio data output ( output ) - output for two?s complement serial audio data. this pin must be pulled-up or pulled-down to select master or slave mode. see ?master/slave mode? on page 24. sdin 7 serial audio data input ( input ) - input for two?s complement serial audio data. dgnd 8 digital ground ( input ) - ground reference for the internal digital section. vd 9 digital power ( input ) - positive power for the internal digital section. vl 10 logic power ( input ) - positive power for the digital input/output interface. m0 11 mode select 0 ( input ) - in conjunction with m1, selects operat ing mode. functionality is described in the hardware mode speed configuration table. m1 12 mode select 1 ( input ) - in conjunction with m0, selects operat ing mode. functionality is described in the hardware mode speed configuration table. i2s/lj 13 serial audio interface select (input) - selects either the left-justified or i 2 s format for the serial audio interface. rst 14 reset ( input ) - the device enters a low power mode when this pin is driven low. vq1 15 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. vq2 16 quiescent voltage ( input ) - connection for internal quiescent reference voltage. aina ainb 17, 18 analog input ( input ) - the full scale input level is specified in the adc analog characteristics specifica- tion table. vq3 19 quiescent voltage ( input ) - connection for internal quiescent reference voltage. va 20 analog power (input) - positive power for the internal analog section. agnd 21 analog ground ( input ) - ground reference for the internal analog section. filt+ 22 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. amutec 23 channel a mute control (output) - this pin is active during power-up initialization, reset, muting, when master clock to left/right clock freque ncy ratio is incorrect, or power-down. aouta- aouta+ aoutb+ aoutb- 24, 25, 26, 27 differential analog audio output ( output ) - the full scale differential output level is specified in the analog characteristics specification table. bmutec 28 channel b mute control (output) - this pin is active during power-up initialization, reset, muting, when master clock to left/right clock freque ncy ratio is incorrect, or power-down.
cs4271 ds592f1 9 3. characteristics and specifications (all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics an d specifications are derived from measurem ents taken at nominal supply voltages and t a = 25 c.) specified operat ing conditions (agnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v, all voltages with respect to ground.) (note 1) notes: 1. operation beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. 2. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. parameters symbol min nom max units dc power supplies: positive analog positive digital positive logic va vd vl 4.75 3.1 2.37 5.0 3.3 3.3 5.25 5.25 5.25 v v v ambient operating temperature (power applied) commercial grade automotive grade t a -10 -40 - - +70 +85 c c parameter symbol min typ max units dc power supplies: analog logic digital va vl vd -0.3 -0.3 -0.3 - - - +6.0 +6.0 +6.0 v v v input current (note 2) i in -- 10 ma analog input voltage v in gnd-0.3 - va+0.3 v digital input voltage v ind -0.3 - vl+0.3 v ambient operating temperature (power applied) t a -50 - +95 c storage temperature t stg -65 - +150 c
cs4271 10 ds592f1 dac analog characteristi cs - commercial grade (notes 3 to 7) notes: 3. one-half lsb of triangular pdf dither is added to data. 4. performance measurements taken with a full-scale 997 hz sine wave under test load r l = 3 k ? , c l = 10 pf 5. measurement bandwidth is 10 hz to 20 khz. 6. logic ?0? = gnd = 0v; logic ?1? = vl; vl = va unless otherwise noted. 7. v fs is tested under load r l but does not include attenuation due to z out parameter symbol min typ max unit dynamic performance dynamic range 24-bits a-weighted unweighted 16-bits unweighted 108 105 - 114 111 94 - - - db db db total harmonic distortion + noise 0 db -20 db -60 db thd+n - - - -100 -91 -51 -94 - -45 db db db idle channel noise / signal-to-noise ratio - 114 - db interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full scale different ial output voltage v fs 0.91xva 0.96xva 1.01xva vpp output resistance (note 7) z out - 100 - ? minimum ac-load resistance r l -3-k ? maximum load capacitance c l - 100 - pf
cs4271 ds592f1 11 dac analog characteristi cs - automotive grade (notes 3 to 7) parameter symbol min typ max unit dynamic performance dynamic range 24-bits a-weighted unweighted 16-bits unweighted 106 103 - 114 111 94 - - - db db db total harmonic distortion + noise 0 db -20 db -60 db thd+n - - - -100 -91 -51 -92 - -43 db db db idle channel noise / signal-to-noise ratio - 114 - db interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch icgm - 0.1 - db gain drift - 100 - ppm/c analog output characteristics and specifications full scale different ial output voltage v fs 0.91xva 0.96xva 1.01xva vpp output resistance (note 7) z out - 100 - ? minimum ac-load resistance r l -3-k ? maximum load capacitance c l - 100 - pf
cs4271 12 ds592f1 dac combined interpol ation & on-chip anal og filter response (note 12) parameter fast roll-off unit min typ max single speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .547 - - fs stopband attenuation (note 10) 90 - - db group delay - 12/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 10) 80 - - db group delay - 4.6/fs - s quad speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 10) 90 - - db group delay - 4.7/fs - s
cs4271 ds592f1 13 dac combined interp olation & on-chip analog filter response (cont) (note 12) notes: 8. slow roll-off interpolation filter is only available in control port mode. 9. response is clock dependent and will scale with fs. no te that the response plots (figures 21 to 44) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 10. single and double speed mode measurement bandwidth is from stopband to 3 fs. quad speed mode measurement bandwidth is from stopband to 1.34 fs. 11. de-emphasis is available only in single speed mode; only 44.1 khz de-emphasis is available in stand- alone mode. 12. plots of this data are contained in the ?appen dix? on page 47. see figure 21 through figure 44. parameter slow roll-off (note 8) unit min typ max single speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 64 - - db group delay - 6.5/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .792 - - fs stopband attenuation (note 10) 70 - - db group delay - 3.9/fs - s quad speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .868 - - fs stopband attenuation (note 10) 75 - - db group delay - 4.2/fs - s
cs4271 14 ds592f1 adc analog characteristi cs - commercial grade measurement bandwidth is 10 hz to 20 khz unless ot herwise specified. input is 1 khz sine wave. notes: 13. referred to the typi cal full-scale input voltage. parameter symbol min typ max unit single speed mode fs = 48 khz dynamic range a-weighted unweighted 102 99 108 105 - - db db total harmonic distortion + noise (note 13) -1 db -20 db -60 db thd+n - - - -98 -85 -45 -92 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 102 99 - 108 105 102 - - - db db db total harmonic distortion + noise (note 13) -1 db -20 db -60 db 40khz bandwidth -1 db thd+n - - - - -98 -85 -45 -95 -92 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 102 99 - 108 105 102 - - - db db db total harmonic distortion + noise (note 13) -1 db -20 db -60 db 40khz bandwidth -1 db thd+n - - - - -98 -85 -45 -95 -92 - - - db db db db dynamic performance for all modes interchannel isolation - 110 - db interchannel phase deviation - 0.0001 - degree dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5% gain drift - 100 - ppm/c offset error hpf enabled hpf disabled - - 0 100 - - lsb lsb analog input characteristics full-scale input voltage 0.51xva 0.565xva 0.62xva vpp input impedance 18 - - k ?
cs4271 ds592f1 15 adc analog characteristi cs - automotive grade measurement bandwidth is 10 hz to 20 khz unless othe rwise specified. input is 1 khz sine wave.) notes: 14. referred to the typi cal full-scale input voltage. parameter symbol min typ max unit single speed mode fs = 48 khz dynamic range a-weighted unweighted 101 98 108 105 - - db db total harmonic distortion + noise (note 14) -1 db -20 db -60 db thd+n - - - -98 -85 -45 -91 - - db db db double speed mode fs = 96 khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 101 98 - 108 105 102 - - - db db db total harmonic distortion + noise (note 14) -1 db -20 db -60 db 40khz bandwidth -1 db thd+n - - - - -98 -85 -45 -95 -91 - - - db db db db quad speed mode fs = 192 khz dynamic range a-weighted unweighted 40khz bandwidth unweighted 101 98 - 108 105 102 - - - db db db total harmonic distortion + noise (note 14) -1 db -20 db -60 db 40khz bandwidth -1 db thd+n - - - - -98 -85 -45 -95 -91 - - - db db db db dynamic performance for all modes interchannel isolation - 110 - db interchannel phase deviation - 0.0001 - degree dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5% gain drift - 100 - ppm/c offset error hpf enabled hpf disabled - - 0 100 - - lsb lsb analog input characteristics full-scale input voltage 0.51xva 0.565xva 0.62xva vpp input impedance 18 - - k ?
cs4271 16 ds592f1 adc digital filter characteristics (note 17) notes: 15. the filter frequency res ponse scales precisely with fs. 16. response shown is for fs equal to 48 khz. filter characteristics scale with fs. 17. plots of this data are contained in the ?appendix? on page 47. see figure 45 through figure 56. parameter symbol min typ max unit single speed mode passband (-0.1 db). (note 15) 0 - 0.47 fs passband ripple. - - 0.035 db stopband. (note 15) 0.58 - - fs stopband attenuation. -95 - - db group delay. t gd -12/fs- s double speed mode passband (-0.1 db). (note 15) 0 - 0.45 fs passband ripple. - - 0.035 db stopband. (note 15) 0.68 - - fs stopband attenuation. -92 - - db group delay. t gd -9/fs- s quad speed mode passband (-0.1 db). (note 15) 0 - 0.24 fs passband ripple. - - 0.035 db stopband. (note 15) 0.78 - - fs stopband attenuation. -97 - - db group delay. t gd -5/fs- s high pass filter characteristics frequency response -3.0 db. -0.13 db. (note 16) -1 20 - - hz hz phase deviation @ 20 hz. (note 16) - 10 - deg passband ripple. - - 0 db filter settling time. 10 5 /fs s
cs4271 ds592f1 17 dc electrical characteristics (gnd = 0 v, all voltages with respect to ground. mclk=12.288 mhz; master mode) notes: 18. power down mode is defined as rst = low with all clocks and data lines held static. 19. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. digital characteristics parameter symbol min typ max unit power supply power supply current va (normal operation) vl,vd = 5 v vl,vd = 3.3 v i a i d i d - - - 45 41.5 24 53 49 28 ma ma ma power supply current va (power-down mode)(note 18) vl,vd=5 v i a i d - - 0.025 1.76 - - ma ma power consumption vl, vd=5 v (normal operation) vl, vd = 3.3 v (power-down mode) - - - - - - 433 305 9 510 358 - mw mw mw power supply rejection rati o (1 khz) (note 19) psrr - 60 - db quiescent voltage nominal quiescent voltage vq - 0.48xva - vdc maximum dc current so urce/sink from vq - 1 - a vq output impedance - 25 - k ? filt+ filt+ nominal voltage filt+ - va - vdc mutec mutec low-level output voltage - 0 - v mutec high-level output voltage - va - v maximum mutec drive current - 3 - ma parameter symbol min typ max units high-level input voltage (% of vl) v ih 70% - - v low-level input voltage (% of vl) v il --30%v high-level output voltage at i o = 2 ma v oh vl - 1.0 - - v low-level output voltage at i o = 2 ma v ol --0.4v input leakage current i in -- 10 a
cs4271 18 ds592f1 switching characteristics - serial audio port (logic "0" = gnd = 0 v; logic "1" = vl, c l = 20 pf) notes: 20. in control port mode, the ratio[1:0] bi ts must be configured according to tables 8 and 9 on pages 28 and 29. parameter symbol min typ max unit sample rate single speed mode double speed mode quad speed mode fs fs fs 4 50 100 - - - 50 100 200 khz khz khz mclk specifications mclk frequency stand-alone mode (note 20) control port mode f mclk f mclk 1.024 1.024 - - 25.600 51.200 mhz mhz mclk input pulse width high/low stand-alone mode (note 20) control port mode t clkhl t clkhl 16 8 - - - - ns ns mclk output duty cycle 45 50 55 % master mode lrck duty cycle - 50 - % sclk duty cycle - 50 - % sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0 - 32 ns sdin valid to sclk rising setup time t sdis 16 - - ns sclk rising to sdin hold time t sdih 20 - - ns slave mode lrck duty cycle 40 50 60 % sclk period (note 20) single speed mode double speed mode quad speed mode t sclkw t sclkw t sclkw - - - - - - s s s sclk pulse width high t sclkh 30 - - ns sclk pulse width low t sclkl 48 - - ns sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0 - 32 ns sdin valid to sclk rising setup time t sdis 16 - - ns sclk rising to sdin hold time t sdih 20 - - ns crystal oscillator specifications (xti/xto) crystal frequency range f osc 16.384 - 25.600 mhz 1 128 () fs -------------------- - 1 128 () fs -------------------- - 1 64 () fs ----------------- -
cs4271 ds592f1 19 sdis t slr t sdout sclk output lrck output sdin sdo t sdih t sdis t slr t sdout sclk input lrck input sdin sdo t sdih t sclkh t sclkl t sclkw t figure 1. master mode serial audio port timing figure 2. slave mode se rial audio port timing
cs4271 20 ds592f1 figure 3. format 0, left justified up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 4. format 1, i2s up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 lrck sclk left channel sdata +5 +4 +3 +2 +1 lsb msb-1-2-3-4-5 32 clocks right channel lsb +5 +4 +3 +2 +1 lsb msb - 1 - 2 - 3 - 4 -5 +6 -6 +6 -6 figure 5. format 2, right justified 16-bit data. (available in control port mode only) format 3, right justified 24 -bit data. (available in control port mode only) format 4, right justified 20 -bit data. (available in control port mode only) format 5, right justified 18 -bit data. (available in control port mode only)
cs4271 ds592f1 21 switching characteristics - i2c mode control port (inputs: logic 0 = agnd, logic 1 = vl) notes: 21. data must be held for su fficient time to bridge the 3 00 ns transition time of scl. parameter symbol min max unit i2c mode scl clock frequency. f scl -100khz rst rising edge to start. t irs 500 - ns bus free time between transmissions. t buf 4.7 - s start condition hold time (p rior to first clock pulse). t hdst 4.0 - s clock low time. t low 4.7 - s clock high time. t high 4.0 - s setup time for repeated start condition. t sust 4.7 - s sda hold time from scl falling. (note 21) t hdd 0-s sda setup time to scl rising. t sud 250 - ns rise time of both sda and scl lines. t r -1s fall time of both sda and scl lines. t f -300ns setup time for st op condition. t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 6. i2c mode control port timing
cs4271 22 ds592f1 switching characteristics - spi control port (inputs: logic 0 = agnd, logic 1 = vl) notes: 22. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 23. data must be held for sufficient time to bridge the transition time of cclk. 24. for f sck < 1 mhz parameter symbol min max unit spi mode cclk clock frequency. f sclk -6mhz rst rising edge to cs falling. t srs 500 - ns cclk edge to cs falling. (note 22) t spi 500 - ns cs high time between transmissions. t csh 1.0 - s cs falling to cclk edge. t css 20 - ns cclk low time. t scl 82 - ns cclk high time. t sch 82 - ns cdin to cclk rising setup time. t dsu 40 - ns cclk rising to data hold time. (note 23) t dh 15 - ns rise time of cclk and cdin. (note 24) t r2 -100ns fall time of cclk and cdin. (note 24) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 7. spi control port timing
cs4271 ds592f1 23 4. typical connection diagram ) lj (i2s/ cs / ad0 sda / cdin (m1) scl / cclk (m0) aina ainb rst power down and mode settings (control port) xti xto aouta- aouta+ amutec aoutb- aoutb+ bmutec analog conditioning & mute lrck sclk mclk timing logic & clock sdin ) s (m/ sdout audio data processor dgnd filt+ agnd vd va +5 v +5 v to 3.3 v cs4271 vl 40 pf 40 pf * * * only one must be used. see "grounding and power supply decoupling." see "master/slave mode selection". +5 v to 2.5 v 47 k ? 5.1 ? vq2 vq3 ** optional. see "crystal applications (xti/xto)". ** analog input buffer vq1 1 f 0.1 f 1 f 0.1 f 1 f 0.1 f 1 f 0.1 f 47 f 0.1 f ? not to exceed 1 f. ? figure 8. cs4271 typical connection diagram
cs4271 24 ds592f1 5. applications 5.1 stand-alone mode 5.1.1 recommended power-up sequence 1) when using the cs4271 with an external mclk, hold rst low until the power supply, mclk, and lrck are stable. when using the cs4271 with internally generated mclk, hold rst low until the power supply is stable. 2) bring rst high. if the internally generated mclk is being us ed, it will appear on the mc lk pin prior to 1 ms from the release of rst . 5.1.2 master/slave mode the cs4271 supports operation in either master mode or slave mode. in master mode, lrck and sclk are outputs and are sync hronously generated on-chip. lrck is equal to fs and sclk is equal to 64x fs. in slave mode, lrck and sclk are inputs, requiring extern al generation that is synchronous to mclk. it is recom- mended that sclk be 64x fs to maximize system performance. in stand-alone mode, the cs 4271 will default to slave mode. master mode may be accessed by placing a 47 k ? pull-up to vl on the sdout (m/s ) pin. configuration of clock ratios in each of these modes will be outlined in the tables 3 and 4. 5.1.3 system clocking the cs4271 will operate at sa mpling frequencies from 4 khz to 200 khz. this range is divided into three speed modes as shown in table 1 below. 5.1.3.1 crystal applications (xti/xto) an external crystal may be used in conjunction with the cs4271 to generate the master clock signal. to accomplish this, a 20 pf fundamental mode parallel resonant crystal must be connected between the xti and xto pins as shown in the typical connection diagram on page 23. this crystal must oscillate at the frequency shown in table 2. in this configuration, mclk is a buffered output and, as shown in the typical connection diagram, nothing other than the crystal and it s load capacitors should be connected to xti and xto. th e mclk signal will appear on the mclk pin prior to 1 ms from the release of rst . to operate the cs4271 with an externally generated mclk signal, no crystal should be used, xti should be con- nected to ground and xto should be left unconnected. in this configuration, mclk is an input and must be driven externally with an appropriate speed clock. table 1. speed modes mode sampling frequency single speed 4-50 khz double speed 50-100 khz quad speed 100-200 khz table 2. crystal frequencies mode crystal frequency single speed 512 x fs double speed 256 x fs quad speed 128 x fs
cs4271 ds592f1 25 5.1.3.2 clock ratio selection depending on the use of an external crystal, or whet her the cs4271 is in master or slave mode, different mckl/lrck and sclk/lrck ratios may be used. thes e ratios are shown in the tables 3 and 4 below. table 3. clock ratios - stand alone mode with external crystal external crystal used, mclk=output master mode mclk/lrck sclk/lrck lrck single speed 256 64 fs double speed 128 64 fs quad speed 128 64 fs slave mode mclk/lrck sclk/lrck lrck single speed 256 32, 64, 128 fs double speed 128 32, 64 fs quad speed 128 32, 64 fs table 4. clock ratios - stand alone mode without external crystal external crystal not used, mclk=input master mode mclk/lrck sclk/lrck lrck single speed 256 64 fs double speed 128 64 fs quad speed 64 32 fs slave mode mclk/lrck sclk/lrck lrck single speed 256 32, 64, 128 fs 384 32, 48, 64, 96, 128 fs 512 32, 64, 128 fs double speed 128 32, 64 fs 192 32, 48, 64 fs 256 32, 64 fs quad speed 64 32 fs 96 48 fs 128 32, 64 fs
cs4271 26 ds592f1 5.1.4 16-bit auto-dither the cs4271 will auto-configure to output properly dithered 16-bit data when placed in sl ave mode and a 32x sclk to lrck ratio is used. in this configuration, one half of a bit of dither is added to the lsb of the 16-bit word. this applies only to the serial audio output of the ad c and will not affect dac performance. see figure 9. 5.1.5 auto-mute the dac output will mute following the reception of 8192 consecutive audio sa mples of static 0 or -1. a single sam- ple of non-static data will release th e mute. detection and muti ng are done in dependently for eac h channel. the common mode on the output will be retained and the mute control pin for that channel will go active during the mute period. 5.1.6 high pass filter the operational amplifiers in the input circuitry drivin g the cs4271 may generate a small dc offset into the adc. the cs4271 includes a high pass filter after the decimator to remove any dc offset whic h could result in recording a dc level, possibly yielding "clicks" when switch ing between devices in a multichannel system. in stand-alone mode, the high pass filter continuously subt racts a measure of the dc offset from the output of the decimation filter. this function ca nnot be disabled in stand-alone mode. 5.1.7 interpolation filter in stand-alone mode, the fast roll-of f interpolation filter is used. filter specifications can be found in section 3. plots of the data are c ontained in the ?appendix? on page 47. 5.1.8 mode selection & de-emphasis the sample rate, fs, can be adjusted from 4 khz to 200 khz . in stand-alone mode, the cs4271 must be set to the proper mode via the mode pins, m1 and m0. de-emphasis, optimized for a 44.1 khz sampling frequency, is avail- able. 5.1.9 serial audio inte rface format selection either i 2 s or left justified serial audio data format may be selected in stan d-alone mode. the selection will affect both the input and output format. placing a 10 k ? pull-up to vl on the i2s/lj pin will select the i 2 s format, while placing a 10 k ? pull-down to dg nd on the i2s/lj pin will select the left justified format. table 5. cs4271 stand-alone mode control mode 1 mode 0 mode sample rate (fs) de-emphasis 0 0 single speed mode 4 khz - 50 khz 44.1 khz 0 1 single speed mode 4 khz - 50 khz off 1 0 double speed mode 50 khz - 100 khz off 1 1 quad speed mode 100 khz - 200 khz off 16-bit w ord 1514131211109876543210 ? bit dither figure 9. adc 16-bit auto-dither
cs4271 ds592f1 27 5.2 control port mode 5.2.1 recommended power-up sequ ence - access to control port mode 1) when using the cs4271 with an external mclk, hold rst low until the power supply, mclk, and lrck are stable. when using the cs4271 with internally generated mclk, hold rst low until the power supply is stable. in this state, the control port is reset to its default settings. 2) bring rst high. the device will remain in a low power state and the control port will be accessib le. if internally generated mclk is being used, it will appear on the mclk pin prior to 1 ms from the release of rst . 3) write 03h to register 07h within 10 ms following the release of rst . this sets the contro l port enable (cpen) and power down (pdn) bits, activating the control port and placing the part in power-down. when using the cs4271 with internally generated mclk, it is nece ssary to wait 1 ms follo wing the release of rst before initi- ating this control port write. 4) the desired register settings can be loaded while keeping the pdn bit set. 5) clear the pdn bit to initiate the power-up sequence. this power-up sequence requires approximately 85 s. 5.2.2 master / slave mode selection the cs4271 supports operation in either master mode or slave mode. in master mode, lrck and sclk are outputs and are sync hronously generated on-chip. lrck is equal to fs and sclk is equal to 64x fs. in slave mode, lrck and sclk are inputs, requiring extern al generation that is synchronous to mclk. it is recom- mended that sclk be 64x fs to maximize system performance. configuration of clock ratios in each of these modes will be outlined in the tables 8 and 9. in control port mode the cs4271 will de fault to slave mode. the user may ch ange this default se tting by changing the status of the m/s bit in the mode control 1 register (01h). 5.2.3 system clocking the cs4271 will operate at sa mpling frequencies from 4 khz to 200 khz. this range is divided into three speed modes as shown in table 6 below. 5.2.3.1 crystal applications (xti/xto) an external crystal may be used in conjunction with the cs4271 to generate the mclk signal. to accomplish this, a 20 pf fundamental mode parallel resonant crystal must be connected between the xti and xto pins as shown in the typical connection diagram on page 23. this crystal must oscillate at the frequen cy shown in table 7. in this configuration, mclk is a buffered output and, as shown in the typical connection diagram, nothing other than the crystal and its load capacitors should be connected to xti and xto. the mclk signal will appear on the mclk pin prior to 1 ms from the release of rst . table 6. speed modes mode sampling frequency single speed 4-50 khz double speed 50-100 khz quad speed 100-200 khz
cs4271 28 ds592f1 to operate the cs4271 with an externally generated mclk signal, no crystal should be used, xti should be con- nected to ground and xto should be left unconnected. in this configuration, mclk is an input and must be driven externally with an appropriate speed clock. 5.2.3.2 clock ratio selection depending on the use of an external crystal, or whet her the cs4271 is in master or slave mode, different mckl/lrck and sclk/lrck ratios may be used. these ratios as well as the control port register bits that must be set in order to obtain them are shown in tables 8 and 9 below. notes: 25. for the ratio1 and ratio0 bits listed ab ove, ?d? indicates that any value may written. table 7. crystal frequencies mode crystal frequency single speed 512 x fs double speed 256 x fs quad speed 128 x fs table 8. clock ratios - control port mode with external crystal external crystal used, mclk=output master mode mclk/lrck sclk/lrck lrck ra tio1 bit ratio0 bit single speed 256 64 fs 0 d 25 512 64 fs 1 d 25 double speed 128 64 fs 0 d 25 256 64 fs 1 d 25 quad speed 128 64 fs d 25 d 25 slave mode mclk/lrck sclk/lrck lrck ra tio1 bit ratio0 bit single speed 256 32, 64, 128 fs 0 d 25 512 32, 64, 128 fs 1 d 25 double speed 128 32, 64 fs 0 d 25 256 32, 64 fs 1 d 25 quad speed 128 32, 64 fs d 25 d 25
cs4271 ds592f1 29 notes: 26. for the ratio0 bit listed above, ?d? indicates that any value may written. table 9. clock ratios - control port mode without external crystal external crystal not used, mclk=input master mode mclk/lrck sclk/lrck lrck ratio1 bit ratio0 bit single speed 256 64 fs 0 0 384 64 fs 0 1 512 64 fs 1 0 768 64 fs 1 1 double speed 128 64 fs 0 0 192 64 fs 0 1 256 64 fs 1 0 384 64 fs 1 1 quad speed 64 32 fs 0 0 96 32 fs 0 1 128 64 fs 1 0 192 64 fs 1 1 slave mode mclk/lrck sclk/lrck lrck ratio1 bit ratio0 bit single speed 256 32, 64, 128 fs 0 d 26 384 32, 48, 64, 96, 128 fs 0 d 26 512 32, 64, 128 fs 0 d 26 768 32, 48, 64, 96, 128 fs 1 d 26 1024 32, 64, 128 fs 1 d 26 double speed 128 32, 64 fs 0 d 26 192 32, 48, 64 fs 0 d 26 256 32, 64 fs 0 d 26 384 32, 48, 64 fs 1 d 26 512 32, 64 fs 1 d 26 quad speed 64 32 fs 0 d 26 96 48 fs 0 d 26 128 32, 64 fs 0 d 26 192 48 fs 1 d 26 256 32, 64 fs 1 d 26
cs4271 30 ds592f1 5.2.4 internal digital loopback in control port mode, the cs4271 supports an internal digi tal loopback mode in which the output of the adc is rout- ed to the input of the dac. this mode may be activated by setting the loop bit in the mode control 2 register (07h). when this bit is set, the status of the dac_dif(2:0) bits in register 01h will be disreg arded by the cs4271. any changes made to the dac_dif(2:0) bi ts while the loop bit is set will have no impact on operati on until the loop bit is released, at which time the digit al interface format of the dac will operate accordin g to the format selected in the dac_dif(2:0) bits. while the loop bit is set, data will be present on the sdout pi n in the format selected in the adc_dif bit in register 06h. 5.2.5 dither for 16-bit data the cs4271 may be configured to properly dither for 16-bit data. to do this, the dither16 bit in the adc control register (06h) must be set. when set, a half bit of dither is added to the least significant bit of the 16 most significant bits of the data word. the remaining bits should be disreg arded. see figure 10. this function is useful when 16-bit devices are downstream of the adc. this bit should not be set when using word lengths greater than 16 bits. it should be noted that this function is supported for all serial audio output formats, and may be activated in either master or slave mode. 5.2.6 auto-mute the auto-mute function is cont rolled by the status of the amute bit in the dac control register. when set, the dac output will mute following the reception of 8192 consecutive audio samples of stat ic 0 or -1. a single sample of non- static data will release the mute. detection and mu ting are done in dependently for each c hannel. auto-mute detec- tion and muting can become dependent on either channel if the muteca=b function is enabled. the common mode on the output will be retained and the mute control pin for that channel will become active during the mute period. the muting function is effected, simila r to volume control changes, by the so ft and zerocross bi ts in the dac vol- ume and mixing control register. the amute bit is set by default. 5.2.7 high pass filter and dc offset calibration the operational amplifiers in the input circuitry driving the cs4271 may generate a small dc offset into the a/d con- verter. the cs4271 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding "clicks" when switching between devices in a multichannel system. the high pass filter continuous ly subtracts a measure of the dc offset from the output of the decimation filter. the high pass filter can be independently enabled and disabled for channels a and b. if the hpfdisablea or hpfdis- ableb bit is set during normal operation, the current val ue of the dc offset for the corresponding channel is frozen and this dc offset will continue to be subtracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1) running the cs4271 with the high pass filter enabled until the filter settles. see the dig ital filter ch aracteristics for filter settling time. 2) disabling the high pass filter and freezing the stored dc offset. 16-bit word 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 disregard contents ? bit dither figure 10. example of dither for 16-bit data with 24-bit left justified format
cs4271 ds592f1 31 a system calibration performed in this way will eliminate offsets anywhere in th e signal path between the calibration point and the cs4271. 5.2.8 interpolation filter to accommodate the increasingly complex requirements of di gital audio systems, the cs4271 incorporates select- able interpolation filter s for each mode of operation. fast and slow roll-off filters are available in each of single, dou- ble, and quad speed modes. these filters have been desi gned to accommodate a variety of musical tastes and styles. the filt_sel bit in the dac control register (02h) is used to select which filter is used. by default, the fast roll-off filter is selected. filter specifications can be found in section 3. plots of the data are c ontained in the ?appendix? on page 47. 5.2.9 de-emphasis three de-emphasis modes are available via the control port. the available filters are optimized for 32 khz, 44.1 khz, and 48 khz sampling rates. see table 13 fo r de-emphasis selection in control port mode. 5.2.10 oversampling modes the cs4271 operates in one of three oversampling modes based on the input sample rate. mode selection is de- termined by the m1 and m0 bits in the mode control 1 re gister. single-speed mode supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode supports input sample rates up to 200 khz and uses an over- sampling ratio of 32x. see table 11 for control port mode settings. 5.3 de-emphasis filter the cs4271 includes on-chip digital de-emphasis. figure 11 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. please see section 5.1.8 for the desired de-emphasis control for st and-alone mode and section 5.2.9 for control port mode. the de-emphasis feat ure is included to acco mmodate audio recordings that utilize 50/15 s pre-emphasis equal- ization as a means of noise reduction. de-emphasis is only available in single speed mode. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 11. de-emphasis curve
cs4271 32 ds592f1 5.4 analog connections 5.4.1 input connections the analog modulator samples th e input at 6.144 mhz (mclk=12.288 mhz). th e digital filter will reject signals with- in the stopband of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,. .. refer to figure 12 for a recommended analo g input buffer that will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. figure 13 shows the full-scale analog input levels. aina vq2 vq1 - + 470 pf c0g cs4271 634 ? 91 ? 2700 pf c0g 10 f 10 f 10 k ? 10 k ? 1 f 0.1 f ainb 2700 pf c0g - + 470 pf c0g 91 ? 634 ? - + vq3 ainl ainr figure 12. cs4271 recommended analog input buffer cs4271 aina ainb full-scale input level = 2.8 vpp 3.9 v 2.5 v 1.1 v 3.9 v 2.5 v 1.1 v figure 13. full-scale analog input
cs4271 ds592f1 33 5.4.2 output connections the recommended output filter configurat ion is shown in figure 14. this filter configuration accounts for the normally differing ac loads on the aout+ and aout- differential output pins. it also shows an ac coupling configuration which minimizes the number of required ac coupling capacitors. the cs4271 does not include phase or amplitude compensation fo r an external filter, an d therefore the dac system phase and amplitude response will be dep endent on the exte rnal analog circuitry. figu re 15 shows the full-scale an- alog output levels. aout+ aout- - + 470 pf c0g cs4271 560 ? 22 f 4.99 k ? 2200 pf c0g 715 ? 2.32 k ? 4.42 k ? 1.33 k ? 1.50 k ? 22 f 1.5 nf c0g 6.8 nf c0g 47 k ? analog out figure 14. cs4271 recommended analog output filter cs4271 aout+ aout- full-scale output level= (ain+) - (ain-)= 5 vpp 3.75 v 2.5 v 1.25 v 3.75 v 2.5 v 1.25 v figure 15. full-scale analog output
cs4271 34 ds592f1 5.5 mute control the mute control pins become active durin g power-up initialization, re set, muting, if the mclk to lrck ratio is in- correct, and during power-down. the auto-mute function causes the mutec pin corres ponding to an individual channel to activate following the reception of 8192 consec utive audio samples of static 0 or -1 on the respective channel. a single sample of non-zero data on this channel will cause the mutec pi n to deactivate. in control port mode, however, auto-mute detection and muting can becom e dependent on either channel if the muteb=a function is enabled. the mutec pins are intended to be used as cont rol for an external mute circ uit in order to add off-chip mute capability. use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. the mutec pins are active- low. see figure 16 below for a suggested active-low mute circuit. 5.6 synchronization of multiple devices in systems where multiple a dcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the sa me for all of the cs4271?s in the system. if only one mclk source is needed, one solution is to place one cs42 71 in master mode, and slave all of the other cs4271?s to the one master. if multiple mclk sources are needed, a possible solution would be to supply all clocks from the same external source and time the cs42 71 reset with the inactive edge of mc lk. this will ensure that all converters begin sampling on the same clock edge. 5.7 grounding and power supply decoupling as with any high resolution converter, the cs4271 requires careful attention to power supply and grounding arrange- ments if its potential performance is to be realized. figure 8 shows the recommended power arrangements, with va and vl connected to clean supplies. vd, which powers th e digital filter, may be run from the system logic supply (vl) or may be powered from the analog supply (va) via a resistor. in this case, no additional devices should be powered from vd. power supply decoupling capacitors shoul d be as near to the cs4271 as possible, with the low value ceramic capacitor being the neares t. all signals, especially clocks, sh ould be kept away from the vref and vcom pins in order to avoid unwanted coupling into t he modulators. the vref and vcom decoupling capacitors, particularly the 0.1 f, must be posi tioned to minimize the electrical path from vref and agnd. the cdb4271 evaluation board demonstrates the optimum layout and power supply arrangements. to mi nimize digital noise, con- nect the cs4271 digital outpu ts only to cmos inputs. lpf +v ee -v ee 560 ? audio out 2 k ? 10 k ? -v ee +v a mmun2111lt1 aout mutec cs4272 ac couple 47 k ? figure 16. suggested active-low mute circuit
cs4271 ds592f1 35 6. control port interface the control port is used to load all the internal settings of the cs4 271. the operation of the control port may be completely asynchronous to the audio sample rate. however, to avoid potential interfer ence problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi a nd i2c, with the cs4271 operating as a slave to control messages in both modes. if i2c operatio n is desired, ad0/cs should be tied to va or agnd. if the cs4271 ever detects a high to low transition on ad0/cs after power-up, spi mode will be selected. th e control port registers are write-only in spi mode. upon release of the rst pin, the cs4271 will wait approximately 10 ms before it begins its start-up se quence. the part defaults to stand-alone mode, in which all operat ional modes are controlled as described under ?stand-alone mode? on page 24. the control port is active at all times, and if bit 1 of register 07h (cpen) is set, the part enters control-port mode and all operational modes are controlled by the control port registers. this bit can be set at any time, but to avoid unpredictable output noi ses, bit 1 (cpen) and bit 0 (pdn) of register 07h should be set by writing 03h before the end of the 10 ms start-up wait period. all re gisters can then be set as desired before releasing the pdn bit to begin the start-up sequence. if system requirem ents do not allow writing to the control port immediately following the release of rst , the sdin line should be held at logic ?0? un til the proper serial mode can be selected. 6.1 spi mode in spi mode, cs is the cs4271 chip select signal, cclk is the cont rol port bit clock, cdin is the input data line from the microcontroller and the chip address is 0010000. all cont rol signals are inputs and data is clocked in on the rising edge of cclk. figure 17 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 00 10000. the eighth bit is a read/write indicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next 8 bits ar e the data which will be placed into th e register designate d by the map. see table 10 on page 36. the cs4271 has map auto increment ca pability, enabled by the incr bit in the map. if incr is 0, then the map will stay constant for succ essive writes. if incr is set, th en map will auto incr ement after each byte is written, al- lowing block writes to successive registers. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0010000 figure 17. control port timing, spi mode
cs4271 36 ds592f1 6.2 i2c mode in i2c mode, sda is a bi-directional data line. data is clocked in to and out of the part by the clock, scl, with the clock to data relationship as shown in figure 18. there is no cs pin. pin ad0 forms the partial chip address and should be tied to va or agnd as required. the upper 6 bits of the 7- bit address field must be 001000. to communicate with the cs4271 , the lsb of the chip address field, which is the first byte sent to the cs4271, should match the setting of the ad0 pin. the eighth bit of the address byte is the r/w bit (high for a read, low for a wr ite). if the operation is a write, the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then followed by the data to be written. if th e operation is a read, then the contents of the register pointed to by the map will be output after the chip address. the cs4271 has map auto increment ca pability, enabled by the incr bit in the map. if incr is 0, then the map will stay constant for succ essive writes. if incr is set, th en map will auto incr ement after each byte is written, al- lowing block reads or writes of successive registers. table 10. memory address pointer (map) 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000 incr - auto map increment enable default = ?0?. 0 - disabled 1 - enabled map(3:0) - memory address pointer default = ?0000?. sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 18. control port timing, i2c mode
cs4271 ds592f1 37 7. register quick reference this table shows the register names and their associated default values. addr function 7 6 5 4 3 2 1 0 01h mode control 1 m1 m0 ratio1 ratio0 m/s dac_dif2 dac_dif1 dac_dif0 00 0 0 0 0 0 0 02h dac control amute filt_sel dem1 dem0 rmp_up rmp_dn inv_b inv_a 10 0 0 0 0 0 0 03h dac volume & mixing control reserved b=a soft zerocross atapi3 atapi2 atapi1 atapi0 00 1 0 1 0 0 1 04h dac ch a vol- ume control mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 00 0 0 0 0 0 0 05h dac ch b vol- ume control mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 00 0 0 0 0 0 0 06h adc control reserved reserved dither16 a dc_dif0 mutea muteb hpfdisablea hpfdisableb 00 0 0 0 0 0 0 07h mode control 2 reserved reserved reserved loop muteca=b freeze cpen pdn 00 0 0 0 0 0 0 08h chip id part3 part2 part1 part0 rev3 rev2 rev1 rev0 00 0 0 0 0 0 0
cs4271 38 ds592f1 8. register description ** all registers are read/write in i2c mode and write only in spi mode, unless otherwise noted** 8.1 mode control 1 - address 01h 8.1.1 functional mode (bits 7:6) function: selects the required range of input sample rates. 8.1.2 ratio select (bits 5:4) function: these bits are used to select the clocking ratios in control port mode. please refer to table 8, ?clock ratios - control port mode with external crystal,? on page 28 or table 9, ?clock ratios - control port mode without external crystal,? on page 29 for informat ion on which of these bits to set to obtain spe- cific clock ratios. 8.1.3 master / slave mode (bit 3) function: this bit selects either master or slave operation. sett ing this bit will select ma ster mode, while clearing this bit will select slave mode. 8.1.4 dac digital inte rface format (bits 2:0) function: the required relationship between lrck, sclk and sdin for the dac is defined by the dac digital interface format and the options are detailed in table 12 and figures 3-5. 76543210 m1 m0 ratio1 ratio0 m/s dac_dif2 dac_dif1 dac_dif0 table 11. functional mode selection m1 m0 mode 0 0 single-speed mode: 4 to 50 khz sample rates (default) 0 1 single-speed mode: 4 to 50 khz sample rates 1 0 double-speed mode: 50 to 100 khz sample rates 1 1 quad-speed mode: 100 to 200 khz sample rates table 12. dac digital interface formats dac_dif2 dac_dif1 dac_ dif0 description format figure 0 0 0 left justified, up to 24-bit data (default) 0 3 001 i 2 s, up to 24-bit data 14 0 1 0 right justified, 16-bit data 2 5 0 1 1 right justified, 24-bit data 3 5 1 0 0 right justified, 20-bit data 4 5 1 0 1 right justified, 18-bit data 5 5 110 reserved 111 reserved
cs4271 ds592f1 39 8.2 dac control - address 02h 8.2.1 auto-mute (bit 7) function: when set, enables the auto-mute function. see ?auto-mute? on page 30. 8.2.2 interpolation filter select (bit 6) function: this function allows the user to se lect whether the interpolation filter has a fast or slow roll off. when set, this bit selects the slow roll off filter, when cleared it selects the fast roll off filter. the - 3 db corner is approximately the same for both f ilters, but the slope of the roll off is greater for the fast roll off filter. 8.2.3 de-emphasis control (bits 5:4) function: implementation of the standard 50/15 s digital de-emphasis filter response, figure 19, requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 khz sample rates. note: de-emphasis is available only in single-speed mode. see table 13 below. 76543210 amute filt_sel dem1 dem0 rmp_up rmp_dn inv_a inv_b table 13. de-emphasis mode selection dem1 dem0 description 0 0 disabled (default) 0 1 44.1 khz de-emphasis 1 0 48 khz de-emphasis 1 1 32 khz de-emphasis gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 19. de-emphasis curve
cs4271 40 ds592f1 8.2.4 soft volume ramp-up after error (bit 3) function: an un-mute will be perfor med after executing a f ilter mode change, after a mclk/lrck ratio change or error, and after changing the functional mode. when this bit is set, this un -mute is effected, similar to attenuation changes, by the soft and zerocross bi ts in the dac volume & mixing control register. when cleared, an immediate un-mute is performed in these instances. note: for best results, it is recommended that this feature be used with the rmp_dn bit. 8.2.5 soft ramp-down before f ilter mode change (bit 2) function: a mute will be performed prior to executing a filter mode change. w hen this bit is set, this mute is effected, similar to attenuation changes, by the so ft and zerocross bits in the dac volume & mixing control register. when cleared, an immediate mute is performed prior to executing a filter mode change. note: for best results, it is reco mmended that this feature be used in conjunction with the rmp_up bit. 8.2.6 invert signal polarity (bits 1:0) function: when set, this bit activates an inversion of the si gnal polarity for the appropriate channel. this is use- ful if a board layout error has occurred, or other situations where a 180 degree phase shift is desirable. 8.3 dac volume & mixing control - address 03h 8.3.1 channel b volume = channel a volume (bit 6) function: the aouta and aoutb volume levels are independently controlled by the a and the b channel vol- ume control bytes when this function is disabled . the volume on both aouta and aoutb are de- termined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. volume and muting functions are ef fected by the soft ramp and zerocross functions be- low. 8.3.2 soft ramp or zero cross enable (bits 5:4) function: soft ramp enable soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. see table 14 on page 41. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audi ble artifacts. the request ed level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero cros sing. the zero cross function is independently mon- 76543210 reserved b=a soft zerocross atapi3 atapi2 atapi1 atapi0
cs4271 ds592f1 41 itored and implemented for each channel. see table 14 on page 41. soft ramp and zero cross enable soft ramp and zero cross enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implem ented on a signal zero cr ossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enco unter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 14 on page 41. 8.3.3 atapi channel mixing and muting (bits 3:0) function: the cs4271 implements the channel mixing func tions of the atapi cd-r om specification. see table 15 on page 42 table 14. soft cross or zero cross mode selection soft zerocross mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled (default) 1 1 soft ramp and zero cross enabled a channel volume control left channel audio data right channel audio data b channel volume control aouta aoutb figure 20. atapi block diagram
cs4271 42 ds592f1 8.4 dac channel a volume control - address 04h see 8.5 dac channel b volume control - address 05h 8.5 dac channel b volume control - address 05h 8.5.1 mute (bit 7) function: the dac output will mute when this bi t is set. though this bit is acti ve high, it should be noted that the mutec pins are active low. th e common mode voltage on the output will be retained when this bit is set. the muting function is effected, simila r to attenuation changes, by the soft and zerocross bits in the volume and mixing co ntrol register. the mute c pin for the respecti ve channel will become active during the mute period if the mute bi t is set. both the amutec and bmutec will become active if either mute register is enabled and the mutecb=a bit (register 7) is enabled. 8.5.2 volume control (bits 6:0) function: the digital volume control allows the user to atten uate the signal in 1 db increments from 0 to -127 db. volume settings are decoded as shown in table 16. the volume changes are implemented as dictat- ed by the soft and zerocross bits in the dac volu me & mixing control register (see section 8.3.2). table 15. atapi decode atapi3 atapi2 atapi1 atapi0 aouta aoutb 0000 mute mute 0001 mute br 0010 mute bl 0 0 1 1 mute b[(l+r)/2] 0100 ar mute 0101 ar br 0110 ar bl 0 1 1 1 ar b[(l+r)/2] 1000 al mute 1001 al br 1010 al bl 1 0 1 1 al b[(l+r)/2] 1100 a[(l+r)/2] mute 1101 a[(l+r)/2] br 1110 a[(l+r)/2] bl 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 76543210 mute vol6 vol5 vol4 vol3 vol2 vol1 vol0 table 16. digital volume control example settings binary code decimal value volume setting 0000000 0 0 db 0010100 20 -20 db 0101000 40 -40 db 0111100 60 -60 db 1011010 90 -90 db
cs4271 ds592f1 43 8.6 adc control - address 06h 8.6.1 dither for 16-bit data (bit 5) function: when set, this bit activates the dither for 16-bit da ta feature as described in ?dither for 16-bit data? on page 30. 8.6.2 adc digital inte rface format (bit 4) function: the required relationship between lrck, sclk and sdout for the adc is defined by the adc dig- ital interface format. the options are detailed in table 17 and may be seen in figure 3 and 4. 8.6.3 adc channel a & b mute (bits 3:2) function: when this bit is set, the output of th e adc for the selected channel will be muted. 8.6.4 channel a & b high pass filter disable (bits 1:0) function: when this bit is set, the internal high-pass filter for the selected channel will be disabled.the current dc offset value will be frozen and continue to be s ubtracted from the conver sion result. see ?high pass filter and dc offset calibration? on page 30. 8.7 mode control 2 - address 07h 8.7.1 digital loopback (bit 4) function: when this bit is set, an internal digital loopback from the adc to th e dac will be enabled. please refer to ?internal digital loopback? on page 30. 8.7.2 amutec = bmutec (bit 3) function: when this function is enabled, the individual co ntrols for amutec and bm utec are internally con- nected through an and gate prior to the output pi ns. therefore, the external amutec and bmutec pins will go active only when the requirem ents for both amutec and bmutec are valid. 76543210 reserved reserved dither16 adc_dif m utea muteb hpfdisablea hpfdisableb table 17. adc digital interface formats adc_dif descripti on format figure 0 left justified, up to 24-bit data (default) 0 3 1 i 2 s, up to 24-bit data 14 76543210 reserved reserved reserved loop muteca=b freeze cpen pdn
cs4271 44 ds592f1 8.7.3 freeze (bit 2) function: this function allows modifications to the control po rt registers without the changes taking effect until freeze is disabled. to make multip le changes in the control port re gisters take effect simultaneous- ly, set the freeze bit, make all register changes, then clear the freeze bit. 8.7.4 control port enable (bit 1) function: this bit is cleared by default, a llowing the device to power-up in stand-alone mode. control port mode can be accessed by setting th is bit. this will allow the operat ion of the device to be controlled by the registers and the pin definitions will confo rm to control port mode. see ?recommended power- up sequence - access to control port mode? on page 27. 8.7.5 power down (bit 0) function: the device will enter a low-po wer state whenever this bit is set. the power-down bit is set by default and must be cleared before normal operation in c ontrol port mode can occur. the contents of the control registers are retained when the device is in power-down. 8.8 chip id - register 08h this is a read-only register. 8.8.1 chip id (bits 7:4) function: chip id code for the cs4271. permanently set to 0000b (0h). 8.8.2 chip revision (bits 3:0) function: chip revision code for the cs4271. revision a is coded as 0000b (0h). revision b is coded as 0000b (0h). b7 b6 b5 b4 b3 b2 b1 b0 part3 part2 part1 part0 rev3 rev2 rev1 rev0
cs4271 ds592f1 45 9. parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise rati o measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting me asurement to refer the measurement to full-scale. this technique ensures that the di stortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including dist ortion components. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with no signal to the input under test and a fu ll-scale signal applied to th e other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
cs4271 46 ds592f1 10.package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. thermal characteristics and specifications notes: 4. ja is specified according to jedec sp ecifications for multi-layer pcbs. inches millimeters note dim min nom max min nom max a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. parameters symbol min typ max units package thermal resistance (note 4) 28-tssop ja jc - - 37 13 - - c/watt c/watt allowable junction temperature - - 135 c 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs4271 ds592f1 47 11.appendix 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 21. dac single speed (fast) stopband rejection figure 22. dac single speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 23. dac single speed (fast) transition band (detail) figure 24. dac single speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 25. dac single speed (slow) stopband rejection figure 26. dac single speed (slow) transition band
cs4271 48 ds592f1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 27. dac single speed (slow) transition band (detail) figure 28. dac single speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 29. dac double speed (fast) stopband rejection figure 30. dac double speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 31. dac double speed (fast) transition band (detail) figure 32. dac double speed (fast) passband ripple
cs4271 ds592f1 49 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 33. dac double speed (slow) stopband rejection figure 34. dac double speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 35. dac double speed (slow) transition band (detail) figure 36. dac double speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 37. dac quad speed (fast) stopband rejection figure 38. dac quad speed (fast) transition band
cs4271 50 ds592f1 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 39. dac quad speed (fast) transition band (detail) figure 40. dac quad speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 41. dac quad speed (slow) stopband rejection figure 42. dac quad speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 43. dac quad speed (slow) transition band (detail) figure 44. dac quad speed (slow) passband ripple
cs4271 ds592f1 51 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 45. adc single speed mode stopband rejection figure 46. adc single speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 47. adc single speed mode transition band (detail) figure 48. adc single speed mode passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db) figure 49. adc double speed mode stopband rejection figure 50. adc double speed mode transition band
cs4271 52 ds592f1 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 51. adc double speed mode transition band (detail) figure 52. adc double speed mode passband ripple -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 frequency (normalized to fs) amplitude (db) figure 53. adc quad speed mode stopband rejection figure 54. adc quad speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 frequency (normalized to fs) amplitude (db) figure 55. adc quad speed mode transition band (detail) figure 56. adc quad speed mode passband ripple
cs4271 ds592f1 53 table 18. revision history release date changes a1 january 2003 advance release pp1 march 2003 preliminary release pp2 october 2003 - corrected the description of pins 17 and 18 on page 6. - corrected the description of pins 17 and 18 on page 8. - updated figure 8 on page 23. - updated table 9 on page 29. - updated the dc electrical characteristics table on page 17. - updated the dac analog filter response tables on pages 10 and 11. - updated the adc digital filter characteristics table on page 16. - updated the dac full scal e differential output vo ltage specification on pages 10 and 11. pp3 september 2004 add lead-free device ordering info. f1 august 2005 final release - updated ordering information on page 2. - updated specified operating conditions table on page 9 to reflect ordering- suffix independent temperature grade information. - updated dac analog characteristics tables on pages 10 and 11 to reflect ordering-suffix independent temperature grade information. - updated adc analog characteristics tables on pages 14 and 15 to reflect ordering-suffix independent temperature grade information. - updated the dc electrical characteristics table on page 17. - corrected error in the sclk period units shown in the switching character- istics - serial audio port table on page 18. - corrected error in the memory address pointer table on page 36. - updated chip id register description on page 44. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com iimportant notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is sub- ject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products a re sold subject to the terms and con- ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limi tation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the pr operty of cirrus and by furnishing this information, cirrus gr ants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns t he copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization w ith respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, a dvertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental dama ge ("critical applications"). cirrus products are not designed, authorized or warranted for use in aircraft systems, mili tary applications, products surg ically implanted into the bo dy, automotive safety or se- curity devices, life support products or other critical applications. incl usion of cirrus products in such applications is understood to be fu lly at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or im- plied, including the implied wa rranties of merchantability and fitness for part icular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus prod- ucts in critical applicat ions, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, in cluding attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trade- marks or service marks of their respective owners. spi is a trademark of motorola, inc.

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