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dac7615 ? 1998 burr-brown corporation pds-1443c printed in u.s.a. november, 1998 quad, serial input, 12-bit, voltage output digital-to-analog converter features l low power: 20mw l unipolar or bipolar operation l settling time: 10 m s to 0.012% l 12-bit linearity and monotonicity: C40 c to +85 c l double-buffered data inputs l small 20-lead ssop package applications l process control l ate pin electronics l closed-loop servo-control l motor control l data acquisition systems l dac-per-pin programmers description the dac7615 is a quad, serial input, 12-bit, voltage output digital-to-analog converter (dac) with guar- anteed 12-bit monotonic performance over the C40 c to +85 c temperature range. an asynchronous reset clears all registers to either mid-scale (800 h ) or zero- scale (000 h ), selectable via the resetsel pin. the individual dac inputs are double buffered to allow for simultaneous update of all dac outputs. the device can be powered from a single +5v supply or from dual +5v and C5v supplies. low power and small size makes the dac7615 ideal for automatic test equipment, dac-per-pin program- mers, data acquisition systems, and closed-loop servo- control. the device is available in 16-pin plastic dip, 16-lead soic, and 20-lead ssop packages and is guaranteed over the C40 c to +85 c temperature range. international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fa x: (520) 889-1510 ? immediate product info: (800) 548-6132 dac a dac register a input register a dac b dac register b input register b dac c dac register c input register c dac d dac register d input register d v refh v dd v ss v outd v outc v outb v outa v refl loaddacs gnd clk cs 12 sdi reset resetsel loadreg serial-to- parallel shift register dac select dac7615 dac7615 sbas091
2 dac7615 specifications at t a = C40 c to +85 c, v dd = +5v, v ss = C5v, v refh = +2.5v, and v refl = C2.5v, unless otherwise noted. dac7615e, p, u dac7615eb, pb, ub parameter conditions min typ max min typ max units accuracy linearity error (1) v ss = 0v or C5v 2 1 lsb (2) linearity matching (3) v ss = 0v or C5v 2 1 lsb differential linearity error v ss = 0v or C5v 1 1 lsb monotonicity 12 [ bits zero-scale error code = 000 h 4 [ lsb zero-scale drift 25 [[ ppm/ c zero-scale matching (3) 2 1 lsb full-scale error code = fff h 4 [ lsb full-scale matching (3) 2 1 lsb zero-scale error code = 00a h , v ss = 0v 8 [ lsb zero-scale drift v ss = 0v 5 10 [[ ppm/ c zero-scale matching (3) v ss = 0v 4 2 lsb full-scale error code = fff h , v ss = 0v 8 [ lsb full-scale matching (3) v ss = 0v 4 2 lsb power supply rejection 30 [ ppm/v analog output voltage output (4) v ss = 0v or C5v v refl v refh [[ v output current C1.25 +1.25 [[ ma load capacitance no oscillation 100 [ pf short-circuit current +5, C15 [ ma short-circuit duration indefinite [ reference input v refh input range v ss = 0v or C5v v refl +1.25 +2.5 [[ v v refl input range v ss = 0v 0 v refh C1.25 [[ v v refl input range v ss = C5v C2.5 v refh C1.25 [[ v dynamic performance settling time (5) to 0.012% 5 10 [[ m s channel-to-channel crosstalk full-scale step 0.1 [ lsb on any other dac, r l = 2k w output noise voltage bandwidth: 0hz to 1mhz 40 [ nv/ ? hz digital input/output logic family ttl-compatible cmos [ logic levels v ih | i ih | 10 m a 2.4 v dd +0.3 [[ v v il | i il | 10 m a C0.3 0.8 [[ v data format straight binary [ power supply requirements v dd 4.75 5.25 [[ v v ss if v ss 1 0v C5.25 C4.75 [[ v i dd 1.5 1.9 [[ ma i ss C2.1 C1.6 [[ ma power dissipation v ss = C5v 15 20 [[ mw v ss = 0v 7.5 10 [[ mw temperature range specified performance C40 +85 [[ c the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. [ specification same as grade to the left. notes: (1) if v ss = 0v, specification applies at code 00a h and above. (2) lsb means least significant bit, with v refh equal to +2.5v and v refl equal to C2.5v, one lsb is 1.22mv. (3) all dac outputs will match within the specified error band. (4) ideal output voltage, does not take into account zero or full-scale error. (5) if v ss = C5v, full-scale step from code 000 h to fff h or vice-versa. if v ss = 0v, full-scale positive step from code 000 h to fff h and negative step from code fff h to 00a h .
3 dac7615 electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. absolute maximum ratings (1) v dd to v ss ........................................................................... C0.3v to +11v v dd to gnd ........................................................................ C0.3v to +5.5v v refl to v ss ............................................................... C0.3v to (v dd C v ss ) v dd to v refh .............................................................. C0.3v to (v dd C v ss ) v refh to v refl ............................................................ C0.3v to (v dd C v ss ) digital input voltage to gnd ...................................... C0.3v to v dd + 0.3v maximum junction temperature ................................................... +150 c operating temperature range ......................................... C40 c to +85 c storage temperature range .......................................... C65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. package/ordering information maximum maximum linearity differential package specification error linearity drawing temperature ordering transport product (lsb) (lsb) package number (1) range number (2) media dac7615p 2 1 16-pin dip 180 C40 c to +85 c dac7615p rails dac7615pb """" " dac7615pb rails dac7615u 2 1 16-lead soic 211 C40 c to +85 c dac7615u rails "" " "" " dac7615u/1k tape and reel dac7615ub 1 1 16-lead soic 211 C40 c to +85 c dac7615ub rails "" " "" " dac7615ub/1k tape and reel dac7615e 2 1 20-lead ssop 334 C40 c to +85 c dac7615e rails "" " "" " dac7615e/1k tape and reel dac7615eb 1 1 20-lead ssop 334 C40 c to +85 c dac7615eb rails "" " "" " dac7615eb/1k tape and reel notes: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. (2 ) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 devices per reel). ordering 1000 pieces o f dac7615eb/1k will get a single 1000-piece tape and reel. for detailed tape and reel mechanical information, refer to appendix b of burr-brown ic data book.
4 dac7615 pin configurationp, u packages top view pdip, soic pin configuratione package top view ssop pin descriptionse package pin label description 1v dd positive analog supply voltage, +5v nominal. 2v outd dac d voltage output 3v outc dac c voltage output 4v refl reference input voltage low. sets minimum out- put voltage for all dacs. 5 nic not internally connected. 6 nic not internally connected. 7v refh reference input voltage high. sets maximum out- put voltage for all dacs. 8v outb dac b voltage output 9v outa dac a voltage output 10 v ss negative analog supply voltage, 0v or C5v nomi- nal. 11 gnd ground 12 sdi serial data input 13 clk serial data clock 14 cs chip select input 15 nic not internally connected. 16 nic not internally connected. 17 loaddacs all dac registers becomes transparent when loaddacs is low. they are in the latched state when loaddacs is high. 18 loadreg the selected input register becomes transparent when loadreg is low. it is in the latched state when loadreg is high. 19 reset asynchronous reset input. sets all dac registers to either zero-scale (000 h ) or mid-scale (800 h ) when low. resetsel determines which code is active. 20 resetsel when low, a low on reset will cause all dac registers to be set to code 000 h . when resetsel is high, a low on reset will set the registers to code 800 h . pin descriptionsp, u packages pin label description 1v dd positive analog supply voltage, +5v nominal. 2v outd dac d voltage output 3v outc dac c voltage output 4v refl reference input voltage low. sets minimum out- put voltage for all dacs. 5v refh reference input voltage high. sets maximum out- put voltage for all dacs. 6v outb dac b voltage output 7v outa dac a voltage output 8v ss negative analog supply voltage, 0v or C5v nomi- nal. 9 gnd ground 10 sdi serial data input 11 clk serial data clock 12 cs chip select input 13 loaddacs all dac registers become transparent when loaddacs is low. they are in the latched state when loaddacs is high. 14 loadreg the selected input register becomes transparent when loadreg is low. it is in the latched state when loadreg is high. 15 reset asynchronous reset input. sets dac and input registers to either zero-scale (000 h ) or mid-scale (800 h ) when low. resetsel determines which code is active. 16 resetsel when low, a low on reset will cause the dac and input registers to be set to code 000 h . when resetsel is high, a low on reset will set the registers to code 800 h . 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd v outd v outc v refl v refh v outb v outa v ss resetsel reset loadreg loaddacs cs clk sdi gnd dac7615p, u 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd v outd v outc v refl nic nic v refh v outb v outa v ss resetsel reset loadreg loaddacs nic nic cs clk sdi gnd dac7615e
5 dac7615 typical performance curves: v ss = 0v at t a = +25 c, v dd = +5v, v ss = 0v, v refh = +2.5v, and v refl = 0v, representative unit, unless otherwise specified. linearity error and differential linearity error vs code (dac a) 200 h 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error and differential linearity error vs code (dac b) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error and differential linearity error vs code (dac c) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error and differential linearity error vs code (dac d) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error vs code (dac a, ?0? and +85?) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 +85? ?0? 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error vs code (dac b, ?0? and +85?) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 +85? ?0? 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h
6 dac7615 typical performance curves: v ss = 0v (cont) at t a = +25 c, v dd = +5v, v ss = 0v, v refh = +2.5v, and v refl = 0v, representative unit, unless otherwise specified. linearity error vs code (dac c, ?0? and +85?) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 +85? ?0? 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error vs code (dac d, ?0? and +85?) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 +85? ?0? 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h positive slew rate and settling time ? 8 ? time ( s) a: output voltage (v) b: output voltage, deviation from +2.5v (lsb) ?.25 2.25 1.75 2.75 1.25 0.75 0.25 ? 6 3 9 0 ? ? 0 1 2 3 4 5 6 7 0v 5v loaddacs a b negative slew rate and settling time ? 8 ? time ( s) a: output voltage (v) b: output voltage, deviation from code 00a h (lsb) ?.25 2.25 1.75 2.75 1.25 0.75 0.25 ? 6 3 9 0 ? ? 0 1 2 3 4 5 6 7 0v 5v loaddacs ab
7 dac7615 typical performance curves: v ss = C5v at t a = +25 c, v dd = +5v, v ss = C5v, v refh = +2.5v, and v refl = C2.5v, representative unit, unless otherwise specified. linearity error and differential linearity error vs code (dac a) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error and differential linearity error vs code (dac c) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error and differential linearity error vs code (dac b) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error and differential linearity error vs code (dac d) 000 h digital input code dle (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error vs code (dac a, ?0? and +85?) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 +85? ?0? 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h linearity error vs code (dac b, ?0? and +85?) 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 +85? ?0? 0.25 0.00 ?.50 ?.25 0.25 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h
8 dac7615 typical performance curves: v ss = C5v (cont) at t a = +25 c, v dd = +5v, v ss = C5v, v refh = +2.5v, and v refl = C2.5v, representative unit, unless otherwise specified. linearity error vs code (dac c, ?0? and +85?) 200 h 000 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 +85? ?0? 0.25 0.00 ?.50 ?.25 0.25 400 h 600 h 800 h a00 h c00 h e00 h fff h 600 v refh current vs code (all dacs set to indicated code) 000 h fff h 400 h c00 h 800 h digital input code v reh current (?) 0 100 200 300 400 500 0 v refl current vs code (all dacs set to indicated code) 000 h fff h 400 h c00 h 800 h digital input code v rel current (?) ?00 ?00 ?00 ?00 ?00 ?00 positive slew rate and settling time ? 8 ? time ( s) a: output voltage (v) b: output voltage, deviation from +2.5v (lsb) ? 2 1 3 0 ? ? ? 4 2 6 0 ? ? 0 1 2 3 4 5 6 7 0v 5v loaddacs a b negative slew rate and settling time ? 8 ? time ( s) a: output voltage (v) b: output voltage, deviation from ?.5v (lsb) ? 2 1 3 0 ? ? ? 4 2 6 0 ? ? 0 1 2 3 4 5 6 7 0v 5v loaddacs a b linearity error vs code (dac d, ?0?c and +85?c) 000 h 200 h digital input code le (lsb) le (lsb) 0.50 0.00 ?.25 ?.50 0.50 +85?c ?0?c 0.25 0.00 ?.50 ?.25 0.25 400 h 600 h 800 h a00 h c00 h e00 h fff h
9 dac7615 theory of operation the dac7615 is a quad, serial input, 12-bit, voltage output dac. the architecture is a classic r-2r ladder configuration followed by an operational amplifier that serves as a buffer. each dac has its own r-2r ladder network and output op amp, but all share the reference voltage inputs. the minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by external voltage references (v refl and v refh , respectively). the digital input is a 16-bit serial word that contains the 12-bit dac code and a 2-bit address code that selects one of the four dacs (the two remaining bits are unused). the converter can be powered from a single +5v supply or a dual 5v supply. each device offers a reset function which immediately sets all dac output voltages and internal registers to either zero-scale (code 000 h ) or mid-scale (code 800 h ). the reset code is selected by the state of the resetsel pin (low = 000 h , high = 800 h ). see figures 1 and 2 for the basic operation of the dac7615. analog outputs when v ss = C5v (dual supply operation), the output amplifier can swing to within 2.25v of the supply rails, over the C40 c to +85 c temperature range. with v ss = 0v (single-supply operation), the output can swing to ground. note that the settling time of the output op amp will be longer with voltages very near ground. also, care must be taken when measuring the zero-scale error when v ss = 0v. if the output amplifier has a negative offset, the output voltage may not change for the first few digital input codes (000 h , 001 h , 002 h , etc.) since the output voltage cannot swing below ground. the behavior of the output amplifier can be critical in some applications. under short-circuit conditions (dac output shorted to ground), the output amplifier can sink a great deal more current than it can source. see the specifications table for more details concerning short circuit current. figure 1. basic single-supply operation of the dac7615. figure 2. basic dual-supply operation of the dac7615. note: (1) p and u package pin configurations shown. (2) as configured, reset low sets all internal registers to code 000 h (0v). if resetsel is high, reset low sets all internal registers to code 800 h (1.25v). 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd v outd v outc v refl v refh v outb v outa v ss resetsel reset loadreg loaddacs cs clk sdi gnd reset dacs (2) update selected register update all dac registers chip select clock serial data in dac7615 (1) 0.1 f 0.1 f 0v to +2.5v 1 f to 10 f +5v + 0v to +2.5v 0v to +2.5v 0v to +2.5v +2.500v note: (1) p and u package pin configurations shown. (2) as configured, reset low sets all internal registers to code 800 h (0v). if resetsel is low, reset low sets all internal registers to code 000 h (?.5v). 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd v outd v outc v refl v refh v outb v outa v ss resetsel reset loadreg loaddacs cs clk sdi gnd reset dacs (2) update selected register update all dac registers chip select clock serial data in dac7615 (1) 0.1 f 0.1 f ?.5v to +2.5v 1 f to 10 f +5v ?v + 0.1 f 1 f to 10 f + ?.5v to +2.5v ?.500v 0.1 f +2.500v ?.5v to +2.5v ?.5v to +2.5v +5v
10 dac7615 reference inputs the reference inputs, v refl and v refh , can be any voltage between v ss + 2.25v and v dd C 2.25v provided that v refh is at least 1.25v greater than v refl . the minimum output of each dac is equal to v refl C 1lsb plus a small offset voltage (essentially, the offset of the output op amp). the maximum output is equal to v refh plus a similar offset voltage. note that v ss (the negative power supply) must either be connected to ground or must be in the range of C 4.75v to C5.25v. the voltage on v ss sets several bias points within the converter. if v ss is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. the current into the reference inputs depends on the dac output voltages and can vary from a few microamps to approximately 0.6 milliamp. bypassing the reference volt- age or voltages with a 0.1 m f capacitor placed as close as possible to the dac7615 package is strongly recommended. digital interface figure 3 and table i provide the basic timing for the dac7615. the interface consists of a serial clock (clk), serial data (sdi), a load register signal (loadreg), and a load all dac registers signal (loaddacs). in addition, a chip select (cs) input is available to enable serial commu- nication when there are multiple serial devices. an asyn- symbol description min typ max units t ds data valid to clk rising 25 ns t dh data held valid after clk rises 20 ns t ch clk high 30 ns t cl clk low 50 ns t css cs low to clk rising 55 ns t csh clk high to cs rising 15 ns t ld1 loadreg high to clk rising 40 ns t ld2 clk rising to loadreg low 15 ns t ldrw loadreg low time 45 ns t lddw loaddacs low time 45 ns t rssh resetsel valid to reset low 25 ns t rstw reset low time 70 ns t s settling time 10 m s figure 3. dac7615 timing. chronous reset input (reset) is provided to simplify start- up conditions, periodic resets, or emergency resets to a known state. the dac code and address are provided via a 16-bit serial interface as shown in figure 3. the first two bits select the input register that will be updated when loadreg goes low (see table ii). the next two bits are not used. the last 12 bits are the dac code which is provided, most significant bit first. table i. timing specifications (t a = C40 c to +85 c). a1 (msb) (lsb) sdi clk cs loadreg a0 x x d11 d10 d9 d3 d2 d1 d0 sdi clk loaddacs reset v out t css t ld1 t cl t ch t ds t dh t ld2 t ldrw t lddw t s t rstw t rssh t csh t s 1 lsb error band 1 lsb error band resetsel
11 dac7615 state of selected selected state of input input all dac a1 a0 loadreg loaddacs reset register register registers l (1) llh (2) h a transparent latched l h l h h b transparent latched h l l h h c transparent latched h h l h h d transparent latched x (3) x h l h none (all latched) transparent x x h h h none (all latched) latched x x x x l all reset (4) reset (4) notes: (1) l = logic low. (2) h = logic high. (3) x = dont care. (4) resets to either 000h or 800 h , per the resetsel state (low = 000 h , high = 800 h ). when reset rises, all registers that are in their latched state retain the reset value. table ii. control logic truth table. cs (1) clk (1) loadreg reset serial shift register h (2) x (3) h h no change l (4) l h h no change l - (5) h h advanced one bit - l h h advanced one bit h (6) xl (7) h no change h (6) xhl (8) no change notes: (1) cs and clk are interchangeable. (2) h = logic high. (3) x = dont care. (4) l = logic low (5) = positive logic transition. (6) a high value is suggested in order to avoid a false clock from advancing the shift register and changing the shift register. (7) if data is clocked into the serial register while loadreg is low, the selected input register will change as the shift register bits flow through a1 and a0. this will corrupt the data in each input register that has been erroneously selected. (8) reset low causes no change in the contents of the serial shift register. table iii. serial shift register truth table. if both cs and clk are used, then cs should rise only when clk is high. if not, then either cs or clk can be used to operate the shift register. see table iii for more information. the digital data into the dac7615 is double-buffered. this allows new data to be entered for each dac without disturb- ing the analog outputs. when the new settings have been entered into the device, all of the dac outputs can be updated simultaneously. the transfer from the input regis- ters to the dac registers is accomplished with a high to low transition on the loaddacs input. because the dac registers become transparent when loaddacs is low, it is possible to keep this pin low and update each dac via loadreg. however, as each new data word is entered into the device, the corresponding output will update immediately when loadreg is taken low. digital input coding the dac7615 input data is in straight binary format. the output voltage is given by the following equation: note that cs and clk are combined with an or gate and the output controls the serial-to-parallel shift register inter- nal to the dac7615 (see the block diagram on the front of this data sheet). these two inputs are completely inter- changeable. in addition, care must be taken with the state of clk when cs rises at the end of a serial transfer. if clk is low when cs rises, the or gate will provide a rising edge to the shift register, shifting the internal data one additional bit. the result will be incorrect data and possible selection of the wrong input register. where n is the digital input code (in decimal). this equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. (v refh C v refl ) ? n 4096 v out = v refl +
12 dac7615 layout a precision analog component requires careful layout, ad- equate bypassing, and clean, well-regulated power supplies. as the dac7615 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. the more digital logic present in the design and the higher the switch- ing speed, the more difficult it will be to achieve good performance from the converter. because the dac7615 has a single ground pin, all return currents, including digital and analog return currents, must flow through the gnd pin. ideally, gnd would be con- nected directly to an analog ground plane. this plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system (see figure 4). the power applied to v dd (as well as v ss , if not grounded) should be well regulated and low noise. switching power supplies and dc/dc converters will often have high-fre- quency glitches or spikes riding on the output voltage. in addition, digital components can create similar high-fre- quency spikes as their internal logic switches states. this noise can easily couple into the dac output voltage through various paths between the power connections and analog output. as with the gnd connection, v dd should be connected to a +5v power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. in addition, the 1 m f to 10 m f and 0.1 m f capacitors shown in figure 4 are strongly recommended. in some situations, additional bypassing may be required, such as a 100 m f electrolytic capacitor or even a pi filter made up of inductors and capacitorsall designed to essentially lowpass filter the +5v supply, removing the high frequency noise (see figure 4). figure 4. suggested power and ground connections for a dac7615 sharing a +5v supply with a digital system. +5v power supply optional digital circuits dac7615 other analog components +5v 100? 1? to 10? ground +5v ground v dd gnd 0.1? ++
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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