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" white electronic designs may 2003 rev. 6 !" # $%"#& '()*+ # *, -* + . !" # $%"#&/ '()*+ # *, -* + . /0#*,-1 $2 #&.&// '()* 3&4 , , 5646- /0&337-15 ,"* , & /0#*,-1 $#&.&// ' ()* . /89 /89 : ;* </89 /89 0' *%=,'"*,4,>) > ,'?0 *%*2*- )*?0 89/ = =*-; - *0# + ),*0 0,*% "*,)* - ",?0 + "), ;),"), >)0,! 4 )"0 -" )0,"0 $* ) * = @ ;"*, a ', a/8 !bb! *,%"0 a/8 !b! *,%"0 a/8 !b$2b ! *,%"0 a/8 !b$b! *,%"0 # 6*c * * -%0 , **',,)* /()0<, * 8?%,' % ? , , * ? )** ,0% *& 0 )"" *, )00 '" * : 0, * * d :ef)""0% 6? 6* * *0 *,' *=*a*, * ,, * * ;"*, + ,* 0 * * - ,* 0 & fd 0-15 flash data inputs/outputs sd 0-15 sram data inputs/outputs a 0-16 address inputs swe 1-2 sram write enable scs 1-2 sram chip selects oe output enable v cc power supply gnd ground nc not connected fwe 1-2 flash write enable fcs 1-2 flash chip select # $%& white electronic designs fd 0-15 flash data inputs/outputs sd 0-15 sram data inputs/outputs a 0-16 address inputs swe 1-2 sram write enable scs 1-2 sram chip selects oe output enable v cc power supply gnd ground nc not connected fwe 1-2 flash write enable fcs 1-2 flash chip select ! " white electronic designs input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lo scs = v ih , oe = v ih, v out = gnd to v cc 10 a sram operating supply current x 16 mode i ccx16 scs = v il , oe = fcs = v ih, f = 5mhz, v cc = 5.5 360 ma standby current i sb fcs = scs = v ih , oe = v ih, f = 5mhz, v cc = 5.5 40 ma sram output low voltage v ol i ol = 2.1ma, v cc = 4.5 0.4 v sram output high voltage v oh i oh = -1.0ma, v cc = 4.5 2.4 v flash v cc active current for read (1) i cc1 fcs = v il , oe = scs = v ih 100 ma flash v cc active current for program or i cc2 fcs = v il , oe = scs = v ih 130 ma erase (2) flash output low voltage v ol i ol = 8.0ma, v cc = 4.5 0.45 v flash output high voltage v oh1 i oh = -2.5 ma, v cc = 4.5 0.85 x v cc v flash output high voltage v oh2 i oh = -100 a, v cc = 4.5 v cc -0.4 v flash low v cc lock out voltage v lko 3.2 v flash data retention 10 years flash endurance (write/erase cycles) 10,000 !" !# $ # % # " $ $ # " % ! % supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.5 +0.8 v ! operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 7.0 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v &''# #!(' # )#% *+,-. )#% % % / 0,-1 2&, /&'' " ! * . 3(' 2&4563212&,52''7632 h x x standby high z standby l l h read data out active l h h read high z active l x l write data in active oe capacitance c oe v in = 0v, f = 1.0mhz 50 pf f/s we 1-2 capacitance c we v in = 0v, f = 1.0mhz 20 pf f/s cs 1-2 capacitance c cs v in = 0v, f = 1.0mhz 20 pf sd 0 - 15 /fd 0 - 15 capacitance c i / o v in = 0v, f = 1.0mhz 20 pf a 0 - a 16 capacitance c ad v in = 0v, f = 1.0mhz 50 pf # !% !# # $%& white electronic designs ! " read cycle time t rc 35 70 ns address access time t aa 35 70 ns output hold from address change t oh 03ns chip select access time t acs 35 70 ns output enable to output valid t oe 20 35 ns chip select to output in low z t clz 1 33ns output enable to output in low z t olz 1 00ns chip disable to output in high z t chz 1 20 25 ns output disable to output in high z t ohz 1 20 25 ns " write cycle time t wc 35 70 ns chip select to end of write t cw 25 60 ns address valid to end of write t aw 25 60 ns data valid to end of write t dw 20 30 ns write pulse width t wp 25 50 ns address setup time t as 05ns address hold time t ah 05ns output active from end of write t ow 1 45ns write enable to output in high z t whz 1 20 25 ns data hold from write time t dh 00ns 28 ! 7/29:2 & 4;& , ! 6< & 865: 28 % % 2 , 2 4 & 4;& , =# # % " # #= " # input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v # !% !# # !% !# ! " white electronic designs # $ ws32k32-xhx # $%& white electronic designs % &$ & ! $ $% write cycle time t avav t wc 70 120 ns chip select setup time t elwl t cs 00ns write enable pulse width t wlwh t wp 35 50 ns address setup time t avwl t as 00ns data setup time t dvwh t ds 30 50 ns data hold time t whdx t dh 00ns address hold time t wlax t ah 45 50 ns chip select hold time t wheh t ch 00ns write enable pulse width high t whwl t wph 20 20 ns duration of byte programming operation (min) t whwh1 14 14 s chip and sector erase time t whwh2 2.2 60 2.2 60 sec read recovery time before write t ghwl 00s v cc set-up time t vcs 50 50 s chip programming time 12.5 12.5 sec output enable setup time t oes 00ns output enable hold time (1) t oeh 10 10 ns % ! ! $% read cycle time t avav t rc 70 120 ns address access time t avqv t acc 70 120 ns chip select access time t elqv t ce 70 120 ns oe to output valid t glqv t oe 35 50 ns chip select to output high z (1) t ehqz t df 20 30 ns oe high to output high z (1) t ghqz t df 20 30 ns output hold from address, cs or oe change, whichever is first t axqx t oh 00ns ># !% 1 ( ! " white electronic designs $% write cycle time t avav t wc 70 120 ns fwe setup time t wlel t ws 00ns fcs pulse width t eleh t cp 35 50 ns address setup time t avel t as 00ns data setup time t dveh t ds 30 50 ns data hold time t ehdx t dh 00ns address hold time t elax t ah 45 50 ns fwe hold from fwe high t ehwh t wh 00ns fcs pulse width high t ehel t cph 20 20 ns duration of programming operation t whwh1 14 14 s duration of erase operation t whwh2 2.2 60 2.2 60 sec read recovery before write t ghel 00ns chip programming time 12.5 12.5 sec % &$ & ! # $%& white electronic designs ' ( ! ! " white electronic designs &$ & ! $ % ! /( ! !% 3(: # # " ?( @ # # " # !#%#!# % )# # $%& white electronic designs ) & $ ! ! " white electronic designs $ ! # $%& white electronic designs &$ & ! % ! /( ! !% 3(: # # " ?( @ # # " # !#% #!#%)# ! " white electronic designs # * ' + 444& a(& & a &44& a (a , &'44b&&', # $%& white electronic designs 444& a(& & a &44& a (a , &'44b&&', )* + , , ! " white electronic designs 444& a(& & a &44& a (a , &'44b&&', 25.27 (0.995) 0.13 (0.005) sq 23.88 (0.940) 0.25 (0.010) sq 0.38 (0.015) 0.05 (0.002) 20.3 (0.800) ref 1.27 (0.050) 4.06 (0.160) max 0.25 (0.010) max see detail "a" 0.84 (0.033) ref detail a 0.83 (0.033) 0.32 (0.013) 0 0 /8 0 #* + , + , # $%& white electronic designs &'()*+ blank = gold plated leads a = solder dip leads , -!'+ m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c ' .'-/ + h1 = 1.075" sq. ceramic hex in-line package, hip (package 400) h = 1.185" sq. ceramic hex in-line package, hip (package 401) g1u = 22.4 mm ceramic quad flat pack, cqfp (package 519) g1t = 22.4mm ceramic quad flat pack, cqfp (package 524) ' 0 1 37 = 35ns sram and 70ns flash 72 = 70ns sram and 120ns flash !-')2')3 $%4.$5 (&'* !' *& !) -) ! 6 ! ' device type sram speed flash speed package smd no. 128k x 16 mixed module 70ns 120ns 66 pin hip (h) 596 2-96900 01hxx 128k x 16 mixed module 70ns 120ns 66 pin hip (h1) 5962-96900 01hyx 128k x 16 mixed module 70ns 120ns 68 lead cqfp/j (g1u) 5962-96900 01h9x 128k x 16 mixed module 35ns 70ns 66 pin hip (h) 596 2-96900 02hxx 128k x 16 mixed module 35ns 70ns 66 pin hip (h1) 5962-96900 02hyx 128k x 16 mixed module 35ns 70ns 68 lead cqfp/j (g1u) 5962-96900 02h9x |
Price & Availability of WSF128K16-XG1TX
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