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rev 1.1.1 12/8/00 characteristics subject to change without notice. 1 of 14 www.xicor.com recommended system management alternative: x4163 for a more integrated solution use xicor system management products block diagram start stop logic slave address register +comparator h.v. generation timing & control word address counter x dec y dec d out 128 x 128 data register r/w pin (6) scl (3) a2 d out load inc ck 8 (7) test control logic ack eeprom start cycle (8) v cc (4) v ss (5) sda (2) a1 (1) a0 16k x24c16 2048 x 8 bit serial eeprom features 2.7v to 5.5v power supply low power cmos active read current less than 1 ma active write current less than 3 ma standby current less than 1? internally organized 2048 x 8 2-wire serial interface bidirectional data transfer protocol sixteen byte page write mode minimizes total write time per byte self-timed write cycle typical write cycle time of 5 ms high reliability endurance: 1,000,000 cycles data retention: 100 years packages 14-lead tssop 8-lead soic description the x24c16 is a cmos 16,384 bit serial eeprom, internally organized 2048 x 8. the x24c16 features a serial interface and software protocol allowing opera- tion on a simple two wire bus. the x24c16 is fabricated with xicors advanced cmos textured poly floating gate technology. the x24c16 utilizes xicors proprietary direct write cell providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.
x24c16 characteristics subject to change without notice. 2 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open col- lector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. address (a 0 , a 1 , a 2 ) the a 0 , a 1 and a 2 inputs are unused by the x24c16, however, they must be tied to v ss to insure proper device operation. pin names pin configuration device operation the x24c16 supports a bidirectional bus oriented pro- tocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master, and the device being controlled is the slave. the master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. therefore, the x24c16 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. symbol description a 0 ? 2 address inputs sda serial data scl serial clock test hold at v ss v ss ground v cc supply voltage nc no connect a 0 a 1 a 2 v ss 1 2 3 4 8 7 6 5 v cc test scl sda x24c16 8-lead soic a 0 a 1 nc nc 1 2 3 4 14 13 12 11 v cc test nc nc x24c16 14-lead tssop nc a 2 v ss 5 6 7 10 9 8 nc scl sda figure 1. data validity scl sda data stable data change
x24c16 characteristics subject to change without notice. 3 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products figure 2. definition of start and stop scl sda start bit stop bit start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24c16 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used by the x24c16 to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24c16 will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the x24c16 will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the x24c16 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24c16 will continue to transmit data. if an acknowledge is not detected, the x24c16 will terminate further data trans- missions. the master must then issue a stop condition to return the x24c16 to the standby power mode and place the device into a known state. figure 3. acknowledge response from receiver scl from master data output from transmitter 1 89 from receiver start acknowledge data output
x24c16 characteristics subject to change without notice. 4 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products device addressing following a start condition, the master must output the address of the slave it is accessing. the most signi? cant four bits of the slave address are the device type identi?r (see figure 4). for the x24c16 this is ?ed as 1010[b]. figure 4. slave addressing the next three bits of the slave address ?ld are the bank select bits. they are used by the host to toggle between the eight 256 x 8 banks of memory. these are, in effect, the most signi?ant bits for the word address. the next three bits of the slave address are an exten- sion of the arrays address and are concatenated with the eight bits of address in the word address ?ld, pro- viding direct access to the whole 2048 x 8 array. following the start condition, the x24c16 monitors the sda bus, comparing the slave address being transmit- ted with its slave address (device type). upon a correct compare, the x24c16 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the x24c16 will execute a read or write operation. write operations byte write for a write operation, the x24c16 requires a second address ?ld. this address ?ld is the word address, comprised of eight bits, providing access to any one of the 2048 words in the array. upon receipt of the word address the x24c16 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the x24c16 begins the internal write cycle to the non- volatile memory. while the internal write cycle is in progress the x24c16 inputs are disabled, and the device will not respond to any requests from the mas- ter. refer to figure 5 for the address, acknowledge and data transfer sequence. 1 a 1 a 0 r/w word address 010a 2 device type identifier high order figure 5. byte write figure 6. page write bus activity: master sda bus bus activity: x24c16 s t a r t slave address s t o p a c k a c k a c k word address data p s s t a r t slave address s t o p a c k a c k a c k a c k a c k data n + 1 word address (n) data n s p data n + 15 note: in this example n = xxxx 000 (b); x = 1 or 0 bus activity: master sda line bus activity: x24c16
x24c16 characteristics subject to change without notice. 5 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products page write the x24c16 is capable of a 16 byte page write opera- tion. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the ?st data word is transferred, the master can trans- mit up to ?teen more words. after the receipt of each word, the x24c16 will respond with an acknowledge. after the receipt of each word, the four low order address bits are internally incremented by one. the high order seven bits of the address remain constant. if the master should transmit more than sixteen words prior to generating the stop condition, the address counter will ?oll over and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowledge and data transfer sequence. acknowledge polling the disabling of the inputs can be used to take advan- tage of the typical 5 ms write cycle time. once the stop condition is issued to indicate the end of the hosts write operation, the x24c16 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the x24c16 is still busy with the write operation, no ack will be returned. if the x24c16 has completed the write oper- ation, an ack will be returned and the host can then proceed with the next read or write operation. refer to flow 1. flow 1. ack polling sequence write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no
x24c16 characteristics subject to change without notice. 6 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle, or hold sda high during the ninth clock cycle and then issue a stop condition. current address read internally, the x24c16 contains an address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the x24c16 issues an acknowledge and transmits the eight bit word. the read operation is terminated by the master by not responding with an acknowledge, and issuing a stop condition. refer to figure 7 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must ?st perform a ?ummy write opera- tion. the master issues the start condition, and the slave address followed by the word address it is to read. after the word address acknowledge, the master imme- diately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the x24c16 and then by the eight bit word. the read operation is terminated by the master by not responding with an acknowledge, and issuing a stop condition. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 7. current address read s t a r t slave address a c k s bus activity: master sda line bus activity: x24c16 data s t o p p figure 8. random read s t a r t slave address a c k a c k s s t a r t slave address word address n s a c k data n s t o p p bus activity: master sda line bus activity: x24c16 sequential read sequential reads can be initiated as either a current address read or random access read. the ?st word is transmitted as with the other read modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24c16 continues to output data for each acknowledge received. the read operation is terminated by the master by not respond- ing with an acknowledge, and then issuing a stop con- dition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 2047), the counter ?olls over to 0 and the x24c16 continues to output data for each acknowl- edge received. refer to figure 9 for the address, acknowledge and data transfer sequence.
x24c16 characteristics subject to change without notice. 7 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products figure 9. sequential read figure 10. typical system configuration slave address s t o p a c k a c k a c k a c k data n data n+1 data n+2 data n+x p bus activity: master sda line bus activity: x24c16 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver pull-up resistors sda scl v cc
x24c16 characteristics subject to change without notice. 8 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products absolute maximum ratings temperature under bias ........................?5 to +135 c storage temperature .............................?5 to +150 c voltage on any pin with respect to v ss .......?v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds)........ 300 c comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70? industrial ?0 c +85? supply voltage limits x24c16?.5 2.5v to 5.5v d.c. operating characteristics (over the recommended operating conditions, unless otherwise speci?d.) capacitance t a = +25?, f = 1.0 mhz, v cc = 5v notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. max. i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100 khz, sda = open, all other inputs = gnd or v cc ?0.3v i cc2 v cc supply current (write) 3 i sb1 (1) v cc standby current x24c16 150 ? scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 5v i sb2 (1) v cc standby current x24c16-3 50 ? scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 3.3v ?0% i sb3 (1) v cc standby current x24c16-2.5 1 a scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 2.5v i sb4 (1) v cc standby current x24c16-1.8 1 a scl = sda = v cc ?0.3v, all other inputs = gnd or v cc , v cc = 1.8v i li input leakage current 10 ? v in = gnd to v cc i lo output leakage current 10 ? v out = gnd to v cc v ll (2) input low voltage ?.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma symbol parameter max. unit test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v
x24c16 characteristics subject to change without notice. 9 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products a.c. conditions of test equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 5v 1533 ? 100pf output a.c. operating characteristics (over the recommended operating conditions, unless otherwise speci?d.) read & write cycle limits power-up timing (4) note: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. unit f scl scl clock frequency 0 400 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 ? t buf time the bus must be free before a new transmission can start 4.7 ? t hd:sta start condition hold time 4.0 ? t low clock low period 4.7 ? t high clock high period 4.0 ? t su:sta start condition setup time (for a repeated start condition) 4.7 ? t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 ? t dh data out hold time 300 ns symbol parameter max. unit t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms
x24c16 characteristics subject to change without notice. 10 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products bus timing write cycle limits notes: (5) typical values are for t a = 25? and nominal supply voltage (5v). (6) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. during the write cycle, the x24c16 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing symbol parameter min. typ. (5) max. unit t wc (6) write cycle time 5 10 ms t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high scl sda 8 th bit word n ack t wc stop condition start condition x24x16 address
x24c16 characteristics subject to change without notice. 11 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products guidelines for calculating typical values of bus pull-up resistors symbol table 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k ? ) bus capacitance (pf) min. resistance max. resistance r max. = c bus t r r min. = i ol min. v cc max. =1.8k ? waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x24c16 characteristics subject to change without notice. 12 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
x24c16 characteristics subject to change without notice. 13 of 14 rev 1.1.1 12/8/00 www.xicor.com for a more integrated solution use xicor system management products packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0?- 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
for a more integrated solution use xicor system management products x24c16 characteristics subject to change without notice. 14 of 14 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.1.1 12/8/00 www.xicor.com ordering information part mark convention device x24c16 x x -x v cc range 2.7 = 2.7v to 5.5v temperature range package s8 = 8-lead soic blank = commercial = 0? to +70? i = ?0 c to +85 c v14 = 14-lead tssop x24c16 x x s8 = 8-lead soic ab = 2.7v to 5.5v, 0? to +70? ad = 2.7v to 5.5v, ?0? to +85? v14 = 14-lead tssop

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