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ht24lc08 cmos 8k 2-wire serial eeprom block diagram pin assignment pin description pin name i/o description a0~a2 i address input sda i/o serial data scl i serial clock input wp i write protect vss negative power supply, ground vcc positive power supply rev. 1.10 1 march 27, 2002 features operating voltage: 2.2v~5.5v low power consumption operation: 5ma max. standby: 5 a max. internal organization: 1024 8 2-wire serial interface write cycle time: 5ms max. automatic erase-before-write operation partial page write allowed 16-byte page write mode write operation with built-in timer hardware controlled write protection 40-year data retention 10 6 rewrite cycles per word commerical temperature range (0 cto+70 c) 8-pin dip/sop package general description the ht24lc08 is an 8k-bit serial read/write non-volatile memory device using the cmos floating gate process. its 8192 bits of memory are organized into 1024 words and each word is 8 bits. the device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. up to two ht24lc08 devices may be connected to the same 2-wire bus. the ht24lc08 is guaranteed for 1m erase/write cycles and 40-year data retention.

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absolute maximum ratings operating temperature (commercial) ............................................................................................... ......... 0 cto70 c storage temperature ............................................................................................................. ............... 50 cto125 c applied vcc voltage with respect to vss .............................................................................................. . 0.3v to 6.0v applied voltage on any pin with respect to vss ........................................................................................................ 0.3v to v cc +0.3v note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=0 cto70 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 2.2 5.5 v i cc1 operating current 5v read at 100khz 2ma i cc2 operating current 5v write at 100khz 5ma v il input low voltage 1 0.3v cc v v ih input high voltage 0.7v cc v cc +0.5 v v ol output low voltage 2.4v i ol =2.1ma 0.4 v i li input leakage current 5v v in =0 or v cc 1 a i lo output leakage current 5v v out =0 or v cc 1 a i stb1 standby current 5v v in =0 or v cc 5 a i stb2 standby current 2.4v v in =0 or v cc 4 a c in input capacitance (see note) f=1mhz 25 c 6pf c out output capacitance (see note) f=1mhz 25 c 8pf note: these parameters are periodically sampled but not 100% tested a.c. characteristics ta=0 cto70 c symbol parameter remark standard mode* v cc =5v 10% unit min. max. min. max. f sk clock frequency 100 400 khz t high clock high time 4000 600 ns t low clock low time 4700 1200 ns t r sda and scl rise time note 1000 300 ns t f sda and scl fall time note 300 300 ns t hd:sta start condition hold time after this period the first clock pulse is generated 4000 600 ns t su:sta start condition setup time only relevant for repeated start condition 4000 600 ns t hd:dat data input hold time 0 0 ns t su:dat data input setup time 200 100 ns t su:sto stop condition setup time 4000 600 ns ht24lc08 rev. 1.10 2 march 27, 2002
symbol parameter remark standard mode* v cc =5v 10% unit min. max. min. max. t aa output valid from clock 3500 900 ns t buf bus free time time in which the bus must be free before a new transmission can start 4700 1200 ns t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns t wr write cycle time 5 5ms notes: these parameters are periodically sampled but not 100% tested * the standard mode means v cc =2.2v to 5.5v for relative timing, refer to timing diagrams ht24lc08 rev. 1.10 3 march 27, 2002 functional description serial clock (scl) the scl input is used for positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda) the sda pin is bidirectional for serial data transfer. the pin is open drain driven and may be write-or with any number of other open drain or open collector de - vices. a0, a1, a2 the ht24lc08 uses the a2 input for hard wire ad- dressing and a total of two 8k devices may be ad- dressed on a single bus system. the a0 and a1 pins have no connection. write protect (wp) the ht24lc08 has a write protect pin that provides hardware data protection. the write protect pin allows normal read/write operations when the connection is grounded. when the write protect pin is connected to v cc , the write protection feature is enabled and oper - ates as shown in the following table. wp pin status protect array at v cc full array (8k) at v ss normal read/write operations memory organization internally organized with 1024 8-bit words, the 8k re - quires a 10-bit data word address for random word ad - dressing. device operations clock and data transition data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in data line while the clock line is high will be interpreted as a start or stop condition. start condition a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). stop condition a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (re - fer to start and stop definition timing diagram). acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has re- ceived each word. this happens during the ninth clock cycle. device addressing the 8k eeprom device requires an 8-bit device ad - dress word following a start condition to enable the chip for a read or write operation. the device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the device address). this is common to all the eeprom device. the 8k eeprom uses the a2 device address bit with the next two bits for memory page addressing. the a2 bit must compare its corresponding hard-wired input pin. the a1 and a0 pins have no connection. these page addressing bits on the 8k device should be considered the most significant bits of the data word ad - ( ( ) ( / ! ) 0 ( ! ! " " ) ( 1 / ! 2 ( ! . ! ( ) !
ht24lc08 rev. 1.10 4 march 27, 2002 dress which follows. the a0, a1 and a2 pins have no connection. the 8th bit device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. if the comparison of the device address succeed the eeprom will output a zero at ack bit. if not, the chip will return to a standby state. write operations byte write a write operation requires an 8-bit data word address following the device address word and acknowledg - ment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. after receiving the 8-bit data word, the eeprom will output a zero and the addressing de - vice, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally-timed write cycle to the nonvolatile memory. all inputs are disabled during this write cycle and eeprom will not respond until write is complete (refer to byte write timing). page write the 8k eeprom is capable of a 16-byte page write. a page write is initiated in the same way as a byte write, but the microcontroller does not send a stop con- dition after the first data word is clocked in. instead, af- ter the eeprom acknow ledges the receipt of the first data word, the microcontroller can transmit up to 15 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (refer to page write timing). the data word address lower four bits are internally in - cremented following the receipt of each data word. the higher data word address bits are not incre - mented, retaining the memory page row location. acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com - mand has been issued from the master, the device ini - tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w=0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is completed, then the device will return the ack and the master can then proceed with the next read or write command. '

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ht24lc08 rev. 1.10 5 march 27, 2002 write protect the ht24lc08 can be used as a serial rom when the wp pin is connected to vcc . programming will be inhibited and the entire memory will be write-protected. read operations read operations are initiated in the same way as write operations with the exception that the read/write se - lect bit in the device address word is set to one. there are three read operations: current address read, ran - dom address read and sequential read. current address read the internal data word address counter maintains the last address accessed during the last read or write op - eration, incremented by one. this address stays valid between operations as long as the chip power is main - tained. the address roll over during read from the last byte of the last memory page to the first byte of the first page. the address roll over during write from the last byte of the current page to the first byte of the same page. once the device address with the read/write se - lect bit set to one is clocked in and acknowledged by the eeprom, the current address data word is seri - ally clocked out. the microcontroller does not respond with an input zero but does generate a following stop condition (refer to current read timing). random read a random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the eeprom. the microcontroller must then generate another start con - dition. the microcontroller now initiates a current ad - dress read by sending a device address with the read/write select bit high. the eeprom acknowl - edges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition (refer to random read timing). sequential read sequential reads are initiated by either a current ad - dress read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgment. as long as the eeprom re - ceives an acknowledgment, it will continue to incre - ment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read continues. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a fol - lowing stop condition. 2 ) ( ! ! " " ! ) ( ! ! " " 4 . ( 4 ; ) 4 4 3
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timing diagrams note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the valid start con - dition of sequential command. ht24lc08 rev. 1.10 6 march 27, 2002 < ' - = - > ? 3 - ? 3 - ? 3 > ? 3 > ? 3 * > < ( ! ( ! > 3 0 ) @ ! ) ' 4 . ! . !
ht24lc08 rev. 1.10 7 march 27, 2002 copyright 2002 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holmate technology corp. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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