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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. 1 copyright ? cirrus logic, inc. 2004 (all rights reserved) cirrus logic, inc. www.cirrus.com cs4265 105 db, 24-bit, 192 khz stereo audio codec nov ?04 ds657a2 d/a features z multi-bit delta sigma modulator z 105 db dynamic range z -95 db thd+n z up to 192 khz sampling rates z single-ended analog architecture z volume control with soft ramp ? 0.5 db step size ? zero crossing click-free transitions z popguard tm technology ? minimizes the effects of output transients. z filtered line-level outputs z selectable serial a udio interface formats ? left justified up to 24-bit ?i 2 s up to 24-bit ? right justified 16, 18, 20 and 24-bit z selectable 50/15 s de-emphasis a/d features z multi-bit delta sigma modulator z 105 db dynamic range z -95 db thd+n z stereo 2:1 input multiplexer z programmable gain amplifier (pga) ? +/- 12 db gain, 0.5 db step size ? zero crossing, click-free transitions z pseudo-differential stereo line inputs z stereo microphone inputs ? +32 db gain stage ? low-noise bias supply z up to 192 khz sampling rates z selectable serial audio interface formats ? left justified up to 24-bit ? i2s up to 24-bit z high-pass filter or dc offset calibration 1.8 v to 5 v m u ltib it ? modulator m u ltib it ? modulator linear phase anti-alias filter interpolation filter interpolation filter l e ft d a c o u tp u t right dac output switched capacitor dac and f ilter m u ltib it o ve rs a m p lin g adc m u ltib it o v e rs a m p lin g adc linear phase anti-alias filter high pass f ilte r high pass f ilte r stereo line input serial audio input serial audio o utput 3.3 v to 5 v 3.3 v to 5 v switched capacitor dac and f ilter mux pga volume c ontrol volume c ontrol p c m s erial interfa ce / loopba ck mute control level translator level translator reset i 2 c c ontrol data mute c ontrol mic input 1 & 2 pga +32 db +32 db internal voltage reference ie c 60958-3 transmitter mic bias microphone bias transmitter output register c onfiguration
cs4265 2 ds657a2 system features z synchronous iec60958-3 transmitter ? up to 192 khz sampling rates ?75 ? drive capability z serial audio data input multiplexer z internal digital loopback z supports master or slave operation z mute output control z power down mode ? available for a/d, d/a, codec, mic preamplifier z +3.3 v to +5 v analog power supply z +3.3 v to +5 v digital power supply z direct interface with 1.8 v to 5 v logic levels z supports i2c control port interface general description the cs4265 is a highly in tegrated stereo audio co- dec. the cs4265 performs stereo analog-to-digital (a/d) and digital-to-analog (d/a) conversion of up to 24-bit serial values at sample rates up to 192 khz. a 2:1 stereo input multiplexer is included for selecting between line level or microphone level inputs. the mi- crophone input path includes a +32 db gain stage and a low noise bias voltage supply. the pga is available for line or microphone inputs and provides gain or attenua- tion of 12 db in 0.5 db steps. the output of the pga is followed by an advanced 5th- order, multi-bit delta sigma modulator and digital filter- ing/decimation. sampled data is transmitted by the serial audio interface at rates from 4 khz to 192 khz in either slave or master mode. the d/a converter is based on a 4th-order multi-bit delta sigma modulator with an ultr a-linear low pass filter and offers a volume control that operates with a 0.5 db step size. it incorporates sele ctable soft ramp and zero crossing transition functions to eliminate clicks and pops. standard 50/15 s de-emphasis is available for a 44.1 khz sample rate for comp atibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. integrated level translator s allow easy interfacing be- tween the cs4265 and other devices operating over a wide range of logic levels. ordering in formation CS4265-CNZ, lead free -10 to 70 c 32-pin qfn cdb4265 evaluation board
cs4265 ds657a2 3 table of contents 1. pin descriptions ......................................................................................................... ...... 5 2. characteristics and specifications ..... ................ ............. ............. ............. ........... 7 specified operating conditions . .............. ................ ............. ............. ............. ........... 7 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 7 dac analog characteristics ....................................................................................... 8 dac combined interpolation & on-chip analog filter response.................. 9 adc analog characteristics ..................................................................................... 11 adc analog characteristics ..................................................................................... 13 adc digital filter characteristics......................................................................... 14 dc electrical characteristics ................................................................................ 15 digital interface characteristics ......................................................................... 16 switching characteristics - serial audio port................................................. 17 switching characteristics - i2c control port................................................... 20 3. typical connection diagram .................................................................................... 21 4. applications ............................................................................................................. ....... 22 4.1 recommended power-up sequence ............................................................................. 22 4.2 system clocking .......................................................................................................... ... 22 4.2.1 master clock ...................................................................................................... 22 4.2.2 master mode ...................................................................................................... 23 4.2.3 slave mode ........................................................................................................ 23 4.3 high pass filter and dc of fset calibration .................................................................... 23 4.4 analog input multiplexer, pga, and mic ga in ................................................................ 24 4.5 input connections ........................................................................................................ ... 24 4.5.1 pseudo-differential input ................................................................................... 24 4.6 output connections ....................................................................................................... .25 4.7 output transient control ................................................................................................ 2 5 4.7.1 power-up ............................................................................................................ 25 4.7.2 power-down .... ................................................................................................... 25 4.7.3 serial interface clock changes ......................................................................... 25 4.8 dac serial data input mu ltiplexer .................................................................................. 26 4.9 de-emphasis filter ............................... ........................................................................ .. 26 4.10 internal digital loopback .................... .......................................................................... 2 6 4.11 mute control ............................................................................................................ ..... 26 4.12 aes3 transmitter ............... ................ ................. ................ ................ ............. ........... .27 4.12.1 txout driver ..................................................................................................... 27 4.12.2 mono mode operation .................. ................................................................... 27 4.13 i2c control port description and timing ................. ...................................................... 28 4.14 status reporting ........................................................................................................ ... 29 4.15 reset .................................................................................................................. ......... 29 4.16 synchronization of multiple devices ............................................................................. 30 4.17 grounding and power supp ly decoupling .................................................................... 30 4.18 package considerations ............................................................................................... 30 5. register quick reference ......................................................................................... 31 6. register description ................................................................................................... 33 6.1 chip id - register 01h ................................................................................................... .33 6.2 power control - address 02h ......................................................................................... 33 6.3 dac control - address 03h ...................... ...................................................................... 34 6.4 adc control - address 04h ............................................................................................ 34 6.5 mclk frequency - address 05h .................................................................................... 36 6.6 signal selection - address 06h ...................................................................................... 36 6.7 channel a pga control - address 07h .......................................................................... 36 6.8 channel b pga control - address 08h .......................................................................... 37
cs4265 4 ds657a2 6.9 adc input control - address 09h ................................................................................... 37 6.10 dac channel a volume control - addres s 0ah ........................................................... 38 6.11 dac channel b volume control - addres s 0bh ........................................................... 38 6.12 dac control 2 - address 0ch ....................................................................................... 38 6.13 status - address 0dh .................................................................................................... 39 6.14 status mask - address 0eh .......................................................................................... 40 6.15 status mode msb - address 0fh ........... ...................................................................... 40 6.16 status mode lsb - addr ess 10h ................................................................................... 40 6.17 transmitter control 1 - address 11h ............................................................................. 40 6.18 transmitter control 2 - address 12h ............................................................................. 41 7. parameter definitions ................................................................................................. 43 8. package dimensions ..................................................................................................... 4 4 9. thermal characteristics and specifications ................................................. 44 appendix a: dac filter plots ....................................................................................... .. 45 appendix b: adc filter plots ............................................................................................ .. 47 appendix c: external iec 60958-3 transmitter components .............................................. 49 c.1 iec60958-3 transmitter external compon ents ............................................................. 49 c.2 isolating transformer requ irements .............................................................................. 49 appendix d: channel status buffer management ............................................................... 50 d.1 iec60958-3 channel status (c) bit management ......................................................... 50 d.1.1 accessing the e buffer ....................................................................................... 50 d.1.2 serial copy management system (scms) ....................................................... 51 d.1.3 channel status data e buffer access ............................................................... 51 d.1.3.1 one byte mode ................................................................................... 51 d.1.3.2 two byte mode ................................................................................... 51
cs4265 ds657a2 5 1. pin descriptions pin name # pin description sda 1 serial control data ( input / output ) - bidirectional data line for the i2c control port. scl 2 serial control port clock ( input ) - serial clock for the i2c control port. vlc 3 control port power ( input ) - determines the required signal level for the control port interface. refer to the recommended operating conditi ons for appropriate voltages. reset 4 reset ( input ) - the device enters a low power mode when this pin is driven low. va 5 analog power (input) - positive power for the internal analog section. agnd 6 analog ground ( input ) - ground reference for the internal analog section. aina ainb 7, 8 analog input ( input ) - the full scale level is specified in the adc analog characteristics specification table. sgnd 9 signal ground ( input ) - ground reference for the analog line inputs. afilta afiltb 10, 11 antialias filter connection ( output ) - antialias filter connection for the adc inputs. vq 12 quiescent voltage ( output ) - filter connection for in ternal quiescent voltage. filt+ 13 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. micin1 micin2 14, 15 microphone input ( input ) - the full scale level is specified in th e adc analog characteristics specifica- tion table. 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 top-down (through package) view 32-pin qfn package txout vd dgnd mclk lrck sclk sdout sdin1 sgnd afilta afiltb vq filt+ micin1 micin2 micbias sda scl vlc reset va agnd aina ainb sdin2 txsdin vls mutec aoutb aouta agnd va thermal pad
cs4265 6 ds657a2 micbias 16 microphone bias ( output ) - low noise bias supply for external microphone. electrical characteristics are specified in the dc electrical characteristics table. va 17 analog power (input) - positive power for the internal analog section. agnd 18 analog ground ( input ) - ground reference for the internal analog section. aouta aoutb 19, 20 analog audio output ( output ) - the full scale output level is specified in the dac analog characteris- tics specification table. mutec 21 mute control ( output) - this pin is active during power-up initialization, reset, muting, when master clock left/right clock frequency ratio is incorrect, or power-down. vls 22 serial audio interface power ( input ) - determines the required signal level for the serial audio inter- face. refer to the recommended operating conditions for appropriate voltages. txsdin 23 transmitter serial audio data input ( input) - input for two?s complement serial audio data. sdin2 24 serial audio data input 2 ( input ) - input for two?s complement serial audio data. sdin1 25 serial audio data input 1 ( input ) - input for two?s complement serial audio data. sdout 26 serial audio data output ( output ) - output for two?s complement serial audio data. sclk 27 serial clock (input/output ) - serial clock for the serial audio interface. lrck 28 left right clock (input/output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 29 master clock ( input ) -clock source for the delta-sigma modulators. dgnd 30 digital ground ( input ) - ground reference for the internal digital section. vd 31 digital power ( input ) - positive power for the internal digital section. txout 32 transmitter line driver output ( output) - iec60958-3 driver output. thermal pad - thermal pad - thermal relief pad for optimized heat dissipation.
cs4265 ds657a2 7 2. characteristics and specifications (all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics an d specifications are derived from measurem ents taken at nominal supply voltages and t a = 25 c.) specified operat ing conditions (agnd = dgnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v all voltages with respect to ground.) (note 1) notes: 1. operation beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. 2. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. parameters symbol min nom max units dc power supplies: analog digital logic - serial port logic - control port va vd vls vlc 3.1 3.1 1.71 1.71 5.0 3.3 3.3 3.3 5.25 5.25 5.25 5.25 v v v v ambient operating temperature (power applied) t a -10 - +70 c parameter symbol min typ max units dc power supplies: analog digital logic - serial port logic - control port va vd vls vlc -0.3 -0.3 -0.3 -0.3 - - - - +6.0 +6.0 +6.0 +6.0 v v v v input current (note 2) i in -- 10 ma analog input voltage v ina agnd-0.3 - va+0.3 v digital input voltage logic - serial port logic - control port v ind-s v ind-c -0.3 -0.3 - - vls+0.3 vlc+0.3 v v ambient operating temperature (power applied) t a -20 - +85 c storage temperature t stg -65 - +150 c
cs4265 8 ds657a2 dac analog characteristics (full-scale output sine wave, 997 hz; test load r l = 3 k ? , c l = 10 pf (see figure 1), fs = 48/96/192 khz. measurement bandwidth 10 hz to 20 khz, unless otherwise speci- fied.) note: 3. one-half lsb of triangular pdf dither added to data. 4. guaranteed by design. the dc current draw represents the allowed current draw from the aout pin due to typical leakage through the el ectrolytic dc blocking capacitors. 5. guaranteed by design. see figure 2. r l and c l reflect the recommended minimum resistance and maximum capacitance requ ired for the internal op-amp?s stability. c l affects the dominant pole of the internal output amp; increasing c l beyond 100 pf can cause the internal op-amp to become unstable. parameter all speed modes symbol min typ max unit dynamic performance for va = 5 v dynamic range (note 3) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 96 99 87 90 102 105 93 96 - - - - db db db db total harmonic distortion + noise (note 3) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -95 -82 -42 -93 -73 -33 -89 -76 -36 -87 -67 -27 db db db db db db dynamic performance for va = 3.3 v dynamic range (note 3) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted 93 96 85 88 99 102 90 93 - - - - db db db db total harmonic distortion + noise (note 3) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -92 -79 -39 -90 -70 -30 -84 -71 -31 -82 -62 -22 db db db db db db interchannel isolation (1 khz) - 100 - db dc accuracy interchannel gain mismatch - 0.1 0.25 db gain drift - 100 - ppm/c analog output full scale output voltage 0.60*va 0.65*va 0.70*va v pp dc current draw from an aout pin (note 4) i out --10 a ac-load resistance (note 5) r l 3--k ? load capacitance (note 5) c l --100pf output impedance z out - 100 - ?
cs4265 ds657a2 9 dac combined interpolation & on -chip analog filt er response notes: 6. filter response is guaranteed by design. 7. for single speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double speed mode, the measuremen t bandwidth is 0.577 fs to 1.4 fs. for quad speed mode, the measurement bandwidth is 0.7 fs to 1 fs. 8. de-emphasis is available only in single speed mode. 9. response is clock dependent and will scale with fs. no te that the amplitude vs. frequency plots of this data (figures 18 to 27) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. parameter (note 6,9) symbol min typ max unit combined digital and on-chip analog filter response single speed mode passband (note 6) to -0.05 db corner to -3 db corner 0 0 - - .4780 .4996 fs fs frequency response 10 hz to 20 khz -.01 - +.08 db stopband .5465 - - fs stopband attenuation (note 7) 50 - - db group delay tgd - 10/fs - s de-emphasis error (note 8) fs = 44.1 khz - - +.05/-.25 db combined digital and on-chip analog filter response double speed mode passband (note 6) to -0.1 db corner to -3 db corner 0 0 - - .4650 .4982 fs fs frequency response 10 hz to 20 khz -.05 - +.2 db stopband .5770 - - fs stopband attenuation (note 7) 55 - - db group delay tgd - 5/fs - s combined digital and on-chip analog filter response quad speed mode passband (note 6) to -0.1 db corner to -3 db corner 0 0 - - 0.397 0.476 fs fs frequency response 10 hz to 20 khz 0 - +0.00004 db stopband 0.7 - - fs stopband attenuation (note 7) 51 - - db group delay tgd - 2.5/fs - s
cs4265 10 ds657a2 aoutx agnd 3.3 f v out r l c l figure 1. dac output test load 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 2. m aximum dac loading
cs4265 ds657a2 11 adc analog characteristics test conditions (unless other wise specified): input test sig- nal is a 1 khz sine wave; measurement bandwidth is 10 hz to 20 khz. fs = 48/96/192 khz. line level inputs parameter symbol min typ max unit dynamic performance for va = 5 v dynamic range pga setting: -12 db to +6 db a-weighted unweighted (note 12) 40 khz bandwidth unweighted pga setting: +12 db gain a-weighted unweighted (note 12) 40 khz bandwidth unweighted 99 96 - 93 90 - 105 102 99 99 96 93 - - - - - - db db db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to +6 db -1 db -20 db -60 db (note 12) 40 khz bandwidth -1 db pga setting: +12 db gain -1 db -20 db -60 db (note 12) 40 khz bandwidth -1 db thd+n - - - - - - - - -95 -82 -42 -92 -92 -76 -36 -89 -89 - - - -86 - - - db db db db db db db db dynamic performance for va = 3.3 v dynamic range pga setting: -12 db to +6 db a-weighted unweighted (note 12) 40 khz bandwidth unweighted pga setting: +12 db gain a-weighted unweighted (note 12) 40 khz bandwidth unweighted 94 91 - 90 87 - 102 99 96 96 93 90 - - - - - - db db db db db db
cs4265 12 ds657a2 10. valid when the line leve l inputs are selected. total harmonic distortion + noise (note 11) pga setting: -12 db to +6 db -1 db -20 db -60 db (note 12) 40 khz bandwidth -1 db pga setting: +12 db gain -1 db -20 db -60 db (note 12) 40 khz bandwidth -1 db thd+n - - - - - - - - -92 -79 -39 -84 -89 -73 -33 -81 -86 - - - -83 - - - db db db db db db db db line level inputs parameter symbol min typ max unit interchannel isolation - 90 - db line level input characteristics full-scale input voltage 0.53*va 0.56*va 0.59*va v pp input impedance (note 10) 6.12 6.8 7.48 k ? maximum interchannel input impedance mis- match -5-% line level and microphone level inputs parameter symbol min typ max unit dc accuracy interchannel gain mismatch - 0.1 - db gain error - 5 % gain drift - 100 - ppm/c programmable gain characteristics gain step size - 0.5 - db absolute gain step error - - 0.4 db
cs4265 ds657a2 13 adc analog characteristics (cont) 11. referred to the typical line level full-scale input voltage 12. valid for double and quad speed modes only. 13. valid when the microphone level inputs are selected. microphone level inputs parameter symbol min typ max unit dynamic performance for va = 5 v dynamic range pga setting: -12 db to 0 db a-weighted unweighted pga setting: +12 db a-weighted unweighted 77 74 65 62 83 80 71 68 - - - - db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to 0 db -1 db -20 db -60 db pga setting: +12 db -1 db thd+n - - - - -80 -60 -20 -68 -74 - - - db db db db dynamic performance for va = 3.3 v dynamic range pga setting: -12 db to 0 db a-weighted unweighted pga setting: +12 db a-weighted unweighted 77 74 65 62 83 80 71 68 - - - - db db db db total harmonic distortion + noise (note 11) pga setting: -12 db to 0 db -1 db -20 db -60 db pga setting: +12 db -1 db thd+n - - - - -80 -60 -20 -68 -74 - - - db db db db interchannel isolation - 30 - db microphone level input characteristics full-scale input voltage 0 .013*va 0.014*va 0.015*va v pp input impedance (note 13) - 50 - k ?
cs4265 14 ds657a2 adc digital filter characteristics note: 14. filter response is guaranteed by design. 15. response shown is for fs = 48 khz. 16. response is clock dependent and will scale with fs . note that the response plots (figures 30 to 41) are normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. parameter (note 14, 16) symbol min typ max unit single speed mode passband (-0.1 db) 0 - 0.4896 fs passband ripple - - 0.035 db stopband 0.5688 - - fs stopband attenuation 70 - - db total group delay (fs = output sample rate) t gd -12/fs - s double speed mode passband (-0.1 db) 0 - 0.4896 fs passband ripple - - 0.025 db stopband 0.5604 - - fs stopband attenuation 69 - - db total group delay (fs = output sample rate) t gd -9/fs - s quad speed mode passband (-0.1 db) 0 - 0.2604 fs passband ripple - - 0.025 db stopband 0.5000 - - fs stopband attenuation 60 - - db total group delay (fs = output sample rate) t gd -5/fs - s high pass filter characteristics frequency response -3.0 db -0.13 db (note 15) -1 20 - - hz hz phase deviation @ 20 hz (note 15) - 10 - deg passband ripple - - 0 db filter settling time 10 5 /fs s
cs4265 ds657a2 15 dc electrical characteristics (agnd = dgnd = 0 v, all voltages with respect to ground. mclk=12.288 mhz; fs=48 khz, master mode) notes: 17. power down mode is defines as reset = low with all clock and data lines held static and no analog input. 18. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection diagram. 19. guaranteed by design. the dc current draw represen ts the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. parameter symbol min typ max unit power supply current va = 5 v (normal operation) va = 3.3 v vd, vls, vlc = 5 v vd, vls, vlc = 3.3 v i a i a i d i d - - - - 41 37 39 23 50 45 47 28 ma ma ma ma power supply current. va = 5 v (power-down mode) (note 17). vls, vlc, vd=5 v i a i d - - 0.50 0.54 - - ma ma power consumption (normal operation). va, vd, vls, vlc = 5 v va, vd, vls, vlc = 3.3 v (power-down mode). va , vd, vls, vlc = 5 v - - - - - - 400 198 4.2 485 241 - mw mw mw power supply rejection rati o (1 khz) (note 18) psrr - 60 - db vq characteristics quiescent voltage vq - 0.5 x va - vdc dc current from vq (note 19) i q -- 1 a vq output impedance z q -23 -k ? filt+ nominal voltage filt+ - va - vdc microphone bias voltage micbias - 0.8 x va - vdc current from micbias i mb -- 2ma
cs4265 16 ds657a2 digital interface characteristics notes: 20. serial port signals include: mclk, sclk, lrck, sdin1, sdin2, txsdin, sdout. control port signals in clude: scl, sda, reset . 21. guaranteed by design. parameters (note 20) symbol min typ max units high-level input voltage serial port control port v ih v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il v il - - - - 0.2xvls 0.2xvlc v v high-level output voltage at i o =2 ma serial port control port mutec txout v oh v oh v oh v oh vls-1.0 vlc-1.0 va-1.0 vd-1.0 - - - - - - - - v v v v low-level output voltage at i o =2 ma serial port control port mutec txout v ol v ol v ol v ol - - - - - - - - 0.4 0.4 0.4 0.4 v v v v input leakage current i in --10 a input capacitance (note 21) - - 1 pf maximum mutec drive current - 3 - ma
cs4265 ds657a2 17 switching characteristics - serial audio port (logic ?0? = dgnd = 0 v; logic ?1? = vl, c l = 20 pf) (note 22) notes: 22. see figures 3 and 4 on page 18. parameter symbol min typ max unit sample rate single speed mode double speed mode quad speed mode fs fs fs 4 50 100 - - - 50 100 200 khz khz khz mclk specifications mclk frequency f mclk 1.024 - 51.200 mhz mclk input pulse width high/low t clkhl 8- -ns mclk output duty cycle 45 50 55 % master mode lrck duty cycle - 50 - % sclk duty cycle - 50 - % sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0 - 32 ns sdin valid to sclk rising setup time t sdis 16 - - ns sclk rising to sdin hold time t sdih 20 - - ns slave mode lrck duty cycle 40 50 60 % sclk period single speed mode double speed mode quad speed mode t sclkw t sclkw t sclkw - - - - - - ns ns ns sclk pulse width high t sclkh 30 - - ns sclk pulse width low t sclkl 48 - - ns sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo 0 - 32 ns sdin valid to sclk rising setup time t sdis 16 - - ns sclk rising to sdin hold time t sdih 20 - - ns 10 9 128 () fs -------------------- - 10 9 64 () fs ----------------- - 10 9 64 () fs ----------------- -
cs4265 18 ds657a2 sdis t slr t sdout sclk output lrck output sdin sdo t sdih t sdis t slr t sdout sclk input lrck input sdin sdo t sdih t sclkh t sclkl t sclkw t figure 3. master mode serial audio port timing figure 4. slave mode se rial audio port timing
cs4265 ds657a2 19 figure 5. format 0, left justified up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 channel a - left channel b - right figure 6. format 1, i2s up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 channel a - left channel b - right lrck sclk left channel sdata +5 +4 +3 +2 +1 ls b m sb -1 -2 -3 -4 -5 32 clocks right channel ls b +5 +4 +3 +2 +1 ls b m sb -1 -2 -3 -4 -5 +6 -6 +6 -6 channel a - left channel b - right figure 7. format 2, right justified 16-bit data. format 3, right justified 24-bit data.
cs4265 20 ds657a2 switching characteristics - i2c control port (inputs: logic 0 = dgnd, logic 1 = vlc, c l =30pf) notes: 23. data must be held for sufficient time to brid ge the transition time, t fc , of scl. 24. guaranteed by design. parameter symbol min max unit scl clock frequency f scl - 100 khz reset rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 23) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda (note 24) t rc -1s fall time scl and sda (note 24) t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t lo w t hdd t high t sud stop s tart sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 8. control po rt timing - i2c format
cs4265 ds657a2 21 3. typical connection diagram vls 10 f +3.3v to +5v 47 f vq filt+ 0.1 f 10 f 0.1 f 10 f 0.1 f +1.8v to +5v dgnd vlc 0.1 f +1.8v to +5v scl sda rst 2 k ? note 1 lrck sdin1 agnd digital audio processor micro- controller mclk sclk 0.1 f va vd * capacitors must be c0g or equivalent digital audio output 2.2nf afilta afiltb micin1 micin2 microphone input 1 microphone input 2 2.2nf sdin2 txout txsdin sdout cs4265 2 k ? 0.1 f 10 f micbias ** +3.3v to +5v sgnd signal ground mutec mute drive aouta aoutb 470 ? 470 ? 3.3 f c optional analog muting 3.3 f 10 k ? 10 k ? c r ext r ext see note 2 * * ain1a left analog input 1 10 f 10 f 1800 pf 1800 pf 100 k ? 100 k ? 100 ? 100 ? ain1b right analog input 1 * * 10 f 10 f 10 f note 1: resistors are required for i2c control port operation for best response to fs/2 : () 470 4 470 + = ext ext r fs r c this circuitry is intended for applications where the cs4265 connects directly to an unbalanced output of the design. for internal routing applications please see the dac analog output characteristics section for loading limitations. note 2 : r l r l note 3 note 3: the value of r l is dictated by the microphone carteridge. va 0.1 f agnd 47 k ? note 4: sets the lsb of the 7-bit chip address. see the i2c control port description and timing section. note 4 figure 9. typical connection diagram
cs4265 22 ds657a2 4. applications 4.1 recommended power-up sequence 1) hold reset low until the power supply, mclk, and lrck are stabl e. in this state, the control port is reset to its default settings. 2) bring reset high. the device will remain in a low power state with the pdn bit set by default. the control port will be accessible. 3) the desired register settings can be loaded while the pdn bit remains set. 4) clear the pdn bit to initiate the power-up sequence. 4.2 system clocking the cs4265 will operate at sa mpling frequencies from 4 khz to 200 khz. this range is divided into three speed modes as shown in table 1 below. 4.2.1 master clock mclk/lrck must maintain an integer ratio as shown in table 2. the lrck frequency is equal to fs, the frequency at which audio samples for each channel are clocked into or out of the device. the fm bits (see page 35) and the mclk freq bits (see page 36) configur e the device to generate the proper cl ocks in master mode and receive the proper clocks in slave mode. table 2 illustrates severa l standard audio sample rate s and the required mclk and lrck frequencies. mode sampling frequency single speed 4-50 khz double speed 50-100 khz quad speed 100-200 khz table 1. speed modes
cs4265 ds657a2 23 4.2.2 master mode as a clock master, lrck and sclk will operate as outputs. lrck and sclk are internally derived from mclk with lrck equal to fs and sclk equal to 64 x fs as shown in figure 10. 4.2.3 slave mode in slave mode, sclk and lrck operate as inputs. the left/right clock signal must be equal to the sample rate, fs, and must be synchronously derived fr om the supplied master clock, mclk. the serial bit clock, sclk, must be synchronously derived from the master clock, mclk, and be equal to 128x, 64x, 48x or 32x fs depending on the desired speed mode. refer to table 3 for required clock ratios. 4.3 high pass filter and dc offset calibration when using operational amplifiers in the input circuitry dr iving the cs4265, a small dc offset may be driven into the a/d converter. the cs4265 includes a high pass filter after the decimator to remove any dc offset which could result in recording a dc level, possibly yielding clicks when switching betwe en devices in a multichannel system. lrck (khz) mclk (mhz) 64x 96x 128x 192x 256x 384x 512x 768x 1024x 32 - --- 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 - --- 11.2896 16.9344 22.5792 33.8680 45.1584 48 - --- 12.2880 18.4320 24.5760 36.8640 49.1520 64 - - 8.1920 12.2880 16.3840 24.5760 32.7680 - - 88.2 - - 11.2896 16.9344 22.5792 33.8680 45.1584 - - 96 - - 12.2880 18.4320 24.5760 36.8640 49.1520 - - 128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - - 176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - - 192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - - mode qsm dsm ssm table 2. common clock frequencies single speed double speed quad speed sclk/lrck ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x table 3. slave mode serial bit clock ratios 256 128 64 4 2 1 00 01 10 00 01 10 lrc k sclk 000 001 010 1 1.5 2 011 100 3 4 mc lk fm bits mc lk f req bits figure 10. master mode clocking
cs4265 24 ds657a2 the high pass filter continuously subtract s a measure of the dc offset from the output of the decimation filter. if the hpffreeze bit (see page 35) is set during normal operation, the current value of the dc offset for the each channel is frozen and this dc of fset will continue to be subtract ed from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1) running the cs4265 with the high pass filter enabled unt il the filter settles. see the adc digital filter charac- teristics section for filter settling time. 2) disabling the high pass filter and freezing the stored dc offset. a system calibration performed in this way will eliminate offsets anywhere in th e signal path between the calibration point and the cs4265. 4.4 analog input multiplexer, pga, and mic gain the cs4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier (pga). the input multiplexer is able to select either a line-level input source, or a mic-level input source and route it to the pga. the mic-level input passes through a +32 db gain stage prior to the input multiplexer, allowi ng it to be used for microphone level signals without the need for any external gain. the pga stage provides 12 db of gain or atten- uation in 0.5 db steps. figure 11 shows the architecture of the input multiplexer, pga, and mic gain stages. the ?analog input selection (bit 0)? section on page 38 ou tlines the bit settings necessary to control the input mul- tiplexer and mic gain. ?channel a pga control - addres s 07h? on page 36 and ?channel b pga control - address 08h? on page 37 outlines the register settings necessary to co ntrol the pga. by default, th e line level input is select- ed by the input multiplexer, and the pga is set to 0 db. 4.5 input connections the analog modulator samples th e input at 6.144 mhz (mclk=12.288 mhz). th e digital filter will reject signals with- in the stopband of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,... refer to the typi cal connection diagram for the recommended analog input circuit that will attenuate nois e energy at 6.144 mhz . the use of capacitors which ha ve a large voltage coefficient (such as general purpose ceramics) must be avoided si nce these can degrade signal linearity. any unused analog input pairs should be left unconnected. 4.5.1 pseudo-differential input the cs4265 implements a pseudo-different ial input stage. the sgnd input is intended to be used as a pseudo- differential reference signal. this feature allows fo r common mode noise rejection with single-ended signals. figure 12 shows a basic diagram outlining the internal impl ementation of the pseudo-differential input stage. the typical connection diagram shows the recommended pseudo-d ifferential input topology. if pseudo-differential input pga mux +32 db aina micin1 channel b pga gain bits out to adc channel a out to adc channel b mux +32 db ainb micin2 pga analog input selection bits channel a pga gain bits figure 11. analog input architecture
cs4265 ds657a2 25 functionality is not required, simply connect the sgnd pi n to agnd through the parallel combination of a 10 f and a 0.1 f capacitor. 4.6 output connections the cs4265 dac?s implement a switched-capacitor filter follo wed by a continuous time low pass filter. its response, combined with that of the digital interp olator, is shown in the ?dac filter pl ots? section beginning on page 45. the recommended external analog circuitry is shown in the typical connection diagram. the cs4265 dac is a linear phase design and does not include phase or amplitude compensation for an external filter. therefore, the dac s ystem phase and amplitude resp onse will be dependent on th e external analog circuitry. 4.7 output transient control the cs4265 uses popguard ? technology to minimize the effects of output transients during power-up and power- down. this technique eliminates the audio transients commo nly produced by single-ended single-supply converters when it is implemented with external dc-blocking capacitors connected in se ries with the audio outputs. to make best use of this feature, it is ne cessary to understand its operation. 4.7.1 power-up when the device is initially power ed-up, the dac outputs aouta and aoutb are clamped to vq which is initially low. after the pdn bit is released (set to ?0?), the outputs begin to ramp with vq toward s the nominal quiescent volt- age. this ramp takes approximately 200 ms to complete. the gradual voltage ramping allows time for the external dc-blocking capacitors to ch arge to vq, effectively blocking the quiesc ent dc voltage. audi o output will begin after approximately 2000 sample periods. 4.7.2 power-down to prevent audio transients at power-down the dc-blocking capacitors must fully discha rge before tu rning off the power. in order to do this, either the pdn should be set or the device should be reset about 250 ms before removing power. during this time, the voltage on vq and the dac outputs will gradually discharge to gnd. if power is removed before this 250 ms time period has pass ed a transient will occur when the va su pply drops below th at of vq. there is no minimum time for a power cycle, power may be re-applied at any time. 4.7.3 serial interface clock changes when changing the clock ratio or sample rate it is recommended that zero data (or near zero data) be present on the selected sdin pin for at least 10 lrck samples before the change is made. during the clocking change the dac outputs will always be in a zero data state. if non-zero serial audio input is present at the time of switching, a slight click or pop may be heard as the dac outpu t automatically goes to it?s zero data state. + - va + - aina ainb sgnd in to pga in to pga 10 f 0.1 f note: if pseudo-differential input functionality is not required, the connections shown with dashed line should be added. figure 12. pseudo-differential input stage cs4265
cs4265 26 ds657a2 4.8 dac serial data input multiplexer the cs4265 contains a 2-to-1 serial data input multiplexe r. this allows two separate data sources to be input into the dac without the use of any external multiplexing components. the ?dac sdin source (bit 7)? section on page 36 describes the control port settings necessary to control the multiplexer. 4.9 de-emphasis filter the cs4265 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 khz. the filter response is shown in figure 13. the frequency resp onse of the de-emphasis curve will scale proportionally with changes in sam- ple rate, fs. please see sectio n 6.3.3 for de-emphasis control. the de-emphasis featur e is included to accommodate audi o recordings that utilize 50/15 s pre-emphasis equaliza- tion as a means of noise reduction. de-emphasis is only available in single speed mode. 4.10 internal digital loopback the cs4265 supports an internal digital loopback mode in which the output of the adc is routed to the input of the dac. this mode may be activated by setting the loop bi t in the signal selection register (06h - see page 36). when this bit is set, the status of the dac_dif[1:0] bits in register 03h will be disregarded by the cs4265. any changes made to the dac_dif[1:0] bits while the loop bit is set will have no impact on operat ion until the loop bit is cleared, at which time the digit al interface format of the dac will operat e according to the format selected by the dac_dif[1:0] bits. while the loop bit is set, data will be present on the sdout pin in the format selected by the adc_dif bit in register 04h. 4.11 mute control the mutec pin becomes active during power-up initialization, re set, muting, if the mclk to lrck ratio is incorrect, and during power-down. the mutec pin is intended to be used as control for an external mute circuit in order to add off-chip mute capability. use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 13. de-emphasis curve
cs4265 ds657a2 27 channel noise/signal-to-noise ratios which are only limited by the external mute circuit. the mutec pin is an active- low cmos driver. see figure 14 below for a suggested active-low mute circuit. 4.12 aes3 transmitter the cs4265 includes an iec60958-3 digital audio transm itter. a comprehensive buffering scheme provides write access to the channel status data. this buffering scheme is described in ?channel status buffer management? on page 50. the iec60958-3 transmitter encodes and transmits audio and digital data according to the iec60958-3 (s/pdif) interface standard. audio and control data are multiplexed together and bi-phase mark encoded. the resulting bit stream is driven to an output connector either directly or through a transformer. the transmitter is clocked from the clock input pin mclk. the channel status (c) bits in the transmitted data stream are taken from storage areas within the cs4265. the user can manually access the internal storage of the cs4265 to configure the transmitted channel status data. the sec- tion ?channel status buffer management? on page 50 de scribes the method of manually accessing the storage ar- eas. the cs4265 transmits all ?0?s in the user (u) data fields. 4.12.1 txout driver the line driver is a low skew, low impedance, single-ended output capable of driving cables directly. the driver is set to ground during reset (reset = low), when no transmit clock is prov ided, and optionally under the control of a register bit. the cs4265 also allows immediate muting of the iec60958-3 transmitter audio data through a control register bit. external components are used to term inate and isolate the external cable from the cs4265. these components are detailed in ?external iec60958-3 transmitter components? on page 49. 4.12.2 mono mode operation an iec60958-3 stream may be used in more than one way to transmit 192 khz sample rate data. one method is to double the frame rate of the current form at. this results is a stereo signal with a sample rate of 192 khz. an alternate method is implemented using the two sub-frames in a 96 khz frame rate iec60958-3 signal to carry consecutive samples of a mono signal, resulting in a 192 khz samp le rate stream. this allows older equipment, whose iec60958-3 transmitters and receivers are not rated for 192 khz frame rate operation, to handle 192 khz sample lpf +v ee -v ee 560 ? audio out 2 k ? 10 k ? -v ee +v a mmun2111lt1 aout mute c ac couple 47 k ? figure 14. suggested active-low mute circuit cs4265
cs4265 28 ds657a2 rate information. in this ?mono mode?, two cables ar e needed for stereo data transfer. the cs4265 offers mono mode operation. the cs4265 is set placed into and out of mono mode with the mmt control bit. in mono mode, the input port will run at the audio sample rate (fs), while t he iec60958-3 transmitter frame rate will be at fs/2. consecutive left or right channel serial aud io data samples may be selected for transmission on the a and b sub-frames, and the channel status block transmitted is also selectable. using mono mode is only necessary if the incoming audio sa mple rate is already at 192 khz and contains both left and right audio data words. the ?mono mode? iec60958-3 output stream may also be achieved by keeping the cs4265 in normal stereo mode, and placing consecutive audi o samples in the left and right positions in an incoming 96 khz word rate data stream. 4.13 i2c control port description and timing the control port is used to access the registers, allowi ng the cs4265 to be configured for the desired operational modes and formats. the operation of th e control port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference probl ems, the control port pins should remain static if no op- eration is required. sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl. a 47 k ? pull-up or pull- down on the sdout pin will set ad0, the least significant bi t of the chip address. a pull- up to vls will set ad0 to ?1? and a pull-down to dgnd will set ad0 to ?0?. the state of sdout is sensed and ad0 is set upon the release of reset. the signal timings for a read and write cycle are shown in figure 15 and figure 16. a st art condition is defined as a falling transition of sda while the clock is high. a stop cond ition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs4265 after a start condition consists of a 7 bit chip address field and a r/w bit (high for a read, low for a write). the upper 6 bits of the 7-bit address field are fixed at 100111. to communicate with a cs4265, the chip address field, which is the first byte sent to the cs4265, should match 100111 followed by the setting of ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the m ap will be output. setting the auto increment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an ac- knowledge bit. the ack bit is output from the cs4265 after each input byte is read, and is input to the cs4265 from the microcontroller after each transmitted byte. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 15. control port timing, i2c write
cs4265 ds657a2 29 since the read operation can not set the map, an aborted write operation is used as a preamble. as shown in figure 16, the write operation is aborted after the acknowledge for the map byte by sending a stop condition. the following pseudocode illustrates an aborted write operation fo llowed by a read operation. send start condition. send 100111x0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 100111x1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in the map allows successi ve reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 4.14 status reporting the cs4265 has comprehensive status re porting capabilities. many conditions ca n be reported in the status regis- ter, as listed in the status register descriptions. see ?status - address 0dh? on page 39. each source may be masked off through mask register bits. in addi tion, each source may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensit ive modes within the microcontroller, many different con- figurations are possible, depending on the needs of the equipment designer. 4.15 reset when reset is low, the cs4265 enters a low power mode and a ll internal states are rese t, including the control port and registers, and the ou tputs are muted. when reset is high, the control port becomes operational and the desired settings should be loaded into the control registers. writing a 0 to the pdn bit in the power control register will then cause the part to leave the low power state a nd begin operation. the delta-sigma modulators settle in a matter of microsec onds after the analog section is powered, either through the application of power or by setting the reset pin high. however, the voltage re ference will take much longer to reach a final value due to the presence of external capaci tance on the filt+ pin. during this voltage reference ramp delay, both sdout and dac outpu ts will be automatically muted. scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 1 ad0 0 sda 1 0 0 1 1 1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 16. control port timing, i2c read
cs4265 30 ds657a2 it is recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent powe r glitch rela ted issues. 4.16 synchronization of multiple devices in systems where multiple a dcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the master clocks and left/right cloc ks must be the same for all of the cs4265?s in the sys- tem. if only one master clock source is needed, one solution is to place one cs4265 in master mode, and slave all of the other cs4265?s to the one master. if multiple ma ster clock sources are needed, a possible solution would be to supply all clocks from the same external source and ti me the cs4265 reset with the inactive edge of master clock. this will ensure that all converters begin samplin g on the same clock edge. 4.17 grounding and powe r supply decoupling as with any high resolution converter, the cs4265 requires careful attention to power supply and grounding arrange- ments if its potential performance is to be realized. figure 9 shows the recommended power arrangements, with va connected to a clean supply. vd, which powers the digital filter, may be run from the system logic supply (vls or vlc) or may be powered from the analog supply (va) via a resistor. in this case, no additional devices should be powered from vd. power supply decoupling capacitors shoul d be as near to the cs4265 as possible, with the low value ceramic capacitor being the nearest. all signals, espe cially clocks, should be ke pt away from the filt+ and vq pins in order to avoid unwanted coupling into the mo dulators. the filt+ and vq decoupling capacitors, partic- ularly the 0.1 f, must be positioned to minimize the electrical path from filt+ and agnd. the cs4265 evaluation board demonstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the cs4265 digital outputs only to cmos inputs. 4.18 package considerations the cs4265 is available in the compact qfn package. the under side of the qfn package reveals a large metal pad that serves as a thermal relief to provide for maximu m heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of vias should be used to connect this copper pad to one or more larger ground pl anes on other pcb layers. in split ground systems, it is recommended that this thermal pad be connected to ag nd for best performance. the cs4265 evaluation board demonstrates the optimum ther mal pad and via configuration.
cs4265 ds657a2 31 5. register quick reference this table shows the register names and their associated default values. addr function 7 6 5 4 3 2 1 0 01h chip id part3 part2 part1 part0 rev3 rev2 rev1 rev0 110 1 0 0 0 1 02h power control freeze reserved reserved reserved pdn_mic pdn_adc pdn_dac pdn 000 0 0 0 0 1 03h dac control 1 reserved reserved dac_dif1 dac_dif0 reserved mutedac deemph reserved 000 0 1 0 0 0 04h adc control fm1 fm0 reserved adc_dif reserved muteadc hpffreeze m/s 000 0 0 0 0 0 05h mclk frequency reserved mclk freq2 mclk freq1 mclk freq0 reserved reserved reserved reserved 000 0 0 0 0 0 06h signal selec- tion sdinsel reserved reserved reserved reserved reserved loop reserved 010 0 0 0 0 0 07h pga ch b gain control reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 000 0 0 0 0 0 08h pga ch a gain control reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 000 0 0 0 0 0 09h analog input control reserved reserved reserved pgasoft pgazero reserved reserved select 000 1 1 0 0 1 0ah dac ch a vol- ume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 000 0 0 0 0 0 0bh dac ch b vol- ume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 000 0 0 0 0 0 0ch dac control 2 dacsoft daczero invertdac reserved reserved reserved reserved reserved 110 0 0 0 0 0 0dh status reserved reserved reserved eftc clkerr reserved adcovfl adcundrfl 000 0 0 0 0 0 0eh status mask reserved reserved reserved eftcm clkerrm reserved adcovflm adcundrflm 000 0 0 0 0 0 0fh status mode msb reserved reserved reserved eftc1 clkerr1 reserved adcovfl1 adcundrfl1 000 0 0 0 0 0 10h status mode lsb reserved reserved reserved eftc0 clkerr0 reserved adcovfl0 adcundrfl0 000 0 0 0 0 0
cs4265 32 ds657a2 11h transmitter control 1 reserved eftci cam reserved reserved reserved reserved reserved 000 0 0 0 0 0 12h transmitter control 2 tx_dif1 tx_dif0 txoff txmute v mmt mmtcs mmtlr 000 0 0 0 0 0 13h - 2ah c-data buffer --- - - - - - addr function 7 6 5 4 3 2 1 0
cs4265 ds657a2 33 6. register description 6.1 chip id - register 01h function: this register is read-only. bits 7 through 4 are the part number id which is 1101b (0dh) and the re- maining bits (3 through 0) are for the chip revision. 6.2 power control - address 02h 6.2.1 freeze (bit 7) function: this function allows modifications to be made to certain control port bits without the changes taking effect until the freeze bit is disa bled. to make multiple changes to these bits take effect simulta- neously, set the freeze bit, make all changes, then clear the freeze bit. the bits affected by the freeze function are listed in table 4 below. 6.2.2 power down mic (bit 3) function: the microphone preamplifier block will enter a low-power state whenev er this bit is set. 6.2.3 power down adc (bit 2) function: the adc pair will remain in a reset state whenever this bit is set. 6.2.4 power down dac (bit 1) function: the dac pair will remain in a reset state whenever this bit is set. 6.2.5 power down device (bit 0) function: b7 b6 b5 b4 b3 b2 b1 b0 part3 part2 part1 part0 rev3 rev2 rev1 rev0 76543210 freeze reserved reserved reserved pdn_mic pdn_adc pdn_dac pdn table 4. freeze-able bits name register bit(s) mutedac 03h 2 muteadc 04h 2 gain[5:0] 07h 5:0 gain[5:0] 08h 5:0 vol[7:0] 0ah 7:0 vol[7:0] 0bh 7:0 txmute 0eh 4
cs4265 34 ds657a2 the device will enter a low-po wer state whenever this bit is set. the power-down bit is set by default and must be cleared before normal operation can oc cur. the contents of the control registers are re- tained when the device is in power-down. 6.3 dac control - address 03h 6.3.1 dac digital inte rface format (bits 5:4) function: the required relationship between lrck, sclk and sdin for the dac is defined by the dac digital interface format and the options are detailed in table 5 and figures 5-7. 6.3.2 mute dac (bit 2) function: the dac outputs will mute an d the mutec pin will become active when this bit is se t. though this bit is active high, it should be noted that the mutec pin is acti ve low. the common mode voltage on the outputs will be retained when this bit is set. the muting function is effected, similar to attenuation changes, by the dacsoft and daczero bits in the dac control 2 register. 6.3.3 de-emphasis control (bit 1) function: the standard 50/15 s digital de-emphasis filter response, figure 17, may be implemented for a sam- ple rate of 44.1 khz when the deemph bit is conf igured as shown in table 6 below. note: de-em- phasis is available only in single-speed mode. 6.4 adc control - address 04h 76543210 reserved reserved dac_dif1 dac_dif0 reserved mutedac deemph reserved table 5. dac digital interface formats dac_dif1 dac_dif0 descri ption format figure 0 0 left justified, up to 24-bit data (default) 0 5 01 i 2 s, up to 24-bit data 16 1 0 right justified, 16-bit data 2 7 1 1 right justified, 24-bit data 3 7 table 6. de-emphasis control deemph description 0 disabled (default) 1 44.1 khz de-emphasis 76543210 fm1 fm0 reserved adc_dif reserved muteadc hpffreeze m/s
cs4265 ds657a2 35 6.4.1 functional mode (bits 7:6) function: selects the required range of sample rates. 6.4.2 adc digital inte rface format (bit 4) function: the required relationship between lrck, sclk and sdout is defined by the adc digital interface format bit. the options are detailed in table 8 and may be seen in figure 5 and 6. 6.4.3 mute adc (bit 2) function: when this bit is set, the serial audio output of the bo th adc channels will be muted. 6.4.4 adc high pass filter freeze (bit 1) function: when this bit is set, the inter nal high-pass filter will be disabled. the current dc offset value will be frozen and continue to be subtracted from the conv ersion result. see ?high pa ss filter and dc offset calibration? on page 23. table 7. functiona l mode selection fm1 fm0 mode 0 0 single-speed mode: 4 to 50 khz sample rates 0 1 double-speed mode: 50 to 100 khz sample rates 1 0 quad-speed mode: 100 to 200 khz sample rates 11reserved table 8. adc digital interface formats adc_dif descripti on format figure 0 left justified, up to 24-bit data (default) 0 5 1 i 2 s, up to 24-bit data 16 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 17. de-emphasis curve
cs4265 36 ds657a2 6.4.5 master / slave mode (bit 0) function: this bit selects either master or slave operation for the serial audio port. setting this bit will select mas- ter mode, while clearing this bit will select slave mode. 6.5 mclk frequency - address 05h 6.5.1 master clock dividers (bits 6:4) function: sets the frequency of the supplied mclk signal. see table 9 below for the appropriate settings. 6.6 signal selection - address 06h 6.6.1 dac sdin source (bit 7) function: this bit is used to select the serial audio data source for the dac as shown in table 10 below. 6.6.2 digital loopback (bit 1) function: when this bit is set, an internal digital loopback from the adc to th e dac will be enabled. please refer to ?internal digital loopback? on page 26. 6.7 channel a pga control - address 07h 76543210 reserved mclk freq2 mclk freq1 mclk freq0 reserved reserved reserved reserved table 9. mclk frequency mclk divider mclk freq2 mclk freq1 mclk freq0 1 000 1.5 001 2 010 3 011 4 100 reserved 101 reserved 11x 76543210 sdinsel reserved reserved reserved reserved reserved loop reserved table 10. dac sdin source selection sdinsel setting dac data source 0 sdin1 1 sdin2 76543210 reserved reserved gain5 gain4 gain3 gain2 gain1 gain0
cs4265 ds657a2 37 6.7.1 channel a pga gain (bits 5:0) function: see ?channel b pga gain (bits 5:0)? on page 37. 6.8 channel b pga control - address 08h 6.8.1 channel b pga gain (bits 5:0) function: sets the gain or attenuation for the adc input pg a stage. the gain may be adjusted from -12 db to +12 db in 0.5 db steps. the gain bits are in two?s complement with the gain0 bit set for a 0.5 db step. register settings outside of the 12 db range are reserved and must not be used. see table 11 for example settings. 6.9 adc input control - address 09h 6.9.1 pga soft ramp or zero cross enable (bits 4:3) function: soft ramp enable soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. see table 12 on page 38. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audi ble artifacts. the request ed level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero cros sing. the zero cross function is independently mon- itored and implemented for each channel. see table 12 on page 38. soft ramp and zero cross enable soft ramp and zero cross enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implem ented on a signal zero cr ossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enco unter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 12 on page 38. 76543210 reserved reserved gain5 gain4 gain3 gain2 gain1 gain0 table 11. example gain and attenuation settings gain[5:0] setting 101000 -12 db 000000 0 db 011000 +12 db 76543210 reserved reserved reserved pgasoft pgazero reserved reserved select
cs4265 38 ds657a2 6.9.2 analog input se lection (bit 0) function: these bits are used to select the input source for the pga and adc. please see table 13 below. 6.10 dac channel a volume control - address 0ah see 6.11 dac channel b volume control - address 0bh 6.11 dac channel b volume control - address 0bh 6.11.1 volume control (bits 7:0) function: the digital volume control allows the user to attenuate the signal in 0.5 db increments from 0 to -127 db. the vol0 bit activates a 0.5 db attenuation when set, and no attenuation when cleared. the vol[7:1] bits activate attenuation equal to their de cimal equivalent (in db). example volume settings are decoded as shown in table table 14. the volu me changes are implemented as dictated by the dacsoft and daczerocross bits in the dac control 2 register (see section 6.12.1). 6.12 dac control 2 - address 0ch table 12. pga soft cross or zero cross mode selection pgasoft pgazerocross mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled (default) table 13. analog input selection select pga/adc input 0 microphone level input 1 line level input 76543210 vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 table 14. digital volume control example settings binary code volume setting 00000000 0 db 00000001 -0.5 db 00101000 -20 db 00101001 -20.5 db 11111110 -127 db 11111111 -127.5 db 76543210 dacsoft daczero invertdac reserved reserved reserved reserved reserved
cs4265 ds657a2 39 6.12.1 dac soft ramp or ze ro cross enable (bits 7:6) function: soft ramp enable soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. see table 15 on page 39. zero cross enable zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audi ble artifacts. the request ed level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero cros sing. the zero cross function is independently mon- itored and implemented for each channel. see table 15 on page 39. soft ramp and zero cross enable soft ramp and zero cross enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implem ented on a signal zero cr ossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enco unter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 15 on page 39. 6.12.2 invert dac output (bit 5) function: when this bit is set, the out put of the dac will be inverted. 6.13 status - address 0dh for all bits in this register, a ?1? means the associated condition has occurred at least once since the register was last read. a ?0? means the associated condition has not occurr ed since the last reading of the register. status bits that are masked off in t he associated mask register will always be ?0? in this register. this register defaults to 00h. 6.13.1 e to f c-buffer transfer function: indicates the completion of an e to f c-buffer tran sfer. see ?channel status buffer management? on page 50 for more information. table 15. dac soft cross or zero cross mode selection dacsoft daczerocross mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled (default) 76543210 reserved reserved reserved eftc clkerr reserved adcovfl adcundrfl
cs4265 40 ds657a2 6.13.2 clock error (bit 3) function: indicates the occurrence of a clock error condition. 6.13.3 adc overflow (bit 1) function: indicates the occurrence of an adc overflow condition. 6.13.4 adc underflow (bit 0) function: indicates the occurrence of an adc underflow condition. 6.14 status mask - address 0eh function: the bits of this register serve as a mask for the st atus sources found in the register ?status - address 0dh? on page 39. if a mask bit is se t to 1, the error is unmasked, mean ing that its occu rrence will affect the status register. if a mask bit is set to 0, the error is masked, meaning th at its occurr ence will not affect the status register. the bit positions align with the corresponding bits in the status register. 6.15 status mode msb - address 0fh 6.16 status mode lsb - address 10h function: the two status mode registers form a 2-bit code fo r each status register function. there are three ways to update the status register in accordance wit h the status condition. in the rising edge active mode, the status bit becomes active on the arrival of the condition. in the falling edge active mode, the status bit becomes active on th e removal of the condition. in leve l active mode, the status bit is active during the condition. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 6.17 transmitter control 1 - address 11h 6.17.1 e to f c-data buffer transfer inhibit (bit 6) function: when cleared, c-data e to f buffer transfers are a llowed. when set, c-data e to f buffer transfers are inhibited. see ?iec60958-3 channel status (c) bit management? on page 50. 76543210 reserved reserved reserved eftcm clkerrm reserved adcovflm adcundrflm 76543210 reserved reserved reserved eftc1 clkerr1 reserved adcovfl1 adcundrfl1 reserved reserved reserved eftc0 clkerr0 reserved adcovfl0 adcundrfl0 76543210 reserved eftci cam reserved reserved reserved reserved reserved
cs4265 ds657a2 41 6.17.2 c-data access mode (bit 5) function: when cleared, the c-data buffer will operate in on e-byte control port ac cess mode. when set, the c- data buffer will op erate in two-byte control port access mode. see ?iec60 958-3 channel status (c) bit management? on page 50. 6.18 transmitter control 2 - address 12h 6.18.1 transmitter digital interface format (bits 7:6) function: the required relationship between lrck, sclk and sdin for the transmitter is defined by the trans- mitter digital interface format and the opti ons are detailed in table 16 and figures 5-7. 6.18.2 transmitter output driver control (bit 5) function: when this bit is cleared, the tr ansmitter output pin driver will be in the normal operat ional mode. when set, the transmitter output pin driver will drive to a constant 0 v. 6.18.3 transmitter mute control (bit 4) function: when this bit is cleare d, the transmitter data w ill be in the norma l operational mode. when set, the transmitter will output all zero data. 6.18.4 transmitted validity bit control (bit 3) function: this bit sets the transmitted validity bit level. when this bit is cleared, valid linear pcm audio data is indicated. when this bit is set, invalid or non- linear pcm audio data is indicated. 6.18.5 transmitter mono/stereo operation control (bit 2) function: when this bit is cleared, the transmitter will opera te in stereo mo de. when set, the transmitter will op- erate in mono mode with one input channel?s data output in both a and b subframes (see ?iec60958- 3 channel status (c) bit management? on page 50) and the cs data defined by the mmtcs bit (see section 6.18.6). 76543210 tx_dif1 tx_dif0 txoff txmute v mmt mmtcs mmtlr table 16. transmitter digital interface formats tx_dif1 tx_dif0 description format figure 0 0 left justified, up to 24-bit data (default) 0 5 01 i 2 s, up to 24-bit data 16 1 0 right justified, 16-bit data 2 7 1 1 right justified, 24-bit data 3 7
cs4265 42 ds657a2 6.18.6 mono mode cs data source (bit 1) function: when this bit is cleared, the transmitter will transmi t the channel a cs data in the a subframe and the channel b cs data in the b subframe. when this bit is set, th e transmitter will transmit the cs data defined for the channel selected by the mmtlr bit in both the a and b subframes. 6.18.7 mono mode channel selection (bit 0) function: when this bit is cleared, channel a input data will be transmitted in both channel a and b subframes in mono mode. when this bit is se t, channel b input data will be tran smitted in both channel a and b subframes in mono mode.
cs4265 ds657a2 43 7. parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise rati o measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting me asurement to refer the measurement to full-scale. this technique ensures that the di stortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including dist ortion components. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with no signal to the input under test and a fu ll-scale signal applied to th e other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
cs4265 44 ds657a2 8. package dimensions notes: 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated te rminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. 9. thermal characteristics and specifications notes: 3. ja is specified according to jedec sp ecifications for multi-layer pcbs. inches millimeters note dim min nom max min nom max a----0.0394----1.001 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2 d 0.1969 bsc 5.00 bsc 1 d2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1 e 0.1969 bsc 5.00 bsc 1 e2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1 e 0.0197 bsc 0.50 bsc 1 l 0.0118 0.0157 0.0197 0.30 0.40 0.50 1 jedec #: mo-220 controlling dimension is millimeters. parameters symbol min typ max units package thermal resistance (note 3) 32-qfn ja jc - - 38 52 - - c/watt c/watt allowable junction temperature - - 125 c side view a1 bottom view top view a pin #1 corner d e d2 l b e pin #1 corner e2 32l qfn (5 x 5 mm body ) package drawing
cs4265 ds657a2 45 appendix a: dac filter plots figure 18. dac single speed stopband rejection figure 19. dac single speed transition band figure 20. dac single speed transition band fi gure 21. dac single speed passband ripple figure 22. dac double speed stopband rejection figure 23. dac double speed transition band
cs4265 46 ds657a2 figure 24. dac double speed transition band figure 25. dac double speed passband ripple figure 26. dac quad speed stopband rejection figure 27. dac quad speed transition band 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 amplitude (db) frequency(normalized to fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 amplitude (db) frequency(normalized to fs) figure 28. dac quad speed transition band fi gure 29. dac quad speed passband ripple 0.4 0.45 0.5 0.55 0.6 0.65 0.7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 amplitude (db) frequency(normalized to fs)
cs4265 ds657a2 47 appendix b: adc filter plots figure 30. adc single speed stopband rejection f igure 31. adc single speed stopband rejection figure 32. adc single speed transition band (detail) figure 33. adc single speed passband ripple figure 34. adc double speed stopband rejection figure 35. adc double speed st opband rejection -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 0 .05 0 .1 0 .15 0.2 0 .25 0.3 0 .35 0.4 0 .45 0 .5 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db)
cs4265 48 ds657a2 figure 36. adc double speed transition band (de- tail) figure 37. adc double speed passband ripple figure 38. adc quad speed stopband rejection f igure 39. adc quad speed stopband rejection figure 40. adc quad spee d transition band (detail) figure 41. adc quad speed passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.46 0.47 0.48 0.49 0.50 0.51 0.52 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 frequency (normalized to fs) amplitude (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28 frequency (normalized to fs) amplitude (db)
cs4265 ds657a2 49 appendix c: external iec6 0958-3 transmitter components this section details the external components required to interface the iec60958-3 tran smitter to cables and fiber- optic components. c.1 iec60958-3 transmitte r external components the iec60958-3 specifications call for an unbalanc ed drive circuit with an output impedance of 75 ? 20% and a output drive level of 0.5 volts peak-t o-peak 20% when measured across a 75 ? load using no cable. the circuit shown in figure 42 provides the proper output impedance and drive level using st andard 1% resistors. if vd is driven from +3.3 v, use resistor values of 243 ? in place of the 374 ? resistor and a 107 ? resistor in place of the 90.9 ? resistor. the standard connector for a cons umer application is an rca phono socket. the txout pin may be used to drive ttl or cmos gates as shown in figure 43. this circuit may be used for optical connectors for digital audio as they typically implement tt l or cmos compatible inputs. this circuit is also useful when driving multiple digital audio outputs as rs422 line drivers typically implem ent ttl compatible inputs. c.2 isolating transformer requirements please refer to the application note an134: aes and spdif recomme nded transformers for resources on trans- former selection. 374-r txp 90.9 ? txout rca phono figure 42. consumer output circuit (vd = 5 v) cs4265 txout ttl or cmos gate figure 43. ttl/cmos output circuit cs4265
cs4265 50 ds657a2 appendix d: channel st atus buffer management the cs4265 has a comprehensive channel status (c) data buffering scheme wh ich allows the user to manage the c data through the control port. d.1 iec60958-3 channel sta tus (c) bit management the cs4265 contains sufficient ram to store a full block of c data for both a and b channels (192x2 = 384 bits). the user may read from or write to these ram buffers through the control port. the cs4265 manages the flow of channel status data at th e block level, meaning that ent ire blocks of channel status information are buffered at the input, synchronized to the output time base, and then transmitted. the buffering scheme involves a cascade of 2 block-si zed buffers, named e and f, as show n in figure 44. the msb of each byte represents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 13h) is the consumer/professional bit for channel status block a. the e buffer is accessible from the control port, allowing re ad and writing of the c data. the f buffer is used as the source of c data for the iec60958-3 transmitter. the f buffer accepts block trans fers from the e buffer. d.1.1 accessing the e buffer the user can monitor the data being transferred by reading the e buffer, which is mapped into the register space of the cs4265, through the control port. the user can modify the data to be transmitted by writing to the e buffer. the user can configure the status regist er such that eftc bit is set whenever an e to f transfer completes. with this configuration in place, periodic po lling of the status register allows determination of the time periods acceptable for e buffer interaction. also provided is an ?e to f? inhibit bit. the ?e to f? buff er transfer is disabled whenever the user sets this bit. this may be used whenever ?long? control port interactions are occurring. control port to aes3 transmitter e 24 words 8-bits 8-bits ab f transmit data buffer figure 44. channel status data buffer structure
cs4265 ds657a2 51 a flowchart for reading and writing to the e buffer is show n in figure 45. for writing, the sequence starts after an e to f transfer, which is base d on the output timebase. d.1.2 serial copy management system (scms) the cs4265 allows read/modif y/write access to all the channel status bits. for consumer mode scms compliance, the host microcontroller needs to manipulate th e category code, copy bit and l bit appropriately. d.1.3 channel status data e buffer access the e buffer is organized as 24 x 16-bit words. for each word the most sign ificant byte is the a channel data, and the least significant byte is the b channel data (see figure 44). there are two methods of accessing this memory, known as one byte mode and two byte mode. the desired mode is selected through a control register bit. d.1.3.1 one byte mode in many applications, the chan nel status blocks for the a and b channels will be identical. in this situation, if the user reads a byte from one of the channel' s blocks, the correspondin g byte for the other chan nel will be the same. simi- larly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. one byte mode takes advantage of the often iden tical nature of a and b channel status data. when reading data in one byte mode, a single byte is returned, which can be from channel a or b data, depending on a register control bit. if a write is being done, the cs4265 expects a single byte to be input to its control port. this byte will be written to both the a and b locations in the addressed word. one byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of infor- mation in 1 byte's worth of access time. if the control port's auto increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently. d.1.3.2 two byte mode there are those applications in which the a and b channel st atus blocks will not be the same, and the user is inter- ested in accessing both blocks. in these situations, tw o byte mode should be used to access the e buffer. in this mode, a read will cause the cs4265 to output two bytes from its cont rol port. the first by te out will represent the a channel status data, and the 2nd byte will represent the b channel status data. writin g is similar, in that two read the status register (reg 0dh) if set, clear e to f inhibit write e data optionally set e to f inhibit is the eftc bit set? configure the eftc status bit as rising edge active. begin yes no figure 45. flowchart for writing the e buffer
cs4265 52 ds657a2 bytes must now be input to the cs4265's control port. the a channel status data is first, b channel status data sec- ond.
cs4265 ds657a2 53 release date changes a1 may 2004 initial advance release. a2 september 2004 ? updated descriptions of pins 3, 4, 5, and 6 on page 5. ? removed specifications for spi control port. ? added specification for ad0 selection in the i2c control port description and timing section on page 28. ? updated the typical connection diagram on page 21 to reflect the pin changes and ad0 selection method. ? added thermal pad to pin descriptions on page 6. ? added package considerations section on page 30. ? updated the mic level input impedance specification on page 13. table 17. revision history contacting cirrus logic support for all product questions and inquiries co ntact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant informati on to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirru s for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of th ird parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives co nsent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgic ally implanted into the body, life support products or oth- er critical applications (including medi cal devices, aircraft systems or components and pers onal or automotive safety or security devices). inclusion of cirrus prod ucts in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the impl ied warranties of merchantabil- ity and fitness for particular purpose, wi th regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus pr oducts in critical applicatio ns, customer agre es, by such use, to fully indemnify cirrus, its o fficers, directors, employees, distributors and other agents from any and all liability, in- cluding attorne ys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and prod uct names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. purchase of i2c components of cirrus logic, inc., or one of its sublice nsed associated companies conveys a license under the philips i2c patent rights to use those components in a standard i2c system.

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