july 2003 the following document refers to spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this document as a result of offering the device as a spansion product. any changes that have been made are the result of normal documentation impr ovements and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. ve r s a t i l e i o : dq v io and enhanced v io application note publication number 27174 revision a amendment 0 issue date october 23, 2002
publication# 27174 rev: a amendment/ 0 issue date: october 23, 2002 versatile i/o: dq ? v i/o and enhanced ? v i/o application note this document describes the two types of versatile i/o provided by amd flash memory: dq-v i/o and en- hanced-v i/o . also described are the benefits of designing with amd?s versatile i/o flash memory in terms of reducing system complexity, and the limita- tions of each type of versatile i/o interface. what is versatile i/o (v i/o ) versatile i/o (v i/o ) is used on amd flash memory to provide support for i/o signaling that is outside the ?normal? operating range of a device. versatile i/o al- lows a 3.0v amd flash to be compatible with 2.5v or 1.8v devices without the need of expensive voltage translation buffers, as shown in figure 1. also, versa- tile i/o enables this without affecting the overall performance of the flash device. figure 1. i/o signaling to typical 3v flash versatile i/o devices can provide this internal voltage conversion because unlike traditional flash memory, where a single power supply (v cc ) is used to power both the memory array and i/o pins, v cc only powers the memory array while the v i/o pin(s) power the i/o pins. this allows a versatile i/o flash device to directly interface with a wide variety of fpgas, asics, micro- processors, microcontrollers, and other digital devices regardless of the device operating voltage. for exam- ple if a board is using a 3.0v amd flash, and a 1.8v microcontroller. a typical flash would have problems since the typical minimum legal high for a 3.0v device is 2.1v (3.0v * 0.7 = 2.1v), this is higher than the source voltage of the 1.8v microcontroller. with amd?s versatile i/o flash memory the v i/o pin(s) would be connected to the 1.8v source used by the microcontrol- ler, making the voltage levels for the inputs and outputs jedec 1.8v compliant. system performance the performance of the system shown in figure 1 is also greatly affected because of the need for transla- tion buffers. the buffers consume up to 100 ma of current each and data skew will occur any time a signal passes through the buffers. this data skew is due to vari- ations in the propagation delay between parts and also between the individual pins on a buffer. however, the skew between individual pins is typically much smaller than between individual buffer chips. the propagation delays through voltage translation buffers are highly variable, on the order of 2 ns to 7 ns, and discrepant on bi-directional buffers. in figure 1, microcontroller vcc = 1.8v address data control x8 x16 x24 typical 3v flash other 1.8v devices 32 16 8 figure #1 voltage translation buffers
versatile i/o: dq?v i/o and enhanced?v i/o there could be as much as a 5 ns delay between a con- trol or clock signal and the data and address signals. this delay may also occur between the upper and lower address and/or data lines. to put this in perspec- tive, if the flash used in figure 1 is a 66 mhz flash, it could not be safely used at speeds above 50 mhz due to the uncertainty in the translation buffers? propagation delay. dq ? versatile i/o (dq ? v i/o ) amd?s dq based versatile i/o (dq?v i/o ) follows an old standard for compatibility with intel flash devices and other legacy devices. this standard calls for the data pins (dqx) and chip enable (ce#) to be compatible with the versatile i/o voltage while all other pins (ad- dress, oe#, ry/by#, etc) still require signaling at v cc voltage levels. figure 2. i/o signaling to dq?v io 3v flash with v io = 1.8v therefore, as shown in figure 2, only the data lines and chip select signals from the microcontroller and flash can be connected together directly. the address lines, oe#, we#, reset#, ry/by#, byte#, etc. would have to pass through voltage translation buffers in order for the flash to receive legal high values and to prevent the microcontroller from being damaged by 3.0v signals from the flash. amd?s dq?versatile i/o may at first seem to be of lim- ited use since only one 16-bit voltage translator is saved but this small change can greatly increase sys- tem performance. amd?s dq?v i/o parts were designed on the assumption that most high-speed microproces- sors will assert the address and control lines before asserting the data lines. by removing the need for volt- age translation buffers on the data lines and assuming the address and control lines are asserted half a clock cycle before the data lines, the clock rate can be in- creased from 50 mhz to 66 mhz. enhanced ? versatile i/o (enhanced ? v i/o ) amd?s enhanced?versatile i/o is similar to the dq?v i/ o , but with the added benefit of having all input and out- put pins being compatible with the versatile i/o voltage and only the internal core memory and logic operating at the v cc voltage. microcontroller vcc = 1.8v address data control x7 x24 dq-v i/o 3v flash with v i/o = 1.8v voltage translation buffers other 1.8v devices 32 16 8 16 ce#
versatile i/o: dq?v i/o and enhanced?v i/o figure 3. i/o signaling to enhanced?v io 3v flash with v io = 1.8v as shown in figure 3, all the signals on the microcon- troller and flash can be directly connected together without the need of voltage translation buffers. without the need for translation buffers, data skew is no longer a significant problem even if the microcon- troller does not assert the address and control lines before the data lines. the chip count and power con- sumption the circuit in figure 3 has been reduced, from that of figure 1, and the board space required and lay- out complexity have been significantly reduced. voltage range limitations even though versatile i/o expands the voltage range of amd?s flash memories, the range is limited to (unless otherwise stated in the datasheet) the jedec standard voltage range given by the voltage on the v i/o pin(s). for example, if a 3.0v versatile i/o flash is used and 1.8v is being applied to the v i/o pin(s), applying 3.0v signals to the flash device?s i/o will damage the mem- ory. in order to use 3.0v signals, the voltage applied to the v i/o pin(s) must be supplied at 3.0v. this limitation does not prevent the user from using multiple voltage levels when communicating with the flash memory, it simply requires that the v i/o pin(s) be set to the appro- priate voltage. conclusion amd?s versatile i/o allows the designer to reduce cost, chip count, complexity and debug time on designs by eliminating the need for voltage translation buffers and the effects the buffers will have on signal integrity. in addition, designs can be upgraded from 3.0v systems to 2.5v or even 1.8v systems without the need to requalify a new flash device. microcontroller vcc = 1.8v address data control enhanced-v i/o 3v flash with v i/o = 1.8v other 1.8v devices 32 16 8 16 8 24
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