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w27e520 64k 8 electrically eras able eprom publication release date: september 2000 - 1 - revision a2 general description the w27e520 is a high speed, low power electrically erasable and programmable read only memory organized as 65,536 8 bits. it includes latches for the lower 8 address lines to multiplex with the 8 data lines. to cooperate with the mcu , this device could save the external ttl component, also cost and space. it requires only one supply in the range of 4.5v to 5.5v in normal read mode. the w27e520 provides an electrical chip erase function. it will be a great convenient when you need to c hange/update the contents in the device. features high speed access time: 70/90 ns (max.) read operating current: 20 ma (max.) erase/programming operating current 30 ma (max.) standby current: 100 m a (max.) unregulated battery power supply rang e, 4.5v to 5.5v +13v erase and programming voltage high reliability cmos technology - 2k v esd protection - 200 ma latchup immunity fully static operation all inputs and outputs directly ttl/cmos compatible three - state outputs available p ack ages: 20 - pin tssop and 20 - pin sop pin configurations 1 2 3 4 5 6 7 8 18 19 20 13 14 15 16 17 11 12 9 10 ad2 ad0 ad7 gnd ad6 ad4 ad1 ad3 ad5 a9 a11 a13 a15 oe/vpp ale a14 a12 v dd tssop top view a10 a8 18 19 20 1 2 3 4 5 6 7 8 13 14 15 17 11 12 9 10 ad5 ad0 a10 a8 ad1 ad3 ale a14 a12 gnd ad6 ad4 ad2 a11 a13 a15 sop top view a9 oe/vpp vdd ad7 16 block diagram ale oe / v control gnd v dd pp ad7 - ad0 output buffer decoder l a t c h e s a15 - a8 memory array pin description symbol description ad0 - ad7 address/data inputs/outputs a8 - a15 address inputs ale address latch enable oe /v pp outp ut enable, program/erase supply voltage v dd power supply gnd ground
w27e520 - 2 - functional descripti on read mode unlike conventional uveproms, which has ce and oe two control functions, the w27e520 has one oe /v pp and one ale (address_latch_enable) control functions. the ale makes lower address a[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be used to output data during read mode. i.e. lower address a[7:0] and data bus dq[7:0] are multiplexed. oe /v pp controls the output buffer to gate data to the output pins. when addresses are stable, the address access time (t acc ) is equal to the delay from ale to output (t ce ), and data are available at the outputs t oe after the falling edge of oe /v pp , if t acc and t ce timings are met. erase mod e the erase operation is the only way to change data from "0" to "1." unlike conventional uveproms, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the w27e520 uses electrical erasure. ge nerally, the chip can be erased within 100 ms by using an eprom writer with a special erase algorithm. there are two ways to enter erase mode. one is to raise oe /v pp to v pe (13v), v dd = v de (6.5v), a9 = v hh (13v), a10 = high a8&a11 = low, and all other addr ess pins include ad[7:0] keep at fixed low or high. pulsing ale high starts the erase operation. the other way is somewhat like flash, by programming two consecutive commands into the device and then enter erase mode. the two commands are loading data = aa (hex) to addr. = 5555(hex) and data = 10(hex) to addr. = 2aaa(hex). be careful to note that the ale pulse widths of these two commands are different: one is 50us, while the other is 100ms. please refer to the smart erase algorithm 1 & 2. erase verify mode the device will enter the erase verify mode automatically after erase mode. only power down the device can force the device enter normal read mode again. program mode programming is the only way to change cell data from "1" to "0." the program mode is ent ered when oe /v pp is raised to v pp (13v), v dd = v dp (6.5v), the address pins equal the desired addresses, and the input pins equal the desired inputs. pulsing ale high starts the programming operation. program verify mode the device will enter the program ve rify mode automatically after program mode. only power down the device can force the device enter normal read mode again. erase/program inhibit erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. when ale low, erasing or programming of non - target chips is inhibited, so that except for the ale and oe /v pp pins, the w27e520 may have common inputs. standby mode the standby mode significantly reduces v dd current. this mode is entered when ale and oe /v pp keep high. in standby mode, all outputs are in a high impedance state.
w27e520 publication release date: september 2000 - 3 - revision a2 system considerations an eprom's power switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby current levels (i s b ), active current levels (i dd ), and transient current peaks produced by the falling and rising edges of ale transient current magnitudes depend on the device output's capacitive and inductive loading. proper decoupling capacitor selection will suppress tr ansient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between its v dd and gnd. this high frequency, low inherent - inductance capacitor should be placed as close as possible to the device. additionally, for every eight devices, a 4.7 m f electrolytic capacitor should be placed at the array's power supply connection between v dd and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductances. table of operating m odes (v pp = 13v, v pe = 13v, v hh = 12v, v d p = 6.5v, v de = 6.5v, v dd = 5.0v, v di = 5.0v, x = v ih or v il ) mode pin ale oe /v pp other address v dd ad[7:0] address latch enable v ih v ih a in v dd a[7:0] read v il v il a in v dd d out output disable v il /v ih v ih x v dd high z standby v ih v ih x v dd a[7:0] program v ih v pp a in v dp d in erase 1 v ih v pe a8&a11 = v il , a9 = v pe , a10 = v ih , others = x v de x erase 2 v ih v pe first command: addr. = 5555 (hex) v de aa(hex) second command: addr. = 2aaa (hex) v de 10(hex) product identifier - manufacturer v il v i l a8 = v il , a9 = v hh , others = x v di da(hex) product identifier - device v il v il a8 = v ih , a9 = v hh , others = x v di 1f(hex)
w27e520 - 4 - dc characteristics absolute maximum ratings parameter rating unit ambient temperature with power applied - 55 to +125 c storage temperature - 65 to +150 c voltage on all pins with respect to ground except oe /v pp, a9 and v dd pins - 2.0 to +7.0 v voltage on oe /v pp pin with respect to ground - 2.0 to +7.0 v voltage on a9 pin with respect to ground - 2.0 to +7.0 v voltage v dd pin with r espect to ground - 2.0 to +14.0 v notes: 1. exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 2. minimum voltage is - 0.6v dc which may undershoot to - 2.0v for pulses of l ess than 20 ns. maximum output pin voltage is v dd +0.75v dc which may overshoot to +7.0v for pulses of less than 20 ns. dc erase characteristics (t a = 25 c 5 c, v dd = 6.5v 0.25v) parameter sym. conditions limits unit min. typ. max. input l oad current i li v in = v il or v ih - 10 - 10 m a v dd erase current i cp ale = v ih, oe /v pp = v pe a8 & a11 = v il , a9 = v pe , a10 = v ih , others = x - - 30 ma v pp erase current i pp ale = v ih, oe /v pp = v pe a8 & a11 = v il , a9 = v pe , a10 = v ih , others = x - - 30 ma in put low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.4 - v dd +0.3 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.45 v output high voltage (verify) v oh i oh = - 0.4 ma 2.4 - - - a9 sid voltage v hh v dd = 5v 10% 11.5 12 12.5 v a9 erase volt age v pe - 12.75 13 13.25 v v pp erase voltage v pe - 12.75 13 13.25 v v dd supply voltage (erase & erase verify) v de - 6.25 6.5 6.75 v note: v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27e520 publication release date: september 2000 - 5 - revision a2 capacitance (v dd = 4.5v t o 5.5v, t a = 25 c, f = 1 mhz) parameter symbol max. unit input capacitance c in v in = 0v 6 pf output capacitance c out v out = 0v 12 pf ac characteristics ac test conditions parameter conditions input pulse levels 0v/3v input rise and fall times 10 ns input and output timing reference level 1.5v/1.5v output load c l = 100 pf, i oh /i ol = - 0.4 ma/2.1 ma ac test load and waveforms +1.3v 3.3k ohm 100 pf (including jig and scope) d (in914) out 3v 0v 1.5v 1.5v test points test points input output
w27e520 - 6 - read operation dc ch aracteristics (v dd = 4.5v to 5.5v, t a = 0 to 70 c) parameter sym. conditions limits u nit min. typ. max. input load current i li v in = 0v to v dd - 5 - 5 m a output leakage current i lo v out = 0v to v dd - 5 - 5 m a standby v dd current (cmos input) i sb ale = v dd 0.3v, oe /v pp = v dd 0.3v all others inputs = gnd/ v dd 0.3v - - 100 m a v dd operating current i dd ale = v il , i out = 0 ma f = 5 mhz - - 20 ma input low voltage v il - - 0.6 - 0.8 v input high voltage v ih - 2.0 - v dd +0.3 v output low voltage v ol i ol = 2.1 ma - - 0.4 v output high voltage v oh i oh = - 0.4 ma 2.4 - - v read operati on ac characteristic s (v dd = 4.5v to 5.5v, t a = 0 to 70 c) parameter sym. w27e520 - 70 w27e520 - 90 unit min. max. min. max. address latch enable access time t ce - 70 - 90 ns address latch enable width t ale 45 - 45 - ns address access time t acc - 70 - 90 ns address setup time t as 15 - 15 - ns address hold time t ah 15 - 15 - ns output enable access time t oe - 35 - 35 ns oe /v pp high to high - z output t df - 25 - 25 ns output hold from address change t oh 0 - 0 - ns note: v dd must be applied simultaneo usly or before v pp and removed simultaneously or after v pp .
w27e520 publication release date: september 2000 - 7 - revision a2 dc programming chara cteristics (v dd = 6.5v 0.25v, t a = 25 c 5 c) parameter sym. conditions limits unit min. typ. max. input load current i li v in = v il or v ih - 10 - 10 m a v dd prog ram current i cp ale = v ih , oe /v pp = v pp - - 30 ma v pp program current i pp ale = v ih , oe /v pp = v pp - - 30 ma input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.4 - v dd +0.5 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.4 5 v output high voltage (verify) v oh i oh = - 0.4 ma 2.4 - - v a9 silicon i.d. voltage v hh v dd = 5v 10% 11.5 12.0 12.5 v v pp program voltage v pp - 12.75 13.0 13.25 v v dd supply voltage (program) v dp - 6.25 6.5 6.75 v ac programming/erase characteristic s (v dd = 6.5v 0.25v, t a = 25 c 5 c) parameter sym. limits unit min. typ. max. oe /v pp pulse rise time t prt 50 - - ns address latch enable width t ale 500 - - ns ale program pulse width t ppw 47.5 50 52.5 m s ale erase pulse width t epw 95 100 105 ms ale erase pulse width 1 t epw1 47.5 50 52.5 m s ale erase pulse width 2 t epw2 95 100 105 ms latched address setup time t las 100 - - ns latched address hold time t lah 100 - - ns address setup time t as 2.0 - - m s address hold time t ah 0 - - m s oe /v pp setup time t oes 2.0 - - m s oe /v pp hold time t oeh 2.0 - - m s data setup time t ds 2.0 - - m s data h old time t dh 2.0 - - m s data valid from oe /v pp low during erase verify t eoe - - 150 ns data valid from oe /v pp low during program verify t poe - - 150 ns oe /v pp high to output high z t dfp 0 - 130 ns oe /v pp high voltage delay after ale low t vs 2.0 - - m s oe /v pp r ecovery time t vr 2.0 - - m s note: v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27e520 - 8 - timing waveforms ac read waveform oe/vpp ad0-ad7 high z t oe t oh t df v ih v il a8-a15 ale address valid t ce v il v ih v ih v il address data t ale t acc t as t ah high z programming waveform ale ad[7:0] program program (verify) vr poe dfp a[15:8] address stable add data out t ale t t t 13v v ih il v v ih il v v ih il v v ih il v oe/vpp t oes oeh vs ale las lah ds ppw dh add data in rpt t t t t t t t t as t t ah t
w27e520 publication release date: september 2000 - 9 - revision a2 timing waveforms, continued erase waveform 1 oe/vpp 13.0v t prt v ih v il ale v ih v il address valid a[15:8] v ih v il a9 = 12.0v a9 = 13.0v others = v il or v a8 = v il ih a8 = v ih others = v il or v a8, a11 = v il ih a10 = v ih ad[7:0] da 1f d out v ih v il add t epw t vr t oes t oeh t eoe read company sid chip erase erase (verify) read device sid v = 6.5v dd v = 5.0v dd v = 6.5v dd erase waveform 2 oe/vpp t prt v ih v il v ih v il a[15:8] v ih v il a9=12.0 v others=v il or v a8=v il ih a8=v ih ad[7:0] v ih v il address valid t eoe read company sid command 1 command 2 read device sid oes oeh vs t rpt t t t t oes ale las lah ds epw1 dh 55 aa t t t t t as t t aa 10 erase verify chip erase epw2 t a[15:8] = 55 a[15:8] = 2a v =5.0v dd v =6.5v dd v =6.5v dd v =6.5v dd da 1f d out add note: first command address = 5555(hex) with data = aa(hex) second command address = 2aaa(hex) with data = 10(hex)
w27e520 - 10 - smart programming al gorithm 1 start address = first location oe/vpp = 13v program one 50 s pulse last address ? address = first location x = 0 verify byte program one 50 s pulse oe/vpp = v il compare all bytes to data original device passed pass yes increment address no increment address last address ? no pass yes increment x fail x = 25 ? no device yes fail failed m m power down v = 6.5v dd v = 5.0v dd
w27e520 publication release date: september 2000 - 11 - revision a2 smart programming al gorithm 2 start address = first location program one 50 s pulse compare all bytes to data original device passed pass increment address no increment x fail device failed m x = 0 x = 25? yes last address ? yes no pass fail fail pass oe/vpp = 13v oe/vpp = v il verify one byte oe/vpp = v il verify one byte power down v =5.0v dd v = 6.5v dd
w27e520 - 12 - smart erase algorith m 1 start oe/vpp = 13v last address? oe/vpp = v compare all bytes to ffs (hex) pass device increment address no fail fail fail device x = 0 a9 = 13v; a8&a11 = v a10 = v chip erase 100 ms pulse address = first location erase verify x = 20? no yes pass pass yes oe/vpp = v il il increment x il ih power down dd v = 6.5v v = 6.5v dd v = 5.0v dd
w27e520 publication release date: september 2000 - 13 - revision a2 smart erase algorith m 2 start oe/vpp = 13v last address? oe/vpp = v compare all bytes to ffs (hex) pass device increment address no fail fail fail device x = 0 program one 50 s pulse with address = 5555(hex) data = aa(hex) erase verify x = 20? no yes pass pass yes oe/vpp = v il il increment x power down program one 100 ms pulse with address = 2aaa(hex) data = 10(hex) m v = 6.5v dd v = 6.5v dd v = 5.0v dd
w27e520 - 14 - ordering information part no. access time ( n s) operating current max. ( m a) standby current max. ( m a) package w27e520w - 70* 70 20 100 173mil tssop w27e5 20w - 90* 90 20 100 173mil tssop w27e520s - 70* 70 20 100 300mil sop w27e520s - 90* 90 20 100 300mil sop notes: 1. the part no is preliminary and might be changed after project is consoled. 2. winbond reserves the right to make changes to its products without prior notice. 3. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w27e520 publication release date: september 2000 - 15 - revision a2 package dimensions 20 - pin tssop dimension in mm dimension in inches min. nom. max. symbol a b c q a e 0.002 0.09 0.043 0.006 0.18 0.256 bsc 1.10 0.15 l 0.50 0.70 0.028 0.020 e e 4.30 4.48 0.169 0.176 0.003 0.007 0.65 bsc 0.05 min. nom. max. e e b e d a a c l q 1 1 1 1 d 6.40 6.60 0.260 0.252 6.25 6.50 0.256 0.246 0.18 0.30 0.012 0.007 0 8 0 8 20 - pin sop dimension in mm dimension in inches min. nom. max. symbol a b c q a e 0.003 0.229 0.105 0.012 0.330 1.27 bsc 2.67 0.305 l 0.381 0.889 0.035 0.015 e e 7.39 7.60 0.291 0.299 0.009 0.013 0.50 bsc 0.076 min. nom. max. e e b e d a a c l q 1 1 1 1 d 12.6 13.0 0.513 0.497 9.98 10.7 0.420 0.393 0.330 0.508 0.020 0.013 0 8 0 8 0.092 2.34
w27e520 - 16 - version history version date page description a1 jun. 2000 - initial issued a2 sep. 2000 9 correct erase waveform 3 modify address latch enable mode: x - > ain; modify output disable mode: v il - > v il /v ih ; modi fy standby mode: ain - > x; typo correction 1 modify feature description: lvttl - > ttl headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5796096 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change withou t notice. headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5796096 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change withou t notice.

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