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isplsi 3320 in-system programmable high density pld 3320_06 1 features high-density programmable logic 160 i/o pins 14000 pld gates 480 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic high-performance e 2 cmos technology f max = 100 mhz maximum operating frequency t pd = 10 ns propagation delay ttl compatible inputs and outputs electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power isplsi features: ?5v in-system programmable (isp) using lattice isp or boundary scan test (ieee 1149.1) protocol ?increased manufacturing yields, reduced time-to- market, and improved product quality ?reprogram soldered devices for faster debugging 100% ieee 1149.1 boundary scan compatible offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays complete programmable device can combine glue logic and structured designs enhanced pin locking capability five dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control to minimize switching noise flexible pin placement optimized global routing pool provides global interconnectivity pin compatible with isplsi 3160 ispdesignexpert ?logic compiler and com- plete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms functional block diagram output routing pool (orp) global routing pool (grp) boundary scan output routing pool (orp) output routing pool (orp) g3 g2 g1 g0 a0 a1 a2 a3 f3 f2 f1 f0 output routing pool (orp) b0 b1 b2 b3 output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) c0 c1 c2 c3 j3 j2 j1 j0 i3 i2 i1 i0 h3 h2 h1 h0 d0 d1 d2 d3 e0 e1 e2 e3 output routing pool (orp) 0139/3320 or array dq dq dq dq twin glb or array dq dq dq dq and array description the isplsi 3320 is a high-density programmable logic device containing 480 registers, 160 universal i/o pins, five dedicated clock input pins, ten output routing pools (orp) and a global routing pool (grp) which allows complete inter-connectivity between all of these elements. the isplsi 3320 features 5v in-system pro- grammability and in-system diagnostic capabilities. the isplsi 3320 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. the basic unit of logic on the isplsi 3320 device is the twin generic logic block (twin glb) labelled a0, a1...j3. there are a total of 40 of these twin glbs in the isplsi 3320 device. each twin glb has 24 inputs, a program- mable and array and two or/exclusive-or arrays, and eight outputs which can be configured to be either com- binatorial or registered. all twin glb inputs come from the grp. copyright ?1999 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. may 1999 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com
specifications isplsi 3320 2 functional block diagram figure 1. isplsi 3320 functional block diagram global routing pool (grp) g3 g2 g1 g0 boundary scan i/o 111 i/o 110 i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 i/o 103 i/o 102 i/o 101 i/o 100 i/o 99 i/o 98 i/o 97 i/o 96 i/o 127 i/o 126 i/o 125 i/o 124 i/o 123 i/o 122 i/o 121 i/o 120 i/o 119 i/o 118 i/o 117 i/o 116 i/o 115 i/o 114 i/o 113 i/o 112 output routing pool (orp) h3 h2 h1 h0 output routing pool (orp) input bus f3 f2 f1 f0 i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 output routing pool (orp) input bus output routing pool (orp) i3 i2 i1 i0 i/o 143 i/o 142 i/o 141 i/o 140 i/o 139 i/o 138 i/o 137 i/o 136 i/o 135 i/o 134 i/o 133 i/o 132 i/o 131 i/o 130 i/o 129 i/o 128 input bus input bus goe0 goe1 toe reset i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 a0 a1 a2 a3 output routing pool (orp) input bus i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 b0 b1 b2 b3 output routing pool (orp) input bus bscan/ ispen tdi/sdi tck/sclk tms/mode trst tdo/sdo clk 1 clk 0 clk 2 ioclk 1 ioclk 0 y0 y1 y2 y3 y4 i/o 64 i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 71 i/o 72 i/o 73 i/o 74 i/o 75 i/o 76 i/o 77 i/o 78 i/o 79 output routing pool (orp) e0 e1 e2 e3 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 output routing pool (orp) d0 d1 d2 d3 input bus input bus i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 output routing pool (orp) c0 c1 c2 c3 input bus output routing pool (orp) j3 j2 j1 j0 i/o 159 i/o 158 i/o 157 i/o 156 i/o 155 i/o 154 i/o 153 i/o 152 i/o 151 i/o 150 i/o 149 i/o 148 i/o 147 i/o 146 i/o 145 i/o 144 input bus 0139/3320
specifications isplsi 3320 3 all local logic block outputs are brought back into the grp so they can be connected to the inputs of any other logic block on the device. the device also has 160 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. the 160 i/o cells are grouped into ten sets of 16 bits. each of these i/o groups is associated with a logic megablock through the use of the orp. each megablock is able to provide one product term output enable (ptoe) signal which is globally distributed to all i/o cells. that ptoe signal can be generated within any glb in the megablock. each i/o cell can select one of 12 available oes (two global oes and ten ptoes). four twin glbs, 16 i/o cells and one orp are con- nected together to make a logic megablock. the megablock is defined by the resources that it shares. the outputs of the four twin glbs are connected to a set of 16 i/o cells by the orp. the isplsi 3320 device contains ten of these megablocks. the grp has as its inputs the outputs from all of the twin glbs and all of the inputs from the bidirectional i/o cells. all of these signals are made available to the inputs of the twin glbs. delays through the grp have been equal- ized to minimize timing skew and logic glitching. clocks in the isplsi 3320 device are provided through five dedicated clock pins. the five pins provide three clocks to the twin glbs and two clocks to the i/o cells. the table below lists key attributes of the device along with the number of resources available. an additional feature of the isplsi 3320 is the boundary scan capability, which is composed of cells connected between the on-chip system logic and the device? input and output pins. all i/o pins have associated boundary scan registers, with 3-state i/o using three boundary scan registers and inputs using one. the isplsi 3320 supports all ieee 1149.1 mandatory instructions, which include bypass, extest and sample. key attributes of the isplsi 3320 attribute twin glbs registers i/o pins global clocks global oe test oe quantity 40 480 160 5 2 1 table 1-0003/3320 description (continued)
specifications isplsi 3320 4 absolute maximum ratings 1 supply voltage v cc ................................................................................ -0.5 to +7.0v input voltage applied ..................................................................... -2.5 to v cc +1.0v off-state output voltage applied .................................................. -2.5 to v cc +1.0v storage temperature ............................................................................. -65 to 150 c case temp. with power applied ........................................................... -55 to 125 c max. junction temp. (t j ) with power applied (208-pin pqfp and mqfp) .... 150 c max. junction temp. (t j ) with power applied (320-ball bga) ........................ 140 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition capacitance (t a =25 c,f=1.0 mhz) data retention specifications table 2-0008/3320 parameter data retention minimum maximum units isplsi erase/reprogram cycles 20 10000 years cycles symbol table 2-0006/3320 c parameter clock capacitance 11 units typical test conditions 2 pf v = 5.0v, v = 2.0v cc y c i/o capacitance 10 1 pf v = 5.0v, v = 2.0v cc i/o symbol table 2-0005/3320 v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 2.0 0 5.25 v +1 0.8 v v v cc t a ambient temperature 0 70 c
specifications isplsi 3320 5 switching test conditions input pulse levels table 2-0003/3320 input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. 3 ns 10% to 90% output load conditions (see figure 2) test condition r1 r2 cl a 470 ? 390 ? 35pf b 390 ? 35pf 470 ? 390 ? 35pf active high active low c 470 ? 390 ? 5pf 390 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a figure 2. test load dc electrical characteristics over recommended operating conditions v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using twenty 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/3320 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.0v, v = 3.0v, f = 1 mhz ol oh in il in cc in il in il cc out clock il ih condition min. typ. max. units 3 2.4 370 0.4 10 -10 -150 -150 -200 v v a a a a ma ma cc a out cc cc
specifications isplsi 3320 6 external switching characteristics 1, 2, 3 over recommended operating conditions t pd1 units -100 min. test cond. 1. unless noted otherwise, all parameters use 20 ptxor path and orp. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. f max (toggle) may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. 5. reference switching test conditions section. table 2-0030/3320 1 5 3 1 tsu2 + tco1 ( ) -70 min. max. max. description # 2 parameter a 1 data propagation delay, 4pt bypass, orp bypass 10.0 15.0 ns t pd2 a 2 data propagation delay ns f max a 3 clock frequency with internal feedback 100 70.0 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, maximum toggle mhz t su1 6 glb reg. setup time before clock, 4 pt bypass ns 4 t co1 a 7 glb reg. clock to output delay, orp bypass 6.0 ns t h1 8 glb reg. hold time after clock, 4 pt bypass ns t su2 9 glb reg. setup time before clock ns t co2 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock ns t r1 a 12 ext. reset pin to output delay ns t rw1 13 ext. reset pulse duration ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t goeen b 16 global oe output enable ns t goedis c 17 global oe output disable ns t toeen b 18 test oe output enable ns t toedis c 19 test oe output disable ns t wh 20 ext. synchronous clock pulse duration, high 5.0 ns t wl 21 ext. synchronous clock pulse duration, low 5.0 ns t su3 22 i/o reg setup time before ext. synchronous clock (y3, y4) 4.5 ns t h3 23 i/o reg hold time after ext. sync clock (y3, y4) 0.0 ns 77.0 100 6.0 0.0 7.0 0.0 6.5 13.0 7.0 13.5 18.0 18.0 9.0 9.0 12.0 12.0 50.0 83.0 9.0 0.0 11.0 0.0 12.0 6.0 6.0 5.0 0.0 18.0 9.0 10.0 15.0 21.0 21.0 12.0 12.0 15.0 15.0
specifications isplsi 3320 7 internal timing parameters 1 over recommended operating conditions t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036/3320 inputs units -100 min. -70 min. max. max. description # 2 parameter 24 i/o register bypass 3.2 ns t iolat 25 i/o latch delay 18.2 ns t iosu 26 i/o register setup time before clock 9.0 ns t ioh 27 i/o register hold time after clock -4.0 ns grp t ioco 28 i/o register clock to out delay 4.2 ns t ior 29 i/o register reset to out delay 4.2 ns t grp 30 grp delay 3.5 ns glb t 4ptbp 32 4 product term bypass path delay (comb.) 5.3 ns t 1ptxor 34 1 product term/xor path delay 5.8 ns t 20ptxor 35 20 product term/xor path delay 5.8 ns t xoradj 36 xor adjacent path delay 7.3 ns t gbp 37 glb register bypass delay 0.5 ns t gsu 38 glb register setup time before clock 2.5 ns t gh 39 glb register hold time after clock 6.3 ns t gco 40 glb register clock to output delay 1.0 ns 3 t gro 41 glb register reset to output delay 1.0 ns t ptre 42 glb product term reset to register delay 11.5 ns t ptoe 43 glb product term output enable to i/o cell delay 9.3 ns t ptck 44 glb product term clock delay 4.5 4.5 ns orp t orp 45 orp delay 2.0 ns t orpbp 46 orp bypass delay 0.0 ns 7.5 -3.0 1.0 4.9 1.5 13.0 2.5 2.5 3.0 t feedback 31 feedback delay 1.6 ns 1.1 3.5 4.5 4.5 5.5 0.5 0.5 1.0 7.9 9.5 3.2 3.2 1.5 0.0 t 4ptbr 33 4 product term bypass path delay (reg.) 3.8 ns 3.5
specifications isplsi 3320 8 internal timing parameters 1 over recommended operating conditions t ob 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. table 2-0037/3320 outputs units -100 min. -70 min. max. max. description # 2 parameter 47 output buffer delay 3.0 ns t oen 49 i/o cell oe to output enabled 5.0 ns t odis 50 i/o cell oe to output disabled 5.0 ns t gy0/1/2 51 clock delay, y0 or y1 or y2 to global glb clock line 4.0 4.0 ns t ioy3/4 52 clock delay, y3 or y4 to i/o cell global clock line 4.0 4.0 ns global reset t gr 53 global reset to glb and i/o registers 9.0 ns clocks 2.0 4.0 4.0 t obs 48 output buffer delay, slew limited adder 13.0 ns 12.0 3.0 3.0 3.0 3.0 9.0 t goe 54 global oe pad buffer 7.0 ns t toe 55 test oe pad buffer 10.0 ns 5.0 8.0
specifications isplsi 3320 9 isplsi 3320 timing model derivations of t su, t h and t co from the product term clock 1 = = = = t su logic + reg su - clock (min) ( t iobp + t grp + t 20ptxor) + ( t gsu) - ( t iobp + t grp + t ptck(min)) (#24+ #30+ #35) + (#38) - (#24+ #30+ #44) (1.5 + 3.0 + 4.5) + (1.0) - (1.5 + 3.0 + 3.2) = = = = t h clock (max) + reg h - logic ( t iobp + t grp + t ptck(max)) + ( t gh) - ( t iobp + t grp + t 20ptxor) (#24+ #30+ #44) + (#39) - (#24+ #30+ #35) (1.5 + 3.0 + 3.2) + (4.9) - (1.5 + 3.0 + 4.5) = = = = t co clock (max) + reg co + output ( t iobp + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#24 + #30 + #44) + (#40) + (#45 + #47) (1.5 + 3.0 + 3.2) + (0.5) + (1.5 + 2.0) table 2-0042/3320 2.3 ns 3.6 ns 11.7 ns glb reg delay i/o pin (output) orp delay feedback 4 pt bypass 20 pt xor delays control pts input register i/o pin (input) y0,1,2 y3,4 d q grp glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #25 - 29 #30 #33 #32 #31 #34 - 36 #42 - 44 #51 #54 #55 #45 #46 reset #24 #52 rst #53 #53 #37 #38 - 41 #49, 50 #47, 48 goe0,1 toe 0902/3320 note: calculations are based on timing specs for the isplsi 3320-100l.
specifications isplsi 3320 10 power consumption 0127a/3320 i cc can be estimated for the isplsi 3320 using the following equation: i cc = 60 + (# of pts * 0.5) + (# of nets * max. freq * 0.0095) where: # of pts = number of product terms used in design # of nets = number of signals used in device max. freq = highest clock frequency to the device the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of 2 glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 200 300 400 500 600 700 800 0 25 50 75 100 f max (mhz) i cc (ma) notes: configuration of 20 16-bit counters typical current at 5v, 25 c isplsi 3320 power consumption in the isplsi 3320 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3. typical device power consumption vs fmax figure 3 shows the relationship between power and operating speed.
specifications isplsi 3320 11 signal descriptions goe0, goe1 global output enable input pins. i/o input/output pins these are the general purpose i/o pins used by the logic array. toe test output enable pin this pin tristates all i/o pins when a logic low is driven. reset active low (0) reset pin which resets all of the glb and i/o registers in the device. y0, y1, y2 dedicated clock inputs. these clock inputs are connected to one of the clock inputs of all the glbs on the device. y3, y4 dedicated clock inputs. these clock inputs are connected to one of the clock inputs of all the i/o cells on the device. bscan/ ispen input dedicated in-system programming enable input pin. when this pin is high, the bscan tap controller pins tms, tdi, tdo and tck are enabled. when this pin is brought low, the isp state machine control pins mode, sdi, sdo and sclk are enabled. high-to-low transition of this pin will put the device in the programming mode and put all i/o pins in the high-z state. tdi/sdi input this pin performs two functions. it is the test data input pin when ispen is logic high. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi is also used as one of the two control pins for the isp state machine. tck/sclk input this pin performs two functions. it is the test clock input pin when ispen is logic high. when ispen is logic low, it functions as a clock pin for the serial shift register. tms/mode input this pin performs two functions. it is the test mode select input pin when ispen is logic high. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. trst input test reset, active low to reset the boundary scan state machine. tdo/sdo output this pin performs two functions. when ispen is logic low, it functions as the pin to read the isp data. when ispen is high, it functions as test data out. gnd ground (gnd) vcc vcc nc 1 no connect. signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 3320 12 signal locations goe0, goe1 133, 134 ad12, ac11 toe 30 b14 reset 28 d13 y0, y1, y2, y3, y4 132, 130, 129, 128, 127 aa12, ac13, ab13, aa13, ad13 bscan/ ispen 27 b12 tdi/sdi 25 c12 tck/sclk 24 d12 tms/mode 23 a12 trst 29 a13 tdo/sdo 185 m4 gnd 11, 26, 42, 53, 65, 78, 92, 104, 115, a16, b13, c8, d6, d19, f4, f21, h22, j1, m2, n23, t24, u3, 131, 146, 157, 169, 183, 196, 208 w4, w21, aa6, aa19, ab17, ac12, ad9 vcc 14, 39, 58, 80, 99, 118, 143, 162, 181, b10, b18, c3, d4, d21, g2, k23, r2, v23, aa4, aa21,ac7, 203 ac15 nc 1 76, 77, 79, 81, 180, 182, 184 a1, a2, a3, a6, a9, a11, a14, a20, a23, a24, b1, b2, b5, b8, b9, b16, b17, b20, b23, b24, c5, c13, c17, c20, c24, d7, d11, d14, d17, d20, e1, e2, e3, e4, e22, e23, f24, g21, g23, h2, h3, h4, h23, j2, j23, j24, k3, l1, l4, l21, l24, m3, m21, m22, m23, n2, n3, n4, n21, n22, n24, p1, p4, p21, p24, r22, t1, t2, t23, u2, u21, u22, u23, v2, v4, w1, y2, y3, y21, y22, y23, y24, aa5, aa8, aa11, aa14, aa18, ab1, ab5, ab8, ab12, ab20, ac1, ac2, ac5, ac8, ac9, ac16, ac17, ac20, ac23, ac24, ad1, ad2, ad5, ad11, ad14, ad16, ad19, ad22, ad23, ad24 signal 208-pin pqfp/mqfp 320-ball bga 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 3320 13 i/o locations i/o 0 31 c14 i/o 1 32 a15 i/o 2 33 b15 i/o 3 34 c15 i/o 4 35 d15 i/o 5 36 a17 i/o 6 37 c16 i/o 7 38 d16 i/o 8 40 a18 i/o 9 41 a19 i/o 10 43 c18 i/o 11 44 b19 i/o 12 45 d18 i/o 13 46 c19 i/o 14 47 a21 i/o 15 48 b21 i/o 16 49 a22 i/o 17 50 c21 i/o 18 51 b22 i/o 19 52 c22 i/o 20 54 c23 i/o 21 55 d22 i/o 22 56 e21 i/o 23 57 d23 i/o 24 59 d24 i/o 25 60 f22 i/o 26 61 e24 i/o 27 62 f23 i/o 28 63 g22 i/o 29 64 h21 i/o 30 66 g24 i/o 31 67 j21 i/o 32 68 j22 i/o 33 69 h24 i/o 34 70 k21 i/o 35 71 k22 i/o 36 72 k24 i/o 37 73 l22 i/o 38 74 l23 i/o 39 75 m24 i/o 40 82 p23 i/o 41 83 p22 i/o 42 84 r24 i/o 43 85 r23 i/o 44 86 r21 i/o 45 87 u24 i/o 46 88 t22 i/o 47 89 t21 i/o 48 90 v24 i/o 49 91 w24 i/o 50 93 v22 i/o 51 94 w23 i/o 52 95 v21 i/o 53 96 w22 i/o 54 97 aa24 i/o 55 98 aa23 i/o 56 100 ab24 i/o 57 101 aa22 i/o 58 102 ab23 i/o 59 103 ab22 i/o 60 105 ac22 i/o 61 106 ab21 i/o 62 107 aa20 i/o 63 108 ac21 i/o 64 109 ad21 i/o 65 110 ab19 i/o 66 111 ad20 i/o 67 112 ac19 i/o 68 113 ab18 i/o 69 114 aa17 i/o 70 116 ac18 i/o 71 117 ad18 i/o 72 119 aa16 i/o 73 120 ab16 i/o 74 121 ad17 i/o 75 122 aa15 i/o 76 123 ab15 i/o 77 124 ad15 i/o 78 125 ab14 i/o 79 126 ac14 i/o 80 135 ab11 i/o 81 136 ad10 i/o 82 137 ac10 i/o 83 138 ab10 i/o 84 139 aa10 i/o 85 140 ad8 i/o 86 141 ab9 i/o 87 142 aa9 i/o 88 144 ad7 i/o 89 145 ad6 i/o 90 147 ab7 i/o 91 148 ac6 i/o 92 149 aa7 i/o 93 150 ab6 i/o 94 151 ad4 i/o 95 152 ac4 i/o 96 153 ad3 i/o 97 154 ab4 i/o 98 155 ac3 i/o 99 156 ab3 i/o 100 158 ab2 i/o 101 159 aa3 i/o 102 160 y4 i/o 103 161 aa2 i/o 104 163 aa1 i/o 105 164 w3 i/o 106 165 y1 i/o 107 166 w2 i/o 108 167 v3 i/o 109 168 u4 i/o 110 170 v1 i/o 111 171 t4 i/o 112 172 t3 i/o 113 173 u1 i/o 114 174 r4 i/o 115 175 r3 i/o 116 176 r1 i/o 117 177 p3 i/o 118 178 p2 i/o 119 179 n1 i/o 120 186 m1 i/o 121 187 l2 i/o 122 188 l3 i/o 123 189 k1 i/o 124 190 k2 i/o 125 191 k4 i/o 126 192 h1 i/o 127 193 j3 i/o 128 194 j4 i/o 129 195 g1 i/o 130 197 f1 i/o 131 198 g3 i/o 132 199 f2 i/o 133 200 g4 i/o 134 201 f3 i/o 135 202 d1 i/o 136 204 d2 i/o 137 205 c1 i/o 138 206 d3 i/o 139 207 c2 i/o 140 1 b3 i/o 141 2 c4 i/o 142 3 d5 i/o 143 4 b4 i/o 144 5 a4 i/o 145 6 c6 i/o 146 7 a5 i/o 147 8 b6 i/o 148 9 c7 i/o 149 10 d8 i/o 150 12 b7 i/o 151 13 a7 i/o 152 15 d9 i/o 153 16 c9 i/o 154 17 a8 i/o 155 18 d10 i/o 156 19 c10 i/o 157 20 a10 i/o 158 21 c11 i/o 159 22 b11 pqfp/ signal mqfp bga pqfp/ signal mqfp bga pqfp/ signal mqfp bga pqfp/ signal mqfp bga
specifications isplsi 3320 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 i/o 140 i/o 141 i/o 142 i/o 143 i/o 144 i/o 145 i/o 146 i/o 147 i/o 148 i/o 149 gnd i/o 150 i/o 151 vcc i/o 152 i/o 153 i/o 154 i/o 155 i/o 156 i/o 157 i/o 158 i/o 159 tms/mode tck/sclk tdi/sdi gnd bscan/ ispen reset 1 trst /nc toe i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 vcc i/o 8 i/o 9 gnd i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 gnd i/o 20 i/o 21 i/o 22 i/o 23 vcc i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 gnd i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 1 nc 1 nc gnd 1 nc vcc 1 nc i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 gnd i/o 50 i/o 51 i/o 52 i/o 53 i/o 54 i/o 55 vcc i/o 56 i/o 57 i/o 58 i/o 59 gnd i/o 99 i/o 98 i/o 97 i/o 96 i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 i/o 90 gnd i/o 89 i/o 88 vcc i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 goe1 goe0 y0 gnd y1 y2 y3 y4 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 vcc i/o 71 i/o 70 gnd i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 139 i/o 138 i/o 137 i/o 136 vcc i/o 135 i/o 134 i/o 133 i/o 132 i/o 131 i/o 130 gnd i/o 129 i/o 128 i/o 127 i/o 126 i/o 125 i/o 124 i/o 123 i/o 122 i/o 121 i/o 120 tdo/sdo nc 1 gnd nc 1 vcc nc 1 i/o 119 i/o 118 i/o 117 i/o 116 i/o 115 i/o 114 i/o 113 i/o 112 i/o 111 i/o 110 gnd i/o 109 i/o 108 i/o 107 i/o 106 i/o 105 i/o 104 vcc i/o 103 i/o 102 i/o 101 i/o 100 gnd isplsi 3320 top view 208mquad/3320 1. nc pins are not to be connected to any active signal, vcc or gnd. pin configuration isplsi 3320 208-pin pqfp (with heat spreader) and 208-pin mqfp pinout diagram
specifications isplsi 3320 15 signal configuration isplsi 3320 320-ball bga signal diagram 242322212019181716151413121110987654321 a a b b c c d d e e f f g g h h j j k k l l m m n n p p r r t t u u v v w w y y aa aa ab ab ac ac ad ad 242322212019181716151413121110987654321 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. isplsi 3320 bottom view 320bga/3320 nc 1 nc 1 gnd trst nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 vcc nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 vcc nc 1 nc 1 gnd nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd gnd vcc gnd y3 y0 gnd vcc nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd y1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd vcc gnd gnd nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd vcc nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 y4 gnd nc 1 nc 1 vcc vcc y2 gnd gnd nc 1 gnd nc 1 nc 1 nc 1 nc 1 gnd vcc vcc gnd nc 1 vcc vcc gnd toe nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd vcc reset i/o 16 i/o 14 i/o 9 i/o 8 i/o 5 i/o 1 i/o 157 i/o 154 i/o 151 i/o 146 i/o 144 i/o 140 i/o 147 i/o 150 i/o 159 i/o 2 i/o 11 i/o 15 i/o 18 i/o 20 i/o 19 i/o 17 i/o 13 i/o 10 i/o 6 i/o 3 tdi/ sdi i/o 0 i/o 158 i/o 156 i/o 153 i/o 148 i/o 145 i/o 139 i/o 137 i/o 135 i/o 136 i/o 138 i/o 142 i/o 149 i/o 152 i/o 155 i/o 4 i/o 7 i/o 12 i/o 21 i/o 23 i/o 24 i/o 26 i/o 22 i/o 27 i/o 30 i/o 33 i/o 36 i/o 38 i/o 39 i/o 40 i/o 42 i/o 43 i/o 44 i/o 46 i/o 47 i/o 45 i/o 48 i/o 49 i/o 54 i/o 62 i/o 69 i/o 72 i/o 75 i/o 84 i/o 87 i/o 92 i/o 101 i/o 102 i/o 106 i/o 107 i/o 105 i/o 108 i/o 109 i/o 113 i/o 112 i/o 111 i/o 114 sdo/ tdo i/o 115 i/o 117 i/o 118 i/o 121 i/o 122 i/o 127 i/o 126 i/o 129 i/o 131 i/o 134 i/o 132 i/o 130 i/o 133 i/o 128 i/o 125 i/o 124 i/o 123 i/o 119 i/o 120 i/o 116 i/o 110 i/o 103 i/o 100 i/o 99 i/o 97 i/o 93 i/o 90 i/o 86 i/o 83 i/o 80 i/o 78 i/o 76 i/o 73 i/o 68 i/o 65 i/o 61 i/o 59 i/o 60 i/o 63 i/o 67 i/o 70 i/o 79 i/o 82 i/o 91 i/o 95 i/o 98 i/o 96 i/o 94 i/o 89 i/o 88 i/o 85 i/o 81 i/o 77 i/o 74 i/o 71 i/o 66 i/o 64 goe 0 goe 1 i/o 58 i/o 56 i/o 104 i/o 55 i/o 57 i/o 51 i/o 53 i/o 50 i/o 52 i/o 41 i/o 37 i/o 35 i/o 34 i/o 32 i/o 31 i/o 29 i/o 28 i/o 25 i/o 141 i/o 143 tms/ mode tck/ sclk ispen / bscan
specifications isplsi 3320 16 device number grade blank = commercial isplsi 3320 xxx x xxxx x speed 100 = 100 mhz f max 70 = 70 mhz f max power l = low package q = pqfp (with heat spreader) b320 = bga m = mqfp* device family 0212a/3320 table 2-0041a/3320 family f max (mhz) 100 70 ordering number package 208-pin pqfp 208-pin pqfp t pd (ns) 10 15 isplsi isplsi 3320-100lq 100 208-pin mqfp 10 isplsi 3320-100lm* 100 320-ball bga 10 isplsi 3320-100lb320 isplsi 3320-70lq 70 208-pin mqfp 15 isplsi 3320-70lm* *use the 208-pin pqfp for new designs. 70 320-ball bga 15 isplsi 3320-70lb320 commercial part number description ordering information

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