rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad1315 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 high speed active load with inhibit mode functional block diagram product description the ad1315 is a complete, high speed, current switching load designed for use in linear, digital or mixed signal test systems. by combining a high speed monolithic process with a unique surface mount package, this product attains superb electrical performance while preserving optimum packaging densities in an ultrasmall 16-lead, hermetically sealed gull wing package. featuring current programmability of up to +50 ma, the ad1315 is designed to force the device under test to source or sink the programmed i ohprog and i olprog currents. the i oh and i ol currents are determined by applying a corresponding voltage (5 v = 50 ma) to the i oh and i ol pins. the voltage- to-current conversion is performed within the ad1315 thus allowing the current levels to be set by a standard voltage out digital-to-analog converter. the ad1315s transition from ioh to iol occurs when the output voltage of the device under test slews above or below the programmed threshold, or commutation voltage. the commuta- tion voltage is programmable from 2 v to +7 v, covering the large spectrum of logic devices while able to support the large current specifications (48 ma) typically associated with line drivers. to test i/o devices, the active load can be switched into a high impedance state (inhibit mode) electrically removing the active load from the path through the inhibit mode feature. the active load leakage current in inhibit is typically 20 na. the inhibit input circuitry is implemented utilizing high speed differential inputs with a common-mode voltage range of 7 volts and a maximum differential voltage of 4 volts. this allows for the direct interface to the precision of differential ecl timing or the simplicity of switching the active load from a single ended ttl or cmos logic source. with switching speeds from ioh or io~ into inhibit of less than 1.5 ns, the ad1315 can be electrically removed from the signal path on-the-fly. the ad1315 is available in a 16-lead, hermetically sealed gull wing package and is specified to operate over the ambient com- mercial temperature range from 0 c to +70 c. features +50 ma voltage programmable current range 1.5 ns propagation delay inhibit mode function high speed differential inputs for maximum flexibility hermetically sealed small gull wing package compatible with ad1321, ad1324 pin drivers applications automatic test equipment semiconductor test system board level test system
C2C rev. a ad1315Cspecifications (all measurements made in free air at +25 8 c. +v s = +10 v, Cv s = C5.2 v, unless otherwise noted.) AD1315KZ parameter min typ max units comments differential input characteristics inh to inh input voltage, any one input C3.0 4.0 volts differential input range 0.4 ecl 4.0 volts bias current C2.0 1.0 2.0 ma current program voltage range i oh , 0 ma to +50 ma (sink) 1 0 +5.0 volts i ol , 0 ma to C50 ma (source) 1 0 +5.0 volts input resistance 50 k w i ohrtn , i ocrtn range 2 C2.0 +7.0 volts v com , v dut range C2.0 +7.0 volts i oh , 0 ma to +50 ma 0.5 +7.0 volts v dut C v com >1 v i ol , 0 ma to C50 ma C2.0 +4.0 volts v com C v dut >1 v output characteristics 3 active (sink/source) mode transfer function 10 ma/v see figure 1 accuracy see figure 1 linearity error C0.12 +0.12 % fsr gain error C2.0 +2.0 % fsr offset error C1.0 +1.0 ma output current tc 10 m a/ c inhibit mode output capacitance 3.0 pf inhibit leakage C200 20 200 na dynamic performance 3 propagation delay see figure 2 i max to inhibit (t pd1 ) 4 0.5 1.5 ns inhibit to i max (t pd2 ) 4 1.5 3.0 ns power supplies Cv s to +v s difference 15.2 15.4 volts supply range positive supply +9.5 +10 +10.5 volts negative supply C5.45 C5.2 C4.95 volts current positive supply 5 +70 5 +85 +100 ma negative supply 5 C100 5 C85 C70 ma power dissipation 6 1.3 1.54 psrr 7 0.05 %/% notes 1 i ohprog /i olprog voltage range may be extended to C100 mv due to a possible 1 ma offset current. 2 i ohrtn /i olrtn should be connected to v com to minimize power dissipation. 3 v dut = C2 v to +7 v, c total = 10 pf, r dut = 10 w . for inhibit leakage tests, v dut = 0 v to +5.9 v, i oh = C4 ma, i ol = +4 ma, t case = +36 c. 4 measured from the ecl crossing to the 10% change in the output current. 5 i program = 50 ma. 6 maximum power dissipation with +v s = +10 v, Cv s = 5.2 v, i program 50 ma, v com = v dut = 0 v. 7 for a 1% change in +v s or v s , the output current may change a maximum of 0.05% of full scale range (fsr). specifications subject to change without notice.
ad1315 C3C rev. a absolute maximum ratings 1 power supply voltage +v s to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 v Cv s to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C11 v difference from +v s to Cv s . . . . . . . . . . . . . . . . . . . . . 16 v inputs difference from inh to inh . . . . . . . . . . . . . . . . . . . . . 5 v inh, inh . . . . . . . . . . . . . . . . . . +v s C 13.4 v, Cv s + 11 v v com , v dut . . . . . . . . . . . . . . . +v s C 13.1 v, Cv s + 13.2 v i ol , i oh program voltage . . . . . . . . +v s C 15 v, Cv s + 15 v operating temperature range . . . . . . . . . . . . . . . 0 to +70 c storage temperature range . . . . . . . . . . . . C65 c to +125 c lead temperature range (soldering 20 sec) 2 . . . . . . . +300 c pin no. symbol function 1i olrtn logic low current return 2v com communication voltage 3v dut load/dot connection 4Cv s negative supply 5i ohrtn logic high current return 6i olprog logic low current program voltage 7 lid lid connection (internal) 8 gnd ground 9i ohprog logic high current program voltage 10 n/c no connection 11 n/c no connection 12 n/c no connection 13 +v s positive supply 14 inh inhibit 15 inh inhibit 16 n/c no connection 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 to ensure lead coplanarity ( 0.002 inches) and solderability, handling with bare hands should be avoided and the device should be stored in an environment at 24 c, 5 c (75 f, 10 f) with relative humidity not to exceed 65%. connection diagram suggested pad location dimensions shown in inches and (mm). ordering guide temperature package package model range description option* AD1315KZ 0 to +70 c 16-lead gull wing z-16b *z = leaded chip carrier (ceramic).
ad1315 C4C rev. a definition of terms gain the measured transconductance. gain = i out (@ 5 v input ) - i out (@ 0.2 v input ) v prog (@ 5 v ) - v prog (@ 0.2 v ) where: v prog values are measured at i ol /i oh prog gain error the difference between the measured transconductance and the ideal expressed as a % of full-scale range. ideal gain = 10 ma/v gain error = ideal gain - actual gain ideal gain 100 offset error offset error is measured by setting the i ohprog or i olprog inputs to 0.2 v and measuring i out . since both i oh and i ol figure 1. definition of terms figure 2. timing diagram for inhibit transition outputs are unipolar, this small initial offset of 2 ma must be set to allow for measurement of possible negative offset. with a gain of 10 ma/v, a 0.2 v input should yield an output of 2 ma. the difference between the observed output and the ideal 2ma output is the offset error. offset error = i out (@ 0.2 v) C gain 3 v prog (@ 0.2 v) linearity error the deviation of the transfer function from a straight line de- fined by offset and gain expressed as a % of fsr. i out (calc) = gain 3 v prog (@ set point) + offset where: set point = v prog (from 0.2 v to 5 v) i out (fsr) = gain 3 v prog (@ 5 v) + offset linearity error i out ( measured ) - i out ( calc ) i out ( fsr ) 100 figure 3. i ol , i oh offset current vs. temperature figure 4. i ol , i oh gain error vs. temperature figure 5. i ol , i oh linearity error vs. current program voltage
ad1315 C5C rev. a figure 6. +i max , Ci max to inhibit propagation delay vs. temperature figure 7. inhibit to +i max , Ci max propagation delay vs. temperature figure 8. inhibit mode leakage current vs. case temperature figure 9. ad1315 dc test circuit figure 10. ad1315 propagation delay test circuit
ad1315 C6C rev. a functional description the ad1315 is a complete high speed active load designed for use in general purpose instrumentation and digital functional test equipment. the function of the active load is to provide independently variable source and sink currents for the device to be tested. the equivalent circuit for the ad1315 is shown in figure 11. an active load performs the function of loading the output of the device under test with a programmed i oh or i ol . these currents are independently programmable. v com is the commu- tation voltage point at which the load switches from source to sink mode. the active load may also be inhibited, steering cur- rent to the i olrtn and i ohrtn pins, effectively disconnecting it from the test pin. the ad1315 accepts differential digital signals at its inhibit inputs ensuring precise timing control and high noise immunity. the wide inhibit input voltage range allows for ecl power supplies of C5.2 v and 0 v, C3.2 v and +2 v, and 0 v and +5 v. where speed and timing accuracy are less important, ttl or cmos logic levels may be used to toggle the inhibit inputs of the ad1315. single ended operation is possible by biasing one of the inputs to approximately +1.3 v for ttl or v cc /2 for cmos. care should be taken to observe the 4 v maximum allowable input voltage. the i oh and i ol programming inputs accept 0 v to +5 v analog inputs, corresponding to 0 to 50 ma output currents. the v com input, which sets the i oh /i ol switch point, may be set anywhere within the input range of C2 v to +7 v. figure 11. block diagram v dut voltage range in figure 12, v dut range, i oh and i ol typical current maxi- mums are plotted versus dut voltage. in the i oh mode (v dut higher than v com ), the load will sink 50 ma, until its output starts to saturate at approximately C1.5 v. in the i ol mode (v dut lower than v com ), the load will source 50 ma until its output starts to saturate at approximately +5.5 v. at +7 v, the source current will be close to zero. figure 12. allowable current range for i oh , i ol vs. v dut ideally, the commutation point set at v com would provide in- stantaneous current sink/source switching. because of i/v characteristics of the internal bridge diodes, this is not the case. to guarantee full current switching at the dut, at least a 1 volt difference between v com and v dut must be maintained in steady state conditions. because of the relatively fast edge rates exhibited by typical logic device outputs, this should not be a problem in normal ate applications. inhibit mode leakage the ad1315s inhibit-mode leakage current changes with both temperature and bias levels. there are two major contributing effects: transistor reverse-bias collector-base leakage and reverse leakage in the schottky-diode bridge. leakage variations with v dut arise primarily from transistor collector-base leakage, while both effects contribute to leakage current temperature variations. inhibit-mode leakage is weakly dependent on v com and decreases slightly as the difference between v dut and v com is reduced. figure 8 shows typical ad1315 inhibit leakage cur- rent as a function of v dut and temperature. thermal considerations the ad1315 is provided in a 0.550" 3 0.550", 16-lead (bottom brazed) gull wing, surface mount package with a q jc of 10 c/w (typ). thermal resistance (case-to-ambient) vs. air flow for the ad1315 in this package is shown in figure 13. the data pre- sented is for a zif socketed device. for pcb mounted devices (w/30 mils clearance) the thermal resistance should be ~3 to 7% lower with air flows below 320 lfm (1) . notice that the improve- ment in thermal resistance vs. air flow starts to flatten out just above 400 lfm (2) . notes 1 ifm is air flow in linear feet/minute. 2 for convection cooled systems, the minimum recommended airflow is 400 lfm. figure 13. case-to-ambient thermal resistance vs. air flow
ad1315 C7C rev. a applications the ad1315 has been optimized to function as an active load in an ate test system. figure 14 shows a block diagram illus- trating the electronics behind a single pin of a high speed digital functional test system with the ability to test i/o pins on logic devices. the ad1315 active load, ad1321 or ad1324 pin driver, ad1317 high speed dual comparator and the ad664 quad 12-bit voltage dac would comprise the pin electronic portion of the test system. such a system could operate at 100 mhz with the ad1321 (200 mhz with the ad1324) in a data mode or 50 mhz (100 mhz) in the i/o mode. the v com input sets the commutation voltage of the active load. with dut output voltage above v com , the load will sink cur- rent (i oh ). with dut output voltage below v com , the load will source current (i ol ). like the i oh and i ol return lines, the v com must be able to sink or source 50 ma, therefore a standard op amp will not suffice. an op amp with an external complemen- tary output stage or a high power op amp such as the ad842 will work well here. a typical application is shown in figure 15. layout considerations i ohrtn and i olrtn may be connected to any potential between C2 v and +7 v. these return points must be able to source or sink 50 ma, since the i oh and i ol programmed currents are diverted here in the inhibit mode. the rtns may be connected to a suitable gnd. however, to keep transient ground currents to a minimum, they are typically tied to the v com programming voltage point. figure 14. high speed digital test system block diagram figure 15. suggested i ohrtn , i olrtn , v com hookup
ad1315 C8C rev. a c1337aC1C5/97 printed in u.s.a. evaluation board the ad1315 evaluation board allows the designer to easily evaluate the performance of the ad1315 and its suitability for the specific application. the ad1315eb includes a mounted figure 16. ad1315eb evaluation board circuit AD1315KZ active load, an ecl input buffer for inhibit and the oscilloscope probe jacks necessary to properly analyze the true performance of the AD1315KZ. an equipment list is provided in order to minimize variations due to test setups. outline dimensions dimensions shown in inches and (mm). 16-lead gull wing (z-16b)
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