View 33926_1455871.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document number: mc33926 rev. 4.0, 12/2006 freescale semiconductor product preview ? freescale semiconductor, in c., 2007. all rights reserved. *this document contains certain inform ation on a product under development. free- scale reserves the right to change or discontinue this product without notice 5.0 a throttle control h-bridge the 33926 is a monolithic h-bridge power ic designed primarily for automotive electronic th rottle control, but is applicable to any low- voltage dc servo motor control app lication within the current and voltage limits stated in this specification. the 33926 is able to control inductive loads with currents up to 5.0 a peak. rms current capability is subject to the degree of heatsinking provided to the device package. internal peak-current limiting (regulation) is ac tivated at load currents above 6.5 a 1.5 a. output loads can be pulse width modulated (pwm-ed) at frequencies up to 20 khz. a load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller?s a/d input. a status flag output reports undervoltage, overcurrent, and over temperature fault conditions. two independent inputs provide polarity control of two half-bridge totem-pole outputs. two independent disable inputs are provided to force the h-bridge outputs to tri-st ate (high impedance off-state). an input invert input changes the in1 and in2 inputs to low = true logic. features ? 8.0 v to 28 v continuous oper ation (transient operation from 5.0 v to 36 v) ? 225 m ? maximum r ds(on) @ 150c (each h-bridge mosfet) ? 3.0 v and 5.0 v ttl / cmos logic compatible inputs ? overcurrent limiting (regulatio n) via internal constant-off- time pwm ? output short circuit protection (short to vpwr or ground) ? temperature-dependant current-limit threshold reduction ? all inputs have an internal source/sink to define the default (floating input) states ? sleep mode with current draw < 50 a (with input s floating or set to match default logic states) figure 1. 33926 simplified application diagram ordering information device temperature range (t a ) package pc33926pnb/r2 - 40c to 125c 32 pqfn scale 2:1 pnb suffix 98arl10579d 32-pin pqfn bottom view 33926 automotive thro ttle h-bridge actuator/ motor exciter sf fb in1 in2 inv slew d1 d2 en vpwr ccp out1 out2 pgnd agnd mcu 33926 v pwr v dd motor
analog integrated circuit device data 2 freescale semiconductor 33926 internal block diagram internal block diagram figure 2. 33926 simplifi ed internal block diagram vdd logic supply charge pump gate drive and protection logic current mirror and constant off-time pwm current regulator vcp ccp out1 out2 pgnd to gates hs1 ls1 hs2 ls2 vpwr v sense i lim pwm hs1 hs2 ls1 ls2 ls2 en in1 in2 d2 d1 inv slew sf fb agnd pgnd
analog integrated circuit device data freescale semiconductor 3 33926 pin connections pin connections figure 3. 33926 pin connections table 1. 33926 pin definitions a functional description of each pin can be found in the functional description section beginning on page 11 . pin pin name pin function formal name definition 1 in2 logic input input 2 logic input control of out2; e.g., when in2 is logic high, out2 is set to v pwr , and when in2 is logic low, out2 is se t to pgnd. (schmitt trigger input with ~ 80 a source so default condition = out2 high.) 2 in1 logic input input 1 logic input control of out1; e.g., when in1 is logic high, out1 is set to v pwr , and when in1 is logic low, out1 is set to pgnd. (schmitt trigger input with ~ 80 a source so default condition = out1 high.) 3 slew logic input slew rate logic input to select fast or slow slew rate. (schmitt trigger input with ~ 80 a sink so default condition = slow.) 4, 6, 11, 31 v pwr power input positive power supply these pins must be connected together ph ysically as close as possible and directly soldered down to a wide, thick, low resistance supply plane on the pcb. 5, exposed pad agnd analog ground analog signal ground the low current analog signal ground must be connected to pgnd via low impedance path (<<10 m ? , 0 hz to 20 khz). exposed copper pad is also the main heatsinking path for the device. 7 inv logic input input invert sets in1 and in2 to logic low = true. (schmitt trigger input with ~ 80 a sink so default condition = non-inverted.) 8 fb analog output feedback load current feedback output provides ground referenced 0.24% of h-bridge high-side output current. (tie pin to gnd through a resistor if not used.) 9, 17, 25 nc no connect no internal connection is made to this pin. 10 en logic input enable input when en is logic high, the device is operational. when en is logic low, the device is placed in sleep mode. (logic input with ~ 80 a sink so default condition = sleep mode.) transparent top 25 17 18 19 20 21 22 23 24 910111213141516 1 2 3 4 5 6 7 8 26 27 28 29 30 31 32 nc nc vpwr nc in2 in1 slew out1 agnd inv fb en out1 vpwr vpwr out2 out2 agnd out1 d2 pgnd sf d1 out2 out2 ccp vpwr pgnd pgnd pgnd pgnd pgnd out1 view of package
analog integrated circuit device data 4 freescale semiconductor 33926 pin connections 12, 13, 14, 15 out1 power output h-bridge output 1 source of high-side mosfet1 and drain of low-side mosfet1. 16 d2 logic input disable input 2 (active low) when d2 is logic low, both out1 and out2 are tri-stated. (schmitt trigger input with ~80 a sink so default condition = disabled.) 18 ? 20, 22 ? 24 pgnd power ground power ground high-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the pcb. 21 sf logic output - open drain status flag (active low) open drain active low status flag output (requires an external pullup resistor to v dd . maximum permissible load current < 0.5 ma. maximum v ce sat < 0.4 v @ 0.3 ma. maximum permissible pullup voltage < 7.0 v.) 26 d1 logic input disable input 1 (active high) when d1 is logic high, both out1 and out2 are tri-stated. schmitt trigger input with ~80 a source so default condition = disabled. 27, 28, 29, 30 out2 power output h-bridge output 2 source of high-side mosfet2 and drain of low-side mosfet2. 32 ccp analog output charge pump capacitor external reservoir capacitor connection fo r internal charge pump; connected to vpwr. allowable values are 30 n f to 100 n f. note this capacitor is required for the proper performance of the device. table 1. 33926 pin de finitions (continued) a functional description of each pin can be found in the functional description section beginning on page 11 . pin pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33926 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. thes e parameters are not production tested. ratings symbol value unit electrical ratings power supply voltage normal operation (steady-state) transient overvoltage (1) v pwr(ss) v pwr(t) - 0.3 to 28 - 0.3 to 40 v logic input voltage (2) v in - 0.3 to 7.0 v sf output (3) v sf - 0.3 to 7.0 v continuous output current (4) i out(cont) 5.0 a esd voltage (5) human body model machine model charge device model corner pins (1,9,17,25) all other pins v esd1 v esd2 2000 200 750 500 v thermal ratings storage temperature t stg - 65 to 150 c operating temperature (6) ambient junction t a t j - 40 to 125 - 40 to 150 c peak package reflow temperature during reflow (7) , (8) t pprt note 8 c approximate junction-to-board thermal resistance (9) r jb < 1.0 c/w notes 1. device will survive repetitive transient over voltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%. external protection is required to prevent devic e damage in case of a reverse battery condition. 2. exceeding the maximum input voltage on in1, in2, en, inv, slew, d1, or d2 may cause a malfunction or permanent damage to the device. 3. exceeding the pullup resistor voltage on the open drain sf pin may cause permanent damage to the device. 4. continuous output current capability is dependent on suffi cient package heatsinking to keep junction temperature 150 c. 5. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ), and the charge device model (cdm), robotic (c zap = 4.0pf). 6. the limiting factor is junction temperatur e, taking into account the power dissipat ion, thermal resistance, and heat sinking provided. brief non-repetitive excursions of junction temperature above 150 c can be tolerated provided the duration does not exceed 30 seconds maximum. (non-repetitive events are defined as not occurring more than once in 24 hours.) 7. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. 9. exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. the actual r jb (junction-to-pc board) values will vary depending on solder thickness and composition and copper trace thickness and area. maximum current at maximum die temperature represents ~16 w of conduction loss heating in the diagonal pair of output mosfets. therefore, the r ja must be < 5.0 c/w for maximum current at 70 c ambient. module thermal design must be planned accordingly.
analog integrated circuit device data 6 freescale semiconductor 33926 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 8.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power inputs (vpwr) operating voltage range (10) steady-state transient (t < 500 ms) (11) quasi-functional (r ds(on) may increase by 50%) v pwr(ss) v pwr( t ) v pwr(qf) 8.0 ? 5.0 ? ? ? 28 40 8.0 v sleep state supply current (12) en, d2 , inv, slew = logic [0], in1, in2, d1 = logic [1], and i out = 0 a i pwr(sleep) ? ? 50 a standby supply current (part enabled) i out = 0 a, v en = 5.0 v i pwr(standby) ? ? 20 ma undervoltage lockout thresholds v pwr( falling) v pwr( rising) hysteresis v uvlo ( active ) v uvlo ( inactive ) v uvlo ( hys ) 4.15 ? 150 ? ? 200 ? 5.0 350 v v mv charge pump charge pump voltage (cp capacitor = 33 n f), no pwm v pwr = 5.0 v v pwr = 28 v v cp - v pwr 3.5 ? ? ? ? 12 v charge pump voltage (cp capacitor = 33 n f), pwm = 20khz, slew rate = fast v pwr = 5.0 v v pwr = 28 v v cp - v pwr tbd ? ? ? ? tbd v control inputs operating input voltage (en, in1, in2, d1, d2 , inv, slew) v i ? ? 5.5 v input voltage (in1, in2, d1, d2 , inv, slew) (13) logic threshold high logic threshold low hysteresis v ih v il v hys 2.0 ? 250 ? ? 400 ? 1.0 ? v v mv input voltage (en) threshold v th 1.0 ? 2.0 v logic input currents, vpwr = 8.0v inputs en, d2 , inv, slew (internal pull-downs), v ih = 5.0v inputs in1, in2, d1 (internal pull-ups), vil = 0v i in 20 -200 80 -80 200 -20 a notes 10. device specificati ons are characterized over the range of 8.0 v v pwr 28 v. continuous operation above 28 v may degrade device reliability. device is operational down to 5.0 v, but below 8.0 v the output resistance may increase by 50 percent. 11. device will survive the transient overvolt age indicated for a maximum duration of 500 ms. transient not to be repeated more than once every 10 seconds. 12. i pwr(sleep) is with sleep mode activated and en, d2 , inv, slew = logic [0], and in1, in2, d1 = logic [1] or with these inputs left floating. 13. slew input voltage threshold parameters are guaranteed by design.
analog integrated circuit device data freescale semiconductor 7 33926 electrical characteristics static electrical characteristics power outputs out1, out2 output-on resistance (15) , i load = 3.0a v pwr = 8.0v, t j = 25 c v pwr = 8.0v, t j = 150 c v pwr = 5.0v, t j = 150 c r ds(on) ? ? ? 120 ? ? ? 225 325 m ? output current regulation threshold t j < 150 c t j > 160 c (fold back region - see figure 10 ) (14) i lim 5.2 ? 6.5 4.2 8.0 ? a high-side short circuit detection th reshold (short circuit to ground) (14) i sch 11 13 16 a low-side short circuit detection threshold (short circuit to v pwr ) (14) i scl 9.0 11 14 a output leakage current (16) , outputs off, v pwr = 28v v out = v pwr v out = ground i outleak ? ?60 ? ? 100 ? a output mosfet body diode forward voltage drop i out = 3.0 a v f ? ? 2.0 v overtemperature shutdown (14) thermal limit @ t j hysteresis @ t j t lim t hys 175 10 ? ? 200 30 c high-side current sense feedback feedback current (pin fb sourcing current) (17) i out = 0 ma i out = 300 ma i out = 500 ma i out = 1.5 a i out = 3.0 a i out = 6.0 a i fb 0.0 0.0 0.35 2.86 5.71 11.43 ? 270 0.775 3.57 7.14 14.29 50 750 1.56 4.28 8.57 17.15 a a ma ma ma ma status flag (18) status flag leakage current (19) v sf = 5.0 v i sf leak ? ? 5.0 a status flag set voltage (20) i sf = 300 a v sf low ? ? 0.4 v notes 14. this parameter is guaranteed by design. 15. output-on resistance as measured from output to v pwr and from output to gnd. 16. outputs switched off via d1 or d2 . 17. accuracy is better than 20% from 0.5 a to 6.0 a. recommended terminating resistor value: r fb = 270 ?. 18. status flag output is an open drain output requiring a pullup resistor to logic v dd . 19. status flag leakage current is measured with status flag high and not set. 20. status flag set voltage measured with status flag low and set with i fs = 300 a . maximum allowable sink current from this pin is < | 500 a | . maximum allowable pullup voltage < 7.0 v. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33926 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 8.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (21) f pwm ? ? 20 khz maximum switching frequency duri ng current limit regulation (22) f max ? ? 20 khz output on delay (23) v pwr = 14 v t d on ? ? 18 s output off delay (23) v pwr = 14 v t d off ? ? 12 s i lim output constant-off time (24) t a 15 20.5 32 s i lim blanking time (25) t b 12 16.5 27 s disable delay time (26) t ddisable ? ? 8.0 s output rise and fall time (27) slew = slow slew = fast t f , t r 1.5 0.5 3.0 ? 8.0 1.45 s short circuit / overtemperature turn-off (latch-off) time (28) (29) t fault ? 2.0 ? s power-on delay time (29) t pod ? 1.0 5.0 ms output mosfet body diode reverse recovery time (29) t r r 75 100 150 ns charge pump operating frequency (29) f cp ? 7.0 ? mhz notes 21. the maximum pwm frequency is obtained when the device is set to fast slew rate via the slew pin. pwm-ing when slew is set to slow should be limited to frequencies < 11 khz in order to allow the internal high-side dr iver circuitry time to fully enhance the high-side mosfets. 22. the internal current limit circuitry produces a constant-off -time pulse width modulation of the output current. the output l oad?s inductance, capacitance, and resistance char acteristics affect the total switching period (off-time + on-time), and thus the pw m frequency during current limit. 23. * output delay is the time duration from 1.5v on the in1 or in2 input signal to the 20% or 80% point (dependent on the transition direction) of the out1 or out2 signal. if the output is transitioning high-to-low, the delay is from 1.5v on the input signal to the 80% p oint of the output response signal. if the output is transit ioning low-to-high, the delay is from 1.5v on the input signal to the 20% point of the output response signal. see figure 4 , page 9 . 24. the time during which the internal constant-off time pwm current regulation circuit has tri-stated the output bridge. 25. the time during which the current regulation threshold is i gnored so that the short-circuit detection threshold comparators may have time to act. 26. * disable delay time measurement is defined in figure 5 , page 9 . 27. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal with v pwr = 14 v, r load = 3.0 ohm. see figure 6 , page 9 . 28. load currents ramping up to the current r egulation threshold become limited at the i lim value (see figure 7 ). the short circuit currents possess a di/dt that ramps up to the i sch or i scl threshold during the i lim blanking time, registering as a short circuit event detection and causing the shutdown circuitry to force the out put into an immediate tri-state latch-off (see figure 8 ). operation in current limit mode may cause junction temperatures to rise. junction temperatures above ~160 c will cause the output current limit threshold to ?fold back?, or decrease, until ~175 c is reached, after which the t lim thermal latch-off will occur. permissibl e operation within this fold back region is limited to non-repetitive transient event s of duration not to exceed 30 seconds (see figure 9 ). 29. parameter is guaranteed by design.
analog integrated circuit device data freescale semiconductor 9 33926 electrical characteristics timing diagrams timing diagrams figure 4. output delay time figure 5. disable delay time . figure 6. output switching time figure 7. current limit blanking time and constant-off time 5.0 v pwr 0 0 time 1.5v 1.5v 20% 80% t don v out1, 2 (v) v in1, in2 (v) t doff ? 0 v 5.0 v 0 ? v out1, 2 v d1, d2 (v) time 1.5v t ddisable 10% i o = 100ma 90% 90% 10% 10% v out1, 2 (v) t f t r v pwr 0 time i sc short circuit detection threshold i out , current (a) t b 5.0 t a 9.0 0.0 i lim 6.5 t b = i lim blanking time t a = constant-off time (out1 and out2 tri-stated) overload condition t on time
analog integrated circuit device data 10 freescale semiconductor 33926 electrical characteristics timing diagrams figure 8. short circuit detection turn-off time t fault . figure 9. output current limiting foldback region i sc short circuit detection threshold i out , current (a) 5.0 9.0 0.0 i lim 6.5 hard short occurs t fault short circuit condition t b (~16 us) t b time sf set low out1, out2 tri-stated, 6.6 2.5 160 175 t her mal s hu tdo wn t j , junction temperature ( o c) i lim , 6.5 i lim current (a) 4.2 current limit threshold foldback. normal current limit threshold operation within this region must be limited to non-repetitive events not to exceed 30 s maximum duration.
analog integrated circuit device data freescale semiconductor 11 33926 functional description introduction functional description introduction numerous protection and operational features (speed, torque, direction, dynamic breaking, pwm control, and closed-loop control) make the 33926 a very attractive, cost- effective solution for controlling a broad range of small dc motors. the 33926 outputs are capable of supporting peak dc load currents of up to 5.0 a from a 28 v pwr source. an internal charge pump and gate drive circuitry are provided that can support external pwm frequencies up to 20 khz. the 33926 has an analog feedback (current mirror) output pin (the fb pin) that provides a constant-current source ratioed to the active high-side mosfets ? current. this can be used to provide ?real time? mo nitoring of output current to facilitate closed-loop operat ion for motor speed/torque control, or for the detection of open load conditions. two independent inputs, in1 and in2, provide control of the two totem-pole half-bridge outputs. an input invert, inv, changes in1 and in2 to low = true logic. two different output slew rates are selectable via the slew input. two independent disable inputs, d1 and d2 , provide the means to force the h-bridge outputs to a high impedance state (all h- bridge switches off). an en pin controls an enable function that allows the ic to be placed in a power-conserving sleep mode. the 33926 has output current limiting (via constant off-time pwm current regulation), output short-circuit detection with latch-off, a nd overtemperature detection with latch-off. once the device is latched-off due to a fault condition, either of the disable inputs (d1 or d2 ), v pwr , or en must be ?toggled? to clear the status flag. current limiting (load current regulation) is accomplished by a constant-off time pwm method using current limit threshold triggerin g. the current limiting scheme is unique in that it incorpor ates a junction temperature- dependent current limit threshold. this means that the current limit threshold is ?reduced to around 4.2 a? as the junction temperature increa ses above 160c. when the temperature is above 175c , overtemperature shutdown (latch-off) will occur. this co mbination of features allows the device to continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. functional pin description power ground and analog ground (pgnd and agnd) the power and analog ground pins should be connected together with a very low impedance connection. positive power supply (vpwr) vpwr pins are the power supply inputs to the device. all vpwr pins must be connected together on the printed circuit board with as short as possible traces, offering as low impedance as possible between pins. status flag ( sf ) this pin is the device fault st atus output. this output is an active low open drain structure requiring a pullup resistor to v dd . the maximum v dd is < 7.0 v. refer to table 5, truth table , page 14 for the sf output status definition. input invert (inv) the input invert control pin sets in1 and in2 to low = true. this is a schm itt trigger input with ~ 80 a sink; the default condition is non-inver ted. if in1 and in2 are set so that the current is being commanded to flow through the load attached between out1 and out2, changing the logic level at inv will have the effect of re versing the direction of current commanded. thus, the inv input may be used as a ?forward/ reverse? command input. if both in1 and in2 are the same logic level, then changing the logic level at inv will have the effect of changing the bridge?s output from freewheeling high to freewheeling low or vice versa. slew rate (slew) the slew pin is the logic input that selects fast or slow slew rate. schmitt trigger input with ~ 80 a sink so the default condition is slow. when slew is set to slow, pwm-ing should be limited to frequencies less than 11 khz in order to allow the internal high-side driver circuitry time to fully enhance the high-side mosfets. input 1,2 and disable input 1,2 (in1, in2, and d1, d2 ) these pins are input control pins used to control the outputs. these pins are 3.0 v/ 5.0 v cmos-compatible inputs with hysteresis. in1 and in2 independently control out1 and out2, respectively. d1 and d2 are complementary inputs used to tri-state disable the h-bridge outputs. when either d1 or d2 is set (d1 = logic high or d2 = logic low) in the disable state, outputs out1 and out2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply i pwr(standby) current is reduced to a few ma. refer to table 3, static electrical characteristics , page 6 .
analog integrated circuit device data 12 freescale semiconductor 33926 functional description functional pin description h-bridge output (out1, out2) these pins are the outputs of the h-bridge wit h integrated free-wheeling diodes. the brid ge output is controlled using the in1, in2, d1, and d2 inputs. the outputs have pwm current limiting above the i lim threshold. the outputs also have thermal shutdown (tri-state latch-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) is incorporated to distinguish between load currents that are higher than the i lim threshold and short circuit currents. this timer is activated at each output transition. charge pump capacitor (ccp) this pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. the allowable value is from 30 nf to 100 nf. this capacitor must be connected from the ccp pin to the vpwr pin. the device cannot operate properly without the external reservoir capacitor. enable input (en) the en pin is used to place the device in a sleep mode so as to consume very low current s. when the en pin voltage is a logic low state, the device is in the sleep mode. the device is enabled and fully operational when the en pin voltage is logic high. an internal pulldown resistor maintains the device in sleep mode in the event en is driven through a high impedance i/o or an unpowered microcontroller, or the en input becomes disconnected. feedback (fb) the 33926 has a feedback output (fb) for ?real time? monitoring of h-bridge high-side output currents to facilitate closed-loop operation for motor speed and torque control. the fb pin provides current sensing feedback of the h-bridge high-side drivers. wh en running in the forward or reverse direction, a ground-ref erenced 0.24% of load current is output to this pin. through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can ?read? the current proportional voltage with its analog-to-digital converter (adc). this is intended to provide the user with only firs t-order motor current feedback for motor torque control. the resistance range for the linear operation of the fb pin is 100 < r fb < 300 w. if pwm-ing is implemented using the disable pin inputs (either d1 or d2 ), a small filter capacitor (~1.0 f) may be required in parallel with the r fb resistor to ground for spike suppression.
analog integrated circuit device data freescale semiconductor 13 33926 functional device operation operational modes functional device operation operational modes figure 10. operating states pwm current limiting 9.0 6.5 typical short circuit detection threshold typical current limit threshold hard short detect ion and latch-off 0 in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 [1] [0] [1] [0] [1] [0] [1] [0] outputs tri-stated outputs tri-stated outputs operation (per input control condition) time sf , logic out d2 , logic in d1, logic in in n , logic in i load , output current (a) high current load being regulated via constant-off-time pwm moderate current load
analog integrated circuit device data 14 freescale semiconductor 33926 functional device operation logic commands and registers logic commands and registers figure 11. 33926 power stage operation table 5. truth table the tri-state conditions and the stat us flag are reset using d1 or d2 . the truth table uses the foll owing notations: l = low, h = high, x = high or low, and z = high impedance. all output power transistors are switched off. device state input conditions status outputs en d1 d2 in1 in2 sf out1 out2 forward h l h h l h h l reverse h l h l h h l h free wheeling low h l h l l h l l free wheeling high h l h h h h h h disable 1 (d1) h h x x x l z z disable 2 ( d2 ) h x l x x l z z in1 disconnected h l h z x h h x in2 disconnected h l h x z h x h d1 disconnected h z x x x l z z d2 disconnected h x z x x l z z undervoltage lockout (30) h x x x x l z z overtemperature (31) h x x x x l z z short circuit (31) h x x x x l z z sleep mode en l x x x x h z z en disconnected z x x x x h z z notes 30. in the event of an undervoltage condition, the outputs tri-state and status flag is set logic low. upon undervoltage recover y, status flag is reset automatically or automatic ally cleared and the outputs are restored to their original operating condition. 31. when a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-off independent of th e input signals and the status flag is latched to logic low. to rese t from this condition requires the toggling of either d1, d2 , en, or v pwr . out1 out2 pgnd v pw r v pw r pgnd load load current forward off on on off out1 out2 pgnd off on on off v pwr v pw r pgnd load load current reverse out1 out2 pgnd v pwr v pwr pgnd load load current high-side recirculation (forward) on off on off out1 out2 pgnd v pwr v pwr pgnd load load current low-side recirculation (forward) on on off off
analog integrated circuit device data freescale semiconductor 15 33926 functional device operation protection and di agnostic features protection and diagnostic features short circuit protection if an output short circuit condition is detected, the power outputs tri-state (latch-off) independent of the input (in1 and in2) states, and the fault status output flag ( sf ) is set to logic low. if the d1 input changes from logic high to logic low, or if the d2 input changes from logic low to logic high, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic high state. the output stage will always switch into the mode defined by the input pins (in1, in2, d1, and d2 ), provided the device junction temperature is wit hin the specified operating temperature range. internal pwm current limiting the maximum current flow under normal operating conditions should be less than 5.0 a. the instantaneous load currents will be limited to i lim via the internal pwm current limiting circuitry. when the i lim threshold current value is reached, the output stages are tri-stated for a fixed time (t a ) of 20 s typical. depending on the time constant associated with the load characteristics, the output current decreases during the tri-state duration un til the next output on cycle occurs. the pwm current limit threshol d value is dependent on the device junction temperature. when - 40c < t j < 160c, i lim is between the specified minimum/maximum values. when t j exceeds 160 c, the i lim threshold decreases to 4.2 a. shortly above 175 c the device overtemperature circuit will detect t lim and an overtemperature shutdown will occur. this feature implements a gracef ul degradation of operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the motor?s gear-reduction train to be handled. important die temperature excursions above 150c are permitted only for non-repetitive durations < 30 seconds. provision must be made at th e system level to prevent prolonged operation in the current-foldback region. overtemperature shutdown and hysteresis if an overtemperature condit ion occurs, the power outputs are tri-stated (latched-off) and the fault status flag ( sf ) is set to logic low. to reset from this condition , d1 must change from logic high to logic low, or d2 must change from logic low to logic high. when reset, the outp ut stage switches on again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. important resetting from the fault condition will clear the fault status flag. powering down and powering up the device will also reset the 33926 from the fault condition. output avalanche protection an inductive fly-back event, namely when the outputs are suddenly disabled (tri-stated) and vpwr is lost, could result in electrical overstress of the drivers. to prevent this the vpwr input to the 33926 should not exceed 40 v during a fly-back condition. this may be done with either a zener clamp or mov, and/or an ap propriately valued input capacitor with sufficiently low esr (see figure 12 ). figure 12. avalanche protection out1 out2 i/os agnd pgnd bulk low esr cap. vpwr 100nf m v pwr 9
analog integrated circuit device data 16 freescale semiconductor 33926 typical applications introduction typical applications introduction a typical application schematic is shown in figure 13 . for precision high-current applicat ions in harsh, noisy environments, the v pwr by-pass capacitor may need to be substantially larger. figure 13. 33926 typical application schematic vdd logic supply charge pump gate drive and protection logic current mirrors and constant off-time pwm current regulator vcp ccp out1 out2 agnd to gates hs1 ls1 hs2 ls2 vpwr v sense i lim pwm hs1 hs2 ls1 ls2 ls2 en in1 in2 d2 d1 inv slew sf fb pgnd +5.0v r fb 270 ? status flag to adc 1.0 f 33nf v pwr 100nf 100 f m pgnd
analog integrated circuit device data freescale semiconductor 17 33926 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search us ing the 98axxxxxxx xx listed below. pnb suffix 32-pin pqfn plastic package 98arl10579d issue b
analog integrated circuit device data 18 freescale semiconductor 33926 packaging package dimensions pnb suffix 32-pin pqfn plastic package 98arl10579d issue b
analog integrated circuit device data freescale semiconductor 19 33926 additional documentation thermal addendum (rev 2.0) additional documentation thermal addendum (rev 2.0) introduction this thermal addendum is provided as a supplement to the mc33926 technical datasheet. the addendum pr ovides thermal performance information that may be critical in the design and development of system appl ications. all electrical, application, and packaging information is provided in the datasheet. packaging and thermal considerations the mc33926 is offered in a 32 pin pqfn, single die package. there is a single heat source (p), a single junction temperature (t j ), and thermal resistance (r ja ). the stated values are solely for a thermal performance comparison of one package to another in a standardized envir onment. this method ology is not meant to and will not predict the performance of a package in an application-specific environment. stated values were obtained by measurement and simulation according to the standards listed below. standards figure 14. surface mount for power pqfn with exposed pads 32-pin pqfn 33926 pnb suffix 98arl10579d 32-pin pqfn 8.0 mm x 8.0 mm note for package dimensions, refer to the 33926 data sheet. t j = r ja . p table 6. thermal performance comparison thermal resistance [ c/w] r ja (1) , (2) 28 r jb (2) , (3) 12 r ja (1) , (4) 80 r jc (5) 1.0 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-5 and jesd51-7. 3. per jedec jesd51-8, with the board temperature on the center trace near the center lead. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated. 1.0 1.0 0.2 0.2 * all measurements are in millimeters
analog integrated circuit device data 20 freescale semiconductor 33926 additional documentation thermal addendum (rev 2.0) figure 15. thermal test board device on thermal test board table 7. thermal resistance performance r ja is the thermal resistance between die junction and ambient air . 33926pnb pin connections 32-pin pqfn 0.80 mm pitch 8.0 mm x 8.0 mm body a 25 17 18 19 20 21 22 23 24 910111213141516 1 2 3 4 5 6 7 8 26 27 28 29 30 31 32 nc nc vpwr nc in2 in1 slew out1 agnd inv fb en out1 vpwr vpwr out2 out2 agnd out1 d2 pgnd sf d1 out2 out2 ccp vpwr pgnd pgnd pgnd pgnd pgnd out1 material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a: cu heat-spreading areas on board surface ambient conditions: natural convection, still air a [mm 2 ] r ja [ c/w] 0 81 300 49 600 40
analog integrated circuit device data freescale semiconductor 21 33926 additional documentation thermal addendum (rev 2.0) figure 16. device on thermal test board r ja figure 17. transient thermal resistance r j a , 1 w step response, device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 70 80 90 heat spreading area a [mm2] thermal resistance [oc/w ] 0 300 600 r ja [ c/w] x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s ] thermal resistance [oc/w ] r ja [ c/w] x
analog integrated circuit device data 22 freescale semiconductor 33926 revision history revision history revision date description 1.0 3/2006 ? converted to freescale format, implemented changes listed below. ? implemented revision history page. 2.0 9/2006 ? updated figure 2. 33926 simplified internal block diagram. ? revised table2. maximum ratings ? continuous output current changed fr om 5.5a to 5.0a (parameter changed in the text through the document). ? esd voltage: added charge device model. ? peak pin reflow temperature during sol der mounting changed from 260 to 250 deg.c. ? revised table 3. static electrical characteristics ? output current regulation threshold: min value changed from 5.5a to 5.2a. ? high-side short circuit detection thres hold - parameter guaranteed by design. ? low-side short circuit detection threshold - parameter guaranteed by design. ? feedback current: parameter values updated. ? status flag set voltage: max value changed from 1.0v to 0.4v. ? revised table 4. dynamic electrical characteristics ? output off delay: max. value changed from 18 s to 12 s. ? output rise and fall time: max value changed from 8.0 s to 6.0 s. ? short circuit / overtemperature turn-off (latch-off) time: typ and max values changed from 4.0 s, 8.0 s to 1.0 s, 2.0 s respectively. ? charge pump operating frequency: typ 7 mhz, new parameter added into the table. note 25: condition changed from iout = 3.0a to r load = 600 ohm. ? added figure 10. 33926 power stage operation. ? updated figure 11. 33926 typi cal application schematic. ? updated the freescale format to the prevailing form and style ? added thermal addendum. 3.0 10/2006 ? corrected minor typos formatti ng throughout the document. ? corrected labels on the internal block diagram ? added ?these parameters are not production tested? to the maximum ratings heading ? changed the values for logic input voltage (2) and sf output (3) ? made corrections on note (4) , (7) , and (10) for maximum ratings ? changed labels or values for sleep state supply current (12) , undervoltage lockout thresholds , charge pump voltage (cp capacitor = 33 nf), no pwm , input voltage (in1, in2, d1, d2, inv, slew) (13) , logic input currents, vpwr = 8.0v , output-on resistance (15) , iload = 3.0a , output current regulation threshold , output leakage current (16) , outputs off, vpwr = 28v , feedback current (pin fb sourcing current) (17) , and status flag leakage current (19) in the static electrical characteristics ? added charge pump voltage (cp capacitor = 33 nf), pwm = 20khz, slew rate = fast and operating input voltage (en, in1, in2, d1, d2, inv, slew) in the static electrical characteristics ? added note this parameter is guaranteed by design. to static electrical characteristics ? changed labels or values for ilim output constant-off time (24) , ilim blanking time (25) , output rise and fall time (27) and short circuit / overtemperature turn-o ff (latch-off) time (28) (29) in the dynamic electrical characteristics ? made changes or corrections to note (24) , (27) , (28) , and (29) for dynamic electrical characteristics ? made corrections to figure 4, output delay time , figure 5, disable delay time , and figure 6, output switching time in timing diagrams ? added figure 7, current limit blanking time and constant-off time and figure 8, short circuit detection turn-off time t fault in timing diagrams ? added paragraph output avalanche protection and figure 12, avalanche protection to protection and diagnostic features ? made minor label changes to figure 13, 33926 typical application schematic
analog integrated circuit device data freescale semiconductor 23 33926 revision history 4.0 12/2006 ? corrected minor typographic errors on pages 2, 7, 9, 11, 15, and 16. ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 5 . ? added notes pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these limits ma y cause malfunction or permanent damage to the device. on page 5 and freescale?s package reflow capability meets pb-free requirements for jedec standard j-std-020c. for peak package reflow te mperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e .g. remove prefixes/suffixes and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. on page 5 revision date description
mc33926 rev. 4.0 12/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

▲Up To Search▲

Price & Availability of 33926

	To Download 33926 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .