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austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 austin semiconductor, inc. preliminary solid state disk on chip (ssdoc) features ? capacities - 4 gb - 8 gb - 16 gb ? pata compatibility - ata-5 compatible - udma4 supported - pio mode 4 supported - mwdma mode 2 supported ? performance - sustained sequential read bandwidth:16 mb/s - sustained sequential write bandwidth: 5 mb/s ? form factor - bga package ? 31 mm (w) x 31 mm (l) x 4.2-7.8 mm (h) ? weighs approximately 11 grams (typ) ? each nand component, either a 4, 8 or 16gb device, based on the use of single and stacked silicon solutions ? ecc correction = 6 bytes within a 512 byte sector ? automatic sleep mode ? controller contained in base interposer ? slc (single-level cell) nand flash ? reliability - mean time between failure (mtbf) >2,000,000 hours (est.) - program/erase >1,000,000 times (est.) - temp cycle 500/1000 cycles, jedec a104 condition b -55oc to +125oc ? power supply voltage: 5.0v or 3.3 v 10% (typ) ? power consumption (vcc = 5.0 v) - idle: 10 mw (typ) - active: 255 mw (typ) overview the solid state disk is based on a proprietary package stacking technology to create an extremely space conscious, robust solid state disk. the ssd is capable of operating in harsh, vibration prone product platforms such embedded computing applications, heavy transportation, ultra portables, handhelds, mobile computing, digital radio, high-speed networking & enterprise applications, as well as, military, aerospace and industrial applications. for more products and information please visit our web site at www.austinsemiconductor.com ? operating temperature - commercial: 0c to 70c - industrial: -45c to 85c ? shock and vibration - shock: 1500g mil-std0810f - vibration: 15 g rms mil-std0810f ? compliances - lead free - rohs - sn/pb ball option
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 austin semiconductor, inc. preliminary key features ? nand flash controller ? (2) stacks, each containing (2 or 4) nand components ? each nand component, either a 4,8 or 16gb device, based on the use of single ? silicon and stacked silicon solutions ? providing a total bit density of either 4,8 or 16gb ? controller contained in base interposer ? fast ata host to buffer transfer rates supporting true ide, pio/4 mode support ? 512byte sector buffers ? flash memory power-down logic ? ecc correction = 6 bytes within a 512 byte sector ? automatic sleep mode ? burst transfer rate, 16.67mb per second ? sustained transfer rate: 6.7mb per second ? sophisticated wear leveling architecture the pata controller in the pata solid state drive utilizes a 32-bit risc architecture which provides for direct connection of one, two or four nand flash memory devices (2 per channel). an on-chip error correction code (ecc) and cyclic redundancy check (crc) unit generates the required code bytes facilitating error detection and correction of up to six bytes per 512 byte data sector. on the fly code byte generation for read and write operations minimizes ecc performance impacts. the controller?s flash memory interface allows the direct connection of up to 10 chips and support samsung (nand) type flash memory. asi pata solid state drives use single level cell (slc) samsung nand flash memory devices.
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 austin semiconductor, inc. preliminary block diagram 16 gb 16 gb 16 gb 16 gb 16 gb dual enable nand 16 gb dual enable nand 16 gb dual enable nand 16 gb dual enable nand controller 16 gb dual enable nand 16 gb dual enable nand 16 gb dual enable nand 16 gb dual enable nand ide interface nand nand nand nand regulatory compliance since the pata ssd is a component (or a set of components depending on the configuration) on the motherboard, system certifications are the responsibility of the oem or odm. device compliance compliance description pb free components and materials are lead free. rohs restriction of hazardous substance directive
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 austin semiconductor, inc. preliminary product specifications operating conditions maximum ratings stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacity and user addressable sectors unformatted user addressable sector in lba mode 4gb* 7,880,544 8gb* 15,761,088 16gb* 31,522,176 note: formatting and other functions will use some of the space, thus the listed capacity will not be available entirely for data storage. read and write perfomance operation access type mb/second read sustained sequential read bandwidth 16 mb/second write sustained sequential write bandwidth 5 mb/second absolute maximum ratings by device parameter symbol max. min. unit vcc supply voltage vcc_p -0.5 +5.5 v non-operation temperature ti -40 +85 o c
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 austin semiconductor, inc. preliminary operating conditions (continued) recommended operating conditions operating temperature and voltages parameter symbol max. typ min. unit industrial: 0 o c to +70 o c t 0 0-70 o c commercial: -40 o c to +85 o c t 0 0-70 o c tcc_p 4.5 5 5.5 v tcc_p 3.0 3.3 3.6 v ground supply voltage gndpln 0 0 0 v vcc supply voltage dc characteristics (pata controller configuration) symbol paramenter min. max. units conditions v il input low voltage -0.3 +0.8 v v ih input high voltage 2.2 vcc+0.3 v v ol output low voltage 0.45 v i ol =4ma v oh output high voltage 2.4 v i oh =-1ma operating current, v cc_r =5.0v sleep mode 0.2 ma operating, 20 mhz 30 ma operating, 40 mhz 50 ma operating current, v cc_r =3.3v sleep mode .02 m operating, 20 mhz 30 m operating, 40 mhz 50 m i li input leakage current 10 a i lo output leakage current 10 a c i/o input / output capacitance 10 pf i cc i cc
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 austin semiconductor, inc. preliminary electrical characteristics environmental conditions altitude since there are no moving parts, this device is not susceptible to a lack of air molecules and will oper- ate correctly to 85,000 feet above sea level. power consumption setting value active idle current 1.85ma active current 51ma active power 255mw idle power 9.25mw temperature specifications mode max. min. unit operate - commercial 0 +70 o c operate - industrial -40 +85 o c ambient temperature shock and vibration characteristics condition value operating shock 1500g mil-std-810f operating vibration 15g rms mil-std-810f
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 austin semiconductor, inc. preliminary environmental conditions (continued) acoustics this drive has no moving or noise-emitting parts; therefore, it produces negligible sound (0db) in all modes of operation. electrostatic discharge (esd) the pata ssd can withstand an electrostatic discharge of +/- of 2 kv. esd testing is done to demon- strate that the units can withstand discharge encountered in normal handling or operations of the equipment. humidity specifications condition value unit operate non-condensing 5-95 % reliability specifications parameter value mean time between failure (mtbf) >2,000,000 hours (est.) program / erase >1,000,000 time (est.) warranty 2 years
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 austin semiconductor, inc. preliminary mechanical information pata ssd (top, side and bottom views) stacks, each containing (2 or 4) nand components 29.21 sq. 31.00 sq. 1.27mm 1.27mm o0.76 381 plcs 7.41mm 0.61mm 7.41mm 0.61mm 5.01mm 0.61mm (2)high + base 4gb 8gb & 16gb
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 austin semiconductor, inc. preliminary pin assignments
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 austin semiconductor, inc. preliminary pin assignments (continued) n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n22 n23 n24 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v24 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 w21 w22 w23 w24 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 y24 aa1 aa2 aa3 aa4 aa5 aa6 aa7 aa8 aa9 aa10 aa11 aa12 aa13 aa14 aa15 aa16 aa17 aa18 aa19 aa20 aa21 aa22 aa23 aa24 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 ab19 ab20 ab21 ab22 ab23 ab24 ac1 ac2 ac3 ac4 ac5 ac6 ac7 ac8 ac9 ac10 ac11 ac12 ac13 ac14 ac15 ac16 ac17 ac18 ac19 ac20 ac21 ac22 ac23 ac24 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ide_d2 ide_d2 ide_d2 ide_d2 ide_d9 ide_d9 ide_d9 ide_d9 ide_piois16\ ide_piois16\ ide_piois16\ ide_piois16\ ide_d10 ide_d10 ide_d10 ide_d10 fc_wp_en fc_wp_en fc_wp_en fc_wp_en nc vcc_f vcc_f vcc_f vcc_f vcc_f vcc_f vcc_f vcc_p vcc_p vcc_p ide_d8 ide_d8 ide_d8 ide_d8 fout vccpln_in vccpln_in vccpln_in fout fout fout fout nc fout fout fout nc nc vcc_f vcc_f vcc_f vcc_f cout cout cout cout cadj cadj cadj cadj vcc_r vcc_r vcc_r vcc_r nc gndpln gndpln gndpln nc vcc_r vcc_r vcc_r fadj fadj fadj fadj fout fout fout ide_d3 fout fout fout vccnand_in gndpln vccnand_in vccnand_in vccnand_in vccnand_in fc_wp_en1 fc_wp_en1 vccnand_in vccnand_in vccnand_in vccnand_in vccnand_in gndpln gndpln gndpln gndpln vccnand_in gndpln gndpln gndpln gndpln vccnand_in gndpln gndpln gndpln gndpln gndpln gndpln gndpln gndpln gndpln xtalr vcc_c vcc_c vcc_c vcc_c gndpln gndpln gndpln nc vcc_f gndpln vcc_f gndpln vcc_f gndpln vcc_f nc vccpln_in fc_reset vccpln_in vccpln_in vccpln_in vccpln_in vccpln_in vccpln_in xtali xtalc xtalc xtalr xtalc xtalr xtalc xtalr nc vccpln_in vccpln_in vccpln_in vccpln_in vccpln_in vccpln_in vccpln_in gndpln gndpln nc gndpln gndpln nc gndpln gndpln nc gndpln gndpln fc_reset nc gndpln gndpln fc_reset nc gndpln gndpln xtali xtali xtali vcc_c vcc_c vcc_c vccpln_in vccpln_in vccpln_in nc nc nc vcc_f vcc_f vcc_f blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank blank fc_reset
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 austin semiconductor, inc. preliminary signal descriptions g symbol type description ide_a0 output address bus ide_a1 output ide_a2 output ide_d0 input/output data bus. the signals d15..d0 represent the bidirectional data bus; active high signals a "one". ide_d1 input/output ide_d2 input/output ide_d3 input/output ide_d4 input/output ide_d5 input/output ide_d6 input/output ide_d7 input/output ide_d8 input/output ide_d9 input/output ide_d10 input/output ide_d11 input/output ide_d12 input/output ide_d13 input/output ide_d14 input/output ide_d15 input/output ide_intrq output drive interrupt request. ide_iowr\ input i/o data write enable is the strobe signal asserted by the host to write device registers or the data port. diow shall be negated by the host prior to the initiation of an ultra dma burst. stop shall be negated by the host before the data is transferred in an ultra dma burst. the assertion of stop by the host during an ultra dma burst signals the termination of the ultra dma burst. ide_iord\ input i/o data read enable is the strobe signal asserted by the host to read device registers or the data port. ide_cs0\ input drive chip select 0 is used by host to select command block registers. ide_cs1\ input drive chip select 1 is used by host to select command block registers. ide_piois16\ output 16-bit i/o transfer. ide_pdig input/output passed diagnostics. ide_dmarq ide_dmarq\ output dma request. this signal, used for dma data transfers between host and device, shall be asserted by the device when it is ready to transfer data to or from the host. for multi word dma transfers, the direction of data transfer is controller by ide_iord\ and ide_iowr\. when a dms operation is enabled, cs0\ and cs1\ shall not be asserted and transfers shall be 16 bits wide. this signal shall be release when the device is not selected. fc_wait output ready signal to ide_iordy
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 austin semiconductor, inc. preliminary ide_preset input reset fc_wp_en fc_wp_en1 input write protect signal fc_reset input # reset processor. reset# low resets the processor to the initial state and halts all activity. reset# must be low for at least one cycle. on a transition from low to high, a reset exception occurs and the processor starts execution at the reset entry determined by the int4 state. the transition may occur asynchronously to the clock. we recommend connecting this pin to a voltage monitoring circuit with open-drain output (e.g. torex xc61a) supplying a reset signal for supply voltages less than 2.6 or 2.7v, connected to a r/c combination of 100 k and 100 nf giving an additional reset delay in the order of 10 ms. fc_led\ output operation led signal fc_mode fc_ideen output master/slave select and connect to ide_csel for cable select option xtalr output r/c clock oscillator resistor output. the resistor connected between this pin and xtali determines the operating clock frequency. use a 470 resistor to obtain a frequency of about 20 mhz xtalc output r/c clock oscillator capacitor output. connect a 22pf capacitor between this pin and xtali. xtali input r/c clock oscillator input. this input connects to the other side of the resisors and the capacitor connected to xtalr1, xtalr2 and xtalc. connect a 22pf capacitor from this pin to ground. nc not connected vcc_c supply power supply voltage, core vcc_r supply power supply voltage, regulator vcc_f supply power supply voltage, flash memory vcc_p supply power supply voltage, controller fadj input 3.3v flash memory power supply adjustment. connect a 270pf capacitor from this pin to fout. fout output 3.3v flash memory power supply. this output provides a regulated 3.3v supply if the power supply voltage is above 3.3v. this supply voltage must also be connected to the vcc_f pins. cadj input 2.5v core power supply adjustment. connect a 220k resistor from this pin to gnd, a 220k resistor from this pin to cout, and a 270pf capacitor from this pin to cout. cout output 2.5v core power supply. this output provides a regulated 2.5v supply if the power supply voltage is above 3.3v. this supply voltage must be connected to the vcc_c pins. vccnand_in supply 3.3v flash memory power supply vccpln_in supply supply to the controller gndpln supply supply ground
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 austin semiconductor, inc. preliminary typical application design
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 austin semiconductor, inc. preliminary command sets the pata ssd device supports all the mandatory ata commands as defined in the ata/atapi-5 specifi- cation. ata general feature command set the pata ssd device supports the ata general feature command set. common name code execute device diagnostic 90h identify device ech identify device dma eeh initialie drive parameters 91h nop 00h read buffer e4h read dma c8h, c9h read long 22h, 23h read multiple c4h read native max address f8h read sector(s) 20h, 21h read verify sector(s) 40h, 41h recalibrate 1xh seek 7xh set features efh set multiple mode c6h smart b0h translate sector 87h write buffer e8h write dma cah, cbh write long 32h, 31h write multiple c5h write multiple without erase cdh write sector(s) 30h, 31h write sector(s)without erase 38h write verify 3ch
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 15 austin semiconductor, inc. preliminary reference this document also references standards and specifications defined by a variety of organizations. please use the following information to identify the location of an organization's standards information. date or revision numbe r title location february 2000 ata r 5 http://www.t13.org/documents/ uploadeddocuments/project/d1321r3 r ataatapi r 5.pdf december 2004 jedec standard jesd22 r c101c: field r induced charged r device model test method for electrostatic r discharge r withstand thresholds of microelectronic components http://www.jedec.org/download/search/ default2.cfm march 2006 hyperston f2 r 16x, 32 r bit flash memory controller specification http://www.hyperstone.com/fmc_f2_en,15593.html january 2007 jedec standard: electrostatic discharge (esd) sensitivity testing human body model (hbm) http://www.jedec.org/download/search/ default2.cfm glossary this document incorporates many industry and device specific words. use the following list to define a variety of terms and acronyms. yy term definition ata advanced technology attachment cfa compactflash association cprm content protection for recordable media crc cyclic redundancy check dma direct memory access ecc error correction code esd electrostatic discharge hdd hard disk drive hpa host protected area ide integrated device electronics lba logical block addressing mtbf mean time between failure mwdma multi-word dma odm original design manufacturer oem original equipment manufacturer pata parallel ata pcmcia personal computer memory card international assocoation pio programmable input / output sata serial ata ssd solid state drive umda ultra dma, also know ultra ata
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 16 austin semiconductor, inc. preliminary order chart part number storage density sustained transfer rate as3ssd4gb8pbgr/it 4gb 7.7mb/sec AS3SSD8GB8PBGr/it 8gb 7.7mb/sec as3ssd16gb5pbgr/it 16gb 5.0mb/sec as3ssd4gb8pbgr/ct 4gb 7.7mb/sec AS3SSD8GB8PBGr/ct 8gb 7.7mb/sec as3ssd16gb5pbgr/ct 16gb 5.0mb/sec available processes ct = commercial temperature range 0 o c to +70 o c it = industrial temperature range r 40c to +85c r = rohs compliant / lead free blank = sn / pb finish option
austin semiconductor, inc. solid st solid st solid st solid st solid st a a a a a te disk te disk te disk te disk te disk as3ssd4gb8pbg AS3SSD8GB8PBG as3ssd16gb5pbg as3ssd4gb8pbg, AS3SSD8GB8PBG, as3ssd16gb5pbg rev. 1.3 07/09 austin semiconductor, inc. reserves the right to change products or specifications without notice. 17 austin semiconductor, inc. preliminary document title 4gb, 8gb, 16gb solid state disk on chip revision history rev # history release date status 1.0 initial release december 2008 preliminary 1.1 updated mechanical information january 2009 preliminary 1.2 updated order chart march 2009 preliminary 1.3 updated 4gb & 8gb drawi ng july 2009 preliminary

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