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" for more information + ! " using the operation status bits in amd devices application note publication number 22152 revision d amendment 0 issue date july 24, 2002
. publication# 22152 rev: d amendment/ 0 issue date: july 24, 2002 using the operation status bits in amd devices application note first generation flash memory devices required the system cpu to execute the program and erase algo- rithms in software. these algorithms consisted of a complex series of operations with strict timing require- ments in order to set-up, control and monitor the flash device. erroneous execution of these algorithms could render the flash device inoperable thereby compro- mising system reliability. to eliminate concerns by system software designers amd choose to embed the algorithms within the flash device. why are the operation status bits provided? from the system point of view the flash memory de- vice functions both as a memory and as a peripheral to the cpu. operation as a memory device is straight for- ward. operation as a peripheral involves following a command and status protocol similar to other system peripherals. the protocol consist of jedec compliant command sequences which are written to the device followed by status interrogation read from the device. through this protocol the system cpu communicates with a sophisticated state machine internal to the flash memory device. all amd flash devices therefore pro- vide operation status bits to monitor the status of these embedded operations. what can be determined from these status bits? the following information can be determined by polling the operation status bits: 1. program cycle completion 2. chip erase cycle completion 3. sector erase cycle completion 4. checking if a sector is in the erase suspend mode 5. ensuring that the program/erase operation has completed successfully 6. checking if the sector erase time-out window is open (when issuing multiple sector erase commands). 7. checking if the write-to-buffer abort condition has been initiated. what are the status bits provided on amd flash devices? the following operation status bits are provided in the status register of amd flash devices: dq7: data# polling dq6: toggle bit 1 dq5: exceeded timing limits bit dq4: reserved dq3: sector erase timer bit dq2: toggle bit 2 (not offered on all devices) dq1: write-to-buffer abort dq0: reserved in addition to the operation status bits, a ready/busy# (ry/by#) pin is also provided on most amd flash de- vices. checking the ry/by# pin is another method by which the host system can determine if the flash de- vice has completed a program or erase operation. this document also discusses usage of the ry/by# pin as an alternative to polling the operation status bits wher- ever applicable. how do the status bits actually work? internally, amd flash devices multiplex the data pins (dq0-dq7) between the memory array and the status register (see figure 1). when a program or erase op- eration begins, the multiplexer switches the data pins status register in 16-bit mode (btye# pin driven high) u n d un d u n d u n d u n d u n d un d u n d dq 7 d q 6 d q5 d q4 d q3 d q 2 d q1 d q0 status register dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 status register in 8-bit mode (btye# pin driven low) 15 8 7 0 70
2 using the operation status bits in amd devices july 24, 2002 supplement to the status register. the flash device is now operat- ing as a peripheral. by executing a read bus cycle to the flash device the operation status bits are fetched from the status register and presented on the data pins (dq0-dq7). after a program or erase operation is complete, the multiplexer switches the data pins back to the memory array. the flash device now reverts back to operating as a memory. please note that status bits are valid after the we# ris- ing edge on the last command and any applicable program/erase time-outs. figure 1. data pins multiplexed between the memory array and status register how can the host system access the operation status bits? the operation status bits may be accessed by a sim- ple read cycle. all status bits are valid after the rising edge of the final we# pulse in the program/erase com- mand sequence. the microprocessor may (a) continuously poll the status bits immediately after the pro- gram/erase command sequence is written or (b) periodically poll the status bits while performing other tasks. the designer has the option to implement the ap- propriate polling method depending on the specific host system. for an example see figure 2. figure 2. example of am29f040 program operation memory array status registers dq0 - dq7 oe# ce# address pins we# 5555h 2aaah 5555h pa pa program command sequence read status register aah 55h a0h pd status register data bus data write cycle (1) program set up command cycle (1) command unlock cycles (2)
july 24, 2002 using the operation status bits in amd devices 3 supplement using the operation status bits the operation status bits provided on amd flash devices can be used for the following: (using the ry/by# pin as an alternative to the operation status bits is also discussed.) 1. checking if the device has completed a pro- gram operation: to determine if the flash device has completed a program operation the system may (a) poll dq6 or (b) poll dq7 or (c) check the ry/ by# pin. dq6 and dq7 must always be polled in conjunction with dq5 (see item 5, ?ensuring that the program/erase operation has completed success- fully?). a. polling dq6: once the flash device starts a program opera- tion, successively reading from any address will show dq6 to be toggling i.e. if dq6 is a ?1? in the first read cycle, it will be a ?0? in the next. once the program operation is completed, dq6 stops tog- gling and valid array data will be read in the next at- tempt. refer to figure 3 for the polling sequence. note: although dq6 may be read from any ad- dress, amd recommends using a consistent ad- dress throughout the polling sequence. or b. polling dq7: once the flash device starts a program opera- tion, reading the dq7 status bit yields the com- plement of the data last written to dq7. note that dq7 must be read from the location being pro- grammed. once the programming is complete, dq7 returns the true data last written to dq7. refer to figure 4 for the polling sequence. or c. check ry/by# pin: the ry/by# pin will be ?low? if the device has started the program operation, and ?high? when the operation is complete. the ry/by# pin may be tied to the interrupt of the microprocessor. the microprocessor may then perform other tasks after issuing the program command. the ry/by# pin will interrupt the microprocessor when the operation is complete. in the absence of a ry/by# pin, the host system will have to rely on polling the dq6 or dq7 status bits. 2. checking if the device has completed an chip erase operation: to determine if the flash device has completed a chip erase operation the system may (a) poll dq6, (b) poll dq7 or (c) check the ry/by# pin. dq6 and dq7 must always be polled in conjunction with dq5 (see item 5, ?ensuring that the program/ erase operation has completed successfully?). a. polling dq6: once the flash device starts a chip erase oper- ation, successively reading from any address will show dq6 to be toggling. once the chip erase operation is completed, dq6 stops toggling and valid array data will be read on the next attempt. or b. polling dq7: once the device begins a chip erase operation, polling dq7 at any address returns a ?0?. when the chip erase operation is complete, dq7 returns a ?1?. refer to figure 5 for the polling sequence. or c. checking ry/by# pin: the ry/by# pin will be ?low? if the device has started the chip erase operation, and ?high? when the operation is complete. the ry/by# pin may be tied to the interrupt of the microproces- sor. the microprocessor may then perform other tasks after issuing the erase command. the ry/ by# pin will interrupt the microprocessor when the operation is complete. the ry/by# pin will then interrupt the microprocessor when the op- eration is completed. note that some amd de- vices do not offer the ry/by# pin, in which case the host system will have to rely on polling the dq6 or dq7 status bits. 3. checking if a the device has completed a sector erase operation: to determine if a particular sector has completed the erase operation the system will have to poll (a) dq7 or (b) dq6 or (c) check the ry/ by# pin. dq6 and dq7 must always be polled in conjunction with dq5 (see item 5, ?ensuring that the program/erase operation has completed successfully?). a. polling dq6: once the flash device starts a sector erase oper- ation, successively reading from any address will show dq6 to be toggling. once the sector erase operation is completed, dq6 stops toggling and valid array data will be read on the next attempt. or b. polling dq7: once the device starts a sector erase operation, reading dq7 from an address within the sector boundary returns a ?0?. when the sector erase is complete, dq7 returns a ?1?. or c. checking ry/by# pin: the ry/by# pin will be ?low? if the device has started the sector erase operation, and ?high? when the operation is complete. the ry/by# pin may be tied to the interrupt of the microproces- sor. the microprocessor may then perform other
4 using the operation status bits in amd devices july 24, 2002 supplement tasks after issuing the erase command. the ry/ by# pin will interrupt the microprocessor when the operation is complete. note that some amd devices do not offer the ry/by# pin, in which case the host system will have to rely on polling the dq6 or dq7 status bits. 4. checking if a sector is in the erase suspend mode: to determine if a particular sector is in the erase suspend mode the system will have to poll both the dq2 and dq6 operation status bits to- gether. note: the am29f010, am29f100 bulk erase devices do not support the erase suspend feature. polling dq2 & dq6: once a sector is in the erase suspend mode dq2 toggles but dq6 does not , with successive reads from any location within the suspended sector. once in the erase suspend mode, the device can perform a read or program opera- tion in a non-erase suspended sector. when an erase resume command is issued the sector resumes the erase operation and both dq2 and dq6 will continue to toggle. when the erase op- eration is complete, both dq2 and dq6 will stop toggling. note that some amd devices do not offer the dq2 operation status bit, in which case this application is not feasible. refer to fig- ure 6 for the appropriate polling sequence. 5. ensuring that the program/erase operation has completed successfully: the dq5 status bit indi- cates whether program or erase has exceeded internally specified pulse count limits. this a failure condition which signifies that the program/erase operation was not completed successfully. there- fore when polling for program or erase completion, dq5 must also be polled in conjunction with the other status bits. polling dq5: if a program or erase operation is not successful the dq5 status bit will be set to a ? 1 ? . under this condition, dq7 will not output valid data and dq6 will continue to toggle. to acknowledge this condition and return the device to the read mode the system must issue a reset command. refer to figures 3, 4, 5 and 6 for the appropriate polling sequence. 6. checking if the sector erase time-out window is open: all am29xxxxx flash devices support the erasing of multiple sectors after issuing a single sector erase command sequence. the sectors may be selected for erase in any order: for exam- ple sector 9 first and sector 1 next, etc. a sector erase is a six bus cycle operation (see datasheet). there are two unlock write cycles followed by a set- up cycle. two more unlock cycles are then followed by the actual sector erase command cycle (sector address + sector erase command: 30h). after the sector erase command cycle is written (6th bus cy- cle), the sector erase time-out window of 50 s begins. the next sector erase command cycle must be written before this 50 s time-out period expires. every time the system writes an additional sector erase command (30h), the 50 s time-out window is reset and another sector erase command cycle may be written within 50 s. the following example illus- trates the sequence to be implemented to erase 3 sectors. 6th bus cycle: address of the 1st sector to be erased + 30h (sector erase command) 50 s time-out begins 7th bus cycle: address of the 2nd sector to be erased + 30h (sector erase command) time-out window is reset and 50 s time-out begins again 8th bus cycle: address of the 3rd sector to be erased + 30h (sector erase command) sector erase operation begins after 50 s.
july 24, 2002 using the operation status bits in amd devices 5 supplement amd flash devices provide the dq3 status bit to enable the system to check if the sector erase time- out window is open before every sector erase co- mand cycle is issued. check dq3: if the sector erase time-out window is open, dq3 will be a ? 0 ? . when the 50 s time-out has expired, dq3 will be set to a ? 1 ? which indicates that the sector erase operation has begun. any attempt to write additional commands will be ig- nored until the ongoing sector erase operation is completed. to ensure that multiple sector erase commands have been accepted, the sys- tem software should check the status of dq3 prior to and following each sector erase com- mand cycle. refer to figure 7 for the polling se- quence.the first check (prior to the sector erase cycle) is to ensure that the time-out window is still open and the second check (following the sector erase cycle) is to ensure that the com- mand has been accepted. if dq3 is a ? 1 ? on the second status check, it indicates that the 50us time-out has expired and that last sector erase command was not accepted. 7. checking if the write-to-buffer abort condition has been initiated. the dq1 status bit indicates whether a write-to-buffer operation is in progress or has been aborted. polling dq1: if a write-to-buffer operation is in progress or has not been used, the dq1 status bit will be a ? 0 ? . when a write-to-buffer operation is aborted, dq1 will be set to ? 1 ? to indicated the write-to- buffer abort condition has been initiated. implementation issues the following points must be noted when implementing the various polling algorithms discussed above: 1. to determine if dq6 or dq2 is toggling the cpu must: a. read dq0-dq7 b. store dq2/dq6 c. read dq0-dq7 again d. compare current dq2/dq6 value with that stored in step (b). 2. dq5 the dq5 status bit must be checked in conjunction with the dq6 or dq7 status bits when polling the flash device for program/erase completion. see figures 3, 4, 5 and 6. 3. the internal state machine runs asynchronously to the system cpu. the internal switching of the mux is not synchronized with system cpu access. how- ever, the next read cycle will output valid data on dq0-dq7. whenever the status appears to indicate that dq5 is active, the status must be checked again to ensure that the error is valid and not a re- sult of reading during the transition form valid status to valid data.
6 using the operation status bits in amd devices july 24, 2002 supplement polling sequence for the operation status bits figure 3. dq6 toggle bit polling sequence for program completion figure 4. dq7 data polling sequence for program completion note: 1. the term toggle indicates that the system will have to read the status bits consecutively and compare them to determine if they have changed states. 2. dq6 toggles due to either ce# or oe# program/erase command sequence read dq7-dq0 twice address = x dq6 = toggle? yes no dq5 = 1? no yes program/erase not successful read dq7-dq0 twice address = x dq6 = toggle? program/erase completed yes no note: pa = program address of the location being programmed. program command sequence read dq7-dq0 address = va dq7=dq7 data? no yes dq5 = 1? no yes program not successful read dq7-dq0 address = va dq7=dq7 data? program completed no yes note: pa = program address of the location being programmed.
july 24, 2002 using the operation status bits in amd devices 7 supplement figure 5. dq7 data polling sequence for erase completion figure 6. dq2 and dq6 polling sequence note: the term toggle indicates that the system will have to read the status bits consecutively and compare them to determine if they have changed states. erase command sequence read dq7-dq0 address = x or va dq7=1? no yes dq5 = 1? no yes erase not successful read dq7-dq0 address = x or va dq7 = 1? erase completed no yes note: x = address is a ?don?t care? for chip erase. va = address of the location being programmed. sector erase command sequence read dq7-dq0 twice address = va dq6=toggle? yes no dq5 = 1? no yes sector erase not successful read dq7-dq0 twice address = va dq2=toggle? and dq6=toggle? sector erase completed yes no dq2=toggle? no yes sector erase suspended note: va = any address within the sector.
8 using the operation status bits in amd devices july 24, 2002 supplement figure 7. dq3 sector erase timer figure 8. write-to-buffer abort write sector erase unlock/set-up cycles sector erase command cycle dq3 = 1? no yes last sector erase command not accepted write next sector address and sector erase command dq3 = 1? yes no write-to-buffer command cycle load address and data count data count = 0? yes no dq1=0 yes write program buffer to flash confirm command cycle write next address and data pair decrement data count write ?write-to-buffer? unlock/set-up cycles no write to a different sector address write-to-buffer abort condition. must write ?write-to-buffer abort reset? command sequence to return to read mode read dq7-dq0 with addr= last loaded addr dq7= data? dq7= data? read dq7-dq0 with addr= last loaded addr dq7= data? fail or abort pass note: 1. user must reset the device to return to read mode when (1) sector erase timer has expired or (2) write-to-buffer abort condition has occured.
july 24, 2002 using the operation status bits in amd devices 9 supplement summary note: x= address don ? t care. also refer to the section on ? implementation issues ? . applications option 1 option 2 option 3 check if the device has completed a program operation poll dq6 address = x output: toggle ? programming in progress no toggle ? programming completed poll dq7 address = address of the location being programmed output: complement of dq7 ? programming in progress true data ? programming completed check ry/by# pin address = x output: 0 ? programming in progress 1 ? programming completed check if the device has completed a chip erase operation poll dq6 address = x output: toggle = erase in progress no toggle = erase completed poll dq7 address = x output: 0 = erase in progress 1 = erase completed check ry/by# address = x output: 0 = erase in progress 1 = erase completed check if the device has completed a sector erase operation poll dq7 address = any address within the sector output: 0 = erase in progress 1 = erase completed poll dq6 address = x output: dq6 toggling = erase in progress dq6 no toggle = erase completed check if a sector is in the erase suspend mode poll dq2 & dq6 address = any address within the sector output: dq2 toggle & dq6 no toggle = sector erase is suspended ensure that the program/erase operation has completed successfully poll dq5 address = x output: 1 = program/erase not completed successfully check if sector erase time-out window is open poll dq3 address = x output: 0 = sector erase time-out window open 1 = erase has begun check if the write-to- buffer condition has been initiated poll dq1 address = any address within the sector output 0 = write-to-buffer operation in progress 1 = write-to-buffer operation aborted
10 using the operation status bits in amd devices july 24, 2002 supplement revision summary revision a (march 1998) initial release. revision b (august 1998) using the operation status bits modified the paragraph in step 2c to indicate that the ry/by# pin may be used to detect sector erase completion. revision c (february 6, 2002) added write-to-buffer abort information to the follow- ing sections: what can be determined from these status bits? what are the status bits provided on amd flash de- vices? using the operation status bits implementation issues summary revision d (july 24, 2002) status register changed status register 8-15 to undefined. implementation issues changed paragraph three to current state. figure 3. dq6 toggle bit polling sequence for pro- gram completion figure 4. dq7 toggle bit polling sequence for pro- gram completion modified note from va= to pa= added note 2 figure 5. dq7 data polling sequence for erase completion figure 6. dq2 and dq6 polling sequence for erase completion modified note from va= to sa= added note 2 figure 7. dq3 sector erase timer added note figure 8. dq1 write-to-buffer abort extended diagram six more fields and added ? pass. ?
july 24, 2002 using the operation status bits in amd devices 11 supplement trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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