ucc5673 slus438 - february 2000 features ? auto selection multi-mode single ended or low voltage differential termination ? 2.7v to 5.25v operation ? differential failsafe bias ? built-in spi-3 mode change filter/ delay ? meets scsi-1, scsi-2, ultra2 (spi-2 lvd) and ultra3/ultra160 standards ? supports active negation ? 3pf channel capacitance ? reversed disconnect polarity multimode (lvd/se) scsi 9 line terminator 1 27 16 difsens difsens ref 1.3v enable 3 l1? 52 2 l1+ 52 l9? l9+ 56mv +? 56mv ?+ 124 110 se ground switch 26 52 25 52 56mv +? 56mv ?+ 124 110 se ground switch reg 17 diffb 0.6v 2.1v filter/ delay 28 trmpwr trmpwr lv d r e f 1.25v source/sink regulators se ref 2.7v enable sw1 10 a 22 6 hs/gnd hs/gnd 14 gnd 13 discnct se discnct hpd lv d up open down down down up open open mode sw1 other switches hpd lv d se block diagram udg-99162 description the ucc5673 multi-mode low voltage differential and single ended ter - minator is both a single ended terminator and a low voltage differential ter - minator for the transition to the next generation scsi parallel interface (spi-3). the low voltage differential is a requirement for the higher speeds at a reasonable cost and is the only way to have adequate skew budgets. the automatic mode select/change feature switches the terminator be - tween single ended or lvd termination, depending on the bus mode. i f the bus i s i n high voltage differential mode, the terminator lines transition into a high impedance state. the ucc5673 is spi-3, spi-2, and scsi-2 compliant. this device is of - fered in a 2 8 pin tssop package to minimize the footprint. the ucc5673 is also available in a 36 pin mwp package. note: indicated pinout is f or 28 pin tssop pac kage .
2 ucc5673 absolute maximum ratings trmpwr voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v signal line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 5v storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . ?55c to +150c lead temperature (soldering, 10sec.) . . . . . . . . . . . . . +300c all voltages are with respect to gnd. currents are positive into, negative out of the specified terminal. consult packaging sec - tion of the databook for thermal limitations and considerations of packages. recommended operating conditions trmpwr voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.25v diffb l6+ l8? l8+ l7? trmpwr l1+ l4? l3+ l4+ l1? l2+ l2? reg l3? difsens l7+ l6? l5+ gnd 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 l5? n/c discnct l9? l9+ trmpwr hs/gnd hs/gnd connection diagram l3+ hs/gnd l9? l9+ l8? trmpwr n/ c n/ c hs/gnd l2? hs/gnd l1+ l1? l2+ reg hs/gnd l3? l8+ hs/gnd hs/gnd l4+ l4? 14 13 12 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 18 17 16 15 diff b n/c difsens 19 20 21 22 l5+ l5? discnct gnd l7? l7+ l6? l6+ n/ c n/ c n/ c tssop-28 (top view) pwp package qsop-36 (top view) mwp package
3 ucc5673 electrical characteristics unless otherwise stated, these specifications apply for t a =t j = 0c to 70c, trmpwr = 2.7v to 5.25v. parameter test conditions min typ max units trmpwr supply current section trmpwr supply current lvd mode 23 35 ma se mode 14 25 ma discnct mode 250 500 a regulator section 1.25v regulator output voltage lvd mode 1.15 1.25 1.35 v 1.25v regulator source current v reg = 0v ?800 ?420 ?225 ma 1.25v regulator sink current v reg = 3.3v 100 180 420 ma 2.7v regulator output voltage se mode 2.5 2.7 3.0 v 2.7v regulator source current v reg = 0v ?800 ?420 ?225 ma 2.7v regulator sink current v reg = 3.3v 100 180 420 ma diff sense driver (difsens) section 1.3v difsens output voltage difsens 1.2 1.3 1.4 v 1.3v difsens source current v difsens = 0v ?15 ?5 ma 1.3v difsens sink current v difsens = 2.75v 50 200 a differential termination section differential impedance 100 105 110 ? common mode impedance (note 2) 110 150 165 ? differential bias voltage 100 125 mv common mode bias 1.15 1.25 1.35 v output capacitance single ended measurement to ground (note 1) 3 pf single ended termination section impedance z vl v il x x = ? (.) 02 , (note 3) 100 108 116 ? termination current signal level 0.2v, all lines low ?25.4 ?23 ?20 ma signal level 0.5v ?22.4 ?17 ma output leakage 400 na output capacitance single ended measurement to ground (note 1) 3 pf single ended gnd se impedance i = 10ma 20 60 ? disconnect (discnct ) and diff buffer (diffb) input section discnct threshold 0.8 2.0 v discnct input current ?30 ?10 a diffb se to lvd threshold 0.5 0.7 v diffb lvd to hpd threshold 1.9 2.4 v diffb input current ?1 1 a
4 ucc5673 electrical characteristics unless otherwise stated, these specifications apply for t a =t j = 0c to 70c, trmpwr = 2.7v to 5.25v. parameter test conditions min typ max units time delay/filter section mode change delay a new mode change can start any time after a previous mode change has been detected. (note 4 ) 100 180 300 ms note 1: guaranteed by design. not 100% tested in production. note 2: ()() z v ii cm vvvv cm cm = ? +? 12 06 06 . .. ; where vcm = voltage measured with l+ tied to l? and zero current applied; note 3: vl x = output voltage for each terminator minus output pin (l1? through l9?) with each pin unloaded. il x = output current for each terminator minus output pin (l1? through l9?) with the minus output pin forced to 0.2v. note 4: noise on diffb will not cause a false mode change. the time delay is that same for a change from any mode to any other mode. within 300ms after power is applied the mode is defined by the voltage of diffb. pin descriptions diffb: input pin for the comparators that select se, lvd, or hipd modes of operation. this pin should be de- coupled with a 0.1 f capacitor to ground and then cou- pled to the difsens pin through a 20k ? resistor. difsens: connects to the diff sense line of the scsi bus. the bus mode is controlled by the voltage level on this pin. discnct : input pin used to shut down the terminator if the terminator is not connected at the end of the bus. connect this pin to ground to disable the terminator or open pin to activate the terminator. hs/gnd: heat sink ground pins. these should be con- nected to large ground area pc board traces to increase the power dissipation capability. gnd: power supply return. l1? thru l9?: termination lines. these are the active lines in se mode and are the negative lines for lvd mode. in hipd mode, these lines are high impedance. l1+ thru l9+: termination lines. these lines switch to ground in se mode and are the positive lines for lvd mode. in hipd mode, these lines are high impedance. trmpwr: 2.7v to 5.25v power input pin. all scsi buses require a termination network at each end to function properly. specific termination require - ments differ, depending on which types of scsi devices are present on the bus. the ucc5673 is used in multi-mode active termination applications, where single ended (se) and low voltage differential (lvd) devices might coexist. the ucc5673 has both se and lvd termination networks integrated into a single monolithic component. the correct termina - tion network is automatically determined by the scsi bus "difsens" signal. the scsi bus difsens signal line is used to identify which types of scsi devices are present on the bus. on power-up, the ucc5673 difsens drivers will try to de - liver 1.3v to the difsens line. if only lvd devices are present, the difsens line will be successfully driven to 1.3v and the terminators will configure for lvd opera - tion. if any single ended devices are present, they will present a short to ground on the difsens line, signaling the ucc5673(s) to configure into the se mode, accom - modating the se devices. or, if any high voltage differen - tial (hvd) devices are present, the difsens line is pulled high and the terminator will enter a high imped - ance state, effectively disconnecting from the bus. the difsens line is monitored by each terminator through a 50hz noise filter at the diffb input pin. a set of comparators detect and select the appropriate termi - nation for the bus as follows. if the difsens signal is be - application information
5 ucc5673 low 0.5v, the termination network is se. between 0.7v and 1.9v, the termination network switches to lvd, and above 2.4v is hvd, causing the terminators to discon - nect from the bus. the thresholds accommodate differ - ences in ground potential that can occur with long lines. three ucc5673 multi-mode parts are required at each end of the bus to terminate 27 (18 data, plus 9 control) lines. each part includes a difsens driver, but only one is necessary to drive the line. the diffb inputs on all three parts are connected together, allowing them to share the same 50hz noise filter. this multi-mode termi - nator operates in full specification down to 2.7v trmpwr voltage. this accommodates 3.3v systems, with allowance for the 3.3v supply tolerance (+/- 10%), a unidirectional fusing device and cable drop. in 3.3v application information (cont.) reg trmpwr discnct trmpwr diffb reg te r m p o w e r te r m p o w e r 28 13 16 1 17 16 1 28 discnct 13 control lines (9) 20k 20k diff sense 2 2 3 3 4.7 f 0.1 f 25 25 26 26 l1+ l1? l9+ l9? l1+ l1? l9+ l9? 4.7 f diffb 17 0.1 f data lines (9) 4.7 f 4.7 f 4.7 f 4.7 f ucc5673 ucc5673 27 trmpwr 27 trmpwr reg trmpwr discnct diffb 28 13 1 17 2 3 l1+ l1? l9+ l9? 27 trmpwr trmpwr reg 1 28 discnct 13 2 3 l1+ l1? l9+ l9? diffb 17 27 trmpwr 25 25 26 26 data lines (9) 4.7 f 4.7 f reg trmpwr discnct diffb 28 13 1 17 2 3 l1+ l1? l9+ l9? 27 trmpwr trmpwr reg 1 28 discnct 13 2 3 l1+ l1? l9+ l9? diffb 17 27 trmpwr 25 25 26 26 ucc5673 ucc5673 ucc5673 ucc5673 figure 1. application diagram. note: indicated pinout is for 28 pin tssop package. udg-99163
6 ucc5673 unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 trmpwr systems, the ucc3918 is recommended in place of the fuse and diode. the ucc3918's lower volt - age drop allows additional margin over the fuse and di - ode, for the far end terminator. layout is critical for ultra2 and ultra3 systems. the spi-2 standard for capacitance loading is 10pf maximum from each positive and negative signal line to ground, and a maximum of 5pf between the positive and negative sig - nal lines of each pair is allowed. these maximum capaci - tances apply to differential bus termination circuitry that is not part of a scsi device, (e.g. a cable terminator). if the termination circuitry is included as part of a scsi de - vice, (e.g., a host adaptor, disk or tape drive), then the corresponding requirements are 30pf maximum from each positive and negative signal line to ground and 15pf maximum between the positive and negative signal lines of each pair. the spi-2 standard for capacitance balance of each pair and balance between pairs is more stringent. the stan- dard is 0.75pf maximum difference from the positive and negative signal lines of each pair to ground. an additional requirement is a maximum difference of 2pf when com- paring pair to pair. these requirements apply to differen- tial bus termination circuitry that is not part of a scsi device. if the termination circuitry is included as part of a device, then the corresponding balance requirements are 2.25pf maximum difference within a pair, and 3pf from pair to pair. feed-throughs, through-hole connections, and etch lengths need to be carefully balanced. standard multi-layer power and ground plane spacing add about 1pf to each plane. each feed-through will add about 2.5pf to 3.5pf. enlarging the clearance holes on both power and ground planes will reduce the capacitance. similarly, opening up the power and ground planes under the connector will reduce the capacitance for through-hole connector applications. capacitance will also be affected by components, in close proximity, above and below the circuit board. unitrode multi-mode terminators are designed with very tight balance, typically 0.1pf between pins in a pair and 0.3pf between pairs. at each l+ pin, a ground driver drives the pin to ground, while in single ended mode. the ground driver is specially designed to not effect the ca - pacitive balance of the bus when the device is in lvd or disconnect mode. multi-layer boards need to adhere to the 120 ? imped - ance standard, including the connectors and feed- throughs. this is normally done on the outer layers with 4 mil etch and 4 mil spacing between runs within a pair, and a minimum of 8 mil spacing to the adjacent pairs to reduce crosstalk. microstrip technology is normally too low of impedance and should not be used. it is designed for 50 ? rather than 120 ? differential systems. careful consideration must be given to the issue of heat manage- ment. a multi-mode terminator, operating in se mode, will dissipate as much as 130mw of instantaneous power per active line with trmpwr = 5.25v. the ucc5673 is offered in a 28 pin tssop. this package includes two heat sink ground pins. these heat sink/ground pins are directly connected to the die mount paddle under the die and conduct heat from the die to reduce the junction tem - perature. both of the hs/gnd pins need to be connected to etch area or four feed-through per pin connecting to the ground plane layer on a multi-layer board. application information (cont.)
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