View CY2285_1362097.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

100-mhz pentium ? ii clock synthesizer/driver with spread spectrum for mobile pcs CY2285 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07205 rev. *a revised december 14, 2002 0 features ? mixed 2.5v and 3.3v operation complete clock solution for pentium ? ii, and other sim- ilar processor-based motherboards ? two cpu clocks at 2.5v up to 100 mhz ? six synchronous pci clocks, one free-running ? two 3.3v reference clocks at 14.318 mhz ? one 3.3v usb clock running at 48 mhz ? one 3.3v usb/io clock running at 48 mhz/24 mhz spread spectrum clocking for emi control 1.5 ? 4.0 ns delay between cpu and pci clocks power-down, cpu stop and pci stop pins low skew outputs, 175 ps between cpu clocks early pci clock leads pci by 1 ? 4 ns (-2 option) div4 allows dynamic shifting of cpu and pci clocks from the default frequency to default/4 (-2 option) factory-eprom programmable output drive and slew rate for emi customization available in space-saving 28-pin ssop package functional description the CY2285 is a clock synthesizer/driver for pentium ii, or other similar processor-based mobile pcs requiring up to 100-mhz support. the CY2285 outputs two cpu clocks at 2.5v. there are six pci clocks, running at one-half or one-third the cpu clock frequency of 66.6 mhz and 100 mhz respec- tively. one of the pci clocks is free-running. additionally, the part outputs two 3.3v reference clocks at 14.318 mhz. the CY2285 incorporates the intel ? -defined spread spectrum features. it provides a ? 0.6% downspread on the cpu and pci clocks, which can help reduce emi in certain high-speed sys- tems. the CY2285 possesses power-down, cpu stop, and pci stop pins for power management control. the signals are synchro- nized on-chip, and ensure glitch-free transitions on the out- puts. when the cpu_stop input is asserted, the cpu clock outputs are driven low. when the pci_stop input is assert- ed, the pci clock outputs (except the free-running pci clock) are driven low. when the pwr_dwn pin is asserted, the reference oscillator and plls are shut down, and all outputs are driven low. the CY2285-2 features an early pci clock which leads the other pci clocks by 1 ? 4 ns. the CY2285-2 also features a div4 pin which allows for dynamic shifting of cpu and pci clocks from the default frequency to the default/4. notes: 1. one free-running pci clock. 2. one early pci clock. CY2285 selector guide clock outputs CY2285-1 CY2285-2 CY2285-3 cpu (66, 100 mhz) 222 pci (cpu/2, cpu/3 mhz) 6 [1] 7 [1, 2] 6 [1] ref. (14.318 mhz) 2 2 1 usb (48 mhz) 1 1 1 usb/io (48 mhz/24 mhz selectable) 1n/a1 cpu-pci delay 1.5 ? 4.0 ns 1.5 ? 4.0 ns 1.5 ? 4.0 ns epci-pci delay n/a 1.0 ? 4.0 ns n/a spread spectrum ? 0.6% downsprea d ? 0.6% downsprea d ? 0.6% downsprea d intel and pentium are registered trademarks of intel corporation. logic block diagram eprom xtalout xtalin 14.318 mhz osc. cpu pll delay ref1/sel48 cpuclk [0 ? 1] v ddcpu pciclk [1-5] epciclk (-2 option) stop stop logic logic cpu_stop div4 divider pci_stop v ddpci v ddpci v ddref ref0/spread sys pll usbclk v dd48 usb_ioclk/ts (-1 option) v dd48 pciclk_f v ddpci pwr_dwn usbclk/sel100/66 (-2 option) /4 spread (-2,-3 option) ref0 (-2 option) ref1 (-2,-3 option)
CY2285 document #: 38-07205 rev. *a page 2 of 10 pin configurations pin summary: CY2285-1, CY2285-3 name pins description v dd 8, 12, 19, 28 3.3v power supply voltage v ddcpu 25 2.5v power supply for cpu clocks v ss 1, 7, 15, 21, 22 ground xtalin [3] 2 reference crystal input xtalout [3] 3 reference crystal feedback pci_stop 20 active low control input to stop pci clocks cpu_stop 18 active low control input to stop cpu clocks pwr_dwn 17 active low control input to power down device sel100 16 select for enabling 100-mhz or 66-mhz cpu clock high = 100 mhz, low = 66 mhz cpuclk[0:1] 23, 24 2.5v cpu clock outputs pciclk[1:5] 5, 6, 9, 10, 11 3.3v pci clock outputs pciclk_f 4 3.3v free-running pci clock output ref0/spread 26 (-1 option) 3.3v 14.318-mhz reference clock output and power-on spread spectrum enable strap option. strap low = spread spectrum enable strap high = spread spectrum disable spread 26 (-3 option) active low control input to enable spread spectrum ref1/sel48 27 3.3v 14.318-mhz reference clock output and power-on 48-/24-mhz se- lect strap option. strap low = 48 mhz on pin14 strap high = 24 mhz on pin14 usbclk 13 3.3v 48-mhz usb clock output usb_ioclk/ts 14 3.3v 48-mhz or 24-mhz output and three-state strapping option. strap low = enter three-state mode for testing strap high = normal operation note: 3. for best accuracy, use a parallel-resonant crystal, c load = 18 pf. pwrdwn 1 2 3 4 5 6 7 8 9 10 11 12 16 15 ssop top view 13 14 25 24 23 22 21 17 18 19 20 28 27 26 CY2285-1 v ssref xtal_in pciclk_f xtal_out pciclk1 v sspci pciclk2 v ddpci pciclk4 v dd48 pciclk5 usbclk usb_ioclk/ts ref1/sel48 ref0/spread v ddcpu cpuclk0 cpuclk1 v sscpu v sscore v ddcore sel100 v ss48 cpu_stop pci_stop v ddref pciclk3 pwrdwn 1 2 3 4 5 6 7 8 9 10 11 12 16 15 ssop top view 13 14 25 24 23 22 21 17 18 19 20 28 27 26 CY2285-2 ref0 xtal_in pciclk_f xtal_out pciclk1 v sspci pciclk2 v ddpci pciclk4 epciclk pciclk5 v dd48 usbclk/sel100/66 ref1 spread v ddcpu cpuclk0 cpuclk1 v sscpu v sscore v ddcore div4 v ss48 cpu_stop pci_stop v ddref pciclk3 pwrdwn 1 2 3 4 5 6 7 8 9 10 11 12 16 15 ssop top view 13 14 25 24 23 22 21 17 18 19 20 28 27 26 CY2285-3 v ssref xtal_in pciclk_f xtal_out pciclk1 v sspci pciclk2 v ddpci pciclk4 v dd48 pciclk5 usbclk usb_ioclk/ts ref1/sel48 spread v ddcpu cpuclk0 cpuclk1 v sscpu v sscore v ddcore sel100 v ss48 cpu_stop pci_stop v ddref pciclk3
CY2285 document #: 38-07205 rev. *a page 3 of 10 pin summary: CY2285-2 name pins description v dd 8, 13, 19, 28 3.3v power supply v ddcpu 25 2.5v power supply v ss 7, 15, 21, 22 ground xtalin [3] 2 reference crystal input xtalout [3] 3 reference crystal feedback pci_stop 20 active low control input to stop pci clocks cpu_stop 18 active low control input to stop cpu clocks pwr_dwn 17 active low control input to power down device div4 16 active low control input to enable divide-by-four option on cpu and pci clocks cpuclk[0:1] 23, 24 2.5v cpu clock outputs pciclk[1:5] 5, 6, 9, 10, 11 3.3v pci clock outputs pciclk_f 4 3.3v free-running pci clock output epciclk 12 3.3v early pci clock output (not free-running) ref0 1 3.3v 14.318-mhz reference clock output ref1 27 3.3v 14.318-mhz reference clock output usbclk/sel100/66 14 3.3v 48-mhz usb clock output or select input and frequency select strap option (use 10-k ? external strap resistor) strap low = 66.6-mhz cpu frequency strap high = 100-mhz cpu frequency spread 26 active low control input to enable spread spectrum actual clock frequency values clock output target frequency (mhz) actual frequency (mhz) ppm cpuclk 66.67 66.654 ? 240 cpuclk 100 99.77 ? 2300 usb 48-mhz 48 48.008 +167 power management logic cpu_stop pci_stop pwr_dwn cpuclk pciclk pciclk_f other clocks osc. plls x x 0 low low low low off off 0 0 1 low low running running running running 0 1 1 low running running running running running 1 0 1 running low running running running running 1 1 1 running running running running running running
CY2285 document #: 38-07205 rev. *a page 4 of 10 function table: CY2285-1 sel100 sel48 [4] ts [4] spread [4] cpuclk[0:1] pciclk[1:5], pciclk_f usb_ioclk usbclk refclk [0-1] x x 0 x hi-z hi-z hi-z hi-z hi-z 0 1 1 1 (no spread) 66.6 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 0010 ( ? 0.6% downspread) 66.6 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz 1 1 1 1 (no spread) 100 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 1010 ( ? 0.6% downspread) 100 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz function table: CY2285-2 sel100/66 [4] spread div4 cpuclk [0:1] pciclk[1:5], pciclk_f, epciclk usbclk refclk[0:1] 00 ( ? 0.6% downspread) 1 66.67 mhz 33.3 mhz 48 mhz 14.318 mhz 0 1 (no spread) 1 66.67 mhz 33.3 mhz 48 mhz 14.318 mhz 10 ( ? 0.6% downspread) 1 100 mhz 33.3 mhz 48 mhz 14.318 mhz 1 1 (no spread) 1 100 mhz 33.3 mhz 48 mhz 14.318 mhz 00 ( ? 0.6% downspread) 0 16.67 mhz 8.33 mhz 48 mhz 14.318 mhz 0 1 (no spread) 0 16.67 mhz 8.33 mhz 48 mhz 14.318 mhz 10 ( ? 0.6% downspread) 0 25.0 mhz 8.33 mhz 48 mhz 14.318 mhz 1 1 (no spread) 0 25.0 mhz 8.33 mhz 48 mhz 14.318 mhz function table: CY2285-3 sel100 sel48 [4] ts [4] spread [4] cpuclk[0:1] pciclk[1:5], pciclk_f usb_ioclk usbclk refclk1 x x 0 x hi-z hi-z hi-z hi-z hi-z 0 1 1 1 (no spread) 66.6 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 0010 ( ? 0.6% downspread) 66.6 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz 1 1 1 1 (no spread) 100 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 1010 ( ? 0.6% downspread) 100 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz note: 4. power-on strap option.
CY2285 document #: 38-07205 rev. *a page 5 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage .................................................. ? 0.5 to +7.0v input voltage .............................................. ? 0.5v to v dd +0.5 storage temperature (non-condensing) ... ? 65 c to +150 c junction temperature............................................... +150 c static discharge voltage............................................ >2000v (per mil-std-883, method 3015, like v dd pins tied together) operating conditions [5] parameter description min. max. unit v dd analog and digital 3.3v supply voltage 3.135 3.465 v v ddcpu cpu supply voltage 2.375 2.625 v t a operating temperature, ambient 0 70 c c l max. capacitive load on cpuclk pciclk ref 20 30 35 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics over the operating range parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs [6] 2.0 v v il low-level input voltage except crystal inputs [6] 0.8 v v oh high-level output voltage v ddcpu = 2.375v i oh = 12 ma cpuclk 2.0 v v ol low-level output voltage v ddcpu = 2.375v i ol = 12 ma cpuclk 0.4 v v oh high-level output voltage v ddpci , av dd , v ddref = 3.135v i oh = 14.5 ma pciclk 2.4 v i oh = 16 ma ref i oh = 36 ma ref [7] v ol low-level output voltage v ddpci , av dd , v ddref = 3.135v i ol = 9.4 ma pciclk 0.4v v i ol = 9 ma ref i ol = 29 ma ref [7] i ih input high current v ih = v dd ? 10 +10 a i il input low current v il = 0v 10 a i oz output leakage current three-state ? 10 +10 a i dd25 power supply current for 2.5v clocks v ddcpu = 2.625v, v in = 0 or v dd , loaded outputs, cpu = 66.6 mhz 70 ma i dd25 power supply current for 2.5v clocks v ddcpu = 2.625v, v in = 0 or v dd , loaded outputs, cpu = 100 mhz 100 ma i dd33 power supply current for 3.3v clocks v dd = 3.465v, v in = 0 or v dd , loaded outputs 170 ma i dds powerdown current current draw in powerdown state 500 a notes: 5. electrical parameters are guaranteed with these operating conditions. 6. crystal inputs have cmos thresholds, nominally v dd /2. 7. CY2285-2 option only.
CY2285 document #: 38-07205 rev. *a page 6 of 10 switching characteristics [8] over the operating range parameter output description test conditions min. typ. max. unit t 1 all output duty cycle [9] t 1 = t 1a t 1b 45 50 55 % t 2 cpuclk cpu clock rising and falling edge rate between 0.4v and 2.0v 1.0 4.0 v/ns t 2 pciclk pci clock rising and falling edge rate between 0.4v and 2.4v 1.0 4.0 v/ns t 2 ref ref clock rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 cpuclk cpu clock rise time between 0.4v and 2.0v 0.4 1.6 ns t 4 cpuclk cpu clock fall time between 2.0v and 0.4v 0.4 1.6 ns t 5 cpuclk cpu-cpu clock skew measured at 1.25v 100 175 ps t 6 cpuclk, pciclk cpu-pci clock skew measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks 1.5 4.0 ns t 7 pciclk, pciclk pci-pci clock skew measured at 1.5v 250 ps t 7 epciclk, pciclk epci-pci clock skew [7] measured at 1.5v 1.0 4.0 ns t 10 cpuclk cycle-cycle clock jitter measured at 1.25v 700 ps t 11 pciclk cycle-cycle clock jitter measured at 1.5v 500 ps t 12 cpuclk, pciclk power-up time cpu and pci clock stabilization from power-up 3 ms t 13 cpuclk, pciclk /4 frequency slew time [7] time for cpu, epci, and pci clock frequency to change from f to f/4 after select input change 10 25 cycles notes: 8. all parameters specified with loaded outputs. 9. duty cycle is measured at 1.5v when v dd = 3.3v. when v dd = 2.5v, duty cycle is measured at 1.25v.
CY2285 document #: 38-07205 rev. *a page 7 of 10 switching waveforms duty cycle timing t 1a t 1b output all outputs rise/fall time output t 2 t 3 v dd 0v t 2 t 4 cpu-cpu clock skew t 5 cpuclk cpuclk cpu-pci clock skew cpuclk t 6 pciclk t 7 pci/epciclk pciclk pci/epci-pci clock skew cpuclk (internal) pciclk (internal) pciclk (free-running) cpu_stop cpuclk (external) cpu_stop
CY2285 document #: 38-07205 rev. *a page 8 of 10 switching waveforms (continued) pci_stop cpuclk (internal) pciclk (internal) pciclk pci_stop pciclk (external) (free-running) pwr_down cpuclk (internal) pciclk (internal) pwr_dwn pciclk cpuclk (external) (external) vco crystal shaded section on the vco and crystal waveforms indicates that the vco and crystal oscillator are active, and there is a valid clock. ordering information ordering code package name package type operating range CY2285pvc-1 o28 28-pin ssop commercial CY2285pvc-2 o28 28-pin ssop commercial CY2285pvc-3 o28 28-pin ssop commercial
CY2285 document #: 38-07205 rev. *a page 9 of 10 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 28-lead (210-mil) shrunk small outline package o28 51-85079-c
CY2285 document #: 38-07205 rev. *a page 10 of 10 revision history document title: CY2285 100-mhz pentium ? ii clock synthesizer/driver with spread spectrum for mobile pcs document number: 38-07205 rev. ecn no. issue date orig. of change description of change ** 111725 12/16/01 dsg change from spec number: 38-00732 to 38-07205 *a 121840 12/14/02 rbi power up requirements added to operating conditions information
100-mhz pentium ? ii clock synthesizer/driver with spread spectrum for mobile pcs CY2285 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07205 rev. *a revised december 14, 2002 0 features mixed 2.5v and 3.3v operation complete clock solution for pentium ? ii, and other sim- ilar processor-based motherboards ? two cpu clocks at 2.5v up to 100 mhz ? six synchronous pci clocks, one free-running ? two 3.3v reference clocks at 14.318 mhz ? one 3.3v usb clock running at 48 mhz ? one 3.3v usb/io clock running at 48 mhz/24 mhz spread spectrum clocking for emi control 1.5 ? 4.0 ns delay between cpu and pci clocks power-down, cpu stop and pci stop pins low skew outputs, 175 ps between cpu clocks early pci clock leads pci by 1 ? 4 ns (-2 option) div4 allows dynamic shifting of cpu and pci clocks from the default frequency to default/4 (-2 option) factory-eprom programmable output drive and slew rate for emi customization available in space-saving 28-pin ssop package functional description the CY2285 is a clock synthesizer/driver for pentium ii, or other similar processor-based mobile pcs requiring up to 100-mhz support. the CY2285 outputs two cpu clocks at 2.5v. there are six pci clocks, running at one-half or one-third the cpu clock frequency of 66.6 mhz and 100 mhz respec- tively. one of the pci clocks is free-running. additionally, the part outputs two 3.3v reference clocks at 14.318 mhz. the CY2285 incorporates the intel ? -defined spread spectrum features. it provides a ? 0.6% downspread on the cpu and pci clocks, which can help reduce emi in certain high-speed sys- tems. the CY2285 possesses power-down, cpu stop, and pci stop pins for power management control. the signals are synchro- nized on-chip, and ensure glitch-free transitions on the out- puts. when the cpu_stop input is asserted, the cpu clock outputs are driven low. when the pci_stop input is assert- ed, the pci clock outputs (except the free-running pci clock) are driven low. when the pwr_dwn pin is asserted, the reference oscillator and plls are shut down, and all outputs are driven low. the CY2285-2 features an early pci clock which leads the other pci clocks by 1 ? 4 ns. the CY2285-2 also features a div4 pin which allows for dynamic shifting of cpu and pci clocks from the default frequency to the default/4. notes: 1. one free-running pci clock. 2. one early pci clock. CY2285 selector guide clock outputs CY2285-1 CY2285-2 CY2285-3 cpu (66, 100 mhz) 222 pci (cpu/2, cpu/3 mhz) 6 [1] 7 [1, 2] 6 [1] ref. (14.318 mhz) 2 2 1 usb (48 mhz) 1 1 1 usb/io (48 mhz/24 mhz selectable) 1n/a1 cpu-pci delay 1.5 ? 4.0 ns 1.5 ? 4.0 ns 1.5 ? 4.0 ns epci-pci delay n/a 1.0 ? 4.0 ns n/a spread spectrum ? 0.6% downsprea d ? 0.6% downsprea d ? 0.6% downsprea d intel and pentium are registered trademarks of intel corporation. logic block diagram eprom xtalout xtalin 14.318 mhz osc. cpu pll delay ref1/sel48 cpuclk [0 ? 1] v ddcpu pciclk [1-5] epciclk (-2 option) stop stop logic logic cpu_stop div4 divider pci_stop v ddpci v ddpci v ddref ref0/spread sys pll usbclk v dd48 usb_ioclk/ts (-1 option) v dd48 pciclk_f v ddpci pwr_dwn usbclk/sel100/66 (-2 option) /4 spread (-2,-3 option) ref0 (-2 option) ref1 (-2,-3 option)
CY2285 document #: 38-07205 rev. *a page 2 of 10 pin configurations pin summary: CY2285-1, CY2285-3 name pins description v dd 8, 12, 19, 28 3.3v power supply voltage v ddcpu 25 2.5v power supply for cpu clocks v ss 1, 7, 15, 21, 22 ground xtalin [3] 2 reference crystal input xtalout [3] 3 reference crystal feedback pci_stop 20 active low control input to stop pci clocks cpu_stop 18 active low control input to stop cpu clocks pwr_dwn 17 active low control input to power down device sel100 16 select for enabling 100-mhz or 66-mhz cpu clock high = 100 mhz, low = 66 mhz cpuclk[0:1] 23, 24 2.5v cpu clock outputs pciclk[1:5] 5, 6, 9, 10, 11 3.3v pci clock outputs pciclk_f 4 3.3v free-running pci clock output ref0/spread 26 (-1 option) 3.3v 14.318-mhz reference clock output and power-on spread spectrum enable strap option. strap low = spread spectrum enable strap high = spread spectrum disable spread 26 (-3 option) active low control input to enable spread spectrum ref1/sel48 27 3.3v 14.318-mhz reference clock output and power-on 48-/24-mhz se- lect strap option. strap low = 48 mhz on pin14 strap high = 24 mhz on pin14 usbclk 13 3.3v 48-mhz usb clock output usb_ioclk/ts 14 3.3v 48-mhz or 24-mhz output and three-state strapping option. strap low = enter three-state mode for testing strap high = normal operation note: 3. for best accuracy, use a parallel-resonant crystal, c load = 18 pf. pwrdwn 1 2 3 4 5 6 7 8 9 10 11 12 16 15 ssop top view 13 14 25 24 23 22 21 17 18 19 20 28 27 26 CY2285-1 v ssref xtal_in pciclk_f xtal_out pciclk1 v sspci pciclk2 v ddpci pciclk4 v dd48 pciclk5 usbclk usb_ioclk/ts ref1/sel48 ref0/spread v ddcpu cpuclk0 cpuclk1 v sscpu v sscore v ddcore sel100 v ss48 cpu_stop pci_stop v ddref pciclk3 pwrdwn 1 2 3 4 5 6 7 8 9 10 11 12 16 15 ssop top view 13 14 25 24 23 22 21 17 18 19 20 28 27 26 CY2285-2 ref0 xtal_in pciclk_f xtal_out pciclk1 v sspci pciclk2 v ddpci pciclk4 epciclk pciclk5 v dd48 usbclk/sel100/66 ref1 spread v ddcpu cpuclk0 cpuclk1 v sscpu v sscore v ddcore div4 v ss48 cpu_stop pci_stop v ddref pciclk3 pwrdwn 1 2 3 4 5 6 7 8 9 10 11 12 16 15 ssop top view 13 14 25 24 23 22 21 17 18 19 20 28 27 26 CY2285-3 v ssref xtal_in pciclk_f xtal_out pciclk1 v sspci pciclk2 v ddpci pciclk4 v dd48 pciclk5 usbclk usb_ioclk/ts ref1/sel48 spread v ddcpu cpuclk0 cpuclk1 v sscpu v sscore v ddcore sel100 v ss48 cpu_stop pci_stop v ddref pciclk3
CY2285 document #: 38-07205 rev. *a page 3 of 10 pin summary: CY2285-2 name pins description v dd 8, 13, 19, 28 3.3v power supply v ddcpu 25 2.5v power supply v ss 7, 15, 21, 22 ground xtalin [3] 2 reference crystal input xtalout [3] 3 reference crystal feedback pci_stop 20 active low control input to stop pci clocks cpu_stop 18 active low control input to stop cpu clocks pwr_dwn 17 active low control input to power down device div4 16 active low control input to enable divide-by-four option on cpu and pci clocks cpuclk[0:1] 23, 24 2.5v cpu clock outputs pciclk[1:5] 5, 6, 9, 10, 11 3.3v pci clock outputs pciclk_f 4 3.3v free-running pci clock output epciclk 12 3.3v early pci clock output (not free-running) ref0 1 3.3v 14.318-mhz reference clock output ref1 27 3.3v 14.318-mhz reference clock output usbclk/sel100/66 14 3.3v 48-mhz usb clock output or select input and frequency select strap option (use 10-k ? external strap resistor) strap low = 66.6-mhz cpu frequency strap high = 100-mhz cpu frequency spread 26 active low control input to enable spread spectrum actual clock frequency values clock output target frequency (mhz) actual frequency (mhz) ppm cpuclk 66.67 66.654 ? 240 cpuclk 100 99.77 ? 2300 usb 48-mhz 48 48.008 +167 power management logic cpu_stop pci_stop pwr_dwn cpuclk pciclk pciclk_f other clocks osc. plls x x 0 low low low low off off 0 0 1 low low running running running running 0 1 1 low running running running running running 1 0 1 running low running running running running 1 1 1 running running running running running running
CY2285 document #: 38-07205 rev. *a page 4 of 10 function table: CY2285-1 sel100 sel48 [4] ts [4] spread [4] cpuclk[0:1] pciclk[1:5], pciclk_f usb_ioclk usbclk refclk [0-1] x x 0 x hi-z hi-z hi-z hi-z hi-z 0 1 1 1 (no spread) 66.6 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 0010 ( ? 0.6% downspread) 66.6 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz 1 1 1 1 (no spread) 100 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 1010 ( ? 0.6% downspread) 100 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz function table: CY2285-2 sel100/66 [4] spread div4 cpuclk [0:1] pciclk[1:5], pciclk_f, epciclk usbclk refclk[0:1] 00 ( ? 0.6% downspread) 1 66.67 mhz 33.3 mhz 48 mhz 14.318 mhz 0 1 (no spread) 1 66.67 mhz 33.3 mhz 48 mhz 14.318 mhz 10 ( ? 0.6% downspread) 1 100 mhz 33.3 mhz 48 mhz 14.318 mhz 1 1 (no spread) 1 100 mhz 33.3 mhz 48 mhz 14.318 mhz 00 ( ? 0.6% downspread) 0 16.67 mhz 8.33 mhz 48 mhz 14.318 mhz 0 1 (no spread) 0 16.67 mhz 8.33 mhz 48 mhz 14.318 mhz 10 ( ? 0.6% downspread) 0 25.0 mhz 8.33 mhz 48 mhz 14.318 mhz 1 1 (no spread) 0 25.0 mhz 8.33 mhz 48 mhz 14.318 mhz function table: CY2285-3 sel100 sel48 [4] ts [4] spread [4] cpuclk[0:1] pciclk[1:5], pciclk_f usb_ioclk usbclk refclk1 x x 0 x hi-z hi-z hi-z hi-z hi-z 0 1 1 1 (no spread) 66.6 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 0010 ( ? 0.6% downspread) 66.6 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz 1 1 1 1 (no spread) 100 mhz 33.3 mhz 24 mhz 48 mhz 14.318 mhz 1010 ( ? 0.6% downspread) 100 mhz 33.3 mhz 48 mhz 48 mhz 14.318 mhz note: 4. power-on strap option.
CY2285 document #: 38-07205 rev. *a page 5 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage .................................................. ? 0.5 to +7.0v input voltage .............................................. ? 0.5v to v dd +0.5 storage temperature (non-condensing) ... ? 65 c to +150 c junction temperature............................................... +150 c static discharge voltage............................................ >2000v (per mil-std-883, method 3015, like v dd pins tied together) operating conditions [5] parameter description min. max. unit v dd analog and digital 3.3v supply voltage 3.135 3.465 v v ddcpu cpu supply voltage 2.375 2.625 v t a operating temperature, ambient 0 70 c c l max. capacitive load on cpuclk pciclk ref 20 30 35 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics over the operating range parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs [6] 2.0 v v il low-level input voltage except crystal inputs [6] 0.8 v v oh high-level output voltage v ddcpu = 2.375v i oh = 12 ma cpuclk 2.0 v v ol low-level output voltage v ddcpu = 2.375v i ol = 12 ma cpuclk 0.4 v v oh high-level output voltage v ddpci , av dd , v ddref = 3.135v i oh = 14.5 ma pciclk 2.4 v i oh = 16 ma ref i oh = 36 ma ref [7] v ol low-level output voltage v ddpci , av dd , v ddref = 3.135v i ol = 9.4 ma pciclk 0.4v v i ol = 9 ma ref i ol = 29 ma ref [7] i ih input high current v ih = v dd ? 10 +10 a i il input low current v il = 0v 10 a i oz output leakage current three-state ? 10 +10 a i dd25 power supply current for 2.5v clocks v ddcpu = 2.625v, v in = 0 or v dd , loaded outputs, cpu = 66.6 mhz 70 ma i dd25 power supply current for 2.5v clocks v ddcpu = 2.625v, v in = 0 or v dd , loaded outputs, cpu = 100 mhz 100 ma i dd33 power supply current for 3.3v clocks v dd = 3.465v, v in = 0 or v dd , loaded outputs 170 ma i dds powerdown current current draw in powerdown state 500 a notes: 5. electrical parameters are guaranteed with these operating conditions. 6. crystal inputs have cmos thresholds, nominally v dd /2. 7. CY2285-2 option only.
CY2285 document #: 38-07205 rev. *a page 6 of 10 switching characteristics [8] over the operating range parameter output description test conditions min. typ. max. unit t 1 all output duty cycle [9] t 1 = t 1a t 1b 45 50 55 % t 2 cpuclk cpu clock rising and falling edge rate between 0.4v and 2.0v 1.0 4.0 v/ns t 2 pciclk pci clock rising and falling edge rate between 0.4v and 2.4v 1.0 4.0 v/ns t 2 ref ref clock rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 cpuclk cpu clock rise time between 0.4v and 2.0v 0.4 1.6 ns t 4 cpuclk cpu clock fall time between 2.0v and 0.4v 0.4 1.6 ns t 5 cpuclk cpu-cpu clock skew measured at 1.25v 100 175 ps t 6 cpuclk, pciclk cpu-pci clock skew measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks 1.5 4.0 ns t 7 pciclk, pciclk pci-pci clock skew measured at 1.5v 250 ps t 7 epciclk, pciclk epci-pci clock skew [7] measured at 1.5v 1.0 4.0 ns t 10 cpuclk cycle-cycle clock jitter measured at 1.25v 700 ps t 11 pciclk cycle-cycle clock jitter measured at 1.5v 500 ps t 12 cpuclk, pciclk power-up time cpu and pci clock stabilization from power-up 3 ms t 13 cpuclk, pciclk /4 frequency slew time [7] time for cpu, epci, and pci clock frequency to change from f to f/4 after select input change 10 25 cycles notes: 8. all parameters specified with loaded outputs. 9. duty cycle is measured at 1.5v when v dd = 3.3v. when v dd = 2.5v, duty cycle is measured at 1.25v.
CY2285 document #: 38-07205 rev. *a page 7 of 10 switching waveforms duty cycle timing t 1a t 1b output all outputs rise/fall time output t 2 t 3 v dd 0v t 2 t 4 cpu-cpu clock skew t 5 cpuclk cpuclk cpu-pci clock skew cpuclk t 6 pciclk t 7 pci/epciclk pciclk pci/epci-pci clock skew cpuclk (internal) pciclk (internal) pciclk (free-running) cpu_stop cpuclk (external) cpu_stop
CY2285 document #: 38-07205 rev. *a page 8 of 10 switching waveforms (continued) pci_stop cpuclk (internal) pciclk (internal) pciclk pci_stop pciclk (external) (free-running) pwr_down cpuclk (internal) pciclk (internal) pwr_dwn pciclk cpuclk (external) (external) vco crystal shaded section on the vco and crystal waveforms indicates that the vco and crystal oscillator are active, and there is a valid clock. ordering information ordering code package name package type operating range CY2285pvc-1 o28 28-pin ssop commercial CY2285pvc-2 o28 28-pin ssop commercial CY2285pvc-3 o28 28-pin ssop commercial
CY2285 document #: 38-07205 rev. *a page 9 of 10 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 28-lead (210-mil) shrunk small outline package o28 51-85079-c
CY2285 document #: 38-07205 rev. *a page 10 of 10 revision history document title: CY2285 100-mhz pentium ? ii clock synthesizer/driver with spread spectrum for mobile pcs document number: 38-07205 rev. ecn no. issue date orig. of change description of change ** 111725 12/16/01 dsg change from spec number: 38-00732 to 38-07205 *a 121840 12/14/02 rbi power up requirements added to operating conditions information

▲Up To Search▲

Price & Availability of CY2285

	To Download CY2285 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .