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rev.0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ADMCF341 dashdsp 28-lead flash mixed-signal dsp with enhanced analog front end functional block diagram memory block program rom 4k x 24 program flash 4k x 24 program ram 512 x 24 data memory 512 x 16 v ref analog inputs 16-bit three- phase pwm por timer serial port sport 0 pio 2 x 16-bit aux pwm watch- dog timer adsp-21xx base architecture data address generators dag 1 dag 2 program sequencer arithmetic units shifter mac alu program memory address data memory address program memory data data memory data 2.5v sport 1 motor control peripherals adc subsystem i sense amp and trip sha 3 timers multiplexed on external pins 3 6 9 7 2 dashdsp is a trademark of analog devices, inc. features 20 mhz fixed-point dsp core single-cycle instruction execution (50 ns) adsp-21xx family code compatibility independent computational units alu, multiplier/accumulator, barrel shifter multifunction instructions single-cycle context switch powerful program sequencer zero overhead looping conditional instruction execution two independent data address generators memory con?guration 512 16-bit data memory ram 512 24-bit program memory ram 4k 24-bit program memory rom 4k 24-bit program flash memory three independent flash memory sectors 3584 24-bit, 256 24-bit, 256 24-bit low-cost pin-compatible rom option 16-bit watchdog timer programmable 16-bit internal timer with prescaler two double buffered serial ports with spi mode support integrated power-on reset function three-phase 16-bit pwm generation unit: 16-bit center-based pwm generator programmable pwm pulsewidth edge resolution to 50 ns 153 hz minimum switching frequency double/single duty cycle update mode control individual enable and disable for each pwm output high-frequency chopping mode for transformer coupled gate drives external pwmtrip pin integrated 6-channel adc subsystem three bipolar i sense i nputs with programmable sample-and-hold amplifier and overcurrent pro- t ec ti on (usable as three dedicated analog inputs) muxed auxiliary analog inputs internal voltage reference (2.5 v) acquisition synchronized to pwm switching frequency 9-pin digital i/o port bit con?gurable as input or output change of state interrupt support two 16-bit auxiliary pwm timers synthesized analog output programmable frequency 0% to 100% duty cycle two programmable operational modes independent mode/offset mode motor types permanent magnet synchronous motors (pmsm) brushless dc motors (bdcm) ac induction motors (acim) applications refrigerator and air conditioner compressor washing machines industrial variable speed drives hvac
rev. 0 ?2? ADMCF341especifications analog-to-digital converter parameter min typ max unit conditions/comments signal input 0.3 3.5 v vaux0, vaux1, vaux2 resolution 1 12 bits linearity error 2 3 4 bits zero offset 3 e32 0 +7 mv comparator delay 600 ns adc high level input current 2 +10 m av in = 3.5 v adc low level input current 2 e10 m av in = 0.0 v notes 1 resolution varies with pwm switching frequency (double update mode) 78.1 khz = 8 bits, 4.9 khz = 12 bits. 2 2.44khz sample frequency, vaux0, vaux1, vaux2. 3 extrapolated point outside of operating range. 2.44khz sample frequency. specifications subject to change without notice. i sense amplifieretrip parameter min typ max unit conditions/comments i sense signal operating range e400 +400 mv i sense signal input range e800 +800 mv i sense gain e2.6 e2.51 e2.34 % v in = e400 mv to +400 mv i sense gain channel matching 5.5 % v in = e400 mv to +400 mv i sense gain stability 1 0.8 % v in = e400 mv to +400 mv i sense linearity 2 89 bits i sense internal offset voltage 2 1.68 1.87 2.1 v i sense internal offset stability 2 2.1 % i sense signal-to-noise ratio (snrd) 3 51 db i sense signal-to-noise ratio less distortion 54 db (snr) 3 e40 db i sense total harmonic distortion 3 e53 db i sense input current e130 +10 m av in = e400 mv to +400 mv i sense input resistance 11.5 k w trip threshold low e690 e430 mv trip threshold high +430 +690 mv trip minimum pulsewidth 4 5 m s notes 1 variation of gain with v dd and temperature. 2 v in = e400 mv to +400 mv. 3 f in = 1 khz sine wave, v in = e400 mv to +400 mv, f s = 4 khz. 4 high or low trip threshold. current source 1 parameter min typ max unit conditions/comments programming resolution 3 bits tuned current 2 91 100 109 m a notes 1 for adc calibration. 2 0.3 v to 3.5 v i const voltage. (v dd = 5%, gnd = 0 v. t a = e40 c to +85 c. clkin = 10 mhz, unless otherwise noted.)
rev. 0 ADMCF341 ?3? voltage reference parameter min typ max unit conditions/comments voltage level (v ref )2.44 2.50 2.55 v e40 m av in = 0 v i il low level input current e10 m av in = 0 v i ih high level input current reset pin 3 30 m av in = v dd i ih high level input current 4 100 m av in = v dd i ih high level input current 10 m av in = v dd i ozh high level three-state leakage current 5 100 m av in = v dd i ozl low level three-state leakage current 5 e10 m av in = 0 v i dd supply current (idle) 6 55 ma v dd = 5.25 v i dd supply current (dynamic) 6 135 ma v dd = 5.25 v notes 1 output pins pio0-pio8, ah, al, bh, bl, ch, cl. 2 xtal pin. 3 internal pull-up, reset. 4 internal pull-down, pwmtrip, pio0-pio8. 5 three stateable pins, dt1, rfs1, tfs1, sclk1. 6 outputs not switching. specitcations subject to change without notice.
rev. 0 ?4? ADMCF341 specifications (continued) flash memory parameter min typ max unit conditions/comments endurance 10,000 cycles cycle = erase/program/verify data retention 15 years program and erase operating temperature 0 85 ttns ns ns ns ckh ck =-= -= 05 10 05 50 10 15 .. timing requirements: t ckin clkin period 100 150 ns t ckil clkin width low 20 ns t ckih clkin width high 20 ns switching characteristics: t ckl clkout width low 0.5 t ck ?10 ns t ckh clkout width high 0.5 t ck ?10 ns t ckoh clkin high to clkout high 0 20 ns control signals switching characteristics t rsp reset w pwmss s pwmtpw pwmtrip w s i t i i i 1 s
rev. 0 ADMCF341 ?5? timing parameters parameter min max unit serial ports timing requirements t sck sclk period 100 ns t scs dr/tfs/rfs setup before sclk low 15 ns t sch dr/tfs/rfs hold after sclk low 20 ns t scp sclk in width 40 ns switching characteristics t cc clkout high to sclk out 0.25 t ck 0.25 t ck + 20 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 30 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 30 ns t scdh dt hold after sclk high 0 ns t scdd sclk high to dt disable 30 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 25 ns t rdv rfs (multichannel, frame delay zero) to dt valid 30 ns specifications subject to change without notice. t cc t cc t scs t rd t rh t scdv t scde t scdd t tdv t rdv clkout sclk dr rfs in tfs in rfs out tfs out dt tfs (alternate frame mode) rfs (multichannel mode, frame delay 0 [mfd = 0]) t scp t sck t scp t sch t scdh t tde figure 2. serial port timing
rev. 0 ?6? ADMCF341 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADMCF341 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * supply voltage (v dd ) . . . . . . . . . . . . . . . . . . e0.3 v to +7.0 v supply voltage (av dd ) . . . . . . . . . . . . . . . . . e0.3 v to +7.0 v input voltage . . . . . . . . . . . . . . . . . . . . . e0.3 v to v dd +0.3 v output voltage swing . . . . . . . . . . . . . . e0.3 v to v dd +0.3 v operating temperature range (ambient) . . . e40 reset i st i sese 2 1 10 11 12 1 1 2 2 2 2 2 2 2 22 21 20 1 1 1 1 1 i pwmtrip 2 1 i sese 1 0 i sese
rev. 0 ADMCF341 ?7? general description the ADMCF341 is a low-cost, single-chip dsp-based control- ler, suitable for permanent magnet synchronous motors, ac induction motors, and brushless dc motors. the ADMCF341 integrates a 20 mhz, fixed-point dsp core with a complete set of motor control and system peripherals that permits fast, efficient development of motor controllers. the dsp core of the adm cf341 is completely code-com patible with the adsp-21xx dsp family and combines three computa- tional units, data address generators, and a program sequencer. the computational units are an alu, a multiplier/accumulator (mac), and a barrel shifter. there are special instructions for bit manipulation, multiplication ( squared), biased rounding, and global interrupt masking. the system peripherals are the power-on reset circuit (por), the watchdog timer, and two synchronous serial ports. the serial ports are configurable and double buffered, with hardware support for uart, sci, and spi port emulation. the ADMCF341 provides 512 24-bit program memory ram, 4k 24-bit program memory rom, 4k 24-bit program flash memory, and 512 16-bit data memory ram. the user code can be stored and executed from the flash memory. the program and data memory ram can be used for dynamic data storage or can be loaded through the serial port from an external device as in other admcxxx family parts. the program memory rom contains a monitor function as well as useful routines for erasing, programming, and verifying the flash memory. the motor control peripherals of the ADMCF341 provide a 12-bit analog data acquisition system with six analog input channels with three dedicated i sense inputs (combining internal amplification, sampling, and overcurrent pwm shutdown features) and an internal voltage reference. in addition, a three- phase, 16-bit, center-based pwm generation unit can be used to produce high accuracy pwm signals with minimal processor overhead. the ADMCF341 also contains two 16-bit auxiliary pwm timer outputs and nine lines of digital i/o. because the ADMCF341 has a limited number of pins, functions such as the auxiliary pwm timers and the serial communication ports are multiplexed with the nine programmable digital input/ output (pio) pins. the pin functions can be independently selected to allow maximum flexibility for different applications. dsp core architecture overview figure 3 is an overall block diagram of the dsp core of the ADMCF341. the flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. in one processor cycle (50 ns with a 10 mhz clkin) the dsp core can:
rev. 0 ?8? ADMCF341 the processor contains three independent computational units: the arithmetic and logic unit (alu), the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations as well as provides support for division primitives. the mac performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization, and derive-exponent operations. the shifter can be used to efficiently implement numeric format control, including floating-point representations. the internal result (r) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps and subroutine calls and returns in a single cycle. with internal loop counters and loop stacks, the ADMCF341 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. two data address generators (dags) provide addresses for simultaneous dual operand fetches from data memory and pro- gram memory. each dag maintains and updates four address pointers (i registers). whenever the pointer is used to access data (indirect addressing), it is post-modified by the value in one of four modifications (m registers). a length value may be associated with each pointer (l registers) to implement auto- matic modulo addressing for circular buffers. the circular buffering feature is also used by the serial ports for automatic data transfers to and from on-chip memory. dag1 generates only data memory addresses and provides an optional bit-reversal capability. dag2 may generate either program or data memory addresses but has no bit-reversal capability. efficient data trans- fer is achieved with the use of five internal buses: adsp-2100 family user? manual, third edition, with particular reference to the adsp-2171. serial ports the ADMCF341 incorporates two complete synchronous serial ports (sport1 and sport0) for serial communication and multiprocessor communication. following is a brief list of capabilities of the ADMCF341 sports. refer to the adsp-2100 family user? manual , third edition, for further details. m -law companding according to itu (formerly ccitt) recommendation g.711.
rev. 0 ADMCF341 ?9? pin function description the ADMCF341 is available in a 28-lead soic package. table i describes the pins. table i. pin list pin group no. of input/ name pins output function reset 1i pri sprt1 1 2 i sp1pt1 1 r1s1s0 2 sprt0 1 i sp0pt0r0 tss1s0 2 t 1 1 i p it 2 i eq p prt0 i ipp prt 1 01 1 2 pwm pwm pwmtrip 1i pwmts i sese 1 i i sese i i sese 02 i i i st 1 s 1i ps 1 i tes 1 mprtseet prtt 2 s1s0smetr r iterrpteriew tm11 sp 11t spsprt1 irq0 irq1 sprt0 t i pwmpwms pwmtrip sp irq2 t m1 memrmp tm1 i t m1rmrm st 02000t tii iii tii pmm m r t 000000002 rm it 0000001 rm pm 0020000 r 000001 rm rpm 010001 r 02000020 s pm s0 02100021 s pm s1 0220002 s pm s2 00000 r tiii mm m r t 0000001 r 02000020 mmr 021000 r 0000 rm m 0000 rm r 0000 mmr smemrssstem tm1 24-bits of user-programmable, nonvolatile flash memory. a flash programming utility is pro- vided with the development tools, which perform the basic device programming operations: erase, program, and verify. the flash memory array is portioned into three asymmetrically sized sectors of 256 words, 256 words, and 3584 words, labeled sector 0, sector 1, and sector 2, respectively. these sectors are mapped into external program memory address space. four flash memory interface registers are connected to the dsp. these 16-bit registers are mapped into the register area of data memory space. they are named flash memory control register (fmcr), flash memory address register (fmar), flash memory data register low (fmdrl), and flash memory data register high (fmdrh). these registers are diagrammed later in this data sheet. they are used by the flash memory programming utility. the user program may read these registers, but should not modify them directly. the flash programming utility pro- vides a complete interface to the flash memory. it should be noted that the core accesses flash memory through an external memory interface that multiplexes the program memory and data memory buses into a single external bus. therefore, if more than one external transfer must be made in the same instruction, there will be at least an overhead cycle required.
rev. 0 ?10? ADMCF341 special flash registers the flash module has four nonvolatile 8-bit registers called special flash registers (sfrs) that are accessible independent of the main flash array, via the flash programming utility. these registers are for general-purpose, nonvolatile storage. when erased, the special flash registers contain all 0s. to read special flash registers from the user program, call the read_reg routine contained in rom. refer to the admcf34x dsp motor con- troller developers reference manual for an example. boot-from-flash code a security feature is available in the form of a code that, when set, causes the processor to execute the program in flash memory at power-up or reset. in this mode, the flash program- ming utility and debugger are unable to communicate with the ADMCF341. consequently, the contents of the flash memory can be neither programmed nor read. the boot-from-flash code may be set via the flash programming utility, when the user? program is thoroughly tested and loaded into flash program memory at address 0x2200. the user? program must contain a mechanism for clearing the boot-from-flash code if reprogramming the flash memory is desired. the only way to clear boot-from-flash is from within the user program, by calling the flash_init or auto_erase_reg routines that are included in the rom. the user program must be signaled in some way to call the necessary routine to clear the boot-from-flash code. an example would be to detect a high level on a pio pin during startup initialization and then call the flash_init or auto_erase_reg routine. the flash_init routine will erase the entire user program in flash memory before clearing the boot-from-flash code, thus ensuring the security of the user program. if security is not a concern, the auto_erase_reg routine can be used to clear the boot-from-flash code while leaving the user program intact. refer to the admcf34x dsp motor controller developer? refer- ence manual for further instructions and an example of using the boot-from-flash code. flash program boot sequence on power-up or reset, the processor begins instruction execu- tion at address 0x0800 of internal program rom. the rom monitor program that is located there checks the boot-from- flash code. if that code is set, the processor jumps to location 0x2200 in external flash program memory, where it expects to find the user? application program. if the boot-from-flash code is not set, the monitor attempts to boot from an external device as described in the admcf34x dsp motor controller developers reference manual . system interface figure 4 shows a basic system configuration for the ADMCF341 with an external crystal. ADMCF341 xtal clkin 10mhz clkout reset 22 22 s s tm1tt i i tt ti m1i ttm1 10m0 20m t m1 t it t r tm1sp tm1 pr tpr m1sp rstwm1 21spt rst t rst rst st m1 reset m1 rst reset rst st t rst pr
rev. 0 ADMCF341 ?11? pwmtrip r pwmswt0 er rret trip pwmstwtrer pwmtrip i sese 2 i sese 1 i sese pwmse0 tpt tr it te rie it pwmte reisters pwmirti reisters titerrpt trer treepse pwmtimi it reset s s pwms t pwmte0 pwmtm10 pwmt0 pwmp0 pwmswt0 metr pwm10 pwm10 pwm10 pwmm1 tm1 mstt sp reset treset rsp sp pmrm0000 spr tspsst m0sprt1 10sprt0sprt1 1112 tspmemwit m0et 0m1 0000t tsstmemwit m1 treepsepwmtrer tpwmm1 pwm im pmsmipwm pwm mem tpwm t pwm pwmtmpwmt pwmpipwm pwmpwm pwm epwm pwmsei pwmse pwm emmipwm i i tpwm m1pwm t pwmte tpwmte i pwmte
rev. 0 ?12? ADMCF341 the pwm generator is capable of operating in two distinct modes: single update mode and double update mode. in single update mode, the duty cycle values are programmable only once per pwm period, so that the resultant pwm patterns are symmetrical about the midpoint of the pwm period. in double update mode, a second updating of the pwm duty cycle values is implemented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce lower harmonic distortion in three-phase pwm inverters. this tech- nique also permits the closed-loop controller to change the average voltage applied to the machine winding at a faster rate, allowing wider closed-loop bandwidths to be achieved. the operating mode of the pwm block (single or double update mode) is selected by a control bit in modectrl register. the pwm generator of the ADMCF341 also provides an inter- nal signal that synchronizes the pwm switching frequency to the a/d operation. in single update mode, a pwmsync pulse is produced at the start of each pwm period. in double update mode, an additional pwmsync pulse is produced at the mid- point of each pwm period. the width of the pwmsync pulse is programmable through the pwmsyncwt register. the pwm signals produced by the ADMCF341 can be shut off in a number of different ways. first, there is a dedicated asyn- chronous pwm shutdown pin, pwmtrip wpwm ipwm i sese pwm pwmsp tpwm pwmswt spwmm1 ssstti pwmtrip pwm pwm tpwm pwmtrip pwmswt reset tpwm spt sp pwms pwm tpt t1pwm tpwmtm pwmtpwmppwmswt pwmi pwm metrt 1 pwmpwmpwm pwmspwmtmr tpwmpwm pwmtmt pwm 1 t t tspt 20mt0 tpwmtm pwmt pwmtmpwm pwm pwmtm f f f f clkout pwm clkin pwm = = 2 therefore, the pwm switching period, t s , can be written as: t pwmtm t sck = 2 for example, for a 20 mhz clkout and a desired pwm switching frequency of 10 khz (t s = 100 m s), the correct value to load into the pwmtm register is: pwmtm x e = == 20 10 21010 1000 0 3 8 6 3 the largest value that can be written to the 16-bit pwmtm register is 0xffff = 65,535, which corresponds to a minimum pwm switching frequency of: fhz pwm ,min , = = 20 10 265 535 153 6 for a clkout frequency of 20 mhz. pwm switching dead time: pwmdt register the second important pwm block parameter that must be initialized is the switching dead time. this is a short delay time introduced between turning off one pwm signal (e.g., ah) and turning on its complementary signal (e.g., al). this short time delay is introduced to permit the power switch being turned off to completely recover its blocking capability before the comple- mentary switch is turned on. this time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter.
rev. 0 ADMCF341 ?13? dead time is controlled by the pwmdt register. the dead time is inserted into the three pairs of pwm output signals. the dead time, td, is related to the value in the pwmdt register by: t pwmdt t pwmdt f dck clkout == 22 therefore, a pwmdt value of 0x00a (= 10), introduces a 1 m s delay between the turn-off of any pwm signal (for example, ah) and the turn-on of its complementary signal (for example, al). the amount of the dead time can therefore be programmed in increments of 2 t ck (or 100 ns for a 20 mhz clkout). the pwmdt register is a 10-bit register. for a clkout rate of 20 mhz its maximum value of 0x3ff (= 1023) corresponds to a maximum programmed dead time of: tt s dck max = = =m - 1023 2 1023 2 50 10 102 9 sec the dead time can be programmed to zero by writing 0 to the pwmdt register. pwm operating mode: modectrl and sysstat registers the pwm controller of the ADMCF341 can operate in two distinct modes: single update mode and double update mode. the operating mode of the pwm controller is determined by the state of bit 6 of the modectrl register. if this bit is cleared, the pwm operates in the single update mode. setting bit 6 places the pwm in the double update mode. by default, following either a peripheral reset or power-on, bit 6 of the modectrl register is cleared. this means that the default operating mode is single update mode. in single update mode, a single pwmsync pulse is produced in each pwm period. the rising edge of this signal marks the start of a new pwm cycle and is used to latch new values from the pwm configuration registers (pwmtm, pwmdt, pwmpd, and pwmsyncwt) and the pwm duty cycle registers (pwmcha, pwmchb, and pwmchc) into the three-phase timing unit. the pwmseg register is also latched into the output control unit on the rising edge of the pwmsync pulse. in effect, this means that the parameters of the pwm signals can be updated only once per pwm period at the start of each cycle. thus, the generated pwm patterns are symmetrical about the midpoint of the switching period. in double update mode, there is an additional pwmsync pulse produced at the midpoint of each pwm period. the rising edge of this new pwmsync pulse is again used to latch new values of the pwm configuration registers, duty cycle registers, and the pwmseg register. as a result, it is possible to alter both the characteristics (switching frequency, dead time, minimum pulsewidth, and pwmsync pulsewidth) and the output duty cycles at the midpoint of each pwm cycle. conse- quently, it is possible to produce pwm switching patterns that are no longer symmetrical about the midpoint of the period (asymmetrical pwm patterns). in double update mode, operation in the first half or the second half of the pwm cycle is indicated by bit 3 of the sysstat register. in double update mode, this bit is cleared during operation in the first half of each pwm period (between the rising edge of the original pwmsync pulse and the rising edge of the new pwmsync pulse, which is introduced in double update mode). bit 3 of the sysstat register is set during the second half of each pwm period. if required, a user may deter- mine the status of this bit during a pwmsync interrupt service routine. the advantages of double update mode are that lower harmonic voltages can be produced by the pwm process and wider control bandwidths are possible. however, for a given pwm switching frequency, the pwmsync pulses occur at twice the rate in the double update mode. because new duty cycle values must be computed in each pwmsync interrupt service rou- tine, there is a larger computational burden on the dsp in double update mode. width of the pwmsync pulse: pwmsyncwt register the pwm controller of the ADMCF341 produces an internal pwm synchronization pulse at a rate equal to the pwm switching frequency in single update mode and at twice the pwm fre- quency in double update mode. this pwmsync synchronizes the operation of the pwm unit with the a/d converter system. the width of this pwmsync pulse is programmable by the pwmsyncwt register. the width of the pwmsync pulse, t pwmsync , is given by: tt pwmsyncwt pwmsync ck = + () 1 which means that the width of the pulse is programmable from t ck to 256 t ck (corresponding to 50 ns to 12.8 m s for a clkout rate of 20 mhz). following a reset, the pwmsyncwt register contains 0x27 (= 39) so that the default pwmsync width is 2.0 m s. pwm duty cycles: pwmcha, pwmchb, pwmchc registers the duty cycles of the six pwm output signals are controlled by the three duty cycle registers, pwmcha, pwmchb, and pwmchc. the integer value in the register pwmcha con- trols the duty cycle of the signals on ah and al. pwmchb controls the duty cycle of the signals on bh and bl, and pwmchc controls the duty cycle of the signals on ch and cl. the duty cycle registers are programmed in integer counts of the fundamental time unit, t ck , and define the desired on-time of the high side pwm signal produced by the three-phase timing unit over half the pwm period. the switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the pwmdt register. the pwm is center-based. this means that in single update mode the resulting output waveforms are symmetrical and cen- tered in the pwmsync period. figure 7 presents a typical pwm timing diagram illustrating the pwm-related registers (pwmcha, pwmtm, pwmdt, and pwmsyncwt) con- trol over the waveform timing in both half cycles of the pwm period. the magnitude of each parameter in the timing diagram is determined by multiplying the integer value in each register by t ck (typically 50 ns). it may be seen in the timing diagram how dead time is incorporated into the waveforms by moving the switching edges away from the original values set in the pwmcha register.
rev. 0 ?14? ADMCF341 pwmsync ah al pwmcha pwmcha 2 pwmdt pwmsyncwt + 1 2 pwmdt sysstat (3) pwmtm pwmtm figure 7. typical pwm outputs of three-phase timing unit in single update mode each switching edge is moved by an equal amount (pwmdt t ck ) to preserve the symmetrical output patterns. the pwmsync pulse, whose width is set by the pwmsyncwt register, is also shown. bit 3 of the sysstat register indicates which half cycle is active. this can be useful in double update mode, as will be discussed later. the resultant on-times of the pwm signals shown in figure 7 may be written as: t pwmcha pwmdt t ah ck = - 2( ) t pwmtm pwmcha pwmdt t al ck = - - 2( ) the corresponding duty cycles are: d t t pwmcha pwmdt pwmtm ah ah s == - d t t pwmtm pwmcha pwmdt pwmtm al al s == -- obviously, negative values of t ah and t al are not permitted because the minimum permissible value is zero, corresponding to a 0% duty cycle. in a similar fashion, the maximum value is t s , corresponding to a 100% duty cycle. the output signals from the timing unit for operation in double update mode are shown in figure 8. this illustrates a com- pletely general case where the switching frequency, dead time, and duty cycle are all changed in the second half of the pwm period. of course, the same value for any or all of these quanti- ties could be used in both halves of the pwm cycle. however, it can be seen that there is no guarantee that symmetrical pwm signals will be produced by the timing unit in this double update mode. additionally, it is seen that the dead time is inserted into the pwm signals in the same way as in single update mode. pwmcha 2 2 pwmdt 1 2 pwmdt 2 pwmsyncwt 2 + 1 pwmcha 1 pwmtm 1 pwmtm 2 pwmsyncwt 1 + 1 ah al pwmsync sysstat (3) figure 8. t pwmcha pwmcha pwmdt pwmdt t ah ck = +- - ( ) 12 12 t pwmtm pwmtm pwmcha pwmcha pwmdt pwmdt t al ck = +- - -- ( ) 12 1 212 d t t pwmcha pwmcha pwmtm pwmtm pwmdt pwmdt pwmtm pwmtm ah ah s == + + - + + 12 12 12 12 d t t pwmtm pwmtm pwmcha pwmtm pwmtm pwmcha pwmdt pwmcha pwmtm pwmtm al al s == ++ + - ++ + 12 1 12 21 1 12 because for the completely general case in double update mode, the switching period is given by: tp wmtm pwmtm t sck =+ () 12 again, the values of t ah and t al are constrained to lie between zero and t s . pwm signals similar to those illustrated in figure 7 and figure 8 can be produced on the bh, bl, ch, and cl outputs by pro gramming the pwmchb and pwmchc registers in a manner identical to that described for pwmcha. the pwm controller does not produce any pwm outputs until all of the pwmtm, pwmcha, pwmchb, and pwmchc registers have been written to at least once. after these registers have been written, the counters in the three-phase timing unit are enabled. writing to these registers also starts the main pwm timer. if, during initialization, the pwmtm register is written before the pwmcha, pwmchb, and pwmchc registers, the ?st pwmsync pulse (and interrupt if enabled) will be generated (1.5 t ck pwmtm) seconds after the initial write to the pwmtm register in single update mode. in double up- date mode, the trst pwmsync pulse will be generated (t ck pwmtm) seconds after the initial write to the pwmtm regis- ter in single update mode.
rev. 0 ADMCF341 ?15? will remain off (0% duty cycle). additionally, the al signal will be turned on for the entire half period (100% duty cycle). output control unit: pwmseg register the operation of the output control unit is managed by the 9-bit read/write pwmseg register. this register sets two distinct features of the output control unit that are directly useful in the control of ecm or bdcm. the pwmseg register contains three crossover bits, one for each pair of pwm outputs. setting bit 8 of the pwmseg regis- ter enables the crossover mode for the ah/al pair of pwm signals; setting bit 7 enables crossover on the bh/bl pair of pwm signals; and setting bit 6 enables crossover on the ch/cl pair of pwm signals. if crossover mode is enabled for any pair of pwm signals, the high side pwm signal from the timing unit (for example, ah) is diverted to the associated low side output of the output control unit so that the signal will ultimately appear at the al pin. of course, the corresponding low side output of the timing unit is also diverted to the complementary high side output of the output control unit so that the signal appears at pin ah. following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of pwm signals. the pwmseg register also contains six bits (bits 0 to 5) that can be used to individually enable or disable each of the six pwm outputs. if the associated bit of the pwmseg register is set, the corresponding pwm output is disabled regardless of the value of the corresponding duty cycle register. this pwm out- put signal will remain in the off state as long as the corresponding enable/disable bit of the pwmseg register is set. the pwm output enable function gates the crossover func- tion. after a reset, all six enable bits of the pwmseg register are cleared, thereby enabling all pwm outputs by default. in a manner identical to the duty cycle registers, the pwmseg is latched on the rising edge of the pwmsync signal so that changes to this register only become effective at the start of each pwm cycle in single update mode. in double update mode, the pwmseg register can also be updated at the midpoint of the pwm cycle. in the control of an ecm, only two inverter legs are switched at any time, and often the high side device in one leg must be switched on at the same time as the low side driver in a second leg. therefore, by programming identical duty cycles for two pwm channels (for example, let pwmcha = pwmchb) and setting bit 7 of the pwmseg register to cross over the bh/bl pair of pwm signals, it is possible to turn on the high side switch of phase a and the low side switch of phase b at the same time. in the control of an ecm, one inverter leg (phase c in this example) is disabled for a number of pwm cycles. this disable may be implemented by disabling both the ch and cl pwm outputs by setting bits 0 and 1 of the pwmseg register. this is illustrated in figure 7, where it can be seen that both the ah and bl signals are identical, because pwmcha = pwm chb, and the crossover bit for phase b is set. in addition, the other four signals (al, bh, ch, and cl) have been disabled by setting the appropriate enable/disable bits of the pwmseg register. for the situation illustrated in figure 9, the appropriate value for the pwmseg register is 0x00a7. in ecm operation, because each inverter leg is disabled for a certain period of time, the pwmseg register is changed based upon the position of the rotor shaft (motor commutation). effective pwm resolution in single update mode, the same values of pwmcha, pwmchb, and pwmchc are used to detne the on-times in both half cycles of the pwm period. as a result, the effective resolution of the pwm generation process is 2 t ck (or 100 ns for a 20 mhz clkout), since incrementing one of the duty cycle registers by one changes the resultant on-time of the asso- ciated pwm signals by t ck in each half period (or 2 t ck for the full period). in double update mode, improved resolution is possible since different values of the duty cycle registers are used to detne the on-times in both the trst and second halves of the pwm period. as a result, it is possible to adjust the on-time over the whole period in increments of t ck . this corresponds to an effective pwm resolution of t ck in double update mode (or 50 ns for a 20 mhz clkout). table iv. achievable pwm resolution in single and double update modes resolution single update mode double update mode (bit) (khz) pwm frequency (khz) pwm frequency 8 39.1 78.4 9 19.5 39.1 10 9.8 19.5 11 4.9 9.8 12 2.4 4.9 minimum pulsewidth: pwmpd register in many power converter switching applications, it is desirable to eliminate pwm switching pulses shorter than a certain width. it takes a finite time to both turn on and turn off modern power semiconductor devices. therefore, if the width of any of the pwm pulses is shorter than some minimum value, it may be desirable to completely eliminate the pwm switching for that particular cycle. the allowable minimum on-time for any of the six pwm out- puts for half a pwm period that can be produced by the pwm controller may be programmed using the pwmpd register. the minimum on-time is programmed in increments of t ck so that the minimum on-time produced for any half pwm period, t min , is related to the value in the pwmpd register by: tp wmpd t min ck = a pwmpd value of 0x002 defines a permissible minimum on-time of 100 ns for a 20 mhz clkout. in each half cycle of the pwm, the timing unit checks the on- time of each of the six pwm signals. if any of the times is found to be less than the value specified by the pwmpd register, the corresponding pwm signal is turned off for the entire half period, and its complementary signal is turned completely on. consider the example where pwmtm = 200, pwmcha = 5, pwmdt = 3, and pwmpd = 10 with a clkout of 20 mhz, while operating in single update mode. for this case, the pwm switching frequency is 50 khz and the dead time is 300 ns. the minimum permissible on-time of any pwm signal over one-half of any period is 500 ns. clearly, for this example, the dead-time adjusted on-time of the ah signal for one-half a pwm period is (5?) 50 ns = 100 ns. because this is less than the minimum permissible value, output ah of the timing unit
rev. 0 ?16? ADMCF341 pwmcha = pwmchb pwmtm pwmtm ah al bh bl 2 pwmdt 2 pwmdt ch cl figure 9. an example of pwm signals suitable for ecm control. pwmcha = pwmchb, bh/bl are a crossover pair. al, bh, ch, and cl outputs are disabled. operation is in single update mode. gate drive unit: pwmgate register the gate drive unit of the pwm controller adds features that simplify the design of isolated gate drive circuits for pwm inverters. if a transformer-coupled power device gate drive amplifier is used, the active pwm signal must be chopped at a high frequency. the pwmgate register allows the programming of this high-frequency chopping mode. the chopped active pwm signals may be required for the high side drivers only, for the low side drivers only, or for both the high side and low side switches. therefore, independent control of this mode for both high side and low side switches is included with two separate control bits in the pwmgate register. typical pwm output signals with high-frequency chopping enabled on both high side and low side signals are shown in figure 10. chopping of the high side pwm outputs (ah, bh and ch) is enabled by setting bit 8 of the pwmgate register. chopping of the low side pwm outputs (al, bl, and cl) is enabled by setting bit 9 of the pwmgate register. the high chopping frequency is controlled by the 8-bit word (gdclk) written to bits 0 to 7 of the pwmgate register. the period and the frequency of this high-frequency carrier are: t gdclk t chop ck = () + [] 41 f f gdclk chop clkout = + () [] 41 the gdclk value may range from 0 to 255, corresponding to a programmable chopping frequency rate from 19.5 khz to 5 mhz for a 20 mhz clkout rate. the gate drive features must be programmed before operation of the pwm controller and typically are not changed during normal operation of the pwm controller. following a reset, by default, all bits of the pwmgate register are cleared so that high-frequency chop- ping is disabled. pwmtm pwmtm [4 (gdclk+1)] 2 pwmdt 2 pwmdt pwmcha pwmcha ah al figure 10. typical pwm signals with high- frequency gate chopping enabled on both high side and low side switches. (gdclk is the integer equivalent of the value in bits 0 to 7 of the pwmgate register.) pwm shutdown in the event of external fault conditions, it is essential that the pwm system be instantaneously shut down. two methods of sensing a fault condition are provided by the ADMCF341. for the ?st method, a low level on the pwmtrip sp pwmtpwm pwms pwmtrip t pwmtrip pwm t pwmtrip 0 ssstt t i sese m1w i sese i sese pwmtrip t pwmtrip pwmtrip ipwm 1pwmswt0201 wpwm pwmtrip i sese pwm pwmswt r rpwm pwm pwmtrip ii sese i sese pwm pwmtmpwmpwmpwm pwm pwms pwmr tpwm tpwm t
rev. 0 ADMCF341 ?17? adc overview the adc of the ADMCF341 is based upon the single slope con- version technique. this approach offers an inherently monotonic conversion process within the noise and stability of its compo- nents, and there will be no missing codes. the single slope technique has been adopted on the ADMCF341 for four channels that are simultaneously con- verted. refer to figure 11 for the functional schematic of the adc. the main inputs (i sense 1 to i sense 3) are connected to the adc converter through three front end blocks. figure 15 shows the block diagram of a single front end block. each front end block has a bipolar current amplifier (gain = e2.5) designed to acquire the voltage on a current-sensing resistor, whose volt- age can be either positive or negative with respect to the power supply ground rail. the fourth channel has been configured with a serially con- nected 4-to-1 multiplexer. table vi shows the multiplexer input selection codes. one of these auxiliary multiplexed channels is used to acquire the internal voltage reference (v ref ) for calibra- tion purposes. table vi. adc auxiliary channel selection modectrl (1) modectrl (0) select adcmux1 adcmux0 vaux0 0 0 vaux1 0 1 vaux2 1 0 calibration (v ref )1 1 adc1 adc2 adc3 adcaux comp i sense 1 i sense 2 i sense 3 vaux0 vaux1 vaux2 v ref i const current voltage channel1 current voltage channel2 current voltage channel3 4-1 multiplexer vaux0 (v) vaux1 (v) vaux2 (v) vaux3 (v) modectrl reg <0..1> comp comp comp i const filter 12-bit adc timer block v1l v2l v3l vauxl pwmsync (convst) modectrl reg <07> clk modectrl reg <09..10..11> i const _trim reg <2:0> capacitor reset figure 11. adc overview single slope adc operations the adc conversion process is done by comparing each adc input to a reference ramp voltage and timing the comparison of the two signals. the actual conversion point is the time-point intersection of the input voltage and the ramp voltage (vc), as shown in figure 12. this time is converted to counts by the 12- bit adc timer block and is stored in the adc registers. the ramp voltage used to perform the conversion is generated by driving a fixed current into an off-chip capacitor, where the capacitor voltage is: vict c = () table v. fundamental characteristics of pwm generation unit of ADMCF341 parameter min typ max unit 16-bit pwm timer counter resolution 16 bits edge resolution (single update mode) 100 ns edge resolution (double update mode) 50 ns programmable dead time range 0 102 m s programmable dead time increments 100 ns programmable pulse deletion range 0 51 m s programmable pulse deletion increments 50 ns pwm frequency range 153 1 78,431 2 hz pwmsync pulsewidth (t crst ) 2.0 12.8 m s gate drive chop frequency range 0.02 5 mhz notes 1 153 hz is calculated based on 16-bit resolution. 2 78,431 hz is calculated based on 8-bit resolution.
rev. 0 ?18? ADMCF341 following reset, vc = 0 at t = 0. this reset and the start of the conversion process are initiated by the pwmsync pulse, as shown in figure 12. the width of the pwmsync pulse is controlled by the pwmsyncwt register and should be pro- grammed according to figure 13 to ensure complete resetting. in order to compensate for ic process manufacturing tolerances (and to adjust for capacitor tolerances), the current source of the ADMCF341 is software-programmable. using software to set the magnitude of the iconst current generator is accom- plished by selecting one of eight steps over approximately 20% current range. v c v1 pwmsync comparator output v cmax t vil t pwm ? t crst t crst figure 12. analog input block operation the adc system consists of four comparators and a single timer, which may be clocked at either the dsp rate or half the dsp rate, depending on the setting of the adccnt bit (bit 7) of the modectrl register. when this bit is cleared, the timer counts at a slower rate of clkin. when this bit is set, it counts at clkout or twice the rate of clkin. adc1, adc2, adc3, and adcaux are the registers that capture the conver- sion times, which are the timer values when the associated comparator trips. 200 150 100 50 0 0 2 4 6 8 10 decimal counts charging capacitor ? nf figure 13. pwmsyncwt program value adc resolution the adc is intrinsically linked to the pwm block through the pwmsync pulse?s control of the adc conversion process. because of this link, the effective resolution of the adc is a function of both the pwm switching frequency and the rate at which the adc counter timer is clocked. for a clkout period of t ck and a pwm period of t pwm , the maximum count of the adc is given by: max count t t t for modectrl bit max count t t t for modectrl bit pwm crst ck pwm crst ck =- = =- = min min (,( )/ ) (,( )/) 4095 2 70 4095 71 where t pwm is equal to the pwm period if operating in single update mode or equal to half that period if operating in double update mode. for an assumed clkout frequency of 20 mhz and pwmsync pulsewidth of 2.0 m s, the effec- tive resolution of the adc block is tabulated for various pwm switching frequencies in table vii. table vii. adc resolution examples pwm modectrl[7] = 0 modectrl[7] = 1 frequency max effective max effective (khz) count resolution count resolution 2.4 4095 12 4095 12 4 2480 >11 4095 12 8 1230 >10 2460 >11 18 535 >9 1070 >10 25 380 >8 760 >9 programmable current source the ADMCF341 has an internal current source that is used to charge an external capacitor, generating the voltage ramp used for conversion. the magnitude of the output of the current source circuit is subject to manufacturing variations and can vary from one device to the next. therefore, the ADMCF341 includes a programmable current source whose output can always be tuned to within 5% of the target 100 m a. a 3-bit register, i const _trim, allows the user to make this adjust- ment. the output current is proportional to the value written to the register: 0x0 produces the minimum output and 0x7 pro- duces the maximum output. the default value of i const _trim after reset is 0x0. charging capacitor selection the charging capacitor value is selected based on the sample (pwm) frequency desired. a too-small capacitor value will re- duce the available resolution of the adc by having the ramp voltage rise rapidly and convert too quickly, not utilizing all pos- sible counts available in the pwm cycle. a too-large capacitor may not convert in the available pwm cycle returning 0x000. to select a charging capacitor use figure 14. select the sam- pling frequency desired, determine if the current source is to be tuned to a nominal 100 m a or left in the default (0x0 code) trim state, then determine the proper charge capacitor off the appro- priate curve.
rev. 0 ADMCF341 ?19? 100 10 1 1 10 100 c nom ? nf tuned i const default i const figure 14. timing capacitor selection analog front end the main analog inputs of the ADMCF341 (i sense 1 to i sense 3) are connected to the adc converter through three front end blocks. figure 15 shows the block diagram of a single analog front end. sha timer register sha state machine mux overcurrent comparator sha timer counter voltage (this is not available externally on the ADMCF341) current pwmsync clockout modectrl register channel selection (i sense /v) adc conversion status bit (adc register) sha ?2.5 vxl (to adc) trip (to pwmtrip iter triprei triprew 1 e 1 1 2 12 10 1112 e pwms stimer ter sstts i sese ipt reister ttt tre smpe e2 ii s1 tre smpe e ii s1 tre smpe e2 tre smpe e ss s s t smpe t smpe t smpe t smpe tr 1 si
rev. 0 ?20? ADMCF341 each analog front end has two analog inputs: voltage and cur- rent. a 2-to-1 multiplexer selects which input will be converted; the multiplexer selection is determined by the modectrl register. note that in the ADMCF341 only the current inputs (i sense ) are externally available. the current input (i sense ) is amplified through a bipolar ampli- fier (gain e2.5). there is an output offset that matches the amplifier output signal range to the input signal range of the a/ d converter. the amplifier has built-in overcurrent and open- circuit protection. the overcurrent protection shuts the pwm block when the voltage at any of the i sense pins exceeds the trip threshold (high or low). the open-circuit detection shuts the pwm block when any of the i sense inputs is in high impedance (for example, the current sense resistor or transducer is discon- nected). the shutdown signals generated by the amplifiers are then or-ed and filtered in order to avoid a spurious trip caused by the switching of the power devices. the amplifier is followed by a sample-and-hold amplifier (sha). the sha time is user- programmable through the sha timer register. the sampling time is set as a delay from the rising edge of the pwmsync signal and is calculated as: t sha cnt t sample ck =+ (_ ) 2 the sha timer counter has a minimum reload value of 0x0003, which ensures a minimum settling time of the sha output in case the user is programming the sha timer register to a value smaller than 0x0003. this means that the sampling time is programmable from 5 t ck to 65,535 t ck (corresponding to 250 ns to 3.28 ms for a clkout rate of 20 mhz). the sampling time is limited, however, to the rising edge of the following pwmsync cycle. each channel has an independent amplifier, sha, and sha timing unit/state machine. figure 16 shows a conversion sequence of a single channel. at the beginning of the cycle n (rising edge of pwmsync signal (1), the timer counter is loaded with the value contained in the sha_cnt register. after the timer counter has been reloaded, it starts counting down at the clkout rate. in this phase the sha state-machine forces the sha in track (sample) status. when the counter reaches the value of 0x0000 (after the time t sample from the rising edge of pwmsync), the sha state- machine forces the sha in hold status. the conversion of the sampled value is then taking place in the cycle n + 1 [from (4) to (5)] in figure 16 and the result of the conversion is available on the adc register at the cycle n + 2 [rising edge of pwmsync (5)]. on cycle n + 2, the reload value of the timer counter exceeds the period of the pwmsync signal. in this case the sha state- machine forces the sha in hold status at the rising edge of pwmsync of the next cycle (7). the conversion then takes place on cycle n + 3, and the conversion result is available on the adc register at the cycle n + 4 [rising edge of pwmsync (9)]. during the acquire phase (the pwmsync cycle during the sampling of the input value) the conversion takes place. how- ever, the value on the adc registers is not considered valid. this condition is signaled by the adc by setting the lsb of the adc register to high. on cycle n + 4, at the rising edge of the pwmsync signal (9), the timer counter is reloaded with a value smaller than the pwmsync pulsewidth. in this case the sha samples within the pwmsync pulsewidth and the conversion takes place in the same pwmsync cycle [from (10) to (11)]. auxiliary pwm timers overview the ADMCF341 provides two variable frequency, variable duty cycle, 16-bit, auxiliary pwm outputs that, when enabled, are available at the aux1 and aux0 pins. these auxiliary pwm outputs can be used to provide switching signals to other circuits in typical motor control systems, such as power factor corrected front end converters or other switching power con- verters. alternatively, by adding a suitable filter network, the auxiliary pwm output signals can be used as simple single-bit digital-to-analog converters as shown in figure 17. the auxiliary pwm system of the ADMCF341 can operate in two different modes: independent mode and offset mode. the operating mode of the auxiliary pwm system is controlled by bit 8 of the modectrl register. setting bit 8 of the modectrl regis- ter places the auxiliary pwm system in the independent mode. in this mode, the two auxiliary pwm generators are completely independent and separate switching frequencies and duty cycles may be programmed for each auxiliary pwm output. in this mode, the 16-bit auxtm0 register sets the switching frequency of the signal at the aux0 output pin. similarly, the 16-bit auxtm1 register sets the switching frequency of the signal at the aux1 pin. the fundamental time increment for the auxiliary pwm outputs is twice the dsp instruction rate (or 2 t ck ) and the corresponding switching periods are given by: t auxtm t t auxtm t aux ck aux ck 0 1 201 211 = + = + () () since the values in both auxtm0 and auxtm1 can range from 0 to 0xffff, the achievable switching frequency of the auxiliary pwm signals may range from 152.59 hz to 10 mhz for a clkout frequency of 20 mhz. the on-time of the two auxiliary pwm signals is programmed by the two 16-bit auxch0 and auxch1 registers, according to: t aux auxch t t aux auxch t on ck on ck ,() ,() 02 0 12 1 = = so that output duty cycles from 0% to 100% are possible. duty cycles of 100% are produced if the on-time value exceeds the period value. typical auxiliary pwm waveforms in independent mode are shown in figure 18a. when bit 8 of the modectrl register is cleared, the auxiliary pwm channels are placed table viii. fundamental characteristics of auxiliary pwm timers parameter test conditions min typ max unit resolution 16 bits pwm frequency 10 mhz clkin 0.152 mhz
rev. 0 ADMCF341 ?21? in offset mode. in offset mode, the switching frequency of the two signals on the aux0 and aux1 pins are identical and controlled by auxtm0 in a manner similar to that previously described for independent mode. in addition, the on-times of both the aux0 and aux1 signals are controlled by the auxch0 and auxch1 registers as before. in this mode, however, the auxtm1 register defines the offset time from the rising edge of the signal on the aux0 pin to that on the aux1 pin according to: t auxtm t offset ck = + 21 () 1 for correct operation in this mode, the value written to the auxtm1 register must be less than the value written to the auxtm0 register. typical auxiliary pwm waveforms in offset mode are shown in figure 18b. again, duty cycles from 0% to 100% are possible in this mode. in both operating modes, the resolution of the auxiliary pwm system is 16 bits only at the minimum switching frequency (auxtm0 = auxtm1 = 65,535 in independent mode, auxtm0 = 65,535 in offset mode). obviously, as the switch- ing frequency is increased, the resolution is reduced. values can be written to the auxiliary pwm registers at any time. however, new duty cycle values written to the auxch0 and auxch1 registers only become effective at the start of the next cycle. writing to the auxtm0 or auxtm1 registers causes the internal timers to be reset to 0 and new pwm cycles to begin. by default following a reset, bit 8 of the modectrl register is cleared, thus enabling offset mode. in addition, the registers auxtm0 and auxtm1 default to 0xffff, corre- sponding to the minimum switching frequency and zero offset. the on-time registers auxch0 and auxch1 default to 0x0000. auxpwm r1 r2 c1 c2 r1 = r2 = 13k c1 = c2 = 10nf figure 17. auxiliary pwm output filter auxiliary pwm interface, registers, and pins the registers of the auxiliary pwm system are summarized at the end of the data sheet. aux0 aux1 2 (auxtm0 + 1) 2 (auxtm1 + 1) 2 auxch1 2 auxch1 2 auxch0 figure 18a. typical auxiliary pwm signals (all times in increments of t ck ), independent mode aux0 aux1 2 (auxtm0 + 1) 2 (auxtm0 + 1) 2 auxch1 2 auxch0 2 (auxtm1 + 1) figure 18b. typical auxiliary pwm signals (all times in increments of t ck ), offset mode watchdog timer the ADMCF341 incorporates a watchdog timer that can perform a full reset of the dsp and motor control peripherals in the event of software error. the watchdog timer is enabled by writing a timeout value to the 16-bit wdtimer register. the timeout value represents the number of clkin cycles required for the watchdog timer to count down to zero. when the w atchdog timer reaches zero, a full dsp core and motor control peripheral reset is performed. in addition, bit 1 of the sysstat register is set so that after a watchdog reset, the ADMCF341 can determine that the reset was due to the timeout of the watchdog timer and was not an external reset. following a watchdog reset, bit 1 of the sysstat register may be cleared by writing zero to the wdtimer register. this clears the status bit but does not enable the watchdog timer. on reset, the watchdog timer is disabled and is only enabled when the first timeout value is written to the wdtimer register. to prevent the watchdog timer from timing out, the user must write to the wdtimer register at regular intervals (shorter than the programmed wdtimer period value). on all but the first write to wdtimer, the particular value written to the register is unimportant, since writing to wdtimer simply reloads the first value written to this register. programmable digital input/output the ADMCF341 has a nine-pin programmable digital input/ output (pio) port (porta). the nine pins (porta0 porta8) are multiplexed with other on-chip peripheral functions, in accordance with table ix. when configured as a pio, each of these nine pins can act as an input or output, or an interrupt source. the operating mode (pio or alternate function) of pins porta0 to porta8 is controlled by the porta_select register. this 9-bit register has a bit for each input so that the mode of each pin may be selected individually. bit 0 of porta_select controls the operation of the porta0 pin, bit 1 controls the porta1 pin, etc. setting the appropriate bit in the porta_select register causes the corresponding pin to be configured for pio functionality. clearing the bit selects the alternate mode of the corresponding pin. following power-on reset, all bits of porta_select are set such that pio functionality is selected. the second alternate function of porta7 is selected by bit 14 of the porta_select register. the second alternate function of
rev. 0 ?22? ADMCF341 porta8 is selected by bit 15 of the porta_select register. the second alternate function of the porta4 and porta5 pins is selected by bit 4 of modectrl register (sport1 mode: boot mode/uart mode). once pio functionality has been selected for any or all of these nine pins, the direction may be set by the 9-bit porta_dir register. clearing any bit configures the corresponding pio line as an input, while setting the bit configures it as an output. by default, following a reset all bits of porta_dir are cleared, configuring the pio lines as inputs. the data of the porta0 to porta8 lines is controlled by the porta_data register. these registers can be used to read data from those pio lines configured as inputs and write data to those configured as outputs. any of the nine pins that have been configured for pio func- tionality can be made to act as an interrupt source by setting the appropriate bit of the porta_inten register. in order to act as an interrupt source the pin must also be configured as an input. an interrupt is generated upon a change of state (low-to- high transition or high-to-low transition) on any input that has been configured as an interrupt source. following a change of state event on any such input, the corresponding bit is set in the porta_flag register and a common pio interrupt is generated. reading the porta_flag register permits determining the interrupt source. reading the porta_flag register automati- cally clears all bits of the registers. following power-on or reset, all bits of porta_inten are cleared so that no interrupts are enabled. each pio line has an internal pull-down resistor so that follow- ing power-on or reset all nine lines are configured as input pios and will be read as logic lows if left unconnected. pio registers the configuration of all registers of the pio system is shown at the end of the data sheet. interrupt control the ADMCF341 can respond to 18 different interrupt sources with minimal overhead. seven of these interrupts are internal dsp core interrupts and 11 are from the on-chip peripherals. the seven dsp core interrupts are sport0 receive and transmit, sport1 receive (or irq0) and transmit (or irq1), the internal timer, and two software interrupts. the motor control interrupts are the nine porta pios and two from the pwm block (pwmsync pulse and pwmtrip sp irq2 t t m1 tt tpwms pwmst pwmtrip pwmtrip pi pi tm1 iimsit spirq pwms pwmtrip prt pi t i is i pwmtrip 0002p pi irq2 0000 pwms 0 000 pi 0000 si1 0001 si0 0 001 sprt0ti 00010 sprt0ri 0001 sprt1ti irq1 00020 sprt1ri irq0 0002 t 0002p im iims spt i irq2 imst imsm1 ti pm prtp p sp prt 0pwm ts prt 1pwm pwmspwm prt r1rsprt1 prt 1sprt1 t1tsprt1 prt s1ssprt1 s0ssprt0 prt ts0tssprt0 prt2 rs0rssprt0 prt1 t0tsprt0 prt0 r0rsprt0
rev. 0 ADMCF341 ?23? interrupt configuration the ifc and icntl registers of the dsp core control and configure the interrupt controller of the dsp core. the ifc register is a 16-bit register that may be used to force and/or clear any of the eight dsp interrupts. bits 0 to 7 of the ifc register may be used to clear the dsp interrupts while bits 8 to 15 can be used to force a corresponding interrupt. writing to bits 11 and 12 in ifc is the only way to create the two software inter- rupts. the icntl register is used to configure the sensitivity (edge- or level-) of the irq0, irq1, and irq2 interrupts and to enable/disable interrupt nesting. setting bit 0 of icntl config- ures the irq0 as edge-sensitive, while clearing the bit configures it as level-sensitive. bit 1 is used to configure the irq1 interrupt and bit 2 is used to configure the irq2 interrupt. it is recom- mended that the irq2 interrupt always be configured as level-sensitive as this ensures that no peripheral interrupts are lost. setting bit 4 of the icntl register enables interrupt nesting. the configuration of both ifc and icntl registers is shown at the end of the data sheet. interrupt operation following a reset, the rom code on the ADMCF341 must copy a default interrupt vector table into program memory ram from address 0x0000 to 0x002f. since each interrupt source has a dedicated four-word space in this vector table, it is possible to code short interrupt service routines (isr) in place. alternatively, it may be necessary to insert a jump instruction to the appropriate start address of the isr if the isr requires more memory. when an interrupt occurs, the program sequencer ensures that there is no latency (beyond synchronization delay) when processing unmasked interrupts. in the case of the timer, sport0, sport1, and software interrupts, the interrupt controller automatically jumps to the appropriate location in the interrupt vector table. at this point, a jump instruction to the appropriate isr is required. motor control peripheral interrupts are slightly different. when a peripheral interrupt is detected, a bit is set in the irqflag register for pwmsync and pwmtrip or in the porta_flag register for a pio inter- rupt, and the irq2 line is pulled low until all pending interrupts are acknowledged. the dsp software must determine the source of the interrupts by reading the irqflag register. if more than one interrupt occurs simultaneously, the higher priority interrupt service routine is executed. reading the irqflag register clears the pwmtrip and pwmsync bits and acknowl- edges the interrupt, thus allowing further interrupts when the isr exits. a user?s pio interrupt service routine must read the porta_flag register to determine which pio port is the source of the interrupt. reading register porta_flag clears all bits in the registers and acknowledges the interrupt, thus allowing further interrupts after the isr exits. the configuration of all these registers is shown at the end of the data sheet. system controller the system controller block of the ADMCF341 performs the following functions: 1. manages the interface and data transfer between the dsp core and the motor control peripherals. 2. handles interrupts generated by the motor control periph- erals and generates a dsp core interrupt signal irq2. 3. controls the adc multiplexer select lines. 4. enables pwmtrip and pwmsync interrupts. 5. controls the multiplexing of the sport1 and sport0 pins. 6. controls the pwm single/double update mode. 7. controls the adc conversion time modes and the sha timers. 8. controls the auxiliary pwm operation mode. 9. contains a status register (sysstat) that indicates the state of the pwmtrip pin, the watchdog timer, and the pwm timer. 10. performs a reset of the motor control peripherals and control registers following a hardware, software, or watch- dog initiated reset. sport1 and sport0 control the ADMCF341 has two serial ports: sport0 and sport1. sport1 is available with a limited number of pins and is m ainly intended as a secondary port for development tools interfacing and/or code booting from, as well as external serial memory. figure 19 shows the internal multiplexing of the sport0 and sport1 signals. sport0 is intended as a general-purpose communication port. sport0 can support the following operat ing modes: sport, uart, and spi. sport1 configuration there are two operating modes for sport1: boot mode and uart mode. these modes are selectable through bit 4 of the modectrl register. with sport1 in boot mode, the sport1 serial clock (sclk1) is externally available through the sclk1/sclk0 pin. the signal sclk1 is used to drive the external serial memory input clock. the sport1 flag signal (fl1) is externally available through the fl1/dt1 pin. this signal is used to drive the external serial memory input reset. with sport1 configured in uart mode, the sport0 serial clock (sclk0) is externally available through the sclk1/ sclk0 pin. the sport1 data transmit (dt1) is externally available through the fl1/dt1 pin. sport0 configuration sport0 can be configured in the following modes: sport mode, uart mode, and spi mode. sport0 can be configured for uart mode. in this mode the dr0 and rfs0 signals of the internal serial port are connected together. sport0 can be configured to operate as the master spi inter- face. the spi mode is set through bit 14 of the modectrl register. when sport0 is configured as the spi interface, the sport i/o pins assume the configuration shown in table xi.
rev. 0 ?24? ADMCF341 dsp core sport1 dt1 fl1 tfs1 rfs1 dr1 sclk1 dsp core sport0 dt1 fl1 tfs1 rfs1 sclk1 spi control block modectrl register (04) sport1 boot mode/uart mode modectrl register (15) sport0 sport mode/uart mode modectrl register (14..13..12) sport0 spi interface control dt1/fl1 dr1 sclk1/sclk0 dt0 dr0 tfs0 rfs0 figure 19. sport0 and sport1 internal multiplexing (simplified diagram) table xi. sport0 pin assignment in spi mode sport i/o signal spi mode spi mode i/o dt0 (data transmit) mosi output (master output/ slave input) dr0 miso input (master input/ slave output) tfs0 ss output (slave select) rfs0 unused n/a sclk0 sck output (serial clock) the slave select pin automatically generates the select signal at each word transfer. this pin can also be used as a general- purpose i/o during the spi transfer without affecting the sport operations. the spi clock polarity and phase are configurable through bits 13 and 12 of the modectrl register. the spi transfer using clock phase is shown in figures 20 and 21.
rev. 0 ADMCF341 ?25? 12345 n see note 1 see note 2 msb msb lsb lsb sck cycle # sck (polarity = 0) sck (polarity = 1) ss mosi moso note 1. lsb of previously transmitted word 2. undefined figure 20. spi transfer using clock phase cpha = 0 12345 n see note 1 see note 2 msb msb lsb lsb sck cycle # sck (polarity = 0) sck (polarity = 1) ss mosi moso notes 1. lsb of previously transmitted word 2. undefined figure 21. spi transfer using clock phase cpha = 1
rev. 0 ?26? ADMCF341 table xii. peripheral register map address (hex) name bits used function 0x2000 adc1 [15 ...4] adc results for i sense 1 0x2001 adc2 [15 ...4] adc results for i sense 2 0x2002 adc3 [15 ...4] adc results for i sense 3 0x2003 adcaux [15 ...4] adc results for vaux 0x2004 porta_dir [8 . . . 0] pa8 . . . pa0 direction setting 0x2005 porta_data [8 . . . 0] pa8 . . . pa0 input/output data 0x2006 porta_inten [8 . . . 0] pa8 . . . pa0 interrupt enable 0x2007 porta_flag [8 . . . 0] pa8 . . . pa0 interrupt status 0x2008 pwmtm [15 ...0] pwm p eriod 0x2009 pwmdt [9 . . . 0] pwm dead time 0x200a pwmpd [9 . . . 0] pwm pulse deletion time 0x200b pwmgate [9 . . . 0] pwm gate drive contguration 0x200c pwmcha [15 ...0] pwm c hannel a pulsewidth 0x200d pwmchb [15 ...0] pwm c hannel b pulsewidth 0x200e pwmchc [15 ...0] pwm chan nel c pulsewidth 0x200f pwmseg [8 . . . 0] pwm segment select 0x2010 auxch0 [7 . . . 0] aux pwm output 0 0x2011 auxch1 [7 . . . 0] aux pwm output 1 0x2012 auxtm0 [7 . . . 0] auxiliary pwm frequency value 0x2013 auxtm1 [7 . . . 0] auxiliary pwm frequency value/offset 0x2014 reserved 0x2015 modectrl [8 . . . 0] mode control register 0x2016 sysstat [3 . . . 0] system status 0x2017 irqflag [1 . . . 0] interrupt status 0x2018 wdtimer [15 ...0] w atchdog timer 0x2019 . . . 48 reserved 0x2049 porta-select [8 . . . 0] pa8 . . . pa0 mode select 0x204a . . . 5f reserved 0x2060 pwmsyncwt [7 . . . 0] pwmsync pulsewidth 0x2061 pwmswt [0] pwm s/w trip bit 0x2062 . . . 67 reserved 0x2068 i const _trim [2 . . . 0] i const _trim 0x2069 sha1_tm [15 ...0] sam ple hold timer 1 0x206a sha2_tm [15 ...0] sam ple hold timer 2 0x206b sha3_tm [15 ...0] sam ple hold timer 3 0x2070 reserved 0x2080 fmcr [15 ...0] flash memory control register 0x2081 fmar [11 ...0] flash memory address register 0x2082 fmdrh [13 ...0] flash memory data register high 0x2083 fmdrl [15 ...0] flash memory data register low 0x2084 . . . ff reserved
rev. 0 ADMCF341 C27C table xiii. dsp core registers address (hex) name bits function 0x3fff syscntl [15 . . . 0] system control register 0x3ffe memwait [15 . . . 0] memory wait state control register 0x3ffd tperiod [15 . . . 0] interval timer period register 0x3ffc tcount [15 . . . 0] interval timer count register 0x3ffb tscale [7 . . . 0] interval timer scale register 0x3ffa sport0_rx_words1 [15 . . . 0] sport0 multichannel word 1 receive 0x3ff9 sport0_rx_words0 [15 . . . 0] sport0 multichannel word 0 receive 0x3ff8 sport0_tx_words1 [15 . . . 0] sport0 multichannel word 1 transmit 0x3ff7 sport0_tx_words0 [15 . . . 0] sport0 multichannel word 0 transmit 0x3ff6 sport0_ctrl_reg [15 . . . 0] sport0 control register 0x3ff5 sport0_sclkdiv [15 . . . 0] sport0 clock divide register 0x3ff4 sport0_rfsdiv [15 . . . 0] sport0 receive frame sync divide 0x3ff3 sport0_autobuf_ctrl [15 . . . 0] sport0 autobuffer control register 0x3ff2 sport1_ctrl_reg [15 . . . 0] sport1 control register 0x3ff1 sport1_sclkdiv [15 . . . 0] sport1 clock divide register 0x3ff0 sport1_rfsdiv [15 . . . 0] sport1 receive frame sync divide 0x3fef sport1_autobuf_ctrl [15 ...0] sp ort1 autobuffer control register flash memory control register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x2080 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 flash memory address register 0 0 0 0 0 0 0 00 0 0 00 0 0 0 0x2081 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved always read 0 address 11 0 flash memory data register low (fmdrl) 0 0 0 0 0 0 0 00 0 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved always read 0 0x2083 status 5 0 data 7 0 flash memory data register high (fmdrh) 0 0 0 0 0 0 0 00 0 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x2082 data 23 8 most significant bit is on the left. for example, data23 is bit 15 of fmdrh. boot memory flash code figure 22. con?guration of flash memory registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 C28C ADMCF341 pwmsyncwt + 1 f clkout t pwmsync, on = 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 00000 00000000 pwmdt (r/w) pwmdt pwmtm (r/w) pwmtm f clkout 2 pwmtm f pwm = 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 pwmseg (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010 00111 00000000 pwmsyncwt (r/w) pwmsyncwt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000 00000 0000 00 0 0 pwmswt (r/w) dm (0x 2008) dm (0x200f) 2 pwmtm f clkout t d = ch output disable cl output disable bh output disable bl output disable ah output disable al output disable 0 = enable 1 = disable a channel crossover b channel crossover c channel crossover 0 = no crossover 1 = crossover dm (0x2060) dm (0x2061) dm (0x2009) figure 23. con?guration of pwm registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 ADMCF341 C29C 0 0 0 0 0 0 0 0 0 0 low side gate chopping 0 = disable 1 = enable high side gate chopping dm (0x200b) gdclk gate drive chopping frequency pwmgate (r/w) pwmpd (r/w) dm (0x200a) pwmpd pwmcha (r/w) pwm channel a duty cycle dm (0x200c) pwmchb (r/w) pwm channel b duty cycle dm (0x200d) pwmchc (r/w) dm (0x200e) pwm channel c duty cycle t min = pwmpd f clkout f chop = 4 (gdclk + 1) f clkout 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 00 0 figure 24. con?guration of additional pwm registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 C30C ADMCF341 porta_dir (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pa0-pa8 dm (0x2004) 0 = input 1 = output porta_data (r/w) 0 0 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pa0-pa8 dm (0x2005) 0 = low level 1 = high level 0 0 0 00 0 0 0 porta_select (r/w) 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 1 1 1 11 1 1 1 0 = dr0 1 = pa0 0 = dt0 1 = pa1 0 = rfs0 1 = pa2 0 = tfs0 1 = pa3 0 = aux0/clockout 1 = pa8 0 = aux1/pwmsync 1 = pa7 0 = dr1 1 = pa6 0 = sclk1/sclk0 1 = pa4 0 = pwmsync 1 = aux1 0 = dt1/fl1 1 = pa5 0 = clockout 1 = aux0 dm (0x2049) figure 25. con?guration of pio registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 ADMCF341 C31C 0 0 0 0 dm (0x2006) porta_inten (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 00 0 0 0 0 = interrupt disable 1 = interrupt enable 0 0 0 0 dm (0x2007) porta_flag (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = interrupt disable 1 = interrupt enable 0 0 0 0 0 0 0 0 0 0 0 0 figure 26. con?guration of additional pio registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld? hese bits should always be written as shown. 0 0 0 0 dm (0x2010) auxch0 (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2011) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2012) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2013) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aux1 period = 2 (auxtm1) t ck offset = 2 (auxtm1) t ck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 t on, aux0 = 2 (auxch0) t ck t on, aux1 = 2 (auxch1) t ck aux0 period = 2 (auxtm0 + 1) t ck auxch1 (r/w) auxtm0 (r/w) auxtm1 (r/w) figure 27. con?guration of auxiliary pwm register default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset.
rev. 0 C32C ADMCF341 0 0 0 0 dm (0x2000) adc1 (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dm (0x2001) adc2 (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dm (0x2002) adc3 (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dm (0x2003) adcaux (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2068) i const _trim (r/w) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i const min = bits 0 ? 2 cleared. i const max = bits 0 ? 2 set. 0 0 0 00 0 0 00 0 0 00 0 0 0 sha1_tm (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x2069) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x206a) sha2 _tm (r/w) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm (0x206b) sha3 _tm (r/w) conversion status 0 = data ready 1 = not ready conversion status 0 = data ready 1 = not ready conversion status 0 = data ready 1 = not ready figure 28. con?guration of adc registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 ADMCF341 C33C adc mux control 0 = boot mode 1 = uart mode sport1 mode select 0 = disable 1 = enable pwmsync interrupt 0 = disable 1 = enable pwmtrip i nterrupt 0 0 0 0 0 0 00 0 0 0 sysstat (r) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = low 1 = high dm (0x2016) 0 = normal 1 = watchdog reset occurred pwmtrip pin status watchdog status pwm timer status 0 = 1st half of pwm cycle 1 = 2nd half of pwm cycle 0 0 00 0 0 0 00 0 0 00 0 0 0 modectrl (r/w) dm (0x2015) 0 = single update mode 1 = double update mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adc mux control 00 vaux0 01 vaux1 10 vaux2 11 vref 0 0 00 0 0 0 00 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 00 irqflag (r) pwmtrip interrupt pwmsync interrupt dm (0x2017) 0 0 0 0 0 0 00 0 0 00 0 0 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdtimer (w) dm (0x2018) 01 0 = no interrupt 1 = interrupt occurred pwm update mode select adc counter 0 = clkin rate 1 = clkout rate aux pwm mode select channel 1 selection 0 = offset mode 1 = independent mode 0 = i sense 1 = voltage channel 2 selection 0 = i sense 1 = voltage channel 3 selection 0 = i sense 1 = voltage sport 0 mode select 0 = sport mode 1 = uart mode sport 0 spi mode 0 = sport 1 = spi mode spi clock polarity 0 = standard 1 = reverse spi clock phase 0 = pha0 1 = pha1 not used in ADMCF341 set bit to zero figure 29. con?guration of status/control registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 C34C ADMCF341 sport1 receive or irq0 ifc interrupt force interrupt clear 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ti mer so ftware 0 so ftware 1 irq2 ti mer so ftware 0 so ftware 1 irq2 dsp register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sport1 transmit or irq1 sport1 receive or i r q 0 sport1 transmit or i r q 1 1 1 0 0 0 irq0 sensitivity 0 = level 1 = edge icntl irq1 sensitivity irq2 sensitivity interrupt nesting 0 = disable 1 = enable dsp register 43210 imask (r/w) p eripheral (or irq2 ) ti mer sport1 receive (or irq0 ) sport1 transmit (or irq1 ) so ftware 0 so ftware 1 0 0 0 0 0 0 0 00 0 0 00 1 1 0 dsp register 0 = disable (mask) 1 = enable 0 = disable (mask) 1 = enable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sport0 transmit sport0 receive sport0 receive sp ort0 transmit sport0 transmit sport0 receive figure 30. con?guration of interrupt control registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
rev. 0 ADMCF341 C35C 1 dm (0x3ffe) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 memwait (r/w) 1 1 0 0 0 0 00 0 11 1 1 1 sport1 configure 0 = fi, fo, irq0, irq1, sclk 1 = serial port sport1 enable 0 = disabled 1 = enabled syscntl (r/w) dm (0x3fff) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1111111 11111111 sport0 enable 0 = disabled 1 = disabled figure 31. con?guration of registers default bit values are shown; if no value is shown, the bit ?ld is unde?ed at reset. reserved bits are shown on a gray ?ld?hese bits should always be written as shown.
c02470C0C4/02(0) printed in u.s.a. C36C ADMCF341 rev. 0 28-lead wide-body soic (r-28) 0.32 (0.0125) 0.23 (0.0091) 8 0 0.75 (0.029) 0.25 (0.010) 45 1.27 (0.0500) 0.40 (0.016) seating plane 0.30 (0.0118) 0.10 (0.0040) 0.51 (0.020) 0.33 (0.013) 2.65 (0.1043) 2.35 (0.0926) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7125) 17.70 (0.6969) 10.65 (0.419) 10.00 (0.394) 7.60 (0.2992) 7.40 (0.2914) pin 1 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design outline dimensions dimensions shown in mm and (inches).

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