technical data 1 hex unbuffered inverter high - performance silicon - gate cmos the in74hc u 04a is identical in pinout to the ls/a ls04. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/alsttl outputs. this device consists of six single - stage inverters. these inverters are well suited for use as oscillators, pulse shapers , and in many other applications requiring a high - input impedance amplifier. for digital applications, the hc04 is recommended. outputs directly interface to cmos, nmos, and ttl operating voltage range: 2.0 to 6.0 v; 2.5 to 6 v in oscillator configurations . low input current: 1.0 m a high noise immunity characteristic of cmos devices in74hcu04 ordering information in74hcu04n plastic in74hcu04d soic iz74hcu04 chip t a = - 55 to 125 c for all packages logic diagram pin 14 =v cc pin 7 = gnd pin assignment 1 2 3 5 4 6 7 v cc 14 13 12 11 10 8 9 gnd a1 y1 a2 y2 a3 y3 a6 y6 a5 y5 a4 y4 function table inputs output a y l h h l
in74hcu04 2 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) - 0.5 to +7.0 v v in dc input voltage (referenced to gnd) - 1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) - 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip ** soic package ** 750 500 mw tstg storage temperature - 65 to +150 c t l lead temperature, 1 mm from case for 10 secon ds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. ** derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temper ature, all package types - 55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 a v cc =4.5 a v cc =6.0 a - 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. howeve r, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high - impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be t ied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74hcu04 3 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to - 55 c 85 c 125 c u nit v ih minimum high - level input voltage v out =0.1 v * i out 20 m a 2.0 4.5 6.0 1.7 3.6 4.8 1.7 3.6 4.8 1.7 3.6 4.8 v v il maximum low - level input voltage v out = v cc - 0.1 v * i out 20 m a 2.0 4.5 6.0 0.3 0.8 1.1 0.3 0.8 1.1 0.3 0.8 1.1 v v oh minimum hig h - level output voltage v in =v il i ou t 20 m a 2.0 4.5 6.0 1.8 4.0 5.5 1.8 4.0 5.5 1.8 4.0 5.5 v v in =v il i out 4.0 ma i out 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low - level output voltage v in =v ih i out 20 m a 2. 0 4.5 6.0 0.2 0.5 0.5 0.2 0.5 0.5 0.2 0.5 0.5 v v in =v ih i out 4.0 ma i out 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 m a i cc maximum quiescent supply current (pe r package) v in =v cc or gnd i out =0 m a 6.0 2.0 20 40 m a * for v cc = 2.0 v, v out = 0.2 v or v cc ? 0.2 v.
in74hcu04 4 ac electrical characteristics (c l =50pf, input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to - 55 c 85 c 125 c unit t plh , t phl max imum propagation delay, input a to output y (figures 1 and 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns t tlh , t thl maximum output transition time, any output (figures 1 and 2) 2.0 4.5 6.0 70 15 13 85 18 16 100 22 19 ns c in maximum input capacitance - 10 10 10 pf c pd power dissipation capacitance (per inverter) t a =25 ? ? , v cc =5.0 v pf used to determine the no - load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc for load considerations, see chepter 4. 15 t r v cc gnd 90% 50% 10% 90% 50% 10% input a output y t phl t plh t th l t tl h t f * includes all probe and jig capacitance c l * test point device under test output figure 1. switching wavef orms. figure 2. test circuit logic detail (1/6 of device show) a v c c y
in74hcu04 5 typical applications crystal oscillator stable rc oscillator r 2 1/6 hcu04 c 1 r 2 > > r 1 c 1 < c 2 v out c 2 r 1 r 2 r 1 c 1/6 hcu04 1/6 hcu04 1/6 hcu04 v out schmitt trigger high input single - stage amplifier with a 2 to 6 v supply range r 2 r 1 v in v out 1/6 hcu04 1/6 hcu04 r 2 > 6r 1 v cc input output 1 m 1 m 1/6 hcu04 multi - stage amplifier led driver v cc input output 1/6 hcu04 1/6 hcu04 1/6 hcu04 +v 1/6 hcu04 for reduced power suplly current, use high - efficiency leds such as the hewlett - packard hlmp series or equivalent
in74hcu04 6 chip pad diagram iz74hcu04 chip marking 25HCU04A (x=0.992, y=0.092) 1.17 + 0.003 1 . 1 9 + 0 . 0 0 3 (0,0) thickness of chip 0.46 0,02 mm pad l ocation pad no symbol x y pad size* , mm 01 a1 0.110 0.280 0.105x0.105 02 y1 0.170 0.110 0.105x0.105 03 a2 0.350 0.110 0.105x0.105 04 y2 0.610 0.110 0.105x0.105 05 a3 0.850 0.110 0.105x0.105 06 y3 0.950 0.320 0.105x0.105 07 gnd 0.950 0.510 0.105x0.1 05 08 y4 0.950 0.760 0.105x0.105 09 a4 0.850 0.970 0.105x0.105 10 y5 0.610 0.970 0.105x0.105 11 a5 0.350 0.970 0.105x0.105 12 y6 0.170 0.970 0.105x0.105 13 a6 0.110 0.800 0.105x0.105 14 v cc 0.110 0.550 0.105x0.105 * pad size is given as per metalli zation layer
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