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white electronic designs corporation ? (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs
the wedc syncburst - sram family employs high-speed, low- power cmos designs that are fabricated using an advanced cmos process. wedc?s 32mb sync sram integrate two 512k x 32 srams into a single bga package to provide 512k x 64 configuration. all synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (clk). the nbl or no bus latency memory utilizes all the band- width in any combination of operating cycles. address, data inputs, and all control signals except output enable are syn- chronized to input clock. output enable controls the out- puts at any given time and to asynchronous input. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. note: nbl = no bus latency is equivalent to the industry zbt? devices.

sa 0 ? 18 512k x 36 512k x 36 dq 0 ? 31 dq 32 ? 63 oe b web_lw clk cs 2b cs 2 cs 1b oe we clk cs 2 cs 2 cs 1 oe we clk cs 2 cs 2 cs 1 dq 0 ? 31 a 0 ? a 18 a 0 ? a 18 dq 0 ? 31 web_hw u1 u2 fast clock speed: 166, 150, 133, and 100mhz fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns fast oe access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns seperate +2.5v 5% power supplys for core i/o (v dd + v ddq ) double word write control clock-controlled and registered addresses, data i/os and control signals packaging: 119-bump bga package low capacitive bus loading 123456 78 9 adq f dq f dq f dq f nc dq g dq g dq g dq g bdq f dq f dq f dq f nc dq g dq g dq g dq g cdq e dq e dq e dq e nc dq h dq h dq h dq h ddq e dq e dq e dq e nc dq h dq h dq h dq h encncncv ddq v ddq v ddq nc nc nc fsav ddq v dd v dd v dd v dd v dd v ddq sa gsacev ss v ss v ss v ss v ss sa sa hsancv ss we 1 v ss v ss v ss sa sa jsa 18 ce 2 ss clk oe nc nc nc sa 1 sa 0 ksace 2 v ss we 0 v ss v ss v ss sa sa lsancv ss v ss v ss v ss v ss sa sa msav ddq v dd v dd v dd v dd v dd v ddq sa nncncncv ddq v ddq v ddq nc nc nc pdq d dq d dq d dq d nc dq a dq a dq a dq a rdq d dq d dq d dq d nc dq a dq a dq a dq a tdq c dq c dq c dq c nc dq b dq b dq b dq b udq c dq c dq c dq c nc dq b dq b dq b dq b
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs rising edge of the clock and the data is latched in the output register. at the second clock edge the data is driven out of the sram. during read operation oe must be driven low for the device to drive out the requested data. write operation occurs when we is driven low at the rising edge of the clock. the pipe-lined nbl ssram uses a late- late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are regis- tered, and the data associated with that address is required two cycle later.

the wed2zl64512s is an nbl ssram designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe) are synchronized to rising clock edges. output enable (oe) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, cke is driven low, the write enable input signals we are driven high. the internal array is read between the first rising edge and the second

hxx n/a deselect lhl current address read cycle lhh n/a nop/dummy read xxh n/a dummy read llx current address write cycle llx n/a nop/write abort notes: 1. x means ?don?t care.? 2. the rising edge of clock is symbolized by ( ) 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table.
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs

v oltage on v dd s upply r elative to v ss -0.3v to +3.6v v in (dq x ) -0.3v to +3.6v v in (i nputs ) -0.3v to +3.6v s torage t emperature (bga) -55c to +125c s hort c ircuit o utput c urrent 100ma

*stress greater than those listed under ?absolute maximum ratings: may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condtions for extended periods may affect reliability.
i nput h igh (l ogic 1) v oltage v ih 1.7 v dd +0.3 v 1 i nput l ow (l ogic 0) v oltage v il -0.3 0.7 v 1 i nput l eakage c urrent i li 0v - v in - v dd -5 5 a o utput l eakage c urrent i lo o utput ( s ) d isabled , 0v - v in - v dd -5 5 a o utput h igh v oltage v oh i oh = -1.0ma 2.0 --- v 1 o utput l ow v oltage v ol i ol = 1.0ma --- 0.4 v 1 s upply v oltage v dd 2.375 2.625 v 1 notes: 1. all voltages referenced to vss (gnd)

notes: 1. i dd is specified with no output current and increases with faster cycle times. i dd increases with faster cycle times and greater output loading. 2. typical values are measured at 2.5v, 25c, and 10ns cycle time.
notes: 1. this parameter is sampled.

c ontrol i nput c apacitance c l ta = 25c; f = 1mh z 57pf1 i nput /o utput c apacitance (dq) c o ta = 25c; f = 1mh z 68pf1 a ddress c apacitance c a ta = 25c; f = 1mh z 57pf1 c lock c apacitance c ck ta = 25c; f = 1mh z 35pf1

p ower s upply i dd d evice s elected ; a ll i nputs v il or v ih ; c ycle 650 600 560 500 ma 1, 2 c urrent : o perating t ime = t cyc min; v dd = max; o utput o pen p ower s upply i sb 2 d evice d eselected ; v dd = max; a ll i nputs v ss + 0.2 3060606060 ma 2 c urrent : s tandby or v dd - 0.2; a ll i nputs s tatic ; clk f requency = 0 c lock r unning i sb 4 d evice d eselected ; v dd = max; a ll i nputs 140 120 100 80 ma 2 s tandby c urrent v ss + 0.2 or v dd - 0.2; c ycle t ime = t cyc min
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs

c lock t ime t cyc 6.0 6.7 7.5 10.0 ns c lock a ccess t ime t cd -- 3.5 -- 3.8 -- 4.2 -- 5.0 ns o utput enable to d ata v alid t oe -- 3.5 -- 3.8 -- 4.2 -- 5.0 ns c lock h igh to o utput l ow -z t lzc 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns o utput h old from c lock h igh t oh 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns o utput e nable l ow to output l ow -z t lzoe 0.0 -- 0.0 -- 0.0 -- 0.0 -- ns o utput e nable h igh to o utput h igh -z t hzoe -- 3.0 -- 3.0 -- 3.5 -- 3.5 ns c lock h igh to o utput h igh -z t hzc -- 3.0 -- 3.0 -- 3.5 -- 3.5 ns c lock h igh p ulse w idth t ch 2.2 -- 2.5 -- 3.0 -- 3.0 -- ns c lock l ow p ulse w idth t cl 2.2 -- 2.5 -- 3.0 -- 3.0 -- ns a ddress s etup to c lock h igh t as 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns cke s etup to c lock h igh t ces 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns d ata s etup to c lock h igh t ds 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns w rite s etup to c lock h igh t ws 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns c hip s elect s etup to c lock h igh t css 1.5 1.5 1.5 1.5 ns a ddress h old to c lock high t ah 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns cke h old to c lock h igh t ceh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns d ata h old to c lock h igh t dh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns w rite h old to c lock h igh t wh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns c hip s elect h old to c lock h igh t csh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns notes: 1. all address inputs must meet the specified setup and hold times for all rising clock (clk) edges when adv is sampled low and cex is sampled valid. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip enable must be valid at each rising edge of clk (when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device. a read cycle is defined by we high. both cases must meet setup and hold times.

dout zo=50 rl=50 vl=1.25v 30pf* dout 1538 5pf* +2.5v 1667 *including scope and jig capacitance

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white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs notes: write = l means we = l, and bwx = l cex refers to the combination of ce 1 , ce 2 and ce 2 . clock address we 0b we 1b oe b data out t ch t cl t as t ah a 1 a 2 t ws t wh t css t csh t oe t hz oe t lzoe t cd t o h q2-1 q1-1 don't care undefined cex timing waveform of read cycle
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs timing waveform of write cycle notes: write = l means we = l, and bwx = l cex refers to the combination of ce 1 , ce 2 and ce 2 . clock address we 0b we 1b data in t ch t cl a 2 d2-1 d1-1 oe b data out don't care undefined a 1 q0-4 t hzoe q0-3 cex
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs timing waveform of single read/write notes: write = l means we = l, and bwx = l cex refers to the combination of ce 1 , ce 2 and ce 2 . clock a ddress we 0b we 1b oe b data in t ch t cl t ds t dh data out a 2 a 4 a 5 d 2 t oe t lzoe q1 don't care undefined a 1 a 3 a 7 a 6 q3 q4 q7 q6 d5 a 9 a 8 cex
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs notes: write = l means we = l, and bwx = l cex refers to the combination of ce 1 , ce 2 and ce 2 . clock a ddress we 0b we 1b oe b data in t ch t cl data out a 1 a 2 a 3 a 4 a 5 don't care undefined t cyc d5 q4 q1 q2 t oe t lz oe d3 t cd t lzc t hz c t dh t ds cex timing waveform of ce operation
white electronic designs corporation (508) 366-5151 www.whiteedc.com
october 2001 rev. 0 eco #14597 white electronic designs
119 bump pbga all linear dimensions are in millimeters and parenthetically in inches 1.90 (0.075) max 0.711 (0.028) max 1.27 (0.050) typ 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 17.00 (0.669) typ a 1 corner 20.32 (0.800) typ 23.00 (0.905) typ 7.62 (0.300) typ

part number configuration t cd clock wed2zl64512s35bc512k x 64 3 . 5 166 wed2zl64512s38bc512k x 64 3 . 8 150 wed2zl64512s42bc512k x 64 4 . 2 133 wed2zl64512s50bc512k x 64 5 . 0 100 note: ball attach pad for above bga package is 620 microns in diameter. pad is solder mask defined.

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