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vmebus interface controller with d64 functionality vic64 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-09002 rev. ** revised july 22, 1997 features ? an enhanced vic068a ? 64-bit mblt operation ? higher transfer rate complete vmebus interface controller and arbiter ? 58 internal registers for configuration control and vmebus and local operations status ? drives arbitration, interrupt, address modifier, utility, strobe, address line a[7:1], and data line d[7:0] di- rectly and provides control signals to drive remain- ing address and data lines ? direct connection to 68k family and mappable to non-68k processors complete master/slave capability ? supports read, write, write posting, and block trans- fers ? accommodates vmebus timing requirements with internal digital delay line with half-clock granularity ? programmable metastability delay ? programmable data acquisition delays ? provides programmable timeout timers for local bus and vmebus transactions interleaved block transfers ? d64 block transfer capability in conformance with vme64 proposal ? can act as dma master on local bus ? programmable burst counter, transfer length, and in- terleave period ? allows master and slave transfer to occur during in- terleave period ? also supports local module-based dma arbitration support ? supports single-level, priority, and round-robin arbi- tration ? support fair request option as requester interrupt support ? complete support for the vmebus interrupts; inter- rupters and interrupt handler ? seven local interrupt lines ? 8-level interrupt priority encoded ? total of 29 interrupts mapped through the vic64 miscellaneous features ? refresh option for local dram ? four broadcast location monitors ? four module-specific location monitors ? eight interprocessor communication registers see the vmebus interface handbook for more informa- tion functional description cypress ? s vic64 vmebus interface controller with d64 func- tionality is a single chip designed to minimize the cost and board area requirements and to maximize the performance of a vmebus master/slave module. data transfers of 70 mbyte/sec are possible between boards using vic64. in addition to d8, d16, and d32 operations, the vic64 per- forms d64 data transfer. on-chip output buffers are used to provide direct connection to address and data lines. the vic64 is based on the industry-standard vic068a. for most applications, the vic64 is fully software and plug com- patible with the vic068a. (as vic64 uses register bits that are unassigned in vic068a, user code may require simple rework to insure compatibility.) the local bus interface of the vic64 emulates motorola ? s fam- ily of 32-bit 68k processor interfaces. other processors can easily be adapted to interface to the vic64 using appropriate logic. resetting the vic64 the vic64 can be reset by any of three distinct reset condi- tions: internal reset. this reset is the most common means of resetting the vic64. it resets selected register values and logic within the device. system reset. this reset provides a means of resetting the vic64 through the vmebus backplane. the vic64 may also initiate a system reset by writing a configuration register. global reset. this provides the most complete reset of the vic64. it resets all of the vic64 ? s configuration registers. all three reset options are implemented in a different manner and have different effect on the vic64 configuration registers. vic64 vmebus system controller the vic64 is capable of operating as the vmebus system con- troller. it provides vmebus arbitration functions, including: priority, round-robin, and single-level arbitration schemes driving iack daisy-chain driving bgiout daisy-chain (all four levels) driving sysclk output vmebus arbitration timeout timer the system controller functions are enabled by the scon pin of the vic64. this pin is sampled during reset and if low, vic64 performs as system controller. after reset the pin be- comes an output signifying a d64 transfer. vic64 vmebus master cycles the vic64 is capable of becoming the vmebus master in re- sponse to a request from local resources. in this situation, the local resource requests a vmebus transfer. the vic64 makes a request for the vmebus. when the vmebus is granted to the vic64, it then performs the transfer and acknowledges the lo-
vic64 document #: 38-09002 rev. ** page 2 of 13 cal resource and the cycle is complete. the vic64 is capable of all four vmebus request levels. in addition, the following release modes are supported: release on request (ror) release when done (rwd) release on clear (roc) release under rmc control bus capture and hold (bcap) pin configurations ab cde fg hj kl mn p r 1 2 3 4 5 6 9 10 11 12 13 14 15 7 8 a02 ipl2* liacko* locator pin lirq2* asiz1 icfsel* vcc slsel1* gnd vcc fciack* ld6 mwb* pin grid array (pga) lirq5* asiz0 gnd word* a04 irq4* blt* ipl1* lirq1* lirq4* lirq6* a01 a03 a05 a07 irq3* irq7* irq2* irq6* irq1* a06 gnd slsel0* gnd lirq7* lirq3* ipl0* ld2 ld5 ld1 ld3 ld0 ld4 la7 la3 la5 la6 la2 la4 la1 la0 cs* ds* pas* irq5* vcc vcc vcc vcc d00 d01 d04 d03 d05 d06 d07 d02 gnd gnd gnd gnd gnd vcc gnd ld7 gnd gnd bgout0* bgout3* bgout2* bgin2* bgout1* bgin0* bgin3* bgin1* bclr* bbsy* br1* br3* br2* ds1* ds0* br0* ledo ledi lado ladi fc2 fc1 scon*/d64 ddir lwdenin* deno* siz0 siz1 lbg* aben* ireset* halt* dsack0* lbr* rmc* r/w* dsack1* reset* lberr* vcc clk64m uwdenin* swden* isobe* sysclk berr* write* am5 am3 am2 am1 am0 am4 as* lword* dedlk* laen acfail* iackout* sysfail* sysreset* iackin* iack* dtack* bottom view vic64-1
vic64 document #: 38-09002 rev. ** page 3 of 13 pin configurations (continued) 160-pin quad flatpack (qfp) top view vic64-2 1 gnd 120 gdn 2 gnd 119 gnd 3 ipl0* 118 lbg* 4 ipl1* 117 ireset* 5 ipl2* 116 scon*/d64 6 vcc 115 clk64m 7 laen 114 aben* 8 liako* 113 lado 9 lirq1* 112 ladi 10 lirq2* 111 ledi 11 lirq3* 110 vcc 12 lirq4* 109 ledo 13 lirq5* 108 ddir 14 lirq6* 107 uwdenin* 15 lirq7* 106 gnd 16 asiz1* 105 lwdenin* 17 asiz0* 104 deno* 18 icfsel* 103 swden* 19 slsel1* 102 isobe* 20 gnd 101 vcc 21 slsel0* 100 gnd 22 word* 99 d07 23 fciack* 98 d06 24 mwb* 97 d05 25 a1 96 d04 26 gnd 95 vcc 27 a2 94 d03 28 a3 93 d02 29 a4 92 d01 30 vcc 91 d00 31 a5 90 bgout3* 32 a6 89 gnd 33 a7 88 bgout2* 34 gnd 87 bgout1* 35 irq1* 86 bgout0* 36 irq2* 85 sysclk 37 irq3* 84 bgin3* 38 irq4* 83 bgin2* 39 gnd 82 gnd 40 gnd 81 gnd 41 vcc 160 vcc 42 vcc 159 vcc 43 irq5* 158 gnd 44 irq6* 157 blt* 45 irq7* 156 dedlk* 46 vcc 155 ld7 47 sysfail* 154 ld6 48 acfail* 153 ld5 49 sysreset* 152 ld4 50 iackout* 151 ld3 51 iackin* 150 ld2 52 iack* 149 ld1 53 dtack* 148 ld0 54 as* 147 la7 55 gnd 146 la6 56 am0 145 la5 57 am1 144 la4 58 am2 143 la3 59 am3 142 la2 60 gnd 141 gnd 61 vcc 140 vcc 62 am4 139 la1 63 am5 138 la0 64 lword* 137 cs* 65 write* 136 pas* 66 berr* 135 ds* 67 ds0* 134 dsack1* 68 ds1* 133 dsack0* 69 br0* 132 lberr* 70 vss 131 reset* 71 br1* 130 halt* 72 br2* 129 r/w* 73 br3* 128 fc2 74 bclr* 127 fc1 75 bbsy* 126 rmc* 76 bgin0* 125 siz1 77 bgin1* 124 siz0 78 gnd 123 lbr* 79 vcc 122 vcc 80 vcc 121 vcc
vic64 document #: 38-09002 rev. ** page 4 of 13 pin configurations (continued) 144-pin thin quad flatpack (tqfp) top view vic64-3 gnd lbg* irq5* ipl0* 2 3 4 ipl1* ireset* 5 ipl2* scon*/d64 6 vcc clk64m 7 laen aben* 8 liako* lado 9 lirq1* ladi 10 lirq2* ledi 11 lirq3* vcc 12 lirq4* ledo 13 lirq5* 108 ddir 14 lirq6* 107 uwdenin* 15 lirq7* 106 gnd 16 asiz1* 105 lwdenin* 17 asiz0* 104 deno* 18 icfsel* 103 swden* 19 slsel1* 102 isobe* 20 gnd 101 vcc 21 slsel0* 100 gnd 22 word* 99 d07 23 fciack* 98 d06 24 mwb* 97 d05 25 a1 96 d04 26 gnd 95 vcc 27 a2 94 d03 28 a3 93 d02 29 a4 92 d01 30 vcc 91 d00 31 a5 90 bgout3* 32 a6 89 gnd 33 a7 88 bgout2* 34 gnd 87 bgout1* 35 irq1* 86 bgout0* 36 irq2* 85 sysclk irq3* 84 bgin3* irq4* 83 bgin2* 82 81 41 42 43 44 irq6* blt* 45 irq7* dedlk* 46 vcc ld7 47 sysfail* ld6 48 acfail* ld5 49 sysreset* ld4 50 iackout* ld3 51 iackin* ld2 52 iack* ld1 53 dtack* ld0 54 as* la7 55 gnd la6 56 am0 la5 57 am1 la4 58 am2 143 la3 59 am3 142 la2 60 gnd 141 gnd 61 vcc 140 vcc 62 am4 139 la1 63 am5 138 la0 64 lword* 137 cs* 65 write* 136 pas* 66 berr* 135 ds* 67 ds0* 134 dsack1* 68 ds1* 133 dsack0* 69 br0* 132 lberr* 70 vss 131 reset* 71 br1* 130 halt* 72 br2* 129 r/w* 123 br3* 128 fc2 122 bclr* 127 fc1 121 bbsy* 126 rmc* 120 bgin0* 125 siz1 119 bgin1* 124 siz0 118 gnd lbr* 117 116 37 38 39 40 80 79 78 77 76 75 74 73 115 114 113 112 111 110 109 144 1
vic64 document #: 38-09002 rev. ** page 5 of 13 functional description (continued) the vic64 supports a32, a24, and a16, as well as user-defined address spaces. master write-posting the vic64 is capable of performing master write-posting (bus decoupling). in this situation, the vic64 acknowledges the local resource immediately after the request to the vic64 is made, thus freeing the local bus. the vic64 latches the local data to be written and performs the vmebus transfer without the local resource having to wait for vmebus arbitration. indivisible cycles read-modify-write cycles and indivisible multiple-address cycles (imacs) are easily performed using the vic64. significant control is allowed for: requesting the vmebus on the assertion of rmc indepen- dent of mwb* (this prevents any slave access from inter- rupting local indivisible cycles) stretching the vmebus as* making the above behaviors dependent on the local sizi signals deadlock if a master operation is attempted when a slave operation to the same module is in progress, a deadlock condition occurs. the vic64 signals a deadlock condition by asserting the dedlock* signal. this should be used by the local resource requesting the vmebus to try the transfer after the slave access has completed. self-access if the vic64, while it is vmebus master, has a slave select signaled, a self-access has occurred. the vic64 asserts berr* and lberr*. vic64 vmebus slave cycles the vic64 is capable of operating as a vmebus slave controller. the vic64 contains a highly programmable environment to allow for a wide variety of slave configurations. the vic64 allows for: d64, d32, d16, or d8 configuration a32, a24, a16, or user-defined address spaces programmable block transfer support including: ? dma-type block transfer (pas* and dsacki* held asserted) ? non dma-type block transfer (toggle pas&* and dsacki*) ? no support for block transfer programmable data acquisition delays programmable pas* and ds* timing restricted slave accesses (supervisory accesses only) when a slave access is required, the vic64 requests the local bus. when local bus mastership is obtained, the vic64 reads or writes the data to/from the local resource and asserts the dtack* signal to complete the transfer. slave write-posting the vic64 is capable of performing a slave write-post operation (bus decoupling). when enabled, the vic64 latches the data to be written, and acknowledges the vmebus (asserts dtack*) immediately thereafter. this prevents the vmebus from having to wait for local bus access. address modifier (am) codes the vic64 encodes and decodes the vmebus address modifier codes. for vmebus master accesses, the vic64 encodes the appropriate am codes through the vic64 fci and asizi signals, as well as the block transfer status. for slave accesses, the vic64 decodes the am codes and checks the slave select control registers to see if the slave request is to be supported with regard to address spaces, supervisory accesses, and block transfers. the vic64 also supports user-defined am codes; that is, the vic64 can be made to assert and respond to user-defined am codes. vic64 vmebus block transfers the vic64 is capable of both master and slave block transfers. the master vic64 performs a block transfer in one of two modes: the master block transfer with local dma (d16, d32, and d64) the movem-type block transfer (d16 and d32) in addition to these vmebus block transfers, the vic64 is also capable of performing block transfers from one local resource to another in a dma-like fashion. this is referred to as a module-based dma transfer. for d32 block transfers, the vmebus specification restricts block transfers from crossing 256-byte boundaries without toggling the address strobe, in addition to restricting the maximum length of the transfer to 256 bytes. the vic64 allows for easy implementation of block transfers that exceed the 256-byte restriction by releasing the vmebus at the appropriate time and re-arbitrating for the bus at a programmed time later (this in-between time is referred to as the interleave period), while at the same time holding both the local and vmebus addresses with internal latches. all of this is performed without processor/software intervention until the transfer is complete. for d64 block transfers, the vmebus specification allows for bursts of up to 2048 bytes. the vic64 contains two separate address counters for the vmebus and local address buses. in addition, a separate address counter is provided for slave block transfers. the vic64 address counters are 8-bit up-counters that provide for transfers up to 256 bytes. for transfers that exceed the 256 byte limit, the external counters and latches are required. the vic64 is capable of performing a32/a16:d64/d32/d16 master block transfers. for d64 transfers, external logic is required for the multiplexing of the data and address signals for the upper 24 address/data lines. the cy7c964 is specifically designed for this purpose. multiplexing for the lower 8 bits is done within the vic64. the vic64 allows slave accesses to occur during the interleave period. master accesses are also allowed during interleave with programming and external logic. this is referred to as the dual-path option.
vic64 document #: 38-09002 rev. ** page 6 of 13 movem master block transfer this mode of block transfer provides the simplest implementation of vmebus block transfers. for this mode, the local resource simply configures the vic64 for a movem block transfer and proceeds with the consecutive-address cycles (such as a 68k movem instruction). the local resource continues as the local bus master in this mode. master block transfers with local dma in this mode, the vic64 becomes the local bus master and reads or writes the local data in a dma-like fashion. this provides a much faster interface than the movem block transfer, but with less control and fault tolerance. d64 block transfers are not supported by movem protocol. vic64 slave block transfer the vic64 is capable of decoding the address modifier codes to determine that a slave block transfer is desired. in this mode, the vic64 captures the vmebus address, and latches it into internal counters. for subsequent cycles, the vic64 simply increments this counter for each transfer. the local protocol for slave block transfers can be configured in a full handshake mode by toggling both pas* and ds* and expecting dsacki* to toggle, or in an accelerated mode in which only ds* toggles and pas* is asserted throughout the cycle. for d64 slave block transfers, the scon*/d64 signal is asserted to indicate a d64 transfer is in progress. external logic is required to de-multiplex the data from the vmebus address bus for the upper 24 address/data lines. the lower 8 bits are done within the vic64. module-based dma transfers the vic64 can act as a dma controller between two local resources. this mode is similar to that of master block trans- fers with local dma, with the exception that the vmebus is not the source or destination. vic64 interrupt generation and handling facilities the vic64 can generate and handle a seven-level prioritized interrupt scheme similar to that used by the motorola 68k processors. these interrupts include: 7 vmebus interrupts 7 local interrupts 5 vic64 error/status interrupts 8 interprocessor communication interrupts. the vic64 can be configured to act as handler for any of the seven vmebus interrupts. the vic64 can generate the seven vmebus interrupts as well as supplying a user-defined status/id vector. the local priority level (ipl) for vmebus interrupts is programmable. when configured as the system controller, the vic64 drives the iack* daisy chain. the local interrupts can be configured with the following: user-defined local interrupt priority level (ipl) option for vic64 to provide the status/id vector edge or level sensitivity polarity (rising/falling edge, active high/low) the vic64 is also capable of generating local interrupts on certain error or status conditions. these include: acfail* asserted sysfail* asserted failed master write-post (berr* asserted) local dma completion for block transfers arbitration timeout vmebus interrupter interrupt the vic64 can also interrupt on the setting of a module or global switch in the interprocessor communication facilities. interprocessor communication facilities the vic64 includes interprocessor registers and switches that can be written and read through vmebus accesses. these are the only such registers that are directly accessible from the vmebus. included in the interprocessor communication facilities are: four general-purpose 8-bit registers four module switches four global switches vic64 version/revision register (read-only) vic64 reset/halt condition (read-only) vic64 interprocessor communication register semaphores when set through a vmebus access, these switches can interrupt a local resource. the vic64 includes module switches that are intended for a single module, and global switches which are intended to be used as a broadcast. related documents vmebus interface handbook operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% military ? 55 c to +125 c 5v 10%
vic64 document #: 38-09002 rev. ** page 7 of 13 ordering information ordering code package name package type operating range vic64 ? ac a144 144-lead thin quad flatpack commercial vic64 ? bc b144 145-pin plastic pin grid array vic64 ? gc g145 145-pin ceramic pin grid array vic64 ? nc n160 160-lead plastic quad flatpack vic64 ? gi g145 145-pin pin grid array industrial vic64 ? gm g145 145-pin ceramic pin grid array military temp. commercial vic64 ? gmb g145 145-pin ceramic pin grid array mil-std-883 vic64 ? umb u162 160-lead ceramic quad flatpack mil-std-883 vic64 ? um u162 160-lead ceramic quad flatpack military temp. commercial
vic64 document #: 38-09002 rev. ** page 8 of 13 package diagrams 144-pin thin quad flat pack a144
vic64 document #: 38-09002 rev. ** page 9 of 13 package diagrams (continued) 145-pin plastic grid array (cavity up) b144
vic64 document #: 38-09002 rev. ** page 10 of 13 package diagrams (continued) 145-pin grid array (cavity up) g145
vic64 document #: 38-09002 rev. ** page 11 of 13 package diagrams (continued) 160-lead plastic quad flatpack n160
vic64 document #: 38-09002 rev. ** page 12 of 13 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 160-lead ceramic quad flatpack u162
vic64 document #: 38-09002 rev. ** page 13 of 13 document title: vic64 interface controller with d64 functionality document number: 38-09002 rev. ecn no. issue date orig. of change description of change ** 106237 04/19/01 szv change from spec number: 38-00196 to 38-09002

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