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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd789322,789324,789326,789327 8-bit single-chip microcontroller document no. u14673ej1v0pm00 (1st edition) date published march 2000 ns cp(k) print ed in ja p a n preliminary product information the m pd789322, 789324, 789326, and 789327 are m pd789327 subseries (designed for remote controller with on- chip lcd) product in the 78k/0s series. in addition to an 8-bit cpu, they have on-chip hardware for a remote controller with on-chip lcd, including a lcd controller/driver, a serial interface, a key return signal detection circuit, and timers with carrier generator that can easily output waveforms for infrared remote control. the m pd78f9328, a product with on-chip flash memory which can operate on the same supply voltage as for masked rom products and various development tools are also under development. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m m m m pd789327, 789467 subseries users manual: to be prepared 78k/0s series users manual instructions: u11047e features ? rom and ram size data memory item part number program memory (rom) internal high-speed ram lcd display ram packege m pd789322 4 k bytes m pd789324 8 k bytes 256 bytes m pd789326 16 k bytes m pd789327 24 k bytes 512 bytes 24 bytes 52-pin plastic lqfp (1010 mm) ? variable minimum instruction execution time: high speed (0.4 m s: @5.0-mhz operation with main system clock), low speed (1.6 m s: @5.0-mhz operation with main system clock), and ultra low speed (122 m s: @32.768-khz operation with subsystem clock) ? i/o ports: 21 ? serial interface (3-wire serial i/o mode): 1 channel ? lcd controller/driver segment signals: 24 common signals: 4 ? timer: 4 channels ? supply voltage: v dd = 1.8 to 5.5 v applications remote-control devices, healthcare equipment, etc. 2000
preliminary product information u14673ej1v0pm00 2 m m m m pd789322,789324,789326,789327 ordering information part number package m pd789322gb-xxx-8et 52-pin plastic lqfp (10 10 mm) m pd789324gb-xxx-8et 52-pin plastic lqfp (10 10 mm) m pd789326gb-xxx-8et 52-pin plastic lqfp (10 10 mm) m pd789327gb-xxx-8et 52-pin plastic lqfp (10 10 mm) remark xxx indicates rom code suffix.
preliminary product information u14673ej1v0pm00 3 m m m m pd789322,789324,789326,789327 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names . 78k/0s series small, general-purpose small, general-purpose + a/d for inverter control for driving lcd for assp 44 pins 44 pins 42/44 pins 28 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins 44 pins products under mass production products under development y subseries supports smb. pd789014 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 44 pins 44 pins 20 pins 20 pins m pd789026 m pd789046 pd789026 with subsystem clock added pd789014 with timer reinforced and rom and ram expanded uart. low-voltage (1.8-v) operation pd789167 with improved a/d pd789104a with improved timer pd789146 with improved a/d pd789104a with eeprom added pd789124a with improved a/d rc oscillation model of pd789104a pd789104a with improved a/d pd789026 with a/d and multiplier added pd789407a with improved a/d pd789456 with improved i/o pd789446 with improved a/d pd789426 with improved display output pd789426 with improved a/d pd789306 with a/d added rc oscillation model of pd789306 basic subseries for driving lcd for pc keyboard. internal usb function for key pad. internal poc rc oscillation model of pd789860 for keyless entry. internal poc and key return circuit internal inverter control circuit and uart m pd789104a m pd789114a m pd789842 m pd789124a m pd789134a m pd789146 m pd789156 m pd789167 m pd789177 m pd789306 m pd789316 m pd789426 m pd789436 m pd789860 m pd789861 m pd789840 m pd789800 m pd789446 m pd789456 m pd789167y m pd789177y m m m m m m m m m m m m m m m m m m m pd789407a m pd789417a m 88 pins segment: 40 pins, common: 16 pins pd789830 m 144 pins segment/common output: 96 pins pd789835 m for driving dot lcd 52 pins 52 pins for remote controller. internal lcd controller/driver pd789327 m pd789467 m pd789327 with a/d added m
preliminary product information u14673ej1v0pm00 4 m m m m pd789322,789324,789326,789327 the major differences between subseries are shown below. timer rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o v dd min value remark m pd789046 16 k 1 ch m pd789026 4 k-16 k 1 ch 1 ch 34 pins small, general- purpose m pd789014 2 k-4 k 2 ch - - 1 ch -- 1 ch (uart:1 ch) 22 pins 1.8 v - m pd789177 - 8 ch m pd789167 16 k-24 k 3 ch 1 ch 8 ch - 31 pins - m pd789156 - 4 ch m pd789146 8 k-16 k 4 ch - internal eeprom m pd789134a 4 ch m pd789124a 4 ch - rc oscillation version m pd789114a - 4 ch small, general- purpose + a/d m pd789104a 2 k-8 k 1 ch 1 ch - 1 ch 4 ch - 1 ch (uart: 1 ch) 20 pins 1.8 v - for inverter control m pd789842 8 k-16 k 3 ch note 1 ch 1 ch 8 ch - 1 ch (uart: 1 ch) 30 pins 4.0 v - m pd789417a 7 ch m pd789407a 12 k-24 k 3 ch 7 ch - 43 pins m pd789456 - 6 ch m pd789446 6 ch - 30 pins m pd789436 - 6 ch m pd789426 12 k-16 k 6 ch 1 ch (uart: 1 ch) 40 pins - m pd789316 rc oscillation version for lcd driving m pd789306 8 k to 16k 2 ch 1 ch 1 ch 1 ch - - 2 ch (uart: 1 ch) 23 pins 1.8 v - m pd789835 24 k-60 k 6 ch - 2 ch 1 ch 27 pins 1.8 v for dot lcd driving m pd789830 24 k 1 ch 1 ch 1 ch 1 ch - - 1 ch (uart: 1 ch) 30 pins 2.7 v - m pd789467 1 ch - 18 pins m pd789327 4 k-24 k 2 ch - 1 ch 1 ch - 1 ch 21 pins 1.8 v internal lcd m pd789800 - 2 ch (usb: 1 ch) 31 pins 4.0 v m pd789840 8 k 1 ch 4 ch 1 ch 29 pins 2.8 v - m pd789861 rc oscillation version, internal eeprom assp m pd789860 4 k 2 ch - - 1 ch - - - 14 pins 1.8 v internal eeprom note 10-bit timer: 1 channel function subseries name
preliminary product information u14673ej1v0pm00 5 m m m m pd789322,789324,789326,789327 overview of functions item m pd789322 m pd789324 m pd789326 m pd789327 rom 4 kbytes 8 kbytes 16 kbytes 24 kbytes high-speed ram 256 bytes 512 bytes internal memory lcd display ram 24 bytes main system clock (oscillation frequency) ceramic/crystal resonator (1.0 to 5.0 mhz) subsystem clock (oscillation frequency) crystal resonator (32.768 khz) 0.4 m s/1.6 m s (@5.0-mhz operation with main system clock) minimum instruction execution time 122 m s (@32.768-khz operation with sub system clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulation (set, reset, test) etc. i/o ports total: 21 cmos i/o: 21 timers 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 1 serial interface 3-wire serial i/o mode: 1 channel lcd controller/driver segment signal outputs: 24 common signal outputs: 4 maskable internal: 6, external: 2 vectored interrupt sources non-maskable internal: 1 reset reset by reset signal input internal reset by watchdog timer reset via power-on-clear circuit supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40 to +85 c package 52-pin plastic lqfp (10 10 mm)
preliminary product information u14673ej1v0pm00 6 m m m m pd789322,789324,789326,789327 contents 1. pin configuration (top view)............................................................................................ .........8 2. block diagram ............................................................................................................ .....................9 3. pin functions ............................................................................................................ ......................10 3.1 port pins................................................................................................................. ......................10 3.2 non-port pins............................................................................................................. ..................11 3.3 pin i/o circuits and recommended connection of unused pins ..........................................12 4. cpu architecture ......................................................................................................... ................14 4.1 memory space .............................................................................................................. ...............14 4.2 data memory addressing .................................................................................................... .......15 4.3 processor registers....................................................................................................... .............16 5. peripheral hardware functions..........................................................................................2 0 5.1 ports ..................................................................................................................... ........................20 5.2 clock generator........................................................................................................... ................26 5.3 8-bit timer 30, 40........................................................................................................ .................31 5.4 watch timer ............................................................................................................... ..................41 5.5 watchdog timer ............................................................................................................ ..............44 5.6 serial interface 10....................................................................................................... .................46 5.7 lcd controller/driver..................................................................................................... .............50 6. interrupt function ....................................................................................................... ...............56 6.1 interrupt types ........................................................................................................... .................56 6.2 interrupt sources and configuration ....................................................................................... .56 6.3 interrupt function control registers ...................................................................................... ..59 7. standby function ......................................................................................................... ................65 7.1 standby function .......................................................................................................... ..............65 7.2 standby function control register......................................................................................... ..67 8. reset function........................................................................................................... ....................68 8.1 reset function............................................................................................................ .................68 8.2 power failure detection function .......................................................................................... ...70 9. mask option ............................................................................................................... .......................71 10. instruction set overview ............................................................................................... .......72 10.1 conventions.............................................................................................................. .................72 10.2 operations............................................................................................................... ...................74 11. electrical specifications ............................................................................................... .......79 12. package drawing.......................................................................................................... ...............90
preliminary product information u14673ej1v0pm00 7 m m m m pd789322,789324,789326,789327 appendix a. development tools .............................................................................................. .. 91 appendix b. related documents.............................................................................................. .. 93
preliminary product information u14673ej1v0pm00 8 m m m m pd789322,789324,789326,789327 1. pin configuration (top view) 52-pin plastic lqfp (10 10 mm) m m m m pd789322gb-xxx-8et m m m m pd789324gb-xxx-8et m m m m pd789326gb-xxx-8et m m m m pd789327gb-xxx-8et reset p60/to40 p43/kr03 p42/kr02 p41/kr01 p40/kr00 p03 p02 p01 p00 int/p61 x1 x2 v dd v ss xt2 xt1 ic0 p20/sck10 p21/so10 p22/si10 v lc0 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 1 2 3 4 5 6 7 8 9 10 11 39 38 37 36 35 34 33 32 31 30 29 p11 p10 p81/s21 p82/s20 p83/s19 p84/s18 p85/s17 s16 s15 s14 s13 s12 s11 s10 s9 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s23 p80/s22 12 13 28 27 41 40 25 26 caution connect the ic0 (internally connected) pin directly to v ss . com0 to com3: common output reset: reset ic0: internally connected s0 to s23: segment output int: interrupt from peripherals sck10: serial clock input/output kr00 to kr03: key return si10: serial data input p00 to p03: port 0 so10: serial data output p10, p11: port 1 v dd : power supply p20 to p22: port 2 v lc0 : power supply for lcd p40 to p43: port 4 v ss : ground p60, p61: port 6 x1, x2: crystal (main system clock) p80 to p85: port 8 xt1, xt2: crystal (sabsystem clock) to40: timer output
preliminary product information u14673ej1v0pm00 9 m m m m pd789322,789324,789326,789327 2. block diagram v dd v ss ic0 78k/0s cpu core rom 8-bit timer 30 p00 to p03 port 0 p10, p11 port 1 p20 to p22 port 2 p40 to p43 port 4 p60, p61 port 6 watchdog timer s0 to s23 com0 to com3 ram ram space for lcd data 8-bit timer 40 cascaded 16-bit timer serial interface 10 sck10/p20 si10/p22 so10/p21 v lc0 lcd controller/driver system control reset x1 x2 xt1 xt2 interrupt control kr00/p40 to kr03/p43 int/p61 p80 to p85 port 8 watch timer to40/p60 power-on clear remark the internal rom and ram capacities differ depending on the product.
preliminary product information u14673ej1v0pm00 10 m m m m pd789322,789324,789326,789327 3. pin functions 3.1 port pins pin name i/o function after reset alternate function p00 to p03 i/o port 0. this is a 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (pu0). input - p10, p11 i/o port 1. this is a 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (pu0). input - p20 sck10 p21 so10 p22 i/o port 2. this is a 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified in 1-bit units using pull-up resistor option register 2 (pub2). input si10 p40 to p43 i/o port 4. this is a 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified for the whole port using pull-up resistor option register 0 (pu0), or key return mode register 00 (krm00). input kr00 to kr03 p60 to40 p61 i/o port 6. this is a 2-bit i/o port. input/output can be specified in 1-bit units. input int p80 to p85 i/o port 8. this is a 6-bit i/o port. input/output can be specified in 1-bit units. low-level output s22 to s17
preliminary product information u14673ej1v0pm00 11 m m m m pd789322,789324,789326,789327 3.2 non-port pins pin name i/o function after reset alternate function int input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. input p61 kr00 to kr03 input key return signal detection input p40 to p43 to40 output 8-bit timer 40 output input p60 sck10 i/o serial clock input/output of serial interface 10 input p20 si10 input serial data input of serial interface 10 input p22 so10 output serial data output of serial interface 10 input p21 s0 to s16 - s17 to s22 p85 to p80 s23 output lcd controller/driver segment signal outputs low-level output - com0 to com3 output lcd controller/driver common signal outputs low-level output - v lc0 - lcd drive voltage -- x1 input -- x2 - connecting crystal resonator for main system clock oscillation -- xt1 input -- xt2 - connecting crystal resonator for sub system clock oscillation -- reset input system reset input input - v dd - positive power supply -- v ss - ground potential -- ic0 - internally connected. connect to v ss directly. --
preliminary product information u14673ej1v0pm00 12 m m m m pd789322,789324,789326,789327 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins is shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1. table 3-1. types of pin i/o circuits and recommended connection of unused pins pin name i/o circuit type i/o recommend connection of unused pins p00 to p03 p10, p11 5-a p20/sck10 8-a p21/so10 5-a p22/si10 p40/kr00 to p43/kr03 8-a p60/to40 5 input: independently connect to v dd or v ss via a resistor. output: leave open. p61/int 8 input: independently connect to v ss via a resistor. output: leave open. p80/s22 to p85/s17 17-g i/o input: independently connect to v dd or v ss via a resistor. output: leave open. s0 to s16, s23 17-d com0 to com3 18-b output v lc0 - leave open. xt1 input connect to v ss . xt2 - - leave open. reset 2 input - ic0 -- connect directly to v ss directly. figure 3-1. i/o circuit type (1/2) type 2 type 5 schmitt-triggered input with hysteresis characteristics. in p-ch in/out data output disable input enable v dd n-ch v ss
preliminary product information u14673ej1v0pm00 13 m m m m pd789322,789324,789326,789327 figure 3-1. i/o circuit type (2/2) type 5-a type 8 pull-up enable v dd p-ch p-ch in/out data output disable input enable v dd n-ch v ss data v dd p-ch output disable in/out n-ch v ss type 8-a type 17-d pull-up enable v dd p-ch data v dd p-ch output disable in/out n-ch v ss p-ch n-ch p-ch n-ch n-ch n-ch data out v lc0 v lc1 seg v lc2 p-ch p-ch v ss type 17-g type 18-b p-ch n-ch p-ch n-ch n-ch n-ch data v lc0 v lc1 seg v lc2 p-ch p-ch v ss p-ch in/out data output disable input enable v dd n-ch v ss p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch data p-ch n-ch v lc1 v lc0 v lc2 out com v ss remark v lc1 : v lc0 2/3, v lc2 : v lc0 /3
preliminary product information u14673ej1v0pm00 14 m m m m pd789322,789324,789326,789327 4. cpu architecture 4.1 memory space the m pd789322, 789324, 789326, and 789327 are provided with 64 kbytes of accessible memory space. figure 4-1 shows the memory map. figure 4-1. memory map n n n n h + 1 n n n n h special function registers 256 8 bits internal high-speed ram lcd display ram 24 8 bits f f f f h f f 0 0 h f e f f h 0 0 0 0 h program memory space data memory space n n n n h 0 0 0 0 h program area 0 0 8 0 h 0 0 7 f h program area 0 0 4 0 h 0 0 3 f h callt table area reserved 0 0 1 4 h 0 0 1 3 h vector table area internal rom f a 1 8 h f a 1 7 h f a 0 0 h f 9 f f h reserved note note mmmmh mmmmh - 1 note the internal rom capacity and internal high-speed ram capacity depend on the products (see the next table). relevant product name internal rom last address nnnnh internal high-speed ram start address mmmmh m pd789322 0fffh m pd789324 1fffh fe00h m pd789326 3fffh m pd789327 5fffh fd00h
preliminary product information u14673ej1v0pm00 15 m m m m pd789322,789324,789326,789327 4.2 data memory addressing the m pd789322, 789324, 789326, and 789327 are provided with a variety of addressing modes to improve the operability of the memory. in the area that incorporates data memory (fd00h to ffffh) in particular, specific addressing modes that correspond to the particular functions of an area, such as the special function registers (sfrs), are available. figure 4-2 shows the data memory addressing modes. figure 4-2. data memory addressing modes special function registers (sfrs) 256 8 bits internal high-speed ram lcd display ram 24 8 bits f f f f h 0 0 0 0 h direct addressing register indirect addressing based addressing f f 0 0 h f e f f h f f 2 0 h f f 1 f h f e 2 0 h f e 1 f h sfr addressing short direct addressing mmmmh mmmmh - 1 f a 1 8 h f a 1 7 h reserved f a 0 0 h f 9 f f h reserved internal rom note note n n n n h + 1 n n n n h note the internal rom capacity and internal high-speed ram capacity depend on the products (see the next table). relevant product name internal rom last address nnnnh internal high-speed ram start address mmmmh m pd789322 0fffh m pd789324 1fffh fe00h m pd789326 3fffh m pd789327 5fffh fd00h
preliminary product information u14673ej1v0pm00 16 m m m m pd789322,789324,789326,789327 4.3 processor registers 4.3.1 control registers (1) program counter (pc) the pc is a 16-bit register that holds the address information of the next program to be executed. figure 4-3. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the psw is an 8-bit register that indicates the status of the cpu according to the results of instruction execution. figure 4-4. program status word configuration ie z 0 ac 0 0 1 cy 70 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledgement of the cpu. (b) zero flag (z) this flag is set (1) if the result of an operation is zero; otherwise it is reset (0). (c) auxiliary carry flag (ac) ac is set (1) if the result of the operation has a carry from bit 3 or a borrow at bit 3; otherwise it is reset (0). (d) carry flag (cy) cy is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or add instruction. (3) stack pointer (sp) the sp is a 16-bit register that holds the start address of the stack area. only the internal ram area (fd00h to feffh) can be specified as the stack area. figure 4-5. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 caution reset input makes the sp contents undefined, so be sure to initialize the sp before instruction execution.
preliminary product information u14673ej1v0pm00 17 m m m m pd789322,789324,789326,789327 4.3.2 general-purpose registers the m pd789322, 789324, 789326, and 789327 have eight 8-bit general-purpose registers (x, a, c, b, e, d, l, and h). these registers can be used either singly as 8-bit registers or in pairs as 16-bit registers (ax, bc, de, and hl), and can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 4-6. general-purpose register configuration (a) absolute register names r7 r6 r5 r4 r3 r2 r1 r0 8-bit processing 70 rp3 rp2 rp1 rp0 16-bit processing 15 0 (b) functional register names h l d e b c a x 8-bit processing 70 hl de bc ax 16-bit processing 15 0
preliminary product information u14673ej1v0pm00 18 m m m m pd789322,789324,789326,789327 4.3.3 special function registers (sfrs) special function registers are used as peripheral hardware mode registers and control registers, and are mapped in the 256-byte space from ff00h to ffffh. note that the bit number of a bit name that is a reserved word in the ra78k0s and defined under the header file sfrbit.h in the cc78k0s appears enclosed in a circle in the register formats. refer to the register formats in 5. peripheral hardware functions . table 4-1. special function registers (1/2) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ??- ff01h port 1 p1 ??- ff02h port 2 p2 ??- ff03h port 4 p4 ??- ff05h port 6 p6 ??- ff08h port 8 p8 ??- 00h ff20h port mode register 0 pm0 ??- ff21h port mode register 1 pm1 ??- ff22h port mode register 2 pm2 ??- ff24h port mode register 4 pm4 ??- ff26h port mode register 6 pm6 ??- ff28h port mode register 8 pm8 ??- ffh ff32h pull-up resistor option register b2 pub2 ??- ff4ah watch timer mode control register wtm ??- ff58h port function register 8 pf8 r/w ??- 00h ff63h 8-bit compare register 30 cr30 w -?- undefined ff64h 8-bit timer counter 30 tm30 r -?- ff65h 8-bit timer mode control register 30 tmc30 r/w ??- 00h ff66h 8-bit compare register 40 cr40 -?- ff67h 8-bit h width compare register 40 crh40 w -?- undefined ff68h 8-bit timer counter 40 tm40 r -?- ff69h 8-bit timer mode control register 40 tmc40 r/w ??- ff6ah carrier generator output control register 40 tca40 w -?- ff72h serial operation mode register 10 csim10 ??- 00h ff74h transmission/reception shift register 10 sio10 ??- undefined ffb0h lcd display mode register 0 lcdm0 ??- ffb2h lcd clock control register 0 lcdc0 ??- 00h ffddh power-on-clear register 1 pocf1 r/w ??- 00h note note this value is 04h only after a power-on-clear reset.
preliminary product information u14673ej1v0pm00 19 m m m m pd789322,789324,789326,789327 table 4-1. special function registers (2/2) bit unit for manipulation address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffe0h interrupt request flag register 0 if0 ??- 00h ffe4h interrupt mask flag register 0 mk0 ??- ffh ffech external interrupt mode register 0 intm0 -?- fff0h subclock oscillation mode register sckm ??- fff2h subclock control register css ??- fff5h key return mode register 00 krm00 ??- fff7h pull-up resistor option register 0 pu0 ??- fff9h watchdog timer mode register wdtm ??- 00h fffah oscillation stabilization time selection register osts -?- 04h fffbh processor clock control register pcc r/w ??- 02h
preliminary product information u14673ej1v0pm00 20 m m m m pd789322,789324,789326,789327 5. peripheral hardware functions 5.1 ports 5.1.1 port functions various kinds of control operations are possible using the ports provided in the m pd789322, 789324, 789326, and 789327. these ports are illustrated in figure 5-1 and their functions are listed in table 5-1. a number of alternate functions are also provided, except for those ports functioning as digital i/o ports. refer to 3. pin functions for details of the alternate function pins. figure 5-1. ports p40 p00 p03 port 0 port 1 p10 port 4 p43 p11 port 2 p20 p22 port 6 p60 p61 p80 port 8 p85
preliminary product information u14673ej1v0pm00 21 m m m m pd789322,789324,789326,789327 table 5-1. port functions port name pin name function port 0 p00 to p03 this is an i/o port for which input and output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (pu0). port 1 p10, p11 this is an i/o port for which input and output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (pu0). port 2 p20 to p22 this is an i/o port for which input and output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register b2 (pub2). port 4 p40 to p43 this is an i/o port for which input and output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (pu0), or key return mode register 00 (krm00). port 6 p60, p61 this is an i/o port for which input and output can be specified in 1-bit units. port 8 p80 to p85 this is an i/o port for which input and output can be specified in 1-bit units.
preliminary product information u14673ej1v0pm00 22 m m m m pd789322,789324,789326,789327 5.1.2 port configuration the ports consist of the following hardware. table 5-2. port configuration item configuration control registers port mode registers (pmm: m = 0 to 2, 4, 6, 8) pull-up resistor option registers (pu0, pub2) port function register 8 (pf8) ports total: 21 (cmos i/o: 21) pull-up resistors total: 13 (software control: 13) figure 5-2. basic configuration of cmos port wr pum pu wr portm wr portm wr pmm output latch pmn pmmn v dd p-ch pmn internal bus selector caution figure 5-2 shows the basic configuration of a cmos i/o port. this configuration differs depending on the functions of alternate function pins. also, an on-chip pull-up resistor can be connected to port 4 by means of a setting in key return mode register 00 (krm00). remark pu : pull-up resistor option register ( = 0, b2) pmmn: bit n of port mode register m (m = 0 to 2, 4, 6, 8 n = 0 to 5) pmn: bit n of port m rd: port read signal wr: port write signal
preliminary product information u14673ej1v0pm00 23 m m m m pd789322,789324,789326,789327 5.1.3 port function control registers the ports are controlled by the following three types of registers. port mode registers (pm0 to pm2, pm4, pm6, pm8) pull-up resistor option registers (pu0, pub2) port function register 8 (pf8) (1) port mode registers (pm0 to pm2, pm4, pm6, pm8) input and output can be specified in 1-bit units. these registers can be set using a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when using the port pins as their alternate functions, set the port mode register and the output latch as shown in table 5-3. caution because p61 functions alternately as an external interrupt input, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0) before using the port in output mode. figure 5-3. port mode register format symbol76543210addressafter resetr/w pm0 1 1 1 1 pm03 pm02 pm01 pm00 ff20h ffh r/w pm1111111pm11pm10ff21hffhr/w pm2 1 1 1 1 1 pm22 pm21 pm20 ff22h ffh r/w pm4 1 1 1 1 pm43 pm42 pm41 pm40 ff24h ffh r/w pm6111111pm61pm60ff26hffhr/w pm8 1 1 pm85 pm84 pm83 pm82 pm81 pm80 ff28h ffh r/w pmmn pmn pin input/output mode selection (m = 0 to 2, 4, 6, 8 n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
preliminary product information u14673ej1v0pm00 24 m m m m pd789322,789324,789326,789327 table 5-3. port mode registers and output latch settings when using alternate functions alternate function pin name name i/o pm p input 1 p20 sck10 output 0 1 p21 so10 output 0 1 p22 si10 input 1 p40 to p43 kr00 to kr03 input 1 p60 to40 output 0 0 p61 int input 1 p80 to p85 s22 to s17 note output note when using p80 to p85 pins as s22 to s17, set port function register 8 (pf8) to 3fh. remark : dont care pm : port mode register p : port output latch (2) pull-up resistor option register 0 (pu0) this register sets whether to use on-chip pull-up resistors for ports 0, 1, and 4 on a port by port basis. an on- chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on- chip pull-up resistor has been specified using pu0. for those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of pu0. this also applies to alternate-function pins used as output pins. pu0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-4. format of pull-up resistor option register 0 symbol 7 6 5 <4> 3 2 <1> <0> address after reset r/w pu0 0 0 0 pu04 0 0 pu01 pu00 fff7h 00h r/w pu0m port m on-chip pull-up resistor selection (m = 0, 1, 4) 0 an on-chip pull-up resistor is not connected 1 an on-chip pull-up resistor is connected caution always set bits 2, 3, and 5 to 7 to 0.
preliminary product information u14673ej1v0pm00 25 m m m m pd789322,789324,789326,789327 (3) pull-up resistor option register b2 (pub2) this register sets whether to use on-chip pull-up resistors for p20 to p22 in bit units. an on-chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor has been specified using pub2. for those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of pub2. this also applies to alternate-function pins used as output pins. pub2 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-5. format of pull-up resistor option register b2 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w pub2 0 0 0 0 0 pub22 pub21 pub20 ff32h 00h r/w pub2n p2n on-chip pull-up resistor selection (n = 0 to 2) 0 an on-chip pull-up resistor is not connected 1 an on-chip pull-up resistor is connected caution always set bits 3 to 7 to 0. (4) port function register 8 (pf8) this register sets the port function of port 8 in 1-bit units. the pins of port 8 are selected as either lcd segment signal outputs or general-purpose port pins according to the setting of pf8. pf8 can be set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-6. format of port function register 8 symbol76543210addressafter resetr/w pf8 0 0 pf85 pf84 pf83 pf82 pf81 pf80 ff58h 00h r/w pf8n p8n port function (n = 0 to 5) 0 operates as a general-purpose port 1 operates as an lcd segment signal output
preliminary product information u14673ej1v0pm00 26 m m m m pd789322,789324,789326,789327 5.2 clock generator 5.2.1 clock generator function the clock generator generates the clock pulse to be supplied to the cpu and peripheral hardware. there are two types of system clock oscillators: main system clock oscillator (ceramic/crystal resonator) this circuit generates a frequency of 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or by means of a processor clock control register (pcc) setting. subsystem clock oscillator this circuit generates a frequency of 32.768 khz. oscillation can be stopped using the subclock oscillation mode register (sckm). 5.2.2 clock generator configuration the clock generator consists of the following hardware. table 5-4. clock generator configuration item configuration control registers processor clock control register (pcc) subclock oscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
preliminary product information u14673ej1v0pm00 27 m m m m pd789322,789324,789326,789327 figure 5-7. clock generator block diagram subsystem clock oscillatior f xt x1 x2 xt1 xt2 main system clock oscillator f x f x 2 2 f xt 2 1/2 prescaler watch timer lcd controller/driver clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit selector stop mcc pcc1 cls css0 internal bus subclock oscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc)
preliminary product information u14673ej1v0pm00 28 m m m m pd789322,789324,789326,789327 5.2.3 clock generator control registers the clock generator is controlled by the following three registers. processor clock control register (pcc) subclock oscillation mode register (sckm) subclock control register (css) (1) processor clock control register (pcc) this register is used to select the cpu clock and set the frequency division ratio. pcc is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 02h. figure 5-8. format of processor clock control register symbol <7> 6 5 4 3 2 1 0 address after reset r/w pcc mcc 0 0 0 0 0 pcc1 0 fffbh 02h r/w mcc main system clock oscillator operation control 0 operation enabled 1 operation stopped css0 pcc1 cpu clock (f cpu ) selection note minimum instruction execution time: 2f cpu 00f x (0.2 m s) 0.4 m s 01 f x /2 2 (0.8 m s) 1.6 m s 1 f xt /2 (61 m s) 122 m s note the cpu clock is selected by a combination of flag settings in the pcc and css registers. (refer to 5.2.3 (3) subclock control register (css) .) cautions 1. always set bits 0 and 2 to 6 to 0. 2. mcc can be set only when the subsystem clock is selected as the cpu clock. setting mcc to 1 while the main system clock is operating is invalid. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information u14673ej1v0pm00 29 m m m m pd789322,789324,789326,789327 (2) subclock oscillation mode register (sckm) this register is used to select a feedback resistor for the subsystem clock and control the oscillation of the clock. sckm is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-9. format of subclock oscillation mode register symbol 7 6 5 4 3 2 1 <0> address after reset r/w sckm 0 0 0 0 0 0 frc scc fff0h 00h r/w frc feedback resistor selection 0 an on-chip feedback resistor is used 1 an on-chip feedback resistor is not used scc control of subsystem clock oscillator operation 0 operation enabled 1 operation stopped caution always set bits 2 to 7 to 0.
preliminary product information u14673ej1v0pm00 30 m m m m pd789322,789324,789326,789327 (3) subclock control register (css) this register is used to specify whether the main system or subsystem clock oscillator is selected and to indicate the operating status of the cpu clock. css is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-10. format of subclock control register symbol76543210addressafter resetr/w css 0 0 cls css0 0 0 0 0 fff2h 00h r/w note cls cpu clock operating status 0 operating on the output of the (divided) main system clock 1 operating on the output of the subsystem clock css0 selection of main system clock or subsystem clock oscillator 0 main system clock oscillator (divi ded) output 1 subsystem clock oscillator output note bit 5 is read-only. caution always set bits 0 to 3, 6, and 7 to 0.
preliminary product information u14673ej1v0pm00 31 m m m m pd789322,789324,789326,789327 5.3 8-bit timer 30, 40 5.3.1 functions of 8-bit timer 30, 40 the 8-bit timer in the m pd789322, 789324, 789326, and 789327 have 2 channels (timer 30 and timer 40). the operation modes in the following table are possible by means of mode register settings. table 5-5. list of modes channel mode timer 30 timer 40 8-bit timer counter mode (discrete mode) ?? 16-bit timer counter mode (cascade connection mode) ? carrier generator mode ? pwm output mode C ? (1) 8-bit timer counter mode (discrete mode) the timer can be used for the following functions in this mode. 8-bit resolution interval timer 8-bit resolution square wave output (timer 40 only) (2) 16-bit timer counter mode (cascade connection mode) these timers can be used for 16-bit timer operations via a cascade connection. the timer can be used for the following functions in this mode. 16-bit resolution interval timer 16-bit resolution square wave output (3) carrier generator mode in this mode the carrier clock generated by timer 40 is output in the cycle set by timer 30. (4) pwm output mode in this mode, a pulse with an arbitrary duty ratio, which is set by timer 40, is output.
preliminary product information u14673ej1v0pm00 32 m m m m pd789322,789324,789326,789327 5.3.2 configuration of 8-bit timer 30, 40 8-bit timers 30 and 40 consist of the following hardware. table 5-6. configuration of 8-bit timer 30, 40 item configuration timer counter 8 bits 2 (tm30, tm40) registers compare registers: 8 bits 3 (cr30, cr40, crh40) timer outputs 1 (to40) control registers 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 40 (tmc40) carrier generator output control register 40 (tca40) port mode register 6 (pm6)
preliminary product information u14673ej1v0pm00 33 m m m m pd789322,789324,789326,789327 tce30 tcl300 tmd300 tcl301 8-bit timer mode control registedr 30 (tmc30) selector decoder selector selector 8-bit compare register 30 (cr30) 8-bit timer counter 30 (tm30) selector internal reset signal timer 40 match signal (in cascade connection mode) timer 30 match signal (in cascade connection mode) from figure 5-12 (d) count operation start signal (for cascade connection) inttm30 f x /2 6 f x /2 8 timer 40 interrupt request signal (from figure 5-12 (b) ) carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) (from figure 5-12 (c) ) clear cascade connection mode match from figure 5-12 (e) to figure 5-12 (f) to figure 5-12 (g) figure 5-11. block diagram of timer 30 internal bus ovf timer 30 match signal (in carrier generator mode) bit 7 of tm40 (from figure 5-12 (a) )
preliminary product information u14673ej1v0pm00 34 m m m m pd789322,789324,789326,789327 tce40 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 8-bit timer mode control register 40 (tmc40) decoder 8-bit timer counter 40 (tm40) f/f tm30 match signal (in cascade connection mode) count operation start signal to timer 30 (in cascade connection mode) tm40 timer counter match signal (in cascade connection mode) clear f x f x /2 2 8-bit compare register 40 (cr40) selector output control circuit note rmc40 nrzb40 nrz40 carrier generator output control register 40 (tca40) to figure 5-11 (d) count clock input signal to tm30 internal reset signal inttm40 bit 7 of tm40 (in cascade connection mode) to figure 5-11 (a) to figure 5-11 (f) to figure 5-11 (e) match to40/p60 to figure 5-11 (c) carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) reset carrier generator mode pwm mode cascade connection mode figure 5-12. block diagram of timer 40 note refer to figure 5-13 for details. 8-bit h width compare register 40 (crh40) internal bus selector ovf prescaler f x /2 f x /2 2 f x /2 3 f x /2 4 timer 40 interrupt request signal to figure 5-11 (b) timer counter match signal from timer 30 (in carrier generator mode) from figure 5-11 (g)
preliminary product information u14673ej1v0pm00 35 m m m m pd789322,789324,789326,789327 figure 5-13. block diagram of output control circuit (timer 40) f/f rmc40 nrz40 toe40 pm60 p60 output latch selector to40/p60 carrier generator mode carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) (1) 8-bit compare register 30 (cr30) a value specified in cr30 is compared with the count value in 8-bit timer counter 30 (tm30), and if they match, an interrupt request (inttm30) is generated. cr30 is set using an 8-bit memory manipulation instruction. reset input makes this register undefined. caution cr30 cannot be used in carrier generator mode or pwm output mode. (2) 8-bit compare register 40 (cr40) a value specified in cr40 is compared with the count value in 8-bit timer counter 40 (tm40), and if they match, an interrupt request (inttm40) is generated. when operating as a 16-bit timer in cascade connection with tm30, an interrupt request (inttm40) is only generated if both cr30 and tm30, and cr40 and tm40 match simultaneously (inttm30 is not issued). cr40 is set using an 8-bit memory manipulation instruction. reset input makes this register undefined. (3) 8-bit h width compare register (crh40) in carrier generator mode or pwm output mode, a timer output high-level width can be set by writing a value to crh40. crh40 is set using an 8-bit memory manipulation instruction. reset input makes this register undefined.
preliminary product information u14673ej1v0pm00 36 m m m m pd789322,789324,789326,789327 (4) 8-bit timer counter 30, 40 (tm30, tm40) this is an 8-bit register for counting the count pulses. tm30 and tm40 can be read with a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. the conditions under which tm30 and tm40 are cleared to 00h are listed below. (a) discrete mode (i) tm30 upon a reset when tce30 (bit 7 of 8-bit timer mode control register 30 (tmc30)) is cleared to 0 upon a match between tm30 and cr30 if the tm30 count value overflows (ii) tm40 upon a reset when tce40 (bit 7 of 8-bit timer mode control register 40 (tmc40)) is cleared to 0 upon a match between tm40 and cr40 if the tm40 count value overflows (b) cascade connection mode (tm30 and tm40 cleared to 00h simultaneously) upon a reset when the tce40 flag is cleared to 0 upon a simultaneous match between tm30 and cr30, and tm40 and cr40 if the tm30 and tm40 count values overflow simultaneously (c) carrier generator/pwm output mode (tm40 only) upon a reset when the tce40 flag is cleared to 0 upon a match between tm40 and cr40 upon a match between tm40 and crh40 if the tm40 count value overflows
preliminary product information u14673ej1v0pm00 37 m m m m pd789322,789324,789326,789327 5.3.3 8-bit timer 30, 40 control registers 8-bit timers 30 and 40 are controlled by the following 4 registers. 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 40 (tmc40) carrier generator output control register 40 (tca40) port mode register 6 (pm6)
preliminary product information u14673ej1v0pm00 38 m m m m pd789322,789324,789326,789327 (1) 8-bit timer mode control register 30 (tmc30) this register is used to control the timer 30 count clock and operation mode settings. tmc30 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-14. format of 8-bit timer mode control register 30 symbol <7> 6 5 4 3 2 1 0 address after reset r/w tmc30 tce30 0 0 tcl301 tcl300 0 tmd300 0 ff65h 00h r/w tce30 tm30 count control operation note 1 0 tm30 count value cleared and operation stopped 1 count operation starts tcl301 tcl300 timer 30 count clock selection 00 f x /2 6 (78.1 khz) 01 f x /2 8 (19.5 khz) 1 0 timer 40 match signal 1 1 carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) tmd300 tmd401 tmd400 timer 30, timer 40 operation mode selection note 2 0 0 0 discrete mode 1 0 1 cascade connection mode 0 1 1 carrier generator mode 0 1 0 pwm output mode other than above setting prohibited notes 1. the tce30 setting will be ignored in cascade mode because in this case the count operation is controlled by tce40 (bit 7 of tmc40). 2. the operation mode selection is made using a combination of tmc30 and tmc40 register settings. caution in cascade connection mode, the timer 40 output signal is forcibly selected for the count clock. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz
preliminary product information u14673ej1v0pm00 39 m m m m pd789322,789324,789326,789327 (2) 8-bit timer mode control register 40 (tmc40) this register is used to control the timer 40 count clock and operation mode settings. tmc40 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-15. format of 8-bit timer mode control register 40 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc40 tce40 0 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 ff69h 00h r/w tce40 tm40 count control operation note 1 0 tm40 count value cleared and operation stopped (in cascade connection mode, the count value of tm30 is cleared at the same time) 1 count operation starts (in cascade connection mode, the count operation of tm30 starts at the same time) tcl402 tcl401 tcl400 timer 40 count clock selection 000f x (5 mhz) 001 f x /2 2 (1.25 mhz) 010f x /2 (2.5 mhz) 011 f x /2 2 (1.25 mhz) 100 f x /2 3 (625 khz) 101 f x /2 4 (313 khz) other than above setting prohibited tmd300 tmd401 tmd400 timer 30, timer 40 operation mode selection note 2 0 0 0 discrete mode 1 0 1 cascade connection mode 0 1 1 carrier generator mode 0 1 0 pwm output mode other than above setting prohibited toe40 timer output control 0 output disabled (port mode) 1 output enabled notes 1. the tce30 setting will be ignored in cascade mode because in this case the count operation is controlled by tce40 (bit 7 of tmc40). 2. the operation mode selection is made using a combination of tmc30 and tmc40 register settings. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz
preliminary product information u14673ej1v0pm00 40 m m m m pd789322,789324,789326,789327 (3) carrier generator output control register 40 (tca40) this register is used to set the timer output data in the carrier generator mode. tca40 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-16. format of carrier generator output control register 40 symbol76543<2><1><0>addressafter resetr/w tca4000000rmc40nrzb40nrz40ff6ah00hw rmc40 remote controller output control 0 when nrz40 = 1, a carrier pulse is output to the to40/p60 pin 1 when nrz40 = 1, a high level is output to the to40/p60 pin nrzb40 this bit stores the data that nrz40 will output next. data is transferred to nrz40 upon the generation of a timer 30 match signal. nrz40 no return, zero data 0 a low level is output (the carrier clock is stopped) 1 a carrier pulse is output caution tca40 cannot be set with a 1-bit memory manipulation instruction. be sure to set it with an 8-bit memory manipulation instruction. (4) port mode register 6 (pm6) this register is used to set port 6 to input or output in 1-bit units. when the to40/p60 pin is used as a timer output, set the pm60 and p60 output latches to 0. pm6 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 5-17. format of port mode register 6 symbol76543210addressafter resetr/w pm6111111pm61pm60ff26hffhr/w pm6n input/output mode of pin p6n (n = 0, 1) 0 output mode (output buffer on) 1 input mode (output buffer off)
preliminary product information u14673ej1v0pm00 41 m m m m pd789322,789324,789326,789327 5.4 watch timer 5.4.1 watch timer functions the watch timer has the following functions. watch timer interval timer the watch and interval timers can be used at the same time. figure 5-18 shows a block diagram of the watch timer. figure 5-18. watch timer block diagram f x /2 7 f xt selector f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus
preliminary product information u14673ej1v0pm00 42 m m m m pd789322,789324,789326,789327 (1) watch timer an interrupt request (intwt) is generated at 0.5-second intervals using the 4.19-mhz main system clock or 32.768-khz subsystem clock. caution when the main system clock is operating at 5.0 mhz, it cannot be used to generate a 0.5-second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interrupt request (intwti) at preset intervals. table 5-7. interval time of interval timer interval time at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz operation 2 4 1/f w 409.6 m s 488 m s 488 m s 2 5 1/f w 819.2 m s 977 m s 977 m s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 5.4.2 watch timer configuration the watch timer consists of the following hardware. table 5-8. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
preliminary product information u14673ej1v0pm00 43 m m m m pd789322,789324,789326,789327 5.4.3 watch timer control register the following register controls the watch timer. watch timer mode control register (wtm) (1) watch timer mode control register (wtm) this register is used to enable/disable the count clock and operation of the watch timer and set the interval time of the prescaler and operation control of the 5-bit counter. wtm is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-19. format of watch timer mode control register symbol 7 6 5 4 3 2 <1> <0> address after reset r/w wtm wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 ff4ah 00h r/w wtm7 watch timer count clock (f w ) selection 0 f x /2 7 (39.1 khz) 1f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 000 2 4 /f w 001 2 5 /f w 010 2 6 /f w 011 2 7 /f w 100 2 8 /f w 101 2 9 /f w other than above setting prohibited wtm1 5-bit counter operation control 0 cleared after operation stopped 1start wtm0 watch timer operation enable 0 operation stopped (both prescaler and timer cleared) 1 operation enabled remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
preliminary product information u14673ej1v0pm00 44 m m m m pd789322,789324,789326,789327 5.5 watchdog timer 5.5.1 watchdog timer functions the watchdog timer has the following functions. (1) watchdog timer the watchdog timer is used to detect a program runaway. if a runaway is detected, either a non-maskable interrupt or the reset signal can be generated. (2) interval timer the interval timer is used to generate interrupts at preset intervals. 5.5.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 5-9. watchdog timer configuration item configuration control register watchdog timer mode register (wdtm) figure 5-20. watchdog timer block diagram internal bus internal bus 7-bit counter control circuit clear wdtif wdtmk watchdog timer mode register (wdtm) wdtm4 wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4 run
preliminary product information u14673ej1v0pm00 45 m m m m pd789322,789324,789326,789327 5.5.3 watchdog timer control register the watchdog timer is controlled by the following register. watchdog timer mode register (wdtm) (1) watchdog timer mode register (wdtm) this register is used to set the watchdog timer operation mode and whether to enable or disable counting. wdtm is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-21. format of watchdog timer mode register symbol <7> 6 5 4 3 2 1 0 address after reset r/w wdtm run 0 0 wdtm4 wdtm3 0 0 0 fff9h 00h r/w run watchdog timer operation selection note 1 0 counting stopped 1 counter cleared and counting starts wdtm4 wdtm3 watchdog timer operation mode selection note 2 0 0 operation stopped 01 interval timer mode (when an overflow occurs, a maskable interrupt is generated) note 3 1 0 watchdog timer mode 1 (when an overflow occurs, a non-maskable interrupt is generated) 1 1 watchdog timer mode 2 (when an overflow occurs, a reset operation is activated) notes 1. once the run bit has been set (1), it is impossible to clear it (0) by software. consequently, once counting begins, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set (1), it is impossible to clear them (0) by software. 3. the interval timer starts operating as soon as the run bit is set to 1. cautions 1. when the run bit is set to 1, and the watchdog timer is cleared, the actual overflow time will be up to 0.8% shorter than the time specified by the watchdog timer clock selection register. 2. to use watchdog timer mode 1 or 2, be sure to set wdtm4 to 1 after confirming that wdtif (bit 0 of interrupt request flag 0 (if0)) has been set to 0. if wdtif is 1, selecting watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant rewriting ends.
preliminary product information u14673ej1v0pm00 46 m m m m pd789322,789324,789326,789327 5.6 serial interface 10 5.6.1 functions of serial interface 10 serial interface 10 has the following two modes. operation stopped mode 3-wire serial i/o mode (1) operation stopped mode this mode is used to minimize power consumption when serial transfer is not performed. (2) 3-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock line (sck10) and two serial data lines (si10 and so10). as 3-wire serial i/o mode supports simultaneous transmission and reception, the time required for data processing can be reduced. in 3-wire serial i/o mode, it is possible to select whether 8-bit data transmission begins with the msb or lsb, allowing serial interface 10 to be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is effective for connecting peripheral i/o circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75xl, 78k, and 17k series devices. 5.6.2 configuration of serial interface 10 serial interface 10 consists of the following hardware. table 5-10. configuration of serial interface 10 item configuration register transmission/reception shift register 10 (sio10) control register serial operation mode register 10 (csim10) (1) transmission/reception shift register 10 (sio10) this is an 8-bit register used for parallel/serial data conversion and for serial transmission or reception in synchronization with the serial clock. sio10 is set using an 8-bit memory manipulation instruction. reset input makes this register undefined.
preliminary product information u14673ej1v0pm00 47 m m m m pd789322,789324,789326,789327 internal bus si10/p22 serial operation mode register 10 (csim10) csie10 tps101 tps100 dir10 csck10 transmission/reception shift register 10 (sio10) so10/p21 pm21 pm20 sck10/p20 serial clock counter interrupt request generator clock control circuit selector selector intcsi10 f/f tps101 tps100 f x /2 2 f x /2 3 figure 5-22. block diagram of serial interface 10
preliminary product information u14673ej1v0pm00 48 m m m m pd789322,789324,789326,789327 5.6.3 control register for serial interface 10 serial interface 10 is controlled by the following register. serial operation mode register 10 (csim10) figure 5-23. format of serial operation mode register 10 symbol <7> 6 5 4 3 2 1 0 address after reset r/w csim10 csie10 0 tps101 tps100 0 dir10 csck10 0 ff72h 00h r/w csie10 3-wire serial i/o mode operation control 0 operation stopped 1 operation enabled tps101 tps100 selection of count clock when internal clock selected 00 f x /2 2 (1.25 mhz) 01 f x /2 3 (625 khz) other than above setting prohibited dir10 first-bit specification 0msb 1lsb csck10 sio10 clock selection 0 external clock pulse input to the sck10 pin 1 internal clock selected with tps100, tps101 cautions 1. bits 0, 3 and 6 must be fixed to 0. 2. be sure to switch to operation mode after stopping the serial transmission/reception operation. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information u14673ej1v0pm00 49 m m m m pd789322,789324,789326,789327 table 5-11. operation mode settings for serial interface 10 (1) operation stopped mode first bit p22/si10 pin function p21/so10 pin function p20/sck10 pin function p22 p21 p20 csie10 0 csim10 dir10 csck10 pm22 note 1 p22 note 1 pm21 note 1 p21 note 1 pm20 note 1 p20 note 1 shift clock setting prohibited other than above - - (2) 3-wire serial i/o mode first bit p22/si10 pin function p21/so10 pin function p20/sck10 pin function msb lsb si10 note 2 so10 (cmos output) sck10 input sck10 output sck10 input sck10 output csie10 1 csim10 dir10 0 1 csck10 0 1 0 1 pm22 1 note 2 p22 note 2 pm21 0 p21 1 pm20 1 0 1 0 p20 1 1 shift clock external clock internal clock external clock internal clock setting prohibited other than above notes 1. can be used freely as a port 2. can be used as p22 (cmos i/o) only when transmitting remark : dont care
preliminary product information u14673ej1v0pm00 50 m m m m pd789322,789324,789326,789327 5.7 lcd controller/driver 5.7.1 lcd controller/driver functions the lcd controller/driver incorporated in the m pd789322, 789324, 789326, and 789327 has the following features. (1) segment and common signals based on the automatic reading of the display data memory can be automatically output (2) four types of frame frequencies are selectable (3) 24 segment signal outputs (s0 to s23), 4 common signal outputs (com0 to com3) (4) operation with a subsystem clock is possible the maximum number of displayable pixels is shown in table 5-12 below. table 5-12. maximum number of display pixels bias method time division common signals used maximum number of display pixels 1/3 4 com0 to com3 96 (24 segments 4 commons) note the lcd panel of the figure consists of 12 rows with 2 segments per row. 5.7.2 lcd controller/driver configuration the lcd controller/driver consists of the following hardware. table 5-13. configuration of lcd controller/driver item configuration display outputs segment signals: 24 common signals: 4 control registers lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) port function register 8 (pf8)
preliminary product information u14673ej1v0pm00 51 m m m m pd789322,789324,789326,789327 the correspondence with the lcd display ram is shown in figure 5-24 below. figure 5-24. correspondence with lcd display ram address bit segment 76543210 fa17h 0 0 0 0 ? s23 fa16h 0 0 0 0 ? s22 fa15h 0 0 0 0 ? s21 fa14h 0 0 0 0 ? s20 fa13h 0 0 0 0 ? s19 fa12h 0 0 0 0 ? s18 fa11h 0 0 0 0 ? s17 fa10h 0 0 0 0 ? s16 fa0fh 0000 ? s15 fa0eh 0000 ? s14 fa0dh 0000 ? s13 fa0ch 0000 ? s12 fa0bh 0000 ? s11 fa0ah 0000 ? s10 fa09h 0 0 0 0 ? s9 fa08h 0 0 0 0 ? s8 fa07h 0 0 0 0 ? s7 fa06h 0 0 0 0 ? s6 fa05h 0 0 0 0 ? s5 fa04h 0 0 0 0 ? s4 fa03h 0 0 0 0 ? s3 fa02h 0 0 0 0 ? s2 fa01h 0 0 0 0 ? s1 fa00h 0 0 0 0 ? s0 common - com3 - com2 - com1 - com0 remark bits 4 to 7 are fixed to 0.
preliminary product information u14673ej1v0pm00 52 m m m m pd789322,789324,789326,789327 internal bus lcdc03 lcdc02 lcdc01 lcdc00 2 2 selector prescaker lcd clock selection circuit selector f clk 2 6 f clk 2 7 f clk 2 8 f clk 2 9 lcd clock control register 0 (lcdc0) lcdon0 vaon0 lcd display mode register 0 (lcdm0) lcd drive voltage control circuit v lc0 v lc0 v lc0 segment driver common driver com0 com1 com2 com3 3210 3210 65 74 fa00h display data memory lcdon0 selector segment driver 3210 3210 65 74 fa16h lcdon0 s22/p80 timing controller f x /2 5 f x /2 6 f x /2 7 f xt s0 . . . . . . . . . . . . . . . f clk 1 3 2 3 v ss r lcd r lcd r lcd selector segment driver 3210 3210 654 fa17h lcdon0 s23 pf85 pf84 pf83 pf82 pf80 pf81 port function register 8 (pf8) pf80 selector segment driver 3210 3210 65 74 fa11h lcdon0 s17/p85 pf85 . . . . . . . . . . . . f lcd lips0 figure 5-25. lcd controller/driver block diagram
preliminary product information u14673ej1v0pm00 53 m m m m pd789322,789324,789326,789327 5.7.3 lcd controller/driver control registers the lcd controller/driver is controlled by the following three registers. lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) port function register 8 (pf8) (1) lcd display mode register 0 (lcdm0) this register is used to enable/disable operation, and set the operation mode and the supply of power for lcd drive. lcdm0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-26. format of lcd display mode register 0 symbol <7> <6> 5 <4> 3 2 1 0 address after reset r/w lcdm0 lcdon0 vaon0 0 lips0 0 0 0 0 ffb0h 00h r/w lcdon0 lcd display enable/disable 0 display off (all segment outputs are unselected for signal output) 1 display on vaon0 lcd controller/driver operation mode note 0 no internal booster (for 2.7- to 5.5-v display) 1 internal booster enabled (for 1.8- to 5.5-v display) lips0 supply of power for lcd drive note 0 power not supplied for lcd drive 1 power supplied for lcd drive note to reduce power consumption when the lcd display is not being used, set vaon0 and lips0 to 0. cautions 1. always set bits 0 to 3 and 5 to 0. 2. when manipulating vaon0, observe following procedure. a. when internal booster is stopped after changing to the display off condition from the display on condition 1) set the display off condition by setting lcdon0 = 0. 2) set all segment buffers and common buffers to output disabled by setting lips0 = 0. 3) stop the booster by setting vaon0 = 0. b. when the booster is stopped in the display on condition this is prohibited. be sure to stop the booster after changing to the display off condition. c. when the display is turned on from the booster-stoped condition 1) wait about 500 ms after starting the booster by setting vaon0 = 1. 2) set all segment buffers and common buffers to signal output unselected by setting lips0 = 1. 3) set the display on condition by setting lcdon0 = 1.
preliminary product information u14673ej1v0pm00 54 m m m m pd789322,789324,789326,789327 (2) lcd clock control register (lcdc0) this register is used to set the internal and lcd clocks. the frame frequency is determined by the number of lcd clock time divisions. lcdc0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-27. format of lcd clock control register 0 symbol 7 6 5 4 3 2 1 0 address after reset r/w lcdc0 0 0 0 0 l cdc03 lcdc02 lcdc01 lcdc00 ffb2h 00h r/w lcdc03 lcdc02 internal clock (f clk ) selection note 00f xt (32.768 khz) 01 f x /2 5 (156.3 khz) 10 f x /2 6 (78.1 khz) 11 f x /2 7 (39.1 khz) lcdc01 lcdc00 lcd clock (f lcd ) selection 00 f clk /2 6 01 f clk /2 7 10 f clk /2 8 11 f clk /2 9 note select f x so that a clock of at least 32 khz is set for the internal clock f clk . remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz caution always set bits 4 to 7 to 0. examples of the frame frequencies when the internal clock is f xt (32.768 khz) are shown in table 5-14 below. table 5-14. frame frequency (hz) lcd clock (f lcd ) time division f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) 4 163264128
preliminary product information u14673ej1v0pm00 55 m m m m pd789322,789324,789326,789327 (3) port function register 8 (pf8) this register is used to select whether s17/p85 to s22/p80 are used as lcd segment signal outputs or general-purpose ports. pf8 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 5-28. format of port function register 8 symbol76543210addressafter resetr/w pf8 0 0 pf85 pf84 pf83 pf82 pf81 pf80 ff58h 00h r/w pf8n port function of p8n (n = 0 to 5) 0 operates as a general-purpose port 1 operates as an lcd segment signal output
preliminary product information u14673ej1v0pm00 56 m m m m pd789322,789324,789326,789327 6. interrupt function 6.1 interrupt types two types of interrupts are supported. (1) non-maskable interrupts non-maskable interrupt requests are acknowledged unconditionally, i.e. even when interrupts are disabled. these interrupts take precedence over all other interrupts and are not subject to interrupt priority control. a non-maskable interrupt causes the generation of the standby release signal. an interrupt from the watchdog timer is the only non-maskable interrupt source supported in the m pd789322, 789324, 789326, and 789327. (2) maskable interrupts maskable interrupts are subject to mask control. if two or more maskable interrupts occur simultaneously, the default priority listed in table 6-1 applies. a maskable interrupt causes the generation of the standby release signal. maskable interrupts from 2 external and 6 internal sources are supported in the m pd789322, 789324, 789326, and 789327. 6.2 interrupt sources and configuration the m pd789322, 789324, 789326, and 789327 support a total of 9 maskable and non-maskable interrupt sources (see table 6-1 ).
preliminary product information u14673ej1v0pm00 57 m m m m pd789322,789324,789326,789327 table 6-1. interrupt sources interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable - intwdt watchdog timer overflow (with watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (with interval timer mode selected) internal 0004h (b) 1 intp0 pin input edge detection external 0006h (c) 2 intcsi10 end of serial interface 10 3-wire sio transfer reception 0008h 3 intwt watch timer interrupt 000ah 4 inttm30 generation of 8-bit timer 30 matching signal 000ch 5 inttm40 generation of 8-bit timer 40 matching signal internal 000eh (b) 6 intkr00 key return signal detection external 0010h (c) maskable 7 intwti watch timer interval timer interrupt internal 0012h (b) notes 1. default priority is the priority order when more than one maskable interrupt request is generated at the same time. 0 is the highest priority and 7 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 6-1 . remark only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be selected.
preliminary product information u14673ej1v0pm00 58 m m m m pd789322,789324,789326,789327 figure 6-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt internal bus mk if interrupt request ie vector table address generator standby release signal (c) external maskable interrupt internal bus intm0, krm00 mk if ie vector table address generator standby release signal edge detection circuit interrupt request intm0: external interrupt mode register 0 krm00: key return mode register 00 if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
preliminary product information u14673ej1v0pm00 59 m m m m pd789322,789324,789326,789327 6.3 interrupt function control registers interrupts are controlled by the following five registers. interrupt request flag register 0 (if0) interrupt mask flag register 0 (mk0) external interrupt mode register 0 (intm0) program status word (psw) key return mode register 00 (krm00) table 6-2 lists the interrupt requests and the corresponding interrupt request and interrupt mask flags. table 6-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intcsi0 intwt inttm30 inttm40 intkr00 intwti wdtif pif0 csiif0 wtif tmif30 tmif40 krif00 wtiif wdtmk pmk0 csimk0 wtmk tmmk30 tmmk40 krmk00 wtimk
preliminary product information u14673ej1v0pm00 60 m m m m pd789322,789324,789326,789327 (1) interrupt request flag register 0 (if0) an interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. it is cleared (0) when the interrupt request is acknowledged, when the reset signal is input, or when an instruction is executed. if0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 6-2. format of interrupt request flag register 0 symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w if0 wtiif krif00 tmif40 tmif30 wtif csiif0 pif0 wdtif ffe0h 00h r/w if interrupt request flag 0 no interrupt request signal generated 1 an interrupt request signal is generated and an interrupt request made cautions 1. the wdtif flag can be read/written only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. because p61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0) before using the port in output mode.
preliminary product information u14673ej1v0pm00 61 m m m m pd789322,789324,789326,789327 (2) interrupt mask flag register 0 (mk0) interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 6-3. format of interrupt mask flag register 0 symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w mk0 wtimk krmk00 tmmk40 tmmk30 wtmk csimk0 pmk0 wdtmk ffe4h ffh r/w mk interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled cautions 1. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the wdtmk flag results in an undefined value being detected. 2. because p61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0) before using the port in output mode.
preliminary product information u14673ej1v0pm00 62 m m m m pd789322,789324,789326,789327 (3) external interrupt mode register 0 (intm0) this register is used to specify the valid edge for intp0. intm0 is set using an 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 6-4. format of external interrupt mode register 0 symbol 7 6 5 4 3 2 1 0 address after reset r/w intm0 0 0 0 0 es01 es00 0 0 ffech 00h r/w es01 es00 intp0 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges cautions 1. always set bits 0, 1, and 4 to 7 to 0. 2. before setting intm0, set (1) the interrupt mask flag (pmk0) to disable interrupts. to enable interrupts, clear (0) the interrupt request flag (pif0), then clear (0) the interrupt mask flag (pmk0).
preliminary product information u14673ej1v0pm00 63 m m m m pd789322,789324,789326,789327 (4) program status word (psw) the program status word is used to hold the instruction execution results and the current status of the interrupt requests. the ie flag, used to enable and disable maskable interrupts, is mapped to the psw. the psw can be read and written in 8-bit units, as well as in 1-bit units by using bit manipulation instructions and dedicated instructions (ei and di). when a vector interrupt is acknowledged, the psw is automatically saved to the stack, and the ie flag is reset (0). reset input sets the psw to 02h. figure 6-5. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 used in the execution of ordinary instructions ie 0 1 disabled enabled interrupt acknowledgement enable/disable
preliminary product information u14673ej1v0pm00 64 m m m m pd789322,789324,789326,789327 (5) key return mode register 00 (krm00) this register is used to set the pin that is to detect the key return signal (rising edge of port 4). krm00 is set using a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 6-6. format of key return mode register 00 symbol 7 6 5 4 3 2 1 0 address after reset r/w krm00 0 0 0 0 0 0 0 krm000 fff5h 00h r/w krm000 key return signal detection control 0 key return signal not detected 1 key return signal detected (port 4 falling edge detection) cautions 1. always set bits 1 to 7 to 0. 2. before setting krm00, set (1) bit 6 (krmk00) of mk0 to disable interrupts. to enable interrupts, clear (0) krmk00 after clearing (0) bit 6 (krif00) of if0. 3. on-chip pull-up resistors are automatically connected in input mode to the pins specified for key return signal detection (p40 to p43). although these resistors are disconnected when the mode changes to output, key return signal detection continues unchanged. figure 6-7. block diagram of falling edge detection circuit falling edge detection circuit krmk00 krif00 setting signal standby release signal key return mode register 00 (krm00) note selector p40/kr00 p41/kr01 p42/kr02 p43/kr03 note for selecting the pin to be used as falling edge input.
preliminary product information u14673ej1v0pm00 65 m m m m pd789322,789324,789326,789327 7. standby function 7.1 standby function a standby function is incorporated to minimize the systems power consumption. there are two standby modes: halt and stop. the halt and stop modes are selected using the halt and stop instructions. (1) halt mode in this mode, the cpu operating clock is stopped. the average current consumption can be reduced by intermittent operation combining this mode with the normal operation mode. (2) stop mode in this mode, main system clock oscillation is stopped. all operations performed with the main system clock are suspended, thus minimizing power consumption. caution when shifting to stop mode, execute the stop instruction after first stopping the operation of the hardware.
preliminary product information u14673ej1v0pm00 66 m m m m pd789322,789324,789326,789327 table 7-1. operation statuses in halt mode halt mode operation status during main system clock operation halt mode operation status during sub system clock operation item subsystem clock operating subsystem clock stopped main system clock operating main system clock stopped main system clock can be oscillated oscillation st opped cpu operation stopped ports (output latches) status before halt mode setting retained 8-bit timer 30, 40 operable operation stopped watch timer operable operable note 1 operable operable note 2 watchdog timer operable operation stopped power-on-clear circuit operable key return circuit operable serial interface 10 operable operable note 3 lcd controller/driver operable note 4 operable notes 1, 4 operable note 4 operable notes 2, 4 external interrupts operable note 5 notes 1. operation is enabled when the main system clock is selected 2. operation is enabled when the subsystem clock is selected 3. operation is enabled only when an external clock is selected 4. the halt instruction can be set after display instruction execution 5. operation is enabled only for a maskable interrupt that is not masked table 7-2. operation statuses in stop mode stop mode operation status during main system clock operation item subsystem clock operating subsystem clock st opped main system clock oscillation st opped cpu operation stopped ports (output latches) status before stop mode setting retained 8-bit timer 30, 40 operation stopped watch timer operable note 1 operation stopped watchdog timer operation stopped power-on-clear circuit operable key return circuit operable serial interface 10 operable note 2 lcd controller/driver operable note 1 operation stopped external interrupts operable note 3 notes 1. operation is enabled when the subsystem clock is selected. 2. operation is enabled only when an external clock is selected. 3. operation is enabled only for a maskable interrupt that is not masked
preliminary product information u14673ej1v0pm00 67 m m m m pd789322,789324,789326,789327 7.2 standby function control register the oscillation stabilization time selection register (osts) is used to control the wait time from the time stop mode is released by an interrupt request until oscillation stabilizes. osts is set using an 8-bit memory manipulation instruction. reset input sets this register to 04h. note that the time required for oscillation to stabilize after reset input or the release of stop mode by poc will be taken as the time selected by mask option (2 15 /f x , or 2 17 /f x ) (refer to 9. mask option for mask option details) . figure 7-1. format of oscillation stabilization time selection register symbol 7 6 5 4 3 2 1 0 address after reset r/w osts 0 0 0 0 0 osts2 osts1 osts0 fffah 04h r/w osts2 osts1 osts0 oscillation stabilization time selection 000 2 12 /f x (819 m s) 010 2 15 /f x (6.55 ms) 100 2 17 /f x (26.2 ms) other than above setting prohibited caution the wait time required after releasing stop mode does not include the time (a in the following figure) required for the clock oscillation to restart after stop mode is released, regardless of whether stop mode is released by reset input or interrupt. stop mode release x1 pin voltage waveform v ss a remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
preliminary product information u14673ej1v0pm00 68 m m m m pd789322,789324,789326,789327 8. reset function 8.1 reset function the m pd789322, 789324, 789326, and 789327 can be reset using the following three signals. (1) external reset signal input via reset pin (2) internal reset by watchdog timer runaway time detection (3) internal reset using power-on-clear circuit (poc) the external and internal reset signals are functionally equivalent. when reset is input, program execution begins from the addresses written at addresses 0000h and 0001h. if a low-level signal is applied to the reset pin, or if the watchdog timer overflows, a reset occurs, causing each item of the hardware to enter the states listed in table 8-1. while a reset is being applied, or while the oscillation frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state. if a high-level signal is applied to the reset pin, the reset sequence is terminated, and program execution begins once the oscillation stabilization time has elapsed. a reset sequence caused by a watchdog timer overflow is terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time. reset by power-on clear is cleared if the supply voltage rises beyond a specific level, and the program execution is started after the oscillation stabilization time has elapsed. cautions 1. to use an external reset sequence, input a low-level signal to the reset pin for at least 10 m m m m s. 2. when a reset is used to release stop mode, the data of when stop mode was entered is retained during the reset sequence, except for the port pins, which are in the high-impedance state. 3. the oscillation stabilization time after reset input or the release of stop mode by poc can be selected from 2 15 /f x or 2 17 /f x by mask option (refer to 9. mask option). figure 8-1. reset function block diagram reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function v dd power-on-clear circuit
preliminary product information u14673ej1v0pm00 69 m m m m pd789322,789324,789326,789327 table 8-1. status of hardware after reset hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) set stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p2, p4, p6, p8) (output latches) 00h port mode registers (pm0 to pm2, pm4, pm6, pm8) ffh port function register 8 (pf8) 00h pull-up resistor option registers (pu0, pub2) 00h processor clock control register (pcc) 02h subclock oscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time selection register (osts) 04h timer counters (tm30, tm40) 00h compare registers (cr30, cr40, crh40) undefined mode control registers (tmc30, tmc40) 00h 8-bit timer 30, 40 carrier generator output control register (tca40) 00h watch timer mode control register (wtm) 00h watchdog timer mode register (wdtm) 00h serial operation mode register 10 (csim10) 00h serial interface 10 transmission/reception shift register 10 (sio10) undefined display mode register 0 (lcdm0) 00h lcd controller/driver clock control register 0 (lcdc0) 00h power-on-clear circuit power-on-clear register 1 (pocf1) 00h note 3 request flag register 0 (if0) 00h mask flag register 0 (mk0) ffh external interrupt mode register 0 (intm0) 00h interrupts key return mode register 00 (krm00) 00h notes 1. while a reset signal is being input, and during the oscillation stabilization period, only the contents of the pc will be undefined; the remainder of the hardware will be the same state as after reset. 2. in standby mode, ram enters the hold state after reset. 3. the value is 04h only after a power-on-clear reset.
preliminary product information u14673ej1v0pm00 70 m m m m pd789322,789324,789326,789327 8.2 power failure detection function when a reset is generated via the power-on-clear circuit, bit 2 (pocof1) of the power-on-clear register (pocf1) is set (1). this bit is then cleared (0) by an instruction written to pocf1. after a power-on-clear reset (i.e. after program execution has started from address 0000h), a power failure can be detected by detecting pocof1. figure 8-2. format of power-on-clear register 1 symbol 7 6 5 4 3 2 1 0 address after reset r/w pocf1 0 0 0 0 0 pocof1 0 0 ffddh 00h note r/w pocof1 power-on-clear generation status detection 0 power-on-clear not generated, or cleared by write operation 1 power-on-clear reset generated note the value is 04h only after a power-on-clear reset.
preliminary product information u14673ej1v0pm00 71 m m m m pd789322,789324,789326,789327 9. mask option the m pd789322, 789324, 789326, and 789327 have the following mask option. ? oscillation stabilization wait time the oscillation stabilization wait time after the release of stop mode by reset or poc can be selected. <1> 2 15 /f x <2> 2 17 /f x
preliminary product information u14673ej1v0pm00 72 m m m m pd789322,789324,789326,789327 10. instruction set overview the instruction set for the m pd789322, 789324, 789326, and 789327 are listed in this section. 10.1 conventions 10.1.1 operand formats and descriptions the description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform to the assembly specification). if more than one operand format is listed for an instruction, one is selected. uppercase letters, #, !, $, and brackets [ ] are used to specify keywords, which must be written exactly as they appear. the meanings of these special characters are as follows: #: immediate data specification $: relative address specification !: absolute address specification [ ]: indirect address specification immediate data should be described using appropriate values or labels. the specification of values and labels must be accompanied by #, !, $, or [ ]. operand registers, expressed as r or rp in the formats, can be described using both functional names (x, a, c, etc.) and absolute names (r0, r1, r2, and other names listed in table 5-1 below). table 10-1. operand formats and descriptions format description r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or label fe20h to ff1fh immediate data or label (even addresses only) addr16 addr5 0000h to ffffh immediate data or label (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for details concerning special function register symbols, refer to table 4-1 special function registers .
preliminary product information u14673ej1v0pm00 73 m m m m pd789322,789324,789326,789327 10.1.2 operation field definitions a: a register (8-bit accumulator) x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair (16-bit accumulator) bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag to indicate that a non-maskable interrupt is being processed (): contents of a memory location indicated by a parenthesized address or register name x h , x l : higher and lower 8 bits of a 16-bit register : logical product (and) : logical sum (or) " : exclusive or : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 10.1.3 flag operation field definitions (blank): no change 0: clear to 0 1: set to 1 : set or clear according to the result r: restore to the previous value
preliminary product information u14673ej1v0pm00 74 m m m m pd789322,789324,789326,789327 10.2 operations flag mnemonic operand byte clock operation zaccy r, #byte 3 6 r ? byte saddr , #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) mov [hl + byte], a 2 6 (hl + byte) ? a a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl + byte] 2 8 a ? (hl + byte) rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp movw rp, ax note 3 14rp ? ax xchw ax, rp note 3 1 8 ax ? rp notes 1. except when r = a. 2. except when r = a or x. 3. only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ) specified by the processor clock control register (pcc).
preliminary product information u14673ej1v0pm00 75 m m m m pd789322,789324,789326,789327 flag mnemonic operand byte clock operation zaccy a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) add a, [hl + byte] 2 6 a, cy ? a + (hl + byte) a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy addc a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy a, #byte 2 4 a, cy ? a - byte saddr, #byte 3 6 (saddr), cy ? (saddr) - byte a, r 2 4 a, cy ? a - r a, saddr 2 4 a, cy ? a - (saddr) a, !addr16 3 8 a, cy ? a - (addr16) a, [hl] 1 6 a, cy ? a - (hl) sub a, [hl + byte] 2 6 a, cy ? a - (hl + byte) a, #byte 2 4 a, cy ? a - byte - cy saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy a, r 2 4 a, cy ? a - r - cy a, saddr 2 4 a, cy ? a - (saddr) - cy a, !addr16 3 8 a, cy ? a - (addr16) - cy a, [hl] 1 6 a, cy ? a - (hl) - cy subc a, [hl + byte] 2 6 a, cy ? a - (hl + byte) - cy a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) and a, [hl + byte] 2 6 a ? a (hl + byte) remark the instruction clock cycle is based on the cpu clock (f cpu ) specified by the processor clock control register (pcc).
preliminary product information u14673ej1v0pm00 76 m m m m pd789322,789324,789326,789327 flag mnemonic operand byte clock operation zaccy a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) or a, [hl + byte] 2 6 a ? a (hl + byte) a, #byte 2 4 a ? a " byte saddr, #byte 3 6 (saddr) ? (saddr) " byte a, r 2 4 a ? a " r a, saddr 2 4 a ? a " (saddr) a, !addr16 3 8 a ? a " (addr16) a, [hl] 1 6 a ? a " (hl) xor a, [hl + byte] 2 6 a ? a " (hl + byte) a, #byte 2 4 a - byte saddr, #byte 3 6 (saddr) - byte a, r 2 4 a - r a, saddr 2 4 a - (saddr) a, !addr16 3 8 a - (addr16) a, [hl] 1 6 a - (hl) cmp a, [hl + byte] 2 6 a - (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax - word cmpw ax, #word 3 6 ax - word r24r ? r + 1 inc saddr 2 4 (saddr) ? (saddr) + 1 r24r ? r - 1 dec saddr 2 4 (saddr) ? (saddr) - 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 remark the instruction clock cycle is based on the cpu clock (f cpu ) specified by the processor clock control register (pcc).
preliminary product information u14673ej1v0pm00 77 m m m m pd789322,789324,789326,789327 flag mnemonic operand byte clock operation zaccy saddr.bit 3 6 (saddr.bit) ? 1 sfr.bit 3 6 sfr.bit ? 1 a.bit 2 4 a.bit ? 1 psw.bit 3 6 psw bit ? 1 set1 [hl].bit 2 10 (hl).bit ? 1 saddr.bit 3 6 (saddr.bit) ? 0 sfr.bit 3 6 sfr.bit ? 0 a.bit 2 4 a.bit ? 0 psw.bit 3 6 psw.bit ? 0 clr1 [hl].bit 2 10 (hl).bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr psw 1 2 (sp - 1) ? psw, sp ? sp - 1 push rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 psw 1 4 psw ? (sp), sp ? sp + 1 r r r pop rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 sp, ax 2 8 sp ? ax movw ax, sp 2 6 ax ? sp !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 br ax 1 6 pc h ? a, pc l ? x remark the instruction clock cycle is based on the cpu clock (f cpu ) specified by the processor clock control register (pcc).
preliminary product information u14673ej1v0pm00 78 m m m m pd789322,789324,789326,789327 flag mnemonic operand byte clock operation zaccy bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc ? pc + 4 + disp8 if psw.bit = 0 b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 dbnz saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark the instruction clock cycle is based on the cpu clock (f cpu ) specified by the processor clock control register (pcc).
preliminary product information u14673ej1v0pm00 79 m m m m pd789322,789324,789326,789327 11. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd - 0.3 to +6.5 v supply voltage v lc0 - 0.3 to +6.5 v input voltage v i - 0.3 to v dd + 0.3 note v v o1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61 - 0.3 to v dd + 0.3 note v output voltage v o2 com0 to com3, s0 to s16, p80/s22 to p85/s17, s23 - 0.3 to v lc0 + 0.3 note v pin p60/to40 - 30 ma per pin (except p60/to40) - 10 ma output current, high i oh total for all pins (except p60/to40) - 30 ma per pin 30 ma output current, low i ol total for all pins 80 ma operating ambient temperature t a - 40 to +85 c storage temperature t stg - 65 to +150 c note 6.5 v or lower caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
preliminary product information u14673ej1v0pm00 80 m m m m pd789322,789324,789326,789327 main system clock oscillator characteristics (t a = - - - - 40 to +85c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x1 x2 v dd c1 c2 oscillation stabilization time note 2 after v dd has reached the min. oscillation voltage range 4ms oscillation frequency (f x ) note 1 1.0 5.0 mhz crystal resonator x1 x2 ic c1 c2 oscillation stabilization time note 2 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x2 x1 x1 input high-/low- level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
preliminary product information u14673ej1v0pm00 81 m m m m pd789322,789324,789326,789327 subsystem clock oscillator characteristics (t a = - - - - 40 to +85c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 crystal resonator xt2 xt1 ic c4 c3 r oscillation stabilization time note 2 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low- level width (t xth , t xtl ) 14.3 15.6 m s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. the time required for oscillation to stabilize after v dd reaches the min. oscillation voltage range. use a resonator to stabilize oscillation during the oscillation wait time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
preliminary product information u14673ej1v0pm00 82 m m m m pd789322,789324,789326,789327 dc characteristics (t a = - - - - 40 to +85c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin 10 ma output current, low i ol total for all pins 80 ma per pin (except p60/to40) - 1ma p60/to40 v dd = 3.0 v, v oh = 1.0 v - 7 - 15 - 24 ma output current, high i oh total for all pins (except p60/to40) - 15 ma v dd = 2.7 to 5.5 v 0.7 v dd v dd v v ih1 p00 to p03, p10, p11, p21, p22, p60 0.9 v dd v dd v v dd = 2.7 to 5.5 v 0.8 v dd v dd v v ih2 reset, p20, p40 to p43, p61 0.9 v dd v dd v v ih3 x1, x2 v dd - 0.1 v dd v input voltage, high v ih4 xt1, xt2 v dd - 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3 v dd v v il1 p00 to p03, p10, p11, p21, p22, p60 0 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.2 v dd v v il2 reset, p20, p40 to p43, p61 0 0.1 v dd v v il3 x1, x2 0 0.1 v input voltage, low v il4 xt1, xt2 0 0.1 v v oh11 1.8 v dd 5.5 v, i oh = - 100 m a v dd - 0.5 v v oh12 p00 to p03, p10, p11, p20 to p22, p40 to p43, p61 1.8 v dd 5.5 v, i oh = - 500 m a v dd - 0.7 v v oh21 1.8 v dd 5.5 v, i oh = - 400 m a v dd - 0.5 v v oh22 p60/to40 1.8 v dd 5.5 v, i oh = - 2 ma v dd - 0.7 v v oh31 1.8 v dd 5.5 v, i oh = - 100 m a v lc0 - 0.5 v output voltage, high v oh32 p80/s22 to p85/s17 1.8 v dd 5.5 v, i oh = - 500 m a v lc0 - 0.7 v v ol11 1.8 v dd 5.5 v, i ol = 400 m a 0.5 v v ol12 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61 1.8 v dd 5.5 v, i ol = 2 ma 0.7 v v ol21 1.8 v lc0 5.5 v, i ol = 400 m a 0.5 v output voltage, low v ol22 p80/s22 to p85/s17 1.8 v lc0 5.5 v, i ol = 2 ma 0.7 v remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
preliminary product information u14673ej1v0pm00 83 m m m m pd789322,789324,789326,789327 dc characteristics (t a = ?40 to +85c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61, reset 3 m a input leakage current, high i lih2 v in = v dd x1, x2, xt1, xt2 20 m a i lil1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61, reset - 3 m a input leakage current, low i lil2 v in = 0 v x1, x2, xt1, xt2 - 20 m a output leakage current, high i loh v out = v dd 3 m a output leakage current, low i lol v out = 0 v - 3 m a software pull-up resistors r 1 v in = 0 v p00 to p03, p10, p11, p20 to p22, p40 to p43 50 100 200 k w v dd = 5.5 v note 2 2.0 4.0 ma i dd1 5.0-mhz crystal oscillation operating mode v dd = 3.3 v note 3 0.6 1.2 ma v dd = 5.5 v 1.1 2.2 ma i dd2 5.0-mhz crystal oscillation halt mode v dd = 3.3 v 0.4 0.8 ma v dd = 5.5 v 25 55 m a i dd3 32.768-khz crystal oscillation halt mode note 4 v dd = 3.3 v 5 25 m a v dd = 5.5 v 1 10 m a supply current note 1 ceramic/crystal oscillation i dd4 stop mode v dd = 3.3 v 1 5 m a notes 1. current flowing through ports (including current flowing through on-chip pull-up resistors) is not included. 2. high-speed operation (when the processor clock control register (pcc) is set to 00h). 3. low-speed operation (when pcc is set to 02h) 4. when the main system clock is stopped. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
preliminary product information u14673ej1v0pm00 84 m m m m pd789322,789324,789326,789327 ac characteristics (1) basic operation (t a = - - - - 40 to +85c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8.0 m s cycle time (min. instruction execution time) t cy 1.6 8.0 m s interrupt input high-/low-level width t inth , t intl int 10 m s key return pin low-level width t kril kr00 to kr03 10 m s reset low-level width t rsl 10 m s t cy vs. v dd (main system clock) supply voltage v dd (v) 123456 0.1 0.4 0.5 1.0 2.0 10 20 60 cycle time t cy [ s] guaranteed operation range m
preliminary product information u14673ej1v0pm00 85 m m m m pd789322,789324,789326,789327 (2) serial interface 10 (t a = ?40 to +85c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy1 3,200 ns v dd = 2.7 to 5.5 v t kcy1 /2 - 50 ns sck10 high-/low-level width t kh1 , t kl1 t kcy1 /2 - 150 ns v dd = 2.7 to 5.5 v 150 ns si10 setup time (to sck10 - ) t sik1 500 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 - ) t ksi1 800 ns v dd = 2.7 to 5.5 v 0 250 ns so10 output delay time from sck10 t kso1 r = 1 k w , c = 100 pf note 250 1,000 ns note r and c are the load resistance and load capacitance of the so10 output line. (b) 3-wire serial i/o mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck10 cycle time t kcy2 3,500 ns v dd = 2.7 to 5.5 v 400 ns sck10 high-/low-level width t kh2 , t kl2 1,600 ns v dd = 2.7 to 5.5 v 100 ns si10 setup time (to sck10 - ) t sik2 150 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 - ) t ksi2 600 ns v dd = 2.7 to 5.5 v 0 300 ns so10 output delay time from sck10 t kso2 r = 1 k w , c = 100 pf note 250 1,000 ns note r and c are the load resistance and load capacitance of the so10 output line.
preliminary product information u14673ej1v0pm00 86 m m m m pd789322,789324,789326,789327 ac timing measurement point (excluding x1, xt1 input) 0.8 v dd 0.2 v dd test points 0.8 v dd 0.2 v dd clock timing 1/f x t xl t xh x1 input v ih3 (min.) v il3 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) interrupt input timing int t intl t inth key return input timing kr00 to kr03 t kril reset input timing reset t rsl
preliminary product information u14673ej1v0pm00 87 m m m m pd789322,789324,789326,789327 serial transfer timing 3-wire serial i/o mode: t kcyn t kln t khn sck10 t sikn t ksin t kson input data output data si10 so10 remark n = 1, 2
preliminary product information u14673ej1v0pm00 88 m m m m pd789322,789324,789326,789327 lcd characteristics (t a = - - - - 40 to +85c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit vaon0 note 1 = 1 1.8 5.5 v lcd drive voltage v lc0 vaon0 note 1 = 0 2.7 5.5 v lcd division resistance r lcd 50 100 200 k w lcd output voltage differential note 2 (common) v odc i o = 5 m a 1/3 bias 0 0.2 v lcd output voltage differential note 2 (segment) v ods i o = 1 m a 1/3 bias 0 0.2 v notes 1. bit 6 of lcd display mode register 0 (lcdm0) 2. the voltage differential is the difference between the output voltage and the ideal value of the segment and common signal outputs. data memory stop mode low supply voltage data retention characteristics (t a = - - - - 40 to +85c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 3.6 v low voltage detection (poc) voltage v poc response time: 2 ms note 1 1.8 1.9 2.0 v power supply rise time t pth v dd : 0 v ? 1.8 v 0.01 100 ms release signal set time t srel stop cancelled by reset 10 m s cancelled by reset note 3 s oscillation stabilization wait time note 2 t wait cancelled by interrupt request note 4 s notes 1. the response time is the time until the output is inverted following detection of voltage by poc, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. the oscillation stabilization time is the amount of time the cpu operation is stopped in order to avoid unstable operation at the start of oscillation. program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed. 3. 2 15 /f x or 2 17 /f x can be selected using the mask option (refer to 9. mask option ). 4. 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts) (refer to 7.2 standby function control register ). remark f x : main system clock oscillation frequency
preliminary product information u14673ej1v0pm00 89 m m m m pd789322,789324,789326,789327 data retention timing v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
preliminary product information u14673ej1v0pm00 90 m m m m pd789322,789324,789326,789327 12. package drawing m 41 42 27 52 1 14 13 28 s n s j detail of lead end r k m i s l t p q g f h 52-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 0.13 1.1 i 12.0 0.2 j c 10.0 0.2 h 0.32 0.06 0.65 (t.p.) 1.0 0.2 k l 0.5 f 1.1 n p q 0.10 1.4 0.1 0.05 t 0.25 s 1.5 0.1 u 0.6 0.15 s52gb-65-8et-1 m 0.17 + 0.03 - 0.05 r3 + 4 - 3 a b cd u
preliminary product information u14673ej1v0pm00 91 m m m m pd789322,789324,789326,789327 appendix a. development tools the following development tools are available for system development using the m pd789322, 789324, 789326, and 789327. language processing software ra78k0s notes 1, 2, 3 assembler package common to 78k/0s series cc78k0s notes 1, 2 ,3 c compiler package common to 78k/0s series df789328 notes 1, 2, 3, 5 device file for m pd789327 subseries cc78k/0sCl notes 1, 2, 3 c compiler library source file common to 78k/0s series flash memory writing tools flashpro iii (part number: fl-pr3 note 4 , pg-fp3) dedicated flash memory programmer fa-52gb notes 4, 5 adapter for writing to flash memory designed for 52-pin plastic lqfp (gb-8et type) debugging tools ie-78k0s-ns in-circuit emulator in-circuit emulator to debug hardware or software when application systems using the 78k/0s series are developed. the ie-78k0s-ns supports an integrated debugger (id78k0s-ns). the ie-78k0s-ns is used in combination with an interface adapter for connection to an ac adapter, emulation probe, or host machine. ie-70000-mc-ps-b ac adapter ac adapter to supply power from a 100- to 240-v ac outlet. ie-70000-98-if-c interface adapter interface adapter required when using a pc-9800 series computer (except notebook type) as the host machine for the ie-78k0s-ns (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable required when a notebook pc is used as the host machine for the ie-78k0s-ns (pcmcia socket supported). ie-70000-pc-if-c interface adapter interface adapter required when using an ibm pc/at? or compatible as the host machine for the ie-78k0s-ns (isa bus supported). ie-70000-pci-if interface adapter interface adapter required when using a pc incorporating a pci bus as the host machine for the ie-78k0s-ns. ie-789328-ns-em1 note 5 emulation board emulation board to emulate the peripheral hardware specific to the device. the ie- 789328-ns-em1 is used in combination with the in-circuit emulator. np-52gb notes 4, 5 board to connect an in-circuit emulator to the target system. this board is dedicated for a 52-pin plastic lqfp (gb-8et type). sm78k0s notes 1, 2 system simulator common to 78k/0s series id78k0s-ns notes 1, 2 integrated debugger common to 78k/0s series df789328 notes 1, 2, 5 device file for m pd789327 subseries notes 1. based on the pc-9800 series (japanese windows?) 2. based on ibm pc/at or compatibles (japanese/english windows) 3. based on the hp9000 series 700? (hp-ux?), sparcstation? (sunos?, solaris?), and news? (news-os?) 4. manufactured by naito densei machida mfg. co, ltd. (+81-44-822-3813). 5. under development remark the ra78k0s, cc78k0s, and sm78k0s are used in combination with the df789328 device file.
preliminary product information u14673ej1v0pm00 92 m m m m pd789322,789324,789326,789327 real-time os mx78k0s notes 1, 2 os for 78k/0s series notes 1. based on the pc-9800 series (japanese windows) 2. based on ibm pc/at or compatibles (japanese/english windows)
preliminary product information u14673ej1v0pm00 93 m m m m pd789322,789324,789326,789327 appendix b. related documents documents related to devices document no. document name japanese english m pd789322, 789324, 789326, 789327 preliminary product information u14673j this document m pd78f9328 preliminary product information u14411j u14411e m pd789327, 789467 subseries users manual to be prepared to be prepared 78k/0s series users manual instructions u11047j u11047e documents related to development tools (users manual) document no. document name japanese english operation u11622j u11622e assembly language u11599j u11599e ra78k0s assembler package structured assembly language u11623j u11623e operation u11816j u11816e cc78k0s c compiler language u11817j u11817e sm78k0s system simulator windows based reference u11489j u11489e sm78k series system simulator external part user open interface specifications u10092j u10092e id78k0s-ns integrated debugger windows based reference u12901j u12901e ie-78k0s-ns in-circuit emulator u13549j u13549e ie-789328-ns-em1 emulation board to be prepared to be prepared documents related to embedded software (users manual) document no. document name japanese english 78k/0s series os mx78k0s fundamental u12938j u12938e other documents document no. document name english japanese semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to microcontroller-related products by third parties u11416j - caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
preliminary product information u14673ej1v0pm00 94 m m m m pd789322,789324,789326,789327 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
preliminary product information u14673ej1v0pm00 95 m m m m pd789322,789324,789326,789327 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m m m m pd789322,789324,789326,789327 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8

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