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ads5422 14-bit, 62msps sampling analog-to-digital converter features high dynamic range: high sfdr: 85db at 10mhz f in high snr: 72db at 10mhz f in premium track-and-hold: differential or single-ended inputs selectable full-scale input range flexible clocking: differential or single-ended accepts sine or square wave clocking down to 0.5vp-p variable threshold level applications communications receivers test instrumentation ccd imaging 14-bit pipelined a/d core reference and mode select reference ladder and driver timing circuitry error correction logic 3-state outputs t/h d0 d13 +v s ads5422 clk clk oe sel2 refb v ref reft vdrv in 2vp-p 2vp-p cm (+2.5v) pd sel1 ovr in dv ads5422 sbas250 march 2002 www.ti.com copyright ? 2002, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. description the ads5422 is a high-dynamic range 14-bit, 62msps, pipelined analog-to-digital (a/d) converter. it includes a high-bandwidth linear track-and-hold that gives good spuri- ous performance up to the nyquist rate. this high-bandwidth track-and-hold also has a low jitter of only 0.25ps rms, leading to excellent snr performance. the clock input can accept a low level differential sine wave or square wave signal down to 0.5vp-p, further improving the snr perfor- mance. it also accepts a single-ended clock signal and has flexible threshold levels. the ads5422 has a 4vp-p differential input range (2vp-p 2 inputs) for optimum spurious-free dynamic range. the differ- ential operation gives the lowest even-order harmonic compo- nents. a lower input voltage can also be selected using the internal references, further optimizing sfdr. alternatively, a single-ended input range can be used by tying the in input to the common-mode voltage if desired. the ads5422 also provides an over-range flag that indicates when the input signal has exceeded the converter s full-scale range. this flag can also be used to reduce the gain of the front-end signal conditioning circuitry. the ads5422 is avail- able in an lqfp-64 package. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ads5422 2 sbas250 www.ti.com desired full-scale range sel1 sel2 internal v ref 4vp-p gnd gnd 2v 3vp-p gnd +v s 1.5v 2vp-p v ref gnd 1v +v s ....................................................................................................... +6v analog input ........................................................... ( 0.3v) to (+v s +0.3v) logic input ............................................................. ( 0.3v) to (+v s +0.3v) case temperature ......................................................................... +100 c junction temperature .................................................................... +150 c storage temperature ..................................................................... +150 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. absolute maximum ratings (1) electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity ads5422 lqfp-64 pm 40 c to +85 c ads5422y ads5422y/ 250 tape and reel, 250 " """" ads5422y/1k5 tape and reel, 1500 notes: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information timing diagram note: for external reference operation, tie v ref to +v s . the full-scale range will be 2x the reference value. for example, selecting a 2v external reference will set the full-scale values of 1.5v to 3.5v for both in and in inputs. symbol description min typ max units t conv convert clock period 16.1 1 sns t l clock pulse low 7.05 t conv /2 ns t h clock pulse high 7.05 t conv /2 ns t a aperture delay 3 ns t 1 data hold time, c l = 0pf 3.9 ns t 2 new data delay time, c l = 15pf max 7.7 ns t dv data valid output, c l = 15pf 3 ns 10 clock cycles data invalid t a t dv t l t h t conv n 10 n 9n 8n 7n 6n 5n 4n 3n 2n 1n data out data valid output clock analog in n t 2 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 t 1 table i: reference and full-scale range select.
ads5422 3 sbas250 www.ti.com ads5422y parameter conditions min typ max units resolution 14 tested bits specified temperature range ambient air 40 +85 c analog input standard differential input range 2vp-p 2 1.5 3.5 v optional single-ended input range 4vp-p 0.5 4.5 v common-mode voltage 2.5 v optional input ranges selectable 2vp-p or 3vp-p v analog input bias current 1 a input impedance 1.25 || 9 m ? || pf conversion characteristics sample rate 1m 62m samples/s data latency 10 clk cyc dynamic characteristics differential linearity error (largest code error) f = 1mhz 0.65 lsb f = 10mhz 0.65 1.0 lsb no missing codes tested integral nonlinearity error, f = 10mhz 4.0 lsbs spurious-free dynamic range (1) f = 1mhz 85 dbfs (2) f = 10mhz 78 85 dbfs f = 30mhz 81 dbfs 2-tone intermodulation distortion (3) f = 14.5mhz and 15.5mhz ( 7db each tone) 90 dbc signal-to-noise ratio (snr) f = 1mhz 73 dbfs f = 10mhz 70 72 dbfs f = 30mhz 72 dbfs signal-to-(noise + distortion) (sinad) f = 1mhz 72 dbfs f = 10mhz 67 71 dbfs f = 30mhz 71 dbfs output noise input grounded 0.6 lsbs rms aperture delay time 3ns aperture jitter 0.25 ps rms overvoltage recovery time 2ns full-scale step acquisition time 5ns digital inputs logic family (other clock inputs) convert command (start conversion) rising edge of convert clock +0.5 +v s vp-p logic family (other clock inputs) high level input current (4) (v in = 5v) 100 a low level input current (v in = 0v) 10 a high level input voltage +2.0 v low level input voltage +1.0 v input capacitance 5pf digital outputs logic family logic coding low output voltage (i ol = 50 a to 1.6ma) vdrv = 3v +0.2 v high output voltage, (i oh = 50 a to 0.5ma) +2.5 v low output voltage, (i ol = 50 a to 1.6ma) vdrv = 5v +0.2 v high output voltage, (i oh = 50 a to 1.6ma) +2.5 v 3-state enable time oe = h to l 20 40 ns 3-state disable time oe = l to h 2 10 ns output capacitance 5pf accuracy zero error (referred to fs) at 25 c 0.05 1.0 %fs zero error drift (referred to fs) 15 ppm/ c gain error (5) at 25 c 0.5 1.0 %fs gain error drift (5) 20 ppm/ c power-supply rejection of gain ? v s = 5% 68 db internal reference tolerance reft, refb deviation from ideal 10 50 mv external reference voltage range 0.9 2 2.025 v reference input resistance 1.0 k ? power-supply requirements supply voltage: +v s operating +4.75 +5.0 +5.25 v supply current: +i s operating 240 ma output driver supply current (vdrv = 3v) 12 ma power dissipation: vdrv = 3v 1.2 1.4 w power down operating 40 mw thermal resistance, ja lqfp-64 47 c/w notes: (1) spurious-free dynamic range refers to the magnitude of the largest harmonic. (2) dbfs means db relative to full scal e. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. this number will be 6db higher if it is referred to the magnitude of th e 2-tone fundamental envelope. (4) a 50k ? pull-down resistor is inserted internally. (5) includes internal reference. electrical characteristics t a = specified temperature range, typical at 25 c, differential input range = 1.5v to 3.5v, sampling rate = 62mhz, internal reference, and vdrv = 3v, unless otherwise noted. +3v/+5v logic compatible cmos straight offset binary +3v/+5v logic compatible cmos
ads5422 4 sbas250 www.ti.com 33 vdrv output driver supply voltage 34 vdrv output driver supply voltage 35 vdrv output driver supply voltage 36 gnd ground 37 gnd ground 38 gnd ground 39 oe output enable: hi = high impedance 40 pd power down: hi = power down; lo = normal 41 btc hi = binary two s complement 42 gnd ground 43 gnd ground 44 sel2 reference select 2: see table i 45 sel1 reference select 1: see table i 46 v ref internal reference voltage 47 gnd ground 48 gnd ground 49 gnd ground 50 refb bottom reference voltage bypass 51 cm common-mode voltage (midscale) 52 reft top reference voltage bypass 53 gnd ground 54 gnd ground 55 gnd ground 56 gnd ground 57 i in complementary analog input 58 gnd ground 59 i in analog input 60 gnd ground 61 byp reference bypass 62 gnd ground 63 +v s analog supply voltage 64 +v s analog supply voltage pin configuration top view lqfp 1+v s analog supply voltage 2+v s analog supply voltage 3+v s digital supply voltage 4+v s digital supply voltage 5+v s digital supply voltage 6+v s digital supply voltage 7 gnd ground 8 gnd ground 9 i clk convert clock input 10 i clk complementary clock input 11 gnd ground 12 gnd ground 13 gnd ground 14 gnd ground 15 ovr over-range indicator 16 dv data valid pulse: hi = data valid 17 o b1 data bit 1 (d13) (msb) 18 o b2 data bit 2 (d12) 19 o b3 data bit 3 (d11) 20 o b4 data bit 4 (d10) 21 o b5 data bit 5 (d9) 22 o b6 data bit 6 (d8) 23 o b7 data bit 7 (d7) 24 o b8 data bit 8 (d6) 25 o b9 data bit 9 (d5) 26 o b10 data bit 10 (d4) 27 o b11 data bit 11 (d3) 28 o b12 data bit 12 (d2) 29 o b13 data bit 13 (d1) 30 o b14 data bit 14 (d0) (lsb) 31 nc no internal connection 32 nc no internal connection pin i/o designator description pin i/o designator description pin descriptions 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gnd gnd v ref sel1 sel2 gnd gnd btc pd oe gndrv gndrv gndrv vdrv vdrv vdrv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +v s +v s +v s +v s +v s +v s gnd gnd clk clk gnd gnd gndrv gndrv ovr dv +v s +v s gnd byp gnd in gnd in gnd gnd gnd gnd reft cm refb gnd b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 nc nc 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 ads5422y nc = no internal connection
ads5422 5 sbas250 www.ti.com typical characteristics t a = 25 c, v s = +5v, differential input range = 1.5v to 3.5v each input (4vp-p), sampling rate = 62msps, internal reference, and vdrv = 3v, unless otherwise noted. spectral performance amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f in = 15mhz, 1dbfs sfdr = 84.0dbfs snr = 71.2dbfs spectral performance amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f in = 15mhz, 3dbfs sfdr = 85.2dbfs snr = 72.7dbfs spectral performance amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f in = 15mhz, 6dbfs sfdr = 84.6dbfs snr = 73.5dbfs spectral performance amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f in = 1mhz, 1dbfs sfdr = 85.5dbfs snr = 72.3dbfs spectral performance (2vp-p) amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f in = 10mhz, 3dbfs sfdr = 85.2dbfs snr = 69.8dbfs spectral performance amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f in = 10mhz, 1dbfs sfdr = 85dbfs snr = 71.9dbfs
ads5422 6 sbas250 www.ti.com typical characteristics (cont.) t a = 25 c, v s = +5v, differential input range = 1.5v to 3.5v each input (4vp-p), sampling rate = 62msps, internal reference, and vdrv = 3v, unless otherwise noted. two-tone intermodulation distortion amplitude (db) frequency (mhz) 0 5 10 15 20 25 30 0 20 40 60 80 100 120 f 1 = ( 7dbc) = 14.5mhz f 2 = ( 7dbc) = 15.5mhz sfdr = 89.7db differential linearity error dle (lsb) code 0 2000 4000 6000 8000 10000 12000 14000 16000 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 f in = 1mhz integral linearity error ile (lsb) code 0 2000 4000 6000 8000 10000 12000 14000 16000 5 4 3 2 1 0 1 2 3 4 5 f in = 1mhz sfdr and snr vs input frequency sfdr, snr (dbfs) frequency (mhz) 1.0 10 100 100 90 80 70 60 50 40 sfdr snr swept power (sfdr) sfdr (dbfs, dbc) input amplitude (dbfs) 60 50 40 30 20 10 0 100 90 80 70 60 50 40 30 20 10 0 dbc dbfs f in = 10mhz spectral performance (3vp-p) amplitude (db) frequency (mhz) 0 5 10 15 20 25 31 30 0 20 40 60 80 100 120 f in = 10mhz, 3dbfs sfdr = 85.1dbfs snr = 71.9dbfs
ads5422 7 sbas250 www.ti.com application information theory of operation the ads5422 is a high-speed, high-performance, cmos a/d converter built with a fully differential pipeline architec- ture. each stage contains a low-resolution quantizer and digital error correction logic ensuring good differential linear- ity. the conversion process is initiated by a rising edge of the external convert clock. once the signal is captured by the input track-and-hold amplifier, the bits are sequentially en- coded starting with the msb. this process results in a data latency of 10 clock cycles after which the output data is available as a 14-bit parallel word either coded in a straight offset binary or binary two s complement format. the analog input of the ads5422 consists of a differential track-and-hold circuit, as shown in figure 1. the differential topology produces a high level of ac performance at high sampling rates. it also results in a very high usable input bandwidth especially important for intermediate frequency (if) or undersampling applications. both inputs (in, in ) require external biasing up to a common-mode voltage that is typically at the mid-supply level (+v s /2). this is because the on-resistance of the cmos switches is lowest at this voltage, minimizing the effects of the signal-dependent, nonlinearity of r on . the track-and-hold circuit can also con- vert a single-ended input signal into a fully differential signal for the quantizer. for ease of use, the ads5422 incorporates a selectable voltage reference, a versatile clock input and a logic output driver designed to interface to 3v or 5v logic. analog inputs types of applications the analog input of the ads5422 can be configured in various ways and driven with different circuits, depending on the application and the desired level of performance. offering an extremely high dynamic range at high input frequencies, the ads5422 is particularly well suited for communication systems that digitize wideband signals. features on the typical characteristics (cont.) t a = 25 c, v s = +5v, differential input range = 1.5v to 3.5v each input (4vp-p), sampling rate = 62msps, internal reference, and vdrv = 3v, unless otherwise noted. figure 1. simp lified circuit of input track-and-hold amplifier. t&h c in c in s 1 s 2 s 3 s 4 s 6 s 5 in in tracking phase: s 1 , s 2 , s 3 , s 4 closed; s 5 , s 6 open hold phase: s 1 , s 2 , s 3 , s 4 open; s 5 , s 6 closed ads5422 swept power (snr) snr (dbfs, dbc) input amplitude (dbfs) 60 50 40 30 20 10 0 90 80 70 60 50 40 30 20 10 0 dbfs dbc f in = 10mhz output noise histogram (dc common-mode input) count code n 3n 2n 1 n n + 1 n + 2 n + 3 600000 500000 400000 300000 200000 100000 0
ads5422 8 sbas250 www.ti.com ads5422, like the input range selector, or the option of an external reference, provide the needed flexibility to accom- modate a wide range of applications. in any case, the analog interface/driver requirements should be carefully examined before selecting the appropriate circuit configuration. the circuit definition should include considerations on the input frequency spectrum and amplitude, and single-ended versus differential driver configuration, as well as the available power supplies. differential versus single-ended the ads5422 input structure allows it to be driven either single-ended or differentially. differential operation of the ads5422 requires an input signal that consists of an in- phase and a 180 out-of-phase component simultaneously applied to the inputs (in, in ). differential signals offer a number of advantages, which in many applications will be instrumental in achieving the best harmonic performance of the ads5422: the signal amplitude is half of that required for the single- ended operation and is, therefore, less demanding to achieve while maintaining good linearity performance from the signal source. the reduced signal swing allows for more headroom of the interface circuitry and, therefore, a wider selection of the best suitable driver amplifier. even-order harmonics are minimized. improves the noise immunity based on the converter s common-mode input rejection. for the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a dc voltage to the required common-mode level. both inputs are identical in terms of their impedance and performance with the exception that by applying the signal to the complementary input ( in ) instead of the in input will invert the orientation of the input signal relative to the output code. for example, if the input driver operates in inverting mode, using in as the signal input will restore the phase of the signal to its original orientation. time-domain applications may benefit from a single-ended interface configuration and a reduced circuit complexity. driv- ing the ads5422 with a single-ended signal will result in a trade-off of the excellent distortion performance, while main- taining a good signal-to-noise ratio (snr). the trade-off of the differential input configuration over the single-ended is its increase in circuit complexity. in either case, the selection of the driver amplifier should be such that the amplifier s perfor- mance will not degrade the a/d converter's performance. input full-scale range versus performance employing dual supply amplifiers and ac-coupling will usu- ally yield the best results. dc-coupling and/or single-supply amplifiers impose additional design constraints due to their headroom requirements, especially when selecting the 4vp-p input range. the full-scale input range of the ads5422 is defined either by the settings of the reference select pins (sel1, sel2) or by an external reference voltage (see table i). by choosing between the different signal input ranges, trade-offs can be made between noise and distortion performance. for maximizing the snr important for time- domain applications the 4vp-p range may be selected. this range may also be used with low-level ( 6dbfs to 40dbfs) but high frequency inputs (multi-tone). the 3vp-p range may be considered for achieving a combination of both low-noise and distortion performance. here, the snr number is typi- cally 3db down compared to the 4vp-p range, while an improvement in the distortion performance of the driver amplifier may be realized due to the reduced output power level required. the third option, 2vp-p full-scale range, may be considered mainly for applications requiring dc-coupling and/or single-supply operation of the driver and the con- verter. input biasing (v cm ) the ads5422 operates from a single +5v supply, and requires each of the analog inputs to be externally biased to a common-mode voltage of typically +2.5v. this allows a symmetrical signal swing while maintaining sufficient head- room to either supply rail. communication systems are usu- ally ac-coupled in between signal processing stages, mak- ing it convenient to set individual common-mode voltages and allow optimizing the dc operating point for each stage. other applications, such as imaging, process mainly unipolar or dc-restored signals. in this case, the common-mode voltage may be shifted such that the full input range of the converter is utilized. it should be noted that the cm pin is not internally buffered, but ties directly to the reference ladder; therefore, it is recommended to keep loading of this pin to a minimum (< 10 a) to avoid an increase in the converter s nonlinearity. additionally, the dc voltage at the cm pin is not precisely +2.5v, but is subject to the tolerance of the top and bottom references, as well as the resistor ladder. furthermore, the common-mode voltage typically declines with an increase in sampling frequency. this, however, does not affect the performance. input impedance the input of the ads5422 is capacitive, and the driving source needs to provide the slew current to charge or discharge the input sampling capacitor while the track-and- hold amplifier is in track mode (see figure 1). this effectively results in a dynamic input impedance that is a function of the sampling frequency. figure 2 depicts the differential input impedance of the ads5422 as a function of the input fre- quency.
ads5422 9 sbas250 www.ti.com for applications that use op amps to drive the a/d converter, it is recommended that a series resistor be added between the amplifier output and the converter inputs. this will isolate the converter s capacitive input from the driving source and avoid gain peaking, or instability; furthermore, it will create a 1st-order, low-pass filter in conjunction with the specified input capacitance of the ads5422. its cutoff frequency can be adjusted further by adding an external shunt capacitor from each signal input to ground. the optimum values of this rc network, however, depend on a variety of factors includ- ing the ads5422 s sampling rate, the selected op amp, the interface configuration, and the particular application (time figure 2. differential input impedance versus input fre- quency. domain versus frequency domain). generally, increasing the size of the series resistor and/or capacitor will improve the signal-to-noise ratio, however, depending on the signal source, large resistor values may be detrimental to the harmonic distortion performance. in any case, the use of the rc network is optional but optimizing the values to adapt to the specific application is encouraged. analog input driver configurations the following section provides some principal circuit sugges- tions on how to interface the analog input signal to the ads5422. figure 3 shows an example of a typical analog interface circuit. here, it is assumed that the input signal is already available in differential form, i.e. coming from a preceding mixer stage. the differential driver performs an impedance transformation as well as amplifying the signal to match the selected full-scale input range of the ads5422, for example, 4vp-p. the common-mode voltage (v cm ) for the converter input is established by connecting the inputs to the midpoints of resistor divider. the input signal is ac-coupled through capacitors (c c ) to the inputs of the converter which are set to a v cm of approximately +2.5v dc . some differential driver circuits may allow setting an appro- priate common-mode voltage directly at the driver input. this will simplify the interface to the ads5422 and eliminate the external biasing resistors and the coupling capacitors. suit- able integrated circuits include the ths4131 and ths4141. these parts permit a dc-coupled interface solution; how- ever, their use is limited to about a 10mhz input frequency, for which they maintain acceptable distortion performance providing a 2vp-p (max) output swing on 5v supplies. alternatively, combining a differential driver circuit with a step-up transformer can lead to significant improvement of the distortion performance. 1000 100 10 1 0.1 0.01 0.1 1 10 100 1000 differential input impedance vs input frequency f in (mhz) z in (k ? ) figure 3. ac-coupling allows for easy dc biasing of the ads5422 inputs while the input signal is applied by the differential input driver. differential driver ads5422 0.1 f 0.1 f reft refb in in 1k ? 1k ? 1k ? c c c c 1k ? v cm +2.5v v in v in note: bypassing capacitors not shown.
ads5422 10 sbas250 www.ti.com transformer-coupled interface circuits if the application allows for ac-coupling but requires a signal conversion from a single-ended source to drive the ads5422 differentially, using a transformer offers a number of advan- tages. as a passive component, it does not add to the total noise, and by using a step-up transformer, further signal amplification can be realized. as a result, the signal swing of the amplifier driving the transformer can be reduced, leading to more headroom for the amplifier and improved distortion performance. a transformer interface solution is given in figure 4. the input signal is assumed to be an if and bandpass filtered prior to the if amplifier. dedicated if amplifiers are com- monly fixed-gain blocks and feature a very high bandwidth, a low-noise figure and high-intercept point, but at the ex- pense of high quiescent currents, which are often around 100ma. the if amplifier may be ac-coupled, or directly connected to the primary side of the transformer. a variety of miniature rf transformers are readily available from different manufacturers, (e.g., mini-circuits, coilcraft, or trak). for selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. furthermore, the appropriate model must support the targeted distortion level and should not exhibit any core saturation at full-scale voltage levels. since the transformer does not appreciably load the a/d converter s reference, its center tap can be directly tied to the cm pin of the converter, as shown in figure 4. the value of termination resistor r t should be chosen to satisfy the termination requirements of the source impedance (r s ). it can be calculated using the equation r t = n 2 r s to ensure proper impedance matching. transformer coupled, single-ended-to- differential configuration for applications in which the input frequency is limited to approxi- mately 10mhz (e.g., baseband), a high-speed operational ampli- fier may be used. the opa687 is configured for the noninverting mode; this amplifies the single-ended input signal and drives the primary of a rf transformer, as shown in fi gure 5. to maintain the very low distortion performance of the opa687, it may be advantageous to set the full-scale input range of the ads5422 to 3vp-p or 2vp-p (refer to reference section for details on selecting the converter s full-scale range). the circuit also shows the use of an additional rc low-pass filter placed in series with each converter input. this optional filter can be used to set a defined corner frequency and attenuate some of the wideband noise. the actual compo- nent values would need to be tuned for individual application requirements. as a guideline, resistor values are typically in the range of 10 ? to 100 ? , and capacitors in the range of 10pf to 200pf. in any case, the r in and c in values should have a low tolerance. this will ensure that the ads5422 sees closely matched source impedances. figure 4. driving the ads5422 with a low distortion rf amplifier and a transformer suited for if sampling applications. figure 5. converting a single-ended input signal into a differential signal using a rf transformer. ads5422 r in r s r in c in 0.1 f 2.2 f r t 1:n if amplifier v in (if) in in cm optional bandpass filter v cm +2.5v c in + +5v note: supply bypassing not shown. xfr r in r in c in c in 2.2 f 0.1 f r t 0.1 f 1:n r s r g opa687 r 1 r 2 v in + ads5422 in in cm +5v 5v +5v v cm +2.5v
ads5422 11 sbas250 www.ti.com ac-coupled, differential interface with gain the interface circuit example presented in figure 6 employs two opa687s, (decompensated voltage feedback op amps), optimized for gains of 12v/v or higher. implementing a new compensation technique allows to operate the opa687s with a reduced signal gain of 8.5v/v, while maintaining the high loop gain and the associated excellent distortion perfor- mance offered by the decompensated architecture. for a detailed discussion on this circuit and the compensation scheme, refer to the opa687 data sheet. input transformer, t1, converts the single-ended input signal to a differential signal required at the amplifier s inverting inputs, which are tuned to provide a 50 ? impedance match to an assumed 50 ? source. to achieve the 50 ? input match at the primary of the 1:2 transformer, the secondary must see a 200 ? load imped- ance. both amplifiers are configured for the inverting mode resulting in close gain and phase matching of the differential signal. this technique, along with a highly symmetrical layout, is instrumental in achieving a substantial reduction of the second harmonic, while retaining excellent 3rd-order perfor- mance. a common-mode voltage, v cm , is applied to the noninverting inputs of the opa687. additional series 20 ? resistors isolate the output of the op amps from the capacitive load presented by the 80pf capacitors and the input capaci- tance of the ads5422. this 20 ? /80pf combination sets a pole at approximately 88mhz and rolls off some of the wideband noise resulting in a reduction of the noise floor. the measured 2-tone, 3rd-order distortion for the amplifier portion of the circuit of figure 6 is shown in figure 7. the upper curve is for a total 2-tone envelope of 4vp-p, requiring two tones, each 2vp-p across the opa687 outputs. the lower curve is for a 2vp-p envelope resulting in a 1vp-p amplitude per tone. the basic measurement dynamic range for the two close-in spurious tones is approximately 85dbc. the 4vp-p test does not show measurable 3rd-order spuri- ous until 25mhz, while the 2vp-p is unmeasurable up to 40mhz center frequency. 2-tone, 2nd-order intermodulation distortion was unmeasurable for this circuit. if the application requires a dc-coupled interface and conversion from a single-ended source to differential, a circuit using the dual op amp opa2686 may be considered (refer to figure 7 of the opa2686 data sheet). the use of this circuit will be limited to approximately 10mhz input frequency. figure 6. high dynamic range interface circuit with the opa687 set for a gain of +8.5v/v. 1.7pf opa687 opa687 850 ? 50 ? source 20 ? 850 ? 100 ? 20 ? 100 ? 39pf 1.7pf 39pf 1:2 t 1 5v +5v 5v +5v ads5422 +5v 80pf 80pf v cm v cm in in < 6db noise figure figure 7. measured 2-tone, 3rd-order distortion for dif- ferential a/d converter driver. center frequency (mhz) 3rd-order spurious (dbc) 0 60 65 70 75 80 85 5 101520253035404550 4vp-p 2vp-p
ads5422 12 sbas250 www.ti.com reference reference operation integrated into the ads5422 is a bandgap reference circuit including logic that provides a +1v, +1.5v, or +2v reference output by selecting the corresponding pin-strap configura- tion. table i gives a complete overview of the possible reference options and pin configurations. figure 8 shows the basic model of the internal reference circuit. the functional blocks are a 1v bandgap voltage reference, a selectable gain amplifier, the drivers for the top- and bottom reference (reft, refb), and the resistive refer- ence ladder. the ladder resistance measures approximately 1k ? between the reft and refb pin. the ladder is split into two equal segments establishing a common-mode voltage at the ladder midpoint, labeled cm . the ads5422 requires solid bypassing for all reference pins to keep the effects of clock feedthrough to a minimum and to achieve the specified level of performance. figure 8 shows the recommended decoupling scheme. all 0.1 f capacitors should be located as close to the pins as possible. in addition, pins reft, cm, and refb should be decoupled with tantalum surface-mount capacitors (2.2 f or 4.7 f). when operating the ads5422 with the internal reference, the effective full-scale input span for each of the inputs, in and in , is determined by the voltage at the v ref pin, given to: (1) input span (differential, each input) = v ref = (reft refb) in vp-p (2) input span (single-ended) = 2 v ref = 2 (reft refb) in vp-p the top and bottom reference outputs may be used to provide up to 1ma of current (sink or source) to external circuits. degradation of the differential linearity (dnl) and, consequently, the dynamic performance, of the ads5422 may occur if this limit is exceeded. desired full-scale range (fsr) connect connect voltage at v ref voltage at reft voltage at refb (differential) sel1 (pin 45) to: sel2 (pin 44) to: (pin 46) (pin 52) (pin 50) 4vp-p (+16dbm) gnd gnd +2.0v +3.5v +1.5v 3vp-p (+13dbm) gnd +vs +1.5v +3.25v +1.75v 2vp-p (+10dbm) v ref gnd +1.0v +3.0v +2.0v external reference > +3.5v +2.75v to +4.5v +0.5v to +2.25v table i. reference pin configurations and corresponding voltages on the reference pins. figure 8. internal reference circuit of the ads5422 and recommended bypass scheme. range select and gain amplifier to p reference driver bottom reference driver +1v dc bandgap reference ads5422 + + + reft cm refb 2.2 f 2.2 f 2.2 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f refby sel1 sel2 v ref 500 ? 500 ? 45 61 46 44 52 51 50
ads5422 13 sbas250 www.ti.com using external references for even more design flexibility, the ads5422 can be oper- ated with external reference. the utilization of an external reference voltage may be considered for applications requiring higher accuracy, improved temperature stability, or a continu- ous adjustment of the converter s full-scale range. especially in multichannel applications, the use of a common external reference offers the benefit of improving the gain matching between converters. selection between internal or external reference operation is controlled through the v ref pin. the internal reference will become disabled if the voltage applied to the v ref pin exceeds +3.5v dc . once selected, the ads5422 requires two reference voltages a top reference voltage applied to the reft pin and a bottom reference voltage applied to the refb pin (see table i). as illustrated in figure 9, a micropower reference (ref1004) and a dual, single- supply amplifier (opa2234) may be used to generate a precision external reference. note that the function of the range select pins, sel1 and sel2, are disabled while the converter is operating in external reference mode. digital inputs and outputs clock input unlike most a/d converters, the ads5422 contains an inter- nal clock conditioning circuitry. this enables the converter to adapt to a variety of application requirements and different clock sources. with no input signal connected to either clock pin, the threshold level is set to approximately +1.6v by the on-chip resistive voltage divider, as shown in figure 10. the parallel combination of r 1 || r 2 and r 3 || r 4 sets the input impedance of the clock inputs (clk, clk ) to approximately 2.7k ? single-ended, or 5.5k ? differentially. the associated ground referenced input capacitance is approximately 5pf for each input. if a logic voltage other than the nominal +1.6v is desired, the clock inputs can be externally driven to establish an alternate threshold voltage. the ads5422 can be interfaced to standard ttl or cmos logic and accepts 3v or 5v compliant logic levels. in this case, the clock signal should be applied to the clk input, while the complementary clock input ( clk ) should be by- passed to ground by a low-inductance ceramic chip capaci- tor, as shown in figure 11. depending on the quality of the signal, inserting a series, damping resistor may be beneficial to reduce ringing. when digitizing at high sampling rates the clock should have a 50% duty cycle (t h = t l ) to maintain a good distortion performance. figure 9. example for an external reference circuit using a dual, single-supply op amp. figure 10. the differential clock inputs are internally biased. figure 11. single-ended ttl/cmos clock source. applying a single-ended clock signal will provide satisfactory results in many applications. however, unbalanced high-speed logic signals can introduce a high amount of disturbances, such as ringing or ground bouncing. in addition, a high amplitude may cause the clock signal to have unsymmetrical rise and fall times, potentially effecting the converter distortion performance. proper termination practice and a clean pc board layout will help to keep those effects to a minimum. r 3 r 4 r 1 r 2 + + 2.2 f 0.1 f 0.1 f + 2.2 f0.1 f 10 f reft refb ads5422 1/2 opa2234 1/2 opa2234 4.7k ? +5v +5v ref1004 +2.5v +5v r 1 8.5k ? r 2 4k ? r 3 8.5k ? r 4 4k ? clk clk ads5422 clk clk ads5422 47nf ttl/cmos clock source (3v/5v)
ads5422 14 sbas250 www.ti.com to take full advantage of the excellent distortion performance of the ads5422, it is recommended to drive the clock inputs differentially. a low level, differential clock improves the digital feedthrough immunity and minimizes the effect of modulation between the signal and the clock. figure 12 illustrates a simple method of converting a square wave clock from single-ended to differential using an rf trans- former. small surface-mount transformers are readily avail- able from several manufacturers (e.g., model adt1-1 by mini-circuits). a capacitor in series with the primary side may be inserted to block any dc voltage present in the signal. since the clock inputs are self-biased, the secondary side connects directly to the two clock inputs of the converter. figure 13. to calculate the correct value for this resistor, consider the impedance ratio of the selected transformer and the differential clock input impedance of the ads5422, which is approximately 5.5k ? . figure 12. connecting a ground referenced square wave clock source to the ads5422 using a rf transformer. figure 13. applying a sinusoidal clock to the ads5422. table ii. coding table for single-ended input configuration with in tied to the common-mode voltage (v cm ). single-ended binary two s input straight offset complement (in = v cm ) binary (sob) (btc) +fs 1lsb 11 1111 1111 1111 01 1111 1111 1111 (in = v cm + fsr/2) +1/2 fs 11 0000 0000 0000 01 0000 0000 0000 bipolar zero (in = v cm ) 10 0000 0000 0000 00 0000 0000 0000 1/2 fs 01 0000 0000 0000 11 0000 0000 0000 fs (in = v cm fsr/2) 00 0000 0000 0000 10 0000 0000 0000 the clock inputs of the ads5422 can be connected in a number of ways. however, the best performance is obtained when the clock input pins are driven differentially. operating in this mode, the clock inputs accommodate signal swings ranging from 2.5vp-p down to 0.5vp-p differentially. this allows direct interfacing of clock sources such as voltage- controlled crystal oscillators (vcxo) to the ads5422. the advantage here is the elimination of external logic, usually necessary to convert the clock signal into a suitable logic (ttl or cmos) signal which otherwise would create an additional source of jitter. in any case, a very low-jitter clock is fundamental to preserving the excellent ac performance of the ads5422. the converter itself is specified for a very low 0.25ps (rms) jitter, characterizing the outstanding capa- bility of the internal clock and track-and-hold circuitry. gen- erally, as the input frequency increases, the clock jitter becomes more dominant for maintaining a good signal-to- noise ratio. this is particularly critical in if sampling applica- tions where the sampling frequency is lower than input frequency (undersampling). the following equation can be used to calculate the achievable snr for a given input frequency and clock jitter (t ja in ps rms): snr 20 log 1 2 f t 10 in ja = ( ) (3) depending on the nature of the clock source s output imped- ance, an impedance matching might become necessary. for this, a termination resistor, r t , may be installed, as shown in it is not recommended to employ any type of differential ttl logic which suffers from mismatch in delay time and slew rate, leading to performance degradation. alternatively, a low jitter ecl or pecl clock may be ac-coupled directly to the clock inputs using small (0.1 f) capacitors. minimum sampling rate the pipeline architecture of the ads5422 uses a switched capacitor technique in its internal track-and-hold stages. with each clock cycle, charges representing the captured signal level are moved within the a/d pipeline core. the high sampling speed necessitates the use of very small capacitor values. in order to hold the droop errors low, the capacitors require a minimum refresh rate . to maintain accuracy of the acquired sample charge the sampling clock on the ads5422 should not drop below the specified minimum of 1mhz. data output format (btc) the ads5422 makes two data output formats available, either the straight offset binary (sob) code or the binary two s complement (btc) code. the selection of the output coding is controlled through the btc pin. applying a logic high will enable the btc coding, while a logic low will enable for the straight offset binary code. the btc output format is widely used to interface to microprocessors for example. the two code structures are identical with the exception that the msb is inverted for the btc format, see tables ii and iii. clk clk ads5422 0.1 f 1:1 square wave clock source r s r t xfr clk clk ads5422 1:1 r t rf sine source xfr
ads5422 15 sbas250 www.ti.com output enable ( oe ) the digital outputs of the ads5422 can be set to high impedance (tri-state) exercising the output enable pin ( oe ). for normal operation, this pin must be at a logic low potential while a logic high voltage disables the outputs. even though this function effects the output driver stage, the threshold voltages for the oe pin does not depend on the output driver supply (vdrv), but are fixed (see the electrical characteris- tics table and the digital inputs sections). operating the oe function dynamically (e.g., high-speed multiplexing) should be avoided as it will corrupt the conversion process. power-down (pd) a power-down pin is provided which, when taken high, shuts down portions within the ads5422 and reduces the power dissipation to less than 40mw. the remaining active blocks include the internal reference ensuring a fast reactiva- tion time. during power-down, data in the converter pipeline will be lost and new valid data will be subject to the specified pipeline delay. if the pd pin is not used, it should be tied to ground or a logic low level. over range indicator (ovr) if the analog input voltage exceeds the full-scale range set by the reference voltages, an over range condition exists. the ads5422 incorporates a function that monitors the input voltage and detects any such out-of-range condition. the current state can be read at the over range indicator pin (ovr). this output is low when the input voltage is within the defined input range. it will change to a high if the applied signal exceeds the full-scale range. it should be noted that the ovr output is updated along with the data output corresponding to the particular sampled analog input volt- age. therefore, the ovr data is subject to the same pipeline delay as the digital data (10 clock cycles). output loading it is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 15pf. higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. for example, with a typical output slew rate of 0.8v/ns and a total capacitive loading of 10pf (including 4pf output capacitance, 5pf input capacitance of external logic buffer, and 1pf pc board parasitics), a bit transition can cause a dynamic current of (10pf 0.8v/1ns = 8ma). these high current surges can feed back to the analog portion of the ads5422 and ad- versely affect the performance. if necessary, external buffers or latches close to the converter s output pins may be used to minimize the capacitive loading. they also provide the added benefit of isolating the ads5422 from any digital activities on the bus coupling back high frequency noise. power supplies when defining the power supplies for the ads5422, it is highly recommended to consider linear supplies instead of switching types. even with good filtering, switching supplies may radiate noise that could interfere with any high fre- quency input signal and cause unwanted modulation prod- ucts. at its full conversion rate of 62msps, the ads5422 typically requires 240ma of supply current on the +5v supply (+v s ). note that this supply voltage should stay within a 5% tolerance. the ads5422 does not require separate analog and digital supplies, but only one single +5v supply to be connected to all its +v s pins. this is with the exception of the output driver supply pin, vdrv. power dissipation a majority of the ads5422 s total power consumption is used for biasing, therefore, independent of the applied clock fre- quency. figure 14 shows the typical variation in power consumption versus the clock speed. the current on the vdrv supply is directly related to the capacitive loading of the data output pins and care should be taken to minimize such loading. figure 14. power dissipation versus clock frequency. binary two s differential straight offset complement input binary (sob) (btc) +fs 1lsb 11 1111 1111 1111 01 1111 1111 1111 (in = +3.5v, in = +1.5v) +1/2 fs 11 0000 0000 0000 01 0000 0000 0000 bipolar zero 10 0000 0000 0000 00 0000 0000 0000 (in = in = v cm ) 1/2 fs 01 0000 0000 0000 11 0000 0000 0000 fs 00 0000 0000 0000 10 0000 0000 0000 (in = +1.5v, in = +3.5v) table iii. coding table for differential input configura- tion and 4vp-p full-scale input range. power dissipation vs clock frequency sample rate (msps) power dissipation (mw) 700 720 740 760 780 800 820 840 880 45 40 35 30 25 20 15 f in = 10mhz
ads5422 16 sbas250 www.ti.com digital output driver supply (vdrv) a dedicated supply pin, vdrv, provides power to the logic output drivers of the ads5422 and may be operated with a supply voltage in the range of +3.0v to +5.0v. this can simplify interfacing to various logic families, in particular low- voltage cmos. it is recommended to operate the ads5422 with a +3.3v supply voltage on vdrv. this will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line that may affect the ac performance of the converter. the analog supply (+v s ) and driver supply (vdrv) may be tied together, with a ferrite bead or inductor between the supply pins. each of the these supply pins must be bypassed separately with at least one 0.1 f ceramic chip capacitor, forming a pi-filter, as shown in figure 15. the recommended operation for the ads5422 is +5v for the +v s pins and +3.3v on the output driver pin (vdrv). figure 15. basic application circuit of the ads5422 includes recommended supply and reference bypassing. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gnd gnd v ref sel1 sel2 gnd gnd btc pd oe gndrv gndrv gndrv vdrv vdrv vdrv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 +v s +v s +v s +v s +v s +v s gnd gnd clk clk gnd gnd gndrv gndrv ovr dv +v s +v s gnd refby gnd in gnd in gnd gnd gnd gnd reft cm refb gnd b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 nc nc do d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 nc nc 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 ads5422 ovr dv 0.1 f 0.01 f 0.1 f 0.1 f 10 f + 0.1 f 10 f 0.01 f 0.1 f + 0.1 f 50 ? 0.1 f r s r t adt2-1 +v a (5v) +v d (3.3v) 50 ? 22 ? 22 ? 4.7 f 0.1 f 4.7 f 0.1 f + 4.7 f 0.1 f + + 0.1 f 0.1 f 10pf 10pf v in clk in adt2-1
ads5422 17 sbas250 www.ti.com layout and decoupling considerations proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. achieving optimum performance with a fast sampling converter like the ads5422 requires careful attention to the pc board layout to minimize the effect of board parasitics and optimize component placement. a mul- tilayer board usually ensures best results and allows conve- nient component placement. the ads5422 should be treated as an analog component and the +v s pins connected to a clean analog supply. this will ensure the most consistent results, since digital supplies often carry a high level of switching noise which could couple into the converter and degrade the performance. as men- tioned previously, the driver supply pins (vdrv) should also be connected to a low-noise supply. supplies of adjacent digital circuits may carry substantial current transients. the supply voltage must be thoroughly filtered before connecting to the vdrv supply of the converter. all ground connections on the ads5422 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. all ground pins should directly connect to an analog ground plane that covers the pc board area under the converter. because of its high sampling frequency, the ads5422 gen- erates high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. if not sufficiently bypassed, this will add noise to the conversion process. see figure 15 for the recommended supply decoupling scheme for the ads5422. all +v s pins may be connected together and bypassed with a combina- tion of 10nf, 0.1 f ceramic chip capacitors (0805, low esr) and a 10 f tantalum tank capacitor. a similar approach may be used on the driver supply pins, vdrv. in order to minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. they are best placed directly under the package where double-sided component mounting is allowed. in addition, larger bipolar decoupling capacitors (2.2 f to 10 f), effective at lower fre- quencies, should also be used on the main supply pins. they can be placed on the pc board in proximity (< 0.5") of the a/d converter. if the analog inputs to the ads5422 are driven differentially, it is especially important to optimize towards a highly sym- metrical layout. small trace length differences may create phase shifts compromising a good distortion performance. for this reason, the use of two single op amps rather than one dual amplifier, enables a more symmetrical layout and a better match of parasitic capacitances. the pin orientation of the ads5422 package follows a flow-through design with the analog inputs located on one side of the package while the digital outputs are located on the opposite side of the quad-flat package. this provides a good physical isolation between the analog and digital connections. while designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. single- ended clock lines must be short and should not cross any other signal traces. short circuit traces on the digital outputs will minimize capaci- tive loading. trace length should be kept short to the receiving gate (< 2") with only one cmos gate connected to one digital output. if possible, the digital data outputs should be buffered (with 74lcx571, for example). dynamic performance may also be improved with the insertion of series resistors at each data output line. this sets a defined time constant and reduces the slew rate that would otherwise flow due to the fast edge rate. the resistor value may be chosen to result in a time constant of 15% to 25% of the used data rate.
ads5422 18 sbas250 www.ti.com package drawing mtqf008a january 1995 revised december 1996 pm (s-pqfp-g64) plastic quad flatpack 4040152 / c 11/96 32 17 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min gage plane 0,27 33 16 48 1 0,17 49 64 sq sq 10,20 11,80 12,20 9,80 7,50 typ 1,60 max 1,45 1,35 0,08 0,50 m 0,08 0 C 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. may also be thermally enhanced plastic with leads connected to the die pads.
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