View HN29V1G91T-35_1201527.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
flash application design guidelines ade-603-010a rev. 2.0 12/5/00 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi?s or any third party?s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party?s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi?s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi?s sales office for any questions regarding this document or hitachi semiconductor products.
rev. 2.0, 12/00, page iii of 6 preface this document presents flash application guidelines, including points requiring special attention, for developing systems using hitachi and flash memory. hitachi and flash write commands (list of program functions, areas subject to programming, programming example) concept of number of rewrites sample sh interface next step next step next step next step : p1 to p4 : p11, p12 : p13 to p16 ng start of system design ng start of system evaluation hitachi and flash write commands error handling and bad sector processing (errors during reading, erasing, and writing) concept of number of rewrites sample sh interface (basic specifications, overview, sample circuit, input waveforms) sample h8s interface (operating mode, control method, sample circuit, port settings, data transfer to on-chip ram) power shutdown processing : p1 to p5 : p6 to p10 : p11, p12 : p13 to p20 : p20 to p22 : p24, p25 ng data sheet check data sheet : next page ng contact hitachi representative ok system amendment start of system study system design relevant sections in flash application design guidelines rev. 2.0 page hitachi and flash write commands error handling and bad sector processing (errors during reading, erasing, and writing) sample sh interface (input waveforms) power shutdown processing : p3 to p5 : p6 to p10 : p17 to p20 : p24, p25 please contact a hitachi representative in the event of problems relating to flash memory. early diagnosis is vital for solving problems.
rev. 2.0, 12/00, page iv of 6 data sheet pages for reference during the design of a system using hitachi and flash memory are shown below. ng ng ng ng ng ng ng ng ng ng ng ng pin functions system design p6 relevant section and page in hn29w25611 series data sheet ade-203-1178a rev. 1.0 mode setting p7 pin arrangement p3 absolute maximum ratings p17 capacitance p17 command descriptions p8, 9 state transitions p16 function descriptions p36 dc characteristics p18 mode descriptions system amendment reading auto-erase auto-program status register read product id read data recovery read/write : p10 : p10 : p10 : p11 : p11 : p12 ac characteristics test conditions parameters power-on/off, serial mode program, erase, and erase-verify timing waveforms power-on/off serial read erase and status data polling program and status polling product id and status register data recovery read/write clear status register : p18 : p19, 20 : p21, 22 : p23 : p24, 25 : p25 : p26 to 31 : p32 : p33, 34 : p35 command/address/ data input order serial read single-sector erase programming product id code read data recovery read/write : p13 : p13 : p14, 15 : p15 : p15 concerning system use ok ng spec for system use handling of invalid sectors securing system reliability : p36 : p37 : p38
rev. 2.0, 12/00, page v of 6 contents 1. hitachi and flash write commands .......................................................... 1 2. error handling and bad sector processing .................................................. 6 3. concept of number of rewrites ................................................................... 11 4. sample microcomputer interfaces ................................................................ 13 5. power shutdown recovery method ............................................................. 24 6 examples of sector management method..................................................... 26 7 some common questions ............................................................................. 34 8. check list ..................................................................................................... 46
rev. 2.0, 12/00, page vi of 6
rev. 2.0, 12/00, page 1 of 46 1. hitachi and flash write commands 1.1 overview this section describes the differences between the four kinds of auto-program commands, program (1) to program (4). programming operations can be broadly classified into the following three kinds: ? additional write performs additional writing to arbitrary bytes in the erased state (ffh) within a sector. (program1, program3) ? write performs writing to a sector in the erased state. (program2) ? rewrite rewrites data regardless of the write target byte data. (program4)
rev. 2.0, 12/00, page 2 of 46 1.2 list of hitachi and flash program functions program no. target area (column address ca range) column address function figure no. yes ? performs additional writes starting at byte indicated by input column address. ? additional writes are possible on unwritten (ffh) bytes. ? ffh is input for bytes on which writes are not performed. figure 1.2 program(1) additional write data area (ca0 to ca2047) + control area (ca2048 to ca2111) no ? performs additional writes on sector. ? additional writes are possible on unwritten (ffh) bytes. ? ffh is input for bytes on which writes are not performed. figure 1.3 program(2) write data area (ca0 to ca2047) + control area (ca2048 to ca2111) no ? performs additional writes on sectors in erased state (all ffh). ? ffh is input for bytes on which writes are not performed. figure 1.4 program(3) control area additional write control area (ca2048 to ca2111) no ? performs additional writes on control area. ? additional writes are possible on unwritten (ffh) bytes. ? ffh is input for bytes on which writes are not performed. figure 1.5 yes ? performs rewrites starting at byte indicated by input column address. ? rewrites with input data (including ffh data). figure 1.6 program(4) rewrite data area (ca0 to ca2047) + control area (ca2048 to ca2111) no ? performs rewrites on sector. ? rewrites with input data (including ffh data). figure 1.7 notes on use of additional writes ? as additional writes by program(1) and program(3) are also counted in the number of rewrites, the stipulated number of rewrites should not be exceeded. for the method of counting rewrites, see section 3, concept of number of rewrites. ? additional rewrites are performed in byte units.
rev. 2.0, 12/00, page 3 of 46 1.3 areas subject to hitachi and flash programming memory array 0 0 register 2111 2048 2111 ? program(3) (sector) 16383 0 2048 memory array 0 column address program(1) with ca program(4) with ca (sector) 16383 0 memory array 0 register 2111 (column) 2111 (column) 0 0 2111 2111 sector address program(1) without ca program(2) program(4) without ca (sector) 16383 0 register sector address sector address figure 1.1 areas subject to hitachi and flash programming 1.4 examples of use of hitachi and flash program modes examples of the use of the various program modes are shown below. 1. program(1) with ca (additional write) writes are performed on bytes with a value of ffh. (byte-unit additional writes) note: when ffh is input, the result is no change to the existing stored data. 10 0 2111 (column address) (data) 20 30 40 50 60 70 80 ff ff ff ff ff ff ff ff 90 a0 b0 c0 ff ff ... ff ff ff ff ff 10 20 30 40 50 60 70 80 no data 10 memory cell data before writing write data from outside buffer data in actual writes 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 90 a0 b0 c0 ff ff ... ff figure 1.2 program mode example 1 2. program(1) without ca (additional write) 10 0 2111 (column address) (data) 20 30 40 50 60 70 80 ff ff ff ff ff ff ff ff 90 a0 b0 c0 ff ff ... ff ff ff ff ff ff ff ff ff 10 20 30 40 50 60 70 80 no data 10 memory cell data before writing write data from outside buffer data in actual writes 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 90 a0 b0 c0 ff ff ... ff figure 1.3 program mode example 2
rev. 2.0, 12/00, page 4 of 46 3. program(2) (write for pre-erased sectors) writing is performed on sectors in the erased state. note: when ffh is input, the result is no change to the existing stored data. ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... ff ff ff ff ff ff ff ff ff 10 20 30 40 50 60 70 80 no data ff ff ff ff ff ff ff ff 10 20 30 40 50 60 70 80 ff ff ff ff ff ff ... ff 0 2111 (column address) (data) memory cell data before writing write data from outside buffer data in actual writes figure 1.4 program mode example 3 4. program(3) (additional write to control area) writing is performed on bytes with a value of ffh in the control area. note: when ffh is input, the result is no change to the existing stored data. 10 20 30 40 50 60 70 80 20 30 40 ff ff ff ff 90 a0 b0 c0 ff ff ... ff ff ff ff ff 50 60 70 80 no data 10 20 30 40 50 60 70 80 ... ... 20 30 40 50 60 70 80 90 a0 b0 c0 ff ff ... ff 0 2048 2111 (column address) (data) memory cell data before writing write data from outside buffer data in actual writes figure 1.5 program mode example 4 5. program(4) with ca (rewrite) performs rewriting. addresses for which data has been entered from outside are rewritten. (ffh data rewriting is also performed.) 10 20 30 40 50 60 70 80 ff ff ff ff ff ff ff ff 90 a0 b0 c0 ff ff ... ff 50 60 70 80 ff ff ff ff 10 20 30 40 50 60 70 80 no data 50 60 70 80 ff ff ff ff 10 20 30 40 50 60 70 80 90 a0 b0 c0 ff ff ... ff 0 2111 (column address) (data) memory cell data before writing write data from outside buffer data in actual writes figure 1.6 program mode example 5 6. program(4) without ca (rewrite) 10 20 30 40 50 60 70 80 ff ff ff ff ff ff ff ff 90 a0 b0 c0 ff ff ... ff 50 60 70 80 ff ff ff ff 10 20 30 40 50 60 70 80 no data 50 60 70 80 ff ff ff ff 10 20 30 40 50 60 70 80 90 a0 b0 c0 ff ff ... ff 0 2111 (column address) (data) memory cell data before writing write data from outside buffer data in actual writes figure 1.7 program mode example 6
rev. 2.0, 12/00, page 5 of 46 conditions for the use of the program(1) to program(4) modes are summarized below. write execution program(1) program(2) program(3) program(4) can be used write target sector in erased state? program(1) program(3) program(4) can be used program(1) program(4) can be used program(4) can be used yes write target byte in erased state? yes no no no write of control bytes only? yes figure 1.8 conditions for use of each program mode
rev. 2.0, 12/00, page 6 of 46 2. error handling and bad sector processing a read, erase, or rewrite error may occur when hitachi and flash memory is programmed. to secure system reliability, provisions must be made to handle such errors when they occur. the approach to error handling and bad sector processing is outlined below. the most appropriate processing should be incorporated into the system after checking details of flash memory state transitions, status information, etc., in the data sheet. 2.1 errors during reading when a data read is performed, the read data may differ from the written data. therefore, an ecc correction function of 3 or more bits per sector (2 kbytes) should be provided. read data + ecc code write data + ecc code (rewrite corrected data) error correction ecc check 2-kbyte data preparation ecc generation when writing ecc code generation write data + ecc code ok ng ... flash processing ... controller processing start ecc check when reading start start end end figure 2.1 example of read error handling
rev. 2.0, 12/00, page 7 of 46 2.2 errors during erasing the main points for attention when an error occurs during erasing are given below. (1) factory shipped bad sectors, or sectors that have become bad due to erasing or writing, should not be erased or written. (2) carry out a good sector code check before writing or erasing. one option may be to create a check table in which such sectors are recorded. (3) data in a sector in which an error has occurred during erasing will be undefined, and meaningless data will be returned if the sector is read. (4) if an error occurs, record the bad sector, and then issue a clear status register command and restore the flash memory to the state in which commands can be received. read good sector code erase bad sector good sector code check ng ok status read busy ready ready/busy record bad sector record bad sector clear status register ... flash processing ... controller processing start end end figure 2.2 example of erase error handling
rev. 2.0, 12/00, page 8 of 46 2.3 errors during writing the main points for attention when an error occurs during writing are given below. (1) factory shipped bad sectors, or sectors that have become bad due to erasing or writing, should not be erased or written. (2) carry out a good sector code check before writing or erasing. one option may be to create a check table in which such sectors are recorded. (3) error confirmation can be achieved by performing a status register read after writing. (4) data in a sector in which a write error has occurred will be indeterminate, and should not be used for rewriting to a spare sector. (5) any of the following three methods can be used for rewriting. (a) writing data reloaded from an external buffer (see figure 2.4.) requires host to maintain data buffer until successful completion of write command. (b) data recovery read (see figure 2.5.) (c) data recovery write (see figure 2.6.) (6) do not perform any further accesses to a sector in which an error has occurred.
rev. 2.0, 12/00, page 9 of 46 write ng ok ng ok (a) status read busy ready ready/busy start clear status register external buffer data load record bad sector (b) (c) find spare sector write record bad sector find spare sector data recovery write data recovery read status read ... flash processing ... controller processing end (a) writing data reloaded from an external buffer (see figure 2.4.) requires host to maintain data buffer until successful completion of write command. (b) data recovery read (see figure 2.5.) (c) data recovery write (see figure 2.6.) figure 2.3 example of write error handling
rev. 2.0, 12/00, page 10 of 46 2 kb + ecc flash ng rewrite destination controller (1) (2) 2 kb + ecc sector addresses data buffer figure 2.4 writing data reloaded from an external buffer 2 kb + ecc flash ng rewrite destination controller (1) (3) (2) 2 kb + ecc sector addresses data buffer figure 2.5 data recovery read 2 kb + ecc flash ng rewrite destination controller (1) (2) 2 kb + ecc sector addresses data buffer figure 2.6 data recovery write
rev. 2.0, 12/00, page 11 of 46 3. concept of number of rewrites 3.1 definition of number of rewrites this is calculated by totaling the number of operations for each process per sector unit (see below). erase + write 1.0 additional write 1.0 rewrite 1.0 3.2 definition of bad sector occurrence rate [= 1.8(%)] the probability of a defect occurring when the same sector is rewritten 300,000 times. (see figure 3.1.) n = stipulated number of rewrites n number of rewrites 1.8% bad sector occurrence rate figure 3.1 definition of bad sector occurrence rate 3.3 sample calculation of number of spare sectors example: number of spare sectors needed when the entire area of 98% mgm flash is rewritten 300,000 times defect rate of 1.8(%) for 300,000 rewrites with total of 16,384 sectors and mgm rate of 98(%) number of spare sectors needed = 16,384 0.98 0.018 = 290 (sectors) or more
rev. 2.0, 12/00, page 12 of 46 3.4 notes on number of rewrites (1) do not exceed the stipulated number of rewrites on the same sector. (2) if the stipulated number of rewrites is exceeded, unexpected errors may occur in that sector. (3) execute processing on the system side to prevent a system crash in the event of such an error.
rev. 2.0, 12/00, page 13 of 46 4. sample microcomputer interfaces 4.1 sample sh interface this section shows examples of the interface to a microcomputer. operation of the sample sh interface circuit has been confirmed with an sh7709. 4.1.1 basic specifications embedded flash (and) control is performed from the sh by means of simple flash control logic (ttlic, ga, etc.). (1) interfacing is performed via area n (csn). (2) a register to control the flash pins is provided at an area n (csn) address (address: ap). (external ports: ce , we , cde , sc) (3) flash is accessed by area n (csn) address (address: af). (4) 2.5 kbytes of ram are necessary (5 kbytes recommended) as a buffer for providing a spare sector in the event of a flash memory write or read error. ram sh flash ttlic, ga, etc. data bus flash control logic minimum requirement: 2.5 kbytes can be connected externally a0 figure 4.1 flash memory interface block configuration
rev. 2.0, 12/00, page 14 of 46 4.1.2 overview (1) cde performs command/address switching, and so can be low during polling. (2) ce disables all input (including sc), so is overlapped with we , sc, etc. (3) operation is not started by a command not stipulated in the data sheet. ex: 02h, 03h, ... 07h, etc. (4) sc becomes valid after the prescribed procedure. after sa(2) + first access when reading; after sa(2) cde fall when writing. (5) polling is performed by i/o7. (r/b not used.) cpu bus flash v cc v cc reset sc r/b i/o0 to i/o7 v ss an to am, csn d0 to d7 gnd power on reset address qualifier latch figure 4.2 flash memory interface block configuration description of blocks ? address qualifier selects whether an input value from the data bus is to be latched as a signal for control signal setting, or the latch data is to be held. during the latch data hold period, control signals are output to the flash memory, so command, sector address, or other input is performed from the data bus to the flash memory. ? latch latches data input from the data bus, and provides the necessary control signal to the flash memory on the basis of that latched data.
rev. 2.0, 12/00, page 15 of 46 4.1.3 sample circuit cpu bus flash address qualifier latch reset r/b i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 a0 d7 d6 d5 d4 d3 d2 d1 d0 dq dq dq dq power-on reset figure 4.3 flash control logic various kinds of processing are performed on the flash memory by combining the states in (1) and (2) below (see section 4.1.4, input waveforms, for the flow).
rev. 2.0, 12/00, page 16 of 46 (1) address a0 = high & csn csn csn csn = low flash control signals are set in the latch (command setting, sector address setting, data read/write ce , oe , we , cde , etc.). latch input signal name latch data output signal state 1) d0 1; we0 we 0; we fixed high 2) d1 1; cde fixed high 0; cde fixed low 3) d2 1; we0 sc 0; rd sc 4) d3 1; ce fixed high 0; ce fixed low (2) address a0 = low & csn csn csn csn = high latch hold state; command setting and data read/write access executed on the flash memory.
rev. 2.0, 12/00, page 17 of 46 4.1.4 input waveforms sample input waveforms in read, program, and erase operations are shown below. ? serial read (1) (2) ? program (1) (3) ? erase (1) (4) (1) command and address setting 01h a0 d0 to d7 * 1 com flash commands serial read: 00h program2: 1fh sing sec erase: 20h * 2 sa1, sa2 sector addresses sc latch set command set latch set address set address set com 03h sa1 * 1 * 2 sa2 * 2 figure 4.4 example of timing waveforms in command and address setting
rev. 2.0, 12/00, page 18 of 46 (2) read data read sb data read data read data read latch set 0fh sb sb sb a0 d0 to d7 sc figure 4.5 example of read timing waveforms ? read flow i/o a0 d0 to d7 o 1 0fh (clear) o 1 01h (com latch) o 0 00h (serial read) o 1 03h (add latch) o 0 aah (sector add 1) o 0 aah (sector add 2) i 0 data (read data) :: : o 1 0fh (clear)
rev. 2.0, 12/00, page 19 of 46 (3) program a0 d0 to d7 sc latch set data write data write latch set command set program start wait status read latch set 01h 04h 0fh sb sb figure 4.6 example of program timing waveforms ? programming flow i/o a0 d0 to d7 o 1 0fh (clear) o 1 01h (com latch) o 0 11h (program 4) o 1 03h (add latch) o 0 aah (sector add 1) o 0 aah (sector add 2) o 1 04h (sc latch) o 0 ddh (data input) :: : o 1 01h (com latch) o 0 40h (prg start) (status read) o 1 0fh (clear)
rev. 2.0, 12/00, page 20 of 46 (4) erase a0 d0 to d7 sc latch set command set status read latch set erase start wait 0fh 01h figure 4.7 example of erase timing waveforms ? erase flow i/o a0 d0 to d7 o 1 0fh (clear) o 1 01h (com latch) o 0 20h (single erase) o 1 03h (add latch) o 0 aah (sector add 1) o 0 aah (sector add 2) o 1 01h (com latch) o 0 b0h (erase start) (status read) o 1 0fh (clear) 4.2 sample h8s interface 4.2.1 operating mode mode 3/expe = 0 normal single-chip mode is used.
rev. 2.0, 12/00, page 21 of 46 4.2.2 control method control is performed using ports in order to implement simple signal connection and control. port 1 is used for signal control. port 2 is used for data input/output. h8s flash port 1 control signals port 2 data figure 4.8 control method 4.2.3 sample circuit h8s/2100 flash 1 flash 2 port 1 port 2 p10 p11 p12 p13 p14 p15 p16 p17 oe we cde sc ce1 rdy /busy oe we cde sc ce2 rdy /busy i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 res i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 res open p20 p21 p22 p23 p24 p25 p26 p27 power on reset circuit figure 4.9 sample circuit
rev. 2.0, 12/00, page 22 of 46 4.2.4 port settings port 1 settings port 1 p10 p11 p12 p13 p14 p15 p16 p17 flash memory oe we cde sc ce1 ce2 ? rdy/busy input/output out out out out out out out in pull up yes yes yes no yes yes yes yes port 2 settings port 2 p20 p21 p22 p23 p24 p25 p26 p27 flash memory i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 input/output i/o i/o i/o i/o i/o i/o i/o i/o pull up yes yes yes yes yes yes yes yes 4.2.5 data transfer to on-chip ram if the on-chip ram capacity is not sufficient for one flash sector of data to be transferred, one sector of data should be divided for transfer as shown in the example below. example: one sector of data is divided into four parts, which are transferred separately. taking 2048 + 64 bytes as (512 (data area) + 16 (management area)) 4 bytes, 528 bytes are transferred at a time. h8s microcomputer flash on-chip ram 528 528 528 528 528 (1) transfer of 528-byte unit (3) transfer of 528-byte unit (2) 528-byte data processing figure 4.10 example of data transfer
rev. 2.0, 12/00, page 23 of 46 4.3 reference materials (1) 256-mbit flash memory (hn29w25611 series) data sheet (2) sh series hardware manual (3) h8s series hardware manual
rev. 2.0, 12/00, page 24 of 46 5. power shutdown recovery method 5.1 internal circuitry that executes erasing/writing figure 5.1 shows the 256-mbit flash memory circuit configuration and memory cell erase/write operations. memory cells are linked by a source line, word line, and data line, with each signal line driven by peripheral circuitry. in a write, a charge is injected into the floating gate by setting the word line to positive potential. in an erase, the floating gate charge is discharged by setting the word line to negative potential. when power is shut down, the memory cells themselves in the flash memory are not damaged, but memory cell data may become invalid due to faulty operation of the peripheral circuitry that controls memory cell erasing, writing, etc. (see figure 5.1). 256m flash memory (and type) reset ic v cc peripheral circuitry data buffer i/o [7:0] word line data line source line word line erase processing eee source line sense amp word line word line v ss erase/write control circuit floating gate word line write processing floating gate data line eee flash memory cell data line source line (a) image of flash memory circuit configuration (256m flash memory) (b) flash memory erase and write operations (based on 256m flash memory) figure 5.1 flash memory circuit configuration image and erase and write operations
rev. 2.0, 12/00, page 25 of 46 5.2 processing when power shutdown occurs during erase or write operations if power is shut down during erase or write processing, the following processing should be executed. (1) execute a reset by activating the res signal. (the peripheral circuitry will be initialized.) (2) perform erase/write processing again on any sector in which the data has been corrupted due to erasing/writing when the power shutdown occurred. (3) read the good sector codes of all sectors, and perform erase/write processing again on any other sectors that have become bad. note that the processing in (1) and (3) above can be eliminated by connecting an external reset ic (see figure 5.1). in this case, only the processing in (2) should be carried out. 5.3 when power shutdown occurs during reset, read transfer, or other processing execute the processing in (1) and (3) above. note that this processing can be eliminated by connecting an external reset ic. 5.4 if sectors in which a fault has occurred cannot be restored by means of the above processing, processing should be carried out to prevent use of those sectors in the system.
rev. 2.0, 12/00, page 26 of 46 6 examples of sector management method 6.1 flash configuration the flash configuration in the case of a 256-mbit product is shown in figure 6.1. the (2048 + 64) bytes constituting a sector are divided into four, giving (512 + 16) bytes as the minimum unit of data. in this section, (512 + 16) bytes is called a sector, and (2048 + 64) bytes is called a block. 256-mbit flash is composed of 16,384 blocks, with each block consisting of four (512 + 16)-byte sectors. for data writing, the program (4) program command is used. an erase command is only used when erasing data as a block. block 0 block 1 block 2 block 3 block 16382 block 16383 (2048 + 64) bytes (512 + 16) bytes sector 0 (512 + 16) bytes sector 1 (512 + 16) bytes sector 2 (512 + 16) bytes sector 3 4 sectors/block total number of blocks: 16,384 capacity: (2048 + 64) bytes/block figure 6.1 flash configuration each sector is composed of a 512-byte data area, ecc bytes, and sector management bytes. 512 bytes data 16 bytes ecc + management 512 bytes data 16 bytes ecc + management 512 bytes data 16 bytes ecc + management 512 bytes data 16 bytes ecc + management
rev. 2.0, 12/00, page 27 of 46 6.2 block management method the block configuration is shown in table 6.1. table 6.1 block configuration item number of blocks used description bad block recording table 1 block stores good/bad block information block management table 16 blocks manages correspondence between physical block numbers and logical block numbers. logical block numbers are consecutive spare block area (1) m blocks area reserved for bad blocks. for 256-mbyte flash, from data sheet, m = 16,384 0.98 0.018 290 blocks spare block area (2) n blocks area reserved for initial bad blocks. n = 0 to 328 data block area 16384 ? (m +n +16 +1) area that can be used as data area. for 256- mbyte flash, min = 15,750 blocks, max = 16,078 blocks block information 1 block stores total number of blocks in data block area (1) bad block recording table this table performs management of good/bad flash blocks. the management information is created when flash formatting is carried out. this data is saved as a backup for the initial good/bad block information. good/bad information is stored as 1-bit data, and data is held for each physical block. 512 bytes s: 4,096 blocks can be recorded 16 bytes 012345 6 1110 good block bad block 1101 01234567 512 ? ? ecc + management physical block number figure 6.2 block recording table
rev. 2.0, 12/00, page 28 of 46 (2) block management table this table manages the correspondence between physical block numbers and logical block numbers for usable blocks. the management information is created when flash formatting is carried out. the table is updated whenever a bad block occurs during use. the block information in the block management table is shown in figure 6.3. two bytes of data are provided for each logical block, holding the physical block number corresponding to the logical block number. the effective capacity information bit indicates whether a logical block corresponds to a data area. 512 bytes : 256 blocks can be recorded 16 bytes 0123456 0123xx56 255 ? ? effective capacity information logical block number ecc + management xx: spare block number physical block number (14 bits) blank corresponding physical block present : 0 no corresponding physical block : 1 figure 6.3 block management table (3) spare block areas the spare block areas are spare areas in the event of a bad block. figure 6.4 shows the location of each area. the data area is located starting at flash physical block number 0000h. a bad block in the data area is switched to spare block area (1). starting from the highest physical block number, the bad block recording table, block management table, and spare block areas, are located in that order. when there is a bad block, it is placed in the lower good block. for example, if physical block number 3fffh is a bad block, the bad block recording table is placed at 3ffeh.
rev. 2.0, 12/00, page 29 of 46 0000h 0 to 328 blocks 290 blocks 16 blocks 1 block data area spare block area (1) spare block area (2) block management table bad block recording table figure 6.4 alternate block areas
rev. 2.0, 12/00, page 30 of 46 6.3 sector management codes sectors are managed by means of 16-byte management data the management data consists of a sector identification code, block number, good sector identification code, and ecc code. 512 bytes data 16 bytes ecc + management 512 bytes data 16 bytes ecc + management 16 bytes ecc + management 16 bytes ecc + management 512 bytes data 512 bytes data sector management bytes ecc bytes blank sector identification block identification block number good block code figure 6.5 sector management codes (1) good block code stores 3 bytes (1c71c7h) of the ex-factory good block code. (2) block number stores the logical block number to which the sector belongs. (3) block identification code indicates which area (data area, spare block area, block management table, or bad block recording table) the block belongs to. the same code is stored for sectors within the same block (see table 6.2). (4) sector identification indicates the sector status (in use or not used) (see table 6.3). (5) ecc bytes these bytes store the eec code for 512 bytes of data.
rev. 2.0, 12/00, page 31 of 46 table 6.2 examples of block identification code block type example of code data area 0fh spare block area (1) 01h substituted 10h spare block area (2) not used 1fh block management table 00h bad block recording table f0h ex-factory bad block undefined acquired bad block ffh table 6.3 examples of sector identification code sector status example of data in use 00h not used ffh
rev. 2.0, 12/00, page 32 of 46 6.4 sector access methods data area sectors are accessed by sector number. sector numbers start from 0. the quotient resulting from dividing a sector number by 4 is the flash logical block number, and the remainder is the sector position within the block. figure 6.6 shows a comparison between physical block numbers and logical block numbers. block 0 block 1 block 2 bad block (initial) block 4 block 5 bad block (acquired) block 7 block 0 logical format block 1 block 2 block 3 block 6 block 4 block 5 block 7 0 1 2 3 6 4 5 7 block 3 block 6 ? ? ? ? bad block recording table physical format spare block area (2) block management table 16 blocks spare block area (1) figure 6.6 comparison of physical and logical formats with this sector management method, except for bad sectors, logical block number = physical block number. therefore, a method whereby a sector is accessed by performing physical/logical block number conversion, and a method whereby a sector is accessed by performing only bad block physical/logical block number conversion, are possible.
rev. 2.0, 12/00, page 33 of 46 start start access to data access method (1) access method (2) logical block number sector position calculation logical block number calculation from block management table access to data logical block number sector position calculation sector management information read good sector access to data bad sector logical block number calculation from block management table figure 6.7 sector access methods if a sector error occurs, the block to which the relevant sector belongs is identified as a bad block, and substitution is performed.
rev. 2.0, 12/00, page 34 of 46 7 some common questions this section presents a number of technical questions that have been received concerning and flash memory, in a q&a format. 7.1 concerning flash memory [question] what kind of memory is flash memory? [answer] flash memory is a kind of nonvolatile memory (nvm), which retains its data even if power is cut, and features both a high level of integration and electrical programming functions. flash memory is broadly divided into two kinds: random access type and serial access type. and flash is serial access flash memory. [question] what is the difference between and flash and nand flash? [answer] both are serial access type flash memory for data storage use, featuring large capacity and high- speed reading, wiring, and erasing. a major difference between the two relates to the write/erase units. with and flash, the write unit and erase unit are the same. for 256-mbyte flash, this is the (2k + 64)-byte sector unit. with nand flash, the write unit and erase unit are different, with a (512 + 16)-byte page used for writing, and an 8- to 16-kbyte block unit for erasing. [question] what is mgm? [answer] mgm is an abbreviation of mostly good memory. 98% mgm refers to memory in which fewer than 2% of all sectors are invalid (bad) when the product is shipped. this increases chip yield and helps to lower costs.
rev. 2.0, 12/00, page 35 of 46 [question] what is multi-level technology? [answer] in contrast to the two threshold levels, 0 and 1, of conventional memory, this technology controls four threshold levels, 00, 01, 10, and 11, enabling two memory cells' worth of data to be stored in a single memory cell. as multi-level technology enables twice the capacity of conventional technology to be achieved with the same number of memory cells, it is effective in cutting costs by increasing capacity and reducing chip size. conventional cell type multi-level cell type memory cell distribution memory cell distribution memory cell threshold levels memory cell threshold levels
rev. 2.0, 12/00, page 36 of 46 7.2 concerning the interface [question] is it possible to design a system that can support future large-capacity products (512 mbytes and up)? [answer] yes. the functions, command system, and electrical characteristics are compatible with current 512-mbyte flash, but the increase in addresses has to be taken into consideration. the package, also, is identical to the 48-pin tsop (i), and the pins necessary for control are also the same. [question] how should and flash be used? [answer] the optimum method of use is determined by the requirements for the target system flash. generally speaking, there are two methods of use, involving a trade-off between mounting area and performance: 1) using a dedicated controller and a software driver for its interface (pc-ata or ide) 2) incorporating the flash driver in the host cpu firmware, and performing direct control with a cpu of adequate performance (sh-3 80 mhz level) rom cpu firmware flash driver and flash pc-ata/ide cpu controller and flash (1) using a dedicated controller (2) direct control by the cpu
rev. 2.0, 12/00, page 37 of 46 7.3 concerning power shutdown [question] are there any points requiring attention when powering on and off? [answer] the res pin should be driven low before turning on the power. when powering off, check that the chip is in the ready state, then drive the res pin low and cut the power. using this procedure will ensure that data is protected even if the input signal becomes unstable when powering on or off . vihr vilr vilr don ? t care vilr = v ss 0.2 v vihr = v cc 0.2 v v cc res input signal after power-on, the chip performs internal initialization processing, and automatically goes to the standby state. operation is possible as soon as the status changes to ready. [question] won't data be lost if a power cut (momentary power interruption) occurs? [answer] data will not be lost if the flash status is ready. in addition, data will not be lost when the status is busy during reading. if the status is busy during writing/erasing, operation is forcibly terminated before the memory cells go to the normal write/erase state, and so the data in the relevant sector will be undefined. for the sector recovery method in this case, see section 5, power shutdown recovery method.
rev. 2.0, 12/00, page 38 of 46 7.4 concerning reset operations [question] can operation be forcibly reset by issuing a reset command (ffh) in the busy state? [answer] no. no commands are accepted in the busy state. in the case of writing/erasing, it is possible to transit to the standby state by using a reset command (ffh) during the setup state before a start command (writing: 40h, erasing: b0h) is issued. [question] what happens if a hardware reset ( res : low) is performed in the busy state? [answer] all operations are forcibly terminated and a transition is made to the deep standby state. in the case of writing/erasing, the data in the relevant sector will be undefined. the recovery method for a sector with undefined data due to a hardware reset is the same as the sector recovery method after power is cut. see section 5, power shutdown recovery method.
rev. 2.0, 12/00, page 39 of 46 7.5 concerning write operations [question] how many times can program (1) and (3) additional writes be performed? [answer] there is no limit to the number of writes that can be performed with the additional write function. however, an additional write should be counted as one rewrite (programming) operation. for example, when performing additional writes with one sector (2 kbytes) divided into four 512- byte units, the number of rewrite operations for that sector should be counted as 4. [question] what is the difference between program (1) and (3) additional writes and program (4) rewriting? [answer] an additional write can only be performed on ffh data (i.e. data in the erased state) in a sector. rewriting (programming) is a data contents update and overwrite function. for details, see section 1, hitachi and flash write commands. [question] if writing is performed with program (4) by specifying a column address, what happens to data outside the specified range? [answer] for data outside the specified range?that is, areas with no data input from outside?the data prior to the write is retained.
rev. 2.0, 12/00, page 40 of 46 7.6 concerning bad sectors [question] what is a bad sector (invalid sector) in and flash? [answer] and flash memory is based on the mgm (mostly good memory) concept, and allows the existence of sectors that do not operate normally?that is, defective sectors?within the chip. these defective sectors are called bad sectors. both bad sectors present when the product is shipped from the factory, and bad sectors that arise later within the user system (acquired bad sectors), are permitted. [question] how many bad sectors can be expected? [answer] when flash is shipped from the factory, fewer than 2% of all sectors are bad. with 256-mbyte flash this means 16,384 2% 328 sectors. [question] do bad sectors occur during use in the system? [answer] yes. of the 98% or more ex-factory good sectors, it is possible that 1.8% (with 256-mbyte flash: 16,384 (total number of sectors) 98% 1.8% 290 sectors) may become bad. [question] how are ex-factory bad sectors identified? [answer] the data shown in the table below is written in good sectors. if column addresses 820h to 825h are as shown in the table, the sector is good. data in a bad sector is undefined. column address 000h to 81fh 820h 821h 822h 823h 824h 825h 826h to 83fh data 00h 1ch 71h 17h 1ch 71h c7h ffh
rev. 2.0, 12/00, page 41 of 46 [question] how can the occurrence of bad sectors be identified during use in the system? [answer] an error during writing/erasing is identified by reading the status register. after writing/erasing has been performed and the ready state is entered, the relevant bit of the status register (bit 4 for writing, bit 5 for erasing) is checked, and processing ends normally if the bit is 0, or ends with an error if the bit is 1. in a normal end, the memory data values are as expected. read errors should be detected using a method such as eccs. mode detection method erase error status register read write error status register read read error ecc check, etc. [question] when a sector that did not have a good sector code at the time of shipment was rewritten, the processing ended normally. can this sector be used as a good sector? [answer] a sector that does not have a good sector code at the time of shipment is a bad sector. a bad sector is one with a defect of some kind, or one that has a high probability of developing a defect. even if rewriting is performed normally, there is still a possibility of some kind of problem arising, such as with the reliability of the data, for instance. therefore, bad sectors should not be accessed. [question] when a bad sector is read, data of some kind is obtained. will the same data be obtained however many times that sector is read? [answer] as data in a bad sector lacks reliability, there is no guarantee that the same data will be obtained again.
rev. 2.0, 12/00, page 42 of 46 7.7 concerning sector information (good/bad sectors) [question] is it possible to recover ex-factory sector information if it has been erased? [answer] it is extremely difficult to do so. ex-factory bad sectors are identified as the result of various tests conducted during the manufacturing process. in addition to simple write/erase/read tests, a test mode is also used that takes past experience into consideration. there are many modes for the occurrence of a bad sector, and only some of these are tested in ordinary write/erase tests. it is important to save sector information in some way, and ensure that it is not lost. [question] is it ok for sector codes written at the time of shipment to be overwritten with different codes? [answer] yes, this is possible. as long as good/bad sector information can be saved, the method is immaterial. the most appropriate method for the system should be used. [question] will any problems occur if ex-factory sector information is not used? [answer] bad sectors will be used. if a bad sector is used, the data in that sector will be unreliable. even if writing/erasing ends normally, there is a possibility of problems occurring such as data become corrupted when left for a short while. [question] can bad sectors be managed by writing a bad sector code? [answer] no. no data whatever can be written to a bad sector. even if a write is performed successfully, the data will be unreliable.
rev. 2.0, 12/00, page 43 of 46 7.8 concerning sector management [question] what kind of management is necessary? [answer] the following three kinds of management should be carried out. (1) preventing ex-factory bad sectors from being accessed (2) identifying bad sectors that occur during use in the system, and preventing their subsequent access (3) performing sector replacement processing [question] if a power interruption occurs after erasing is completed when rewriting data in the system, the good sector code is lost, and when power is restored the relevant sector becomes a bad sector. is there any way of preventing this conversion to a bad sector? [answer] one method is to hold a sector management table in the flash together with the good sector codes.
rev. 2.0, 12/00, page 44 of 46 7.9 concerning error handling and sector substitution processing [question] when a write error occurs, is it ok to perform a retry on the same sector? [answer] there is a possibility of an error occurring again. the retry should be performed on a different sector. [question] how is the spare block decided when a sector error occurs and sector replacement is performed? [answer] there is no fixed procedure. a method appropriate to the system should be used, such as reserving a certain area as a spare block area, or finding an empty sector when an error occurs and using that sector as the spare block.
rev. 2.0, 12/00, page 45 of 46 7.10 concerning eccs [question] the sector data area is divided into four 512-byte units for use. is a 3-bit ecc necessary for 512 bytes in this case? [answer] yes. [question] is it ok to write a code generated by the ecc function to a management area? [answer] yes, this can be done. [question] why are eccs necessary? [answer] they are used for detecting/correcting random bit errors due to data retention, and preventing read errors. a write error can easily be identified by checking the status, but a read error may occur due to data retention after the write has ended normally. as flash outputs data without detecting changes that may have occurred due to data retention, verification of read data is necessary on the system side. 7.11 concerning disturbance [question] are there any write patterns that are susceptible to disturbance? [answer] no. there is no disturbance problem with good sectors.
rev. 2.0, 12/00, page 46 of 46 8. check list when designing a system incorporating hitachi and flash memory, the specifications in the following check list should be confirmed before starting the design work. item check column remarks must-do items hardware design basic operational condition timing operation command setting system reliability software design basic software design pin arrangement absolute ratings operating environment v cc t opr e/w i cc2 (typ.) v ih (min.) v il (max.) t r /t f other 3.3 ?0.3 v 0 to 70 ? c 300k times 30 ma 2.0 v v cc ?0.2 v 0.8 v 0.2 v 5 ns p1, 18 p17 p36 (290 alternate sectors when using 3-bit ecc) p18 (f = 20 mhz) p18 p18 ( ) p18 p18 ( ) p19 mode setting power-on sequence manufacturer? code read product code read status register read clear status register serial read programming recovery read recovery write power-off sequence all timing items understood that this is mgm. possibility of up to 2% random bad sectors out of 16,384 sectors. only good sectors must be accessed. system should not stop even if a good sector becomes a bad sector when accessed. good sector code must not be deleted except in case of error occurrence. if power supply (3.0 v min.) cannot be sustained, hitachi? recommended power-off sequence must be executed. error provisions (1) provide alternate sectors (at least 290). (2) perform at least 3-bit ecc. power shutdown provisions in case of emergency, perform chip-internal processing with /res signal before powering off. if there is chain data, system must ensure that there is no problem if chain is broken midway. (1) (2) (1) (2) (3) (4) p6, 10, 11, 12 p23 p32 p32 p32 p35 p24, 25 p24, 25 p26, 27 p28 p29 p30, 31 p33 p34 p23 p19 to 22 relevant page of data sheet (ade-203-1178a(z)) p3, 6 p17
flash application design guidelines publication date: 1st edition, march 2000 2nd edition, december 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 2000. all rights reserved. printed in japan.

▲Up To Search▲

Price & Availability of HN29V1G91T-35

	To Download HN29V1G91T-35 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .