ata6617 - ek development board v1.1 features ? all necessary components to put the ata6617 in to operation are included ? placeholders for some optional comp onents for extended functions included ? all pins easily accessible ? easily adaptable watchdog times by replacing a single resistor ? possibility to activate an external npn-tran sistor to boos t the output current of the voltage regulator (jumper jp3) ? possibility to select between master or slave operation (mounting d2 and r1) ? possibility to mount an external quartz to handle ti me-critical applications (not necessary for lin communication) ? push button included to creat e a local wake-up after ente ring sleep or silent mode ? ground coulter clip for connecting prob es when measuring with the oscilloscope figure 0-1. ata6617 - ek development board ata6617 - ek development board v1.1 application note 9149a?auto?03/09
2 9149a?auto?03/09 ata6617 - ek 1. introduction the development board for the ata6617 ic is desi gned to give designers a quick start with the ata6617 ic and to enable prototyping and testing new lin designs. the ata6617 is a dual-chip system-in-package (s ip) product, which is particularly suited for complete lin bus slave and master node applications. it supports highly integrated solutions for in-vehicle lin networks. the first chip is the lin-system-basis-chip (lin sbc) ata6624, which has an integrated 5v voltage regulator, a window watchdog, and a fully integrated lin trans- ceiver, in compliance with the lin specification 2.1. the second chip is an automotive microcontroller from atmel ? ?s series of avr ? 8-bit microcontrollers with advanced risc archi- tecture (attiny167 with 16k flash). all pins of both integrated chips are bonded out to provide customers the same flexibility fo r their applications as they have when using discrete parts. the included avr provides the following features: ? 16 kbytes of in-system programmable fl ash with read-while-write capabilities ? 512 bytes eeprom ? 512 bytes sram ? 16 general purpose i/o lines ? 32 general purpose working registers ? internal 8 mhz rc oscillator calibrated at 5v at 25c ? 2 flexible timer/counters with compare modes ? internal and external interrupts ? lin 2.1 and 1.3 controller or 8-bit uart ? byte-oriented 2-wire serial interface ? master/slave spi serial interface ? 4-channel 10-bit adc ? four software-selectable power-saving modes: ? idle mode stops the cpu while allowing the sram, timer/counters, adc, analog comparator, and interrupt system to continue functioning. ? power-down mode saves the register content s but freezes the osc illator and disables all other chip functions until the next interrupt or hardware reset. ? power-save mode: the asynchronous timer continues to run allowing the user to maintain a timer base while the rest of the device is sleeping. ? adc noise reduction mode stops the cpu and all i/o modules except adc, which minimize switching noise during adc conversions.
3 9149a?auto?03/09 ata6617 - ek the included lin sbc ata6624 provides the following features: ? master and slave operation possible ? supply voltage up to 40v ? operating voltage vs = 5v to 27v ? typically 10 a supply current during sleep mode and vcc is switched off ? vcc-undervoltage detection (4 ms reset time) and watchdog reset logical combined at open drain output nres ? boosting the voltage regulator possib le with an external npn transistor ? lin physical layer according to lin 2.1 specificat ion and saej2602-2 ? wake-up capability via lin-bus, wake pin, or kl_15 pin ? inh output to control an external voltage regulator or to switch off the master pull up resistor ? txd time-out timer ? bus pin is overtemperature and short circuit protected versus gnd and battery ? adjustable watchdog time via external resistor the combination of the features included in ata6617 make it possible to develop simple, yet powerful and low cost slave nodes in lin bus systems. the ic is designed to handle the low-speed data communication in vehicles, for example, in convenience electronics. improved slope control at the lin driver ensures secure data commu- nication up to 20 kbaud. sleep mode and silent mode included in the lin sbc guarantee a very low current consumption. as there is a standard avr microcontroller with all pins available included in the ata6617, the standard toolchain consisting of the avr studio ? , front-end assembler and simulator, and in-cir- cuit-emulator can be used for developing and debugging new applications. using the software components and the development board, it is very easy and inexpensive to create and test a lin network. in the contrast to the standalone avrs, the in ternal 8 mhz rc oscillator has been calibrated at 5v and therefore perfectly fits the output voltage of the integrated voltage regulator. this document has been developed to provide the user with start-up information about the ata6617?s development board. for more detailed information about the use of the ata6617, refer to the corresponding datasheet.
4 9149a?auto?03/09 ata6617 - ek 2. start-up information the development board for the ata6617 is shipped with the default jumper settings and all accessories required for immediate use. the ic mounted on the board is pre-programmed with a firmware in order to test and to under- stand the basic functions directly on the board. after correctly connecting an external 12v dc power supply between the terminals ?+? and ?-?, the lin sbc is in fail-safe mode. a regulated 5v dc voltage, provided by the internal voltage regulator supplying the internal microcontroller, can be measured at the pvcc jumper. after the power is supplied to the microcontroller, the microcontroller switches the lin sbc to normal mode by setting the en pin to high (enable jumper), and starts to trigger the integrated window watchdog. the system is now ready for data transmission via the lin bus. signals fed in at the txd pin are visible on the lin bus, and sig- nals fed in on the lin bus are visible at the rxd pin. in normal mode, the current consumption is approximately 3 ma and the following voltages and signals can be seen at the corresponding pins. table 2-1. overview of pin status at start-up of the development board test point expected behavior ad ditional information symbol jumper nres 5v dc 1 jumper en 5v dc 2 jumper boost 5v dc 3 jumper ntrig frequency f 36.6 hz v pp = 5v 4 txd frequency f 36.6 hz v pp = 5v 5 rxd frequency f 36.6 hz v pp = 5v 6 lin frequency f 36.6 hz v pp ? 11v 7 wake ~11.2v dc 8 inh ~11.2v dc 9 kl15 0v dc 10 pb0 to pb6 frequency f 36.6 hz v pp = 5v 11 pb7 5v dc 11 pa 0 t o pa 3 , pa 5 t o pa 7 frequency f 36.6 hz v pp = 5v 12 pa4 5v dc 12
5 9149a?auto?03/09 ata6617 - ek figure 2-1. ata6617 development boar d with reference point the board?s pre-programmed firmware provides the window watchdog with a valid trigger signal so that the nres pin is not forced to ground and the microcontroller does not receive any resets. for testing purposes and to understanding the system, it can be helpful to see the behavior when the watchdog is not triggered correctly. this can be achieved in two different ways without changing the firmware of the ic: ? remove ntrig jumper no trigger signal reaches the watchdog and the watchdog generates a reset. ? re-program the fuse bit changing the fuse bit ckdiv8 to un-programmed, changes the microcontroller?s internal clock from 1 mhz to 8 mhz. because of this, the trigger signal generated from the microcontroller does not meet the open window from the window watchdog and a reset is generated.
6 9149a?auto?03/09 ata6617 - ek figure 2-2. ata6617 - ek schematic of the development board 2 1 1 dc- s ocket xv1 ll414 8 gnd2 gnd1 d1 x4 3 1 42 s 1 port b x2 x 3 1 1 2 1 2 1 10 9 6 5 2 1 10 9 6 5 pb1 pb5 pb0 pvcc pb 3 pb2 pb4 pb7 pb6 xi s p1 i s p 1 pvcc pa 4 pa 2 pa 5 pb7 port a x1 txd1 pa 1 txd pa 5 pa 3 pvcc pa 0 ntrig jp2 ntrig v+ v s v+ 2 3 1 pa 3 pa 2 pa 7 pa 4 pa 6 rxd1 rxd + + jp 3 r6 c4 1 12 2.2 f mjd 3 1c t1 1 1 2 enable jp1 en pa 4 ata6617 pb6 pa 7 pa 3 pa 5 pb7 q1 q ua rz pa 6 pa 4 wake pb1 pa 1 pvcc pb7 pvcc pa 2 pa 0 rxd txd pb2 pb0 inh v s pvcc 38 3 2 112 1 3 19 3 120 pb5 pb 3 pb4 en pvcc kl_15 ntrig lin v s v+ v s 1 lin r 3 47 k r4 10 k 100 nf c9 100 nf c1 r5 47 k r2 10 k 3 . 3 r 8 10 k r7 33 k r1 47 k en mode kl15 vcc v s ntrig pb5 gnd pb 3 gnd gnd pb4 vcc wake pb6 pb7 pa7 pa6 pa5 pa4 agnd avcc pa 3 lin pb2 pb1 pb0 pa0 pa1 pa2 rxd inh txd tm nre s wd_o s cgnd pvcc pvcc 100 nf c2 10 f c 3 + 100 nf c5 220 pf c 8 22 pf c11 22 pf c10 100 nf c12 22 f c6 10 nf c7 r9 1 k d2 ll414 8 l1 10 h jp5 1 2 jp4 1 2 wake inh kl_15
7 9149a?auto?03/09 ata6617 - ek figure 2-3. ata6617 - ek board component placement; top side, top view
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