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product specification asd0400 ultra low power dual 20/40/65/80 msps, 10-bit analog-to-digital converter functional block diagram adc adc clk control interface c k p c k n p d _ n d v s s d v d d d v d d c k a v s s a v d d ip0 in0 ip1 in1 d0 d1 ck_ext d v s s c k cm_ext s l p _ n c m _ e x t b c orng_0 orng_1 oe_n_0 oe_n_1 10 10 figure 1 : functional block diagram vestre rosten 81, 7075 tiller, norway org. no: no 991 265 163mva phone: +47 73 10 29 00, fax: +47 73 10 29 19 www.arcticsilicon.com page 1 of 16 confidential description the asd0400 is a high performance low power dual analog-to-digital converter (adc). the adc employs internal reference circuitry, a cmos control interface and cmos output data, and is based on a proprietary structure. digital error correction is employed to ensure no missing codes in the complete full scale range. several idle modes with fast startup times exist. each channel can independently be powered down and the entire chip can either be put in standby mode or power down mode. the different modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. the asd0400 has a highly linear tha optimized for frequencies up to nyquist. the differential clock interface is optimized for low jitter clock sources and supports lvds, lvpecl, sine wave and cmos clock inputs. features 10-bit resolution 20/40/65/80 msps maximum sampling rate ultra-low power dissipation: 24/43/65/78 mw 61.6 db snr at 8 mhz f in internal reference circuitry 1.8 v core supply voltage 1.7 C 3.6 v i/o supply voltage parallel cmos output 64 pin qfn package dual channel pin compatible with asd0500 applications medical imaging portable test equipment digital oscilloscopes if communication
product specification table of contents features ............................................................................ 1 applications ..................................................................... 1 description ....................................................................... 1 functional block diagram ............................................... 1 specifications ................................................................... 3 digital and timing specifications ..................................... 8 timing diagram ............................................................... 9 absolute maximum ratings ............................................. 9 pin configuration and description ................................. 10 recommended usage ..................................................... 11 package mechanical data .............................................. 15 product information ....................................................... 16 ordering information ...................................................... 16 datasheet status .............................................................. 16 asd0400 rev v3.2 , 2010.04.23 confidential page 2 of 16
product specification specifications avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, 20/40/65/80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted parameter condition min typ max unit dc accuracy no missing codes guaranteed offset error midscale offset 1 lsb gain error full scale range deviation from typical +/- 6 %fs gain matching gain matching between channels. +/- 3 sigma value at worst case conditions +/- 0.5 %fs dnl differential nonlinearity +/- 0.15 lsb inl integral nonlinearity +/- 0.2 lsb v cm common mode voltage output v avdd /2 v analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale range differential input voltage range 2.0 vpp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply core supply voltage supply voltage to all 1.8v domain pins. see pin configuration and description 1.7 1.8 2.0 v i/o supply voltage output driver supply voltage (ovdd). should be higher than or equal to core supply voltage (v ovdd v dvdd ) 1.7 2.5 3.6 v asd0400 rev v3.2 , 2010.04.23 confidential page 3 of 16
product specification asd0400 l20 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 2 mhz 61.7 dbfs f in = 8 mhz 60 61.6 dbfs f in @ fs/2 61.6 dbfs f in = 20 mhz 61.6 dbfs sndr signal to noise and distortion ratio f in = 2 mhz 61.7 dbfs f in = 8 mhz 60 61.6 dbfs f in @ fs/2 60.5 dbfs f in = 20 mhz 61.6 dbfs sfdr spurious free dynamic range f in = 2 mhz 80 dbc f in = 8 mhz 70 81 dbc f in @ fs/2 70 dbc f in = 20 mhz 80 dbc hd2 second order harmonic distortion f in = 2 mhz -90 dbc f in = 8 mhz -80 -90 dbc f in @ fs/2 -90 dbc f in = 20 mhz -90 dbc hd3 third order harmonic distortion f in = 2 mhz -80 dbc f in = 8 mhz -70 -81 dbc f in @ fs/2 -70 dbc f in = 20 mhz -80 dbc enob effective number of bits f in = 2 mhz 10.0 bits f in = 8 mhz 9.7 9.9 bits f in @ fs/2 9.8 bits f in = 20 mhz 9.9 bits crosstalk signal crosstalk between channels, f in1 =8mhz, f in0 =9.9mhz -105 db power supply analog supply current 8.2 ma digital supply current digital core supply 1.7 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 2.8 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 2.3 ma analog power 14.8 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 8.8 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 23.6 mw power down 9.9 w sleep mode 1 power dissipation, sleep mode one channel 15.2 m w sleep mode 2 power dissipation, sleep mode both channels 7.7 mw clock inputs max. conversion rate 20 msps min. conversion rate 3 msps asd0400 rev v3.2 , 2010.04.23 confidential page 4 of 16
product specification asd0400 l40 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 2 mhz 61.6 dbfs f in = 8 mhz 60.0 61.6 dbfs f in @ fs/2 61.6 dbfs f in = 30 mhz 61.5 dbfs sndr signal to noise and distortion ratio f in = 2 mhz 61.6 dbfs f in = 8 mhz 60.0 61.6 dbfs f in @ fs/2 61.2 dbfs f in = 30 mhz 61.4 dbfs sfdr spurious free dynamic range f in = 2 mhz 80 dbc f in = 8 mhz 70 81 dbc f in @ fs/2 72 dbc f in = 30 mhz 80 dbc hd2 second order harmonic distortion f in = 2 mhz -90 dbc f in = 8 mhz -80 -90 dbc f in @ fs/2 -85 dbc f in = 30 mhz -85 dbc hd3 third order harmonic distortion f in = 2 mhz -80 dbc f in = 8 mhz -70 -81 dbc f in @ fs/2 -72 dbc f in = 30 mhz -80 dbc enob effective number of bits f in = 2 mhz 9.9 bits f in = 8 mhz 9.7 9.9 bits f in @ fs/2 9.9 bits f in = 30 mhz 9.9 bits crosstalk signal crosstalk between channels, f in1 =8mhz, f in0 =9.9mhz -100 db power supply analog supply current 14.4 ma digital supply current digital core supply 3.4 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 5.1 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 4.2 ma analog power 25.9 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 16.6 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 42.5 mw power down 9.7 w sleep mode 1 power dissipation, sleep mode one channel 25.7 m w sleep mode 2 power dissipation, sleep mode both channels 11.3 mw clock inputs max. conversion rate 40 msps min. conversion rate 20 msps asd0400 rev v3.2 , 2010.04.23 confidential page 5 of 16
product specification asd0400 l65 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 8 mhz 60.0 61.6 dbfs f in = 20 mhz 61.6 dbfs f in @ fs/2 61.5 dbfs f in = 40 mhz 61.3 dbfs sndr signal to noise and distortion ratio f in = 8 mhz 60.0 61.6 dbfs f in = 20 mhz 61.6 dbfs f in @ fs/2 60.4 dbfs f in = 40 mhz 61.1 dbfs sfdr spurious free dynamic range f in = 8 mhz 70 77 dbc f in = 20 mhz 77 dbc f in @ fs/2 70 dbc f in = 40 mhz 75 dbc hd2 second order harmonic distortion f in = 8 mhz -80 -90 dbc f in = 20 mhz -95 dbc f in @ fs/2 -85 dbc f in = 40 mhz -90 dbc hd3 third order harmonic distortion f in = 8 mhz -70 -77 dbc f in = 20 mhz -77 dbc f in @ fs/2 -70 dbc f in = 40 mhz -75 dbc enob effective number of bits f in = 8 mhz 9.7 9.9 bits f in = 20 mhz 9.9 bits f in @ fs/2 9.7 bits f in = 40 mhz 9.9 bits crosstalk signal crosstalk between channels, f in1 =8mhz, f in0 =9.9mhz -97 db power supply analog supply current 22.0 ma digital supply current digital core supply 5.2 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 7.9 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 6.4 ma analog power 39.6 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 25.4 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 65.0 mw power down 9.3 w sleep mode 1 power dissipation, sleep mode one channel 38.2 m w sleep mode 2 power dissipation, sleep mode both channels 15.7 mw clock inputs max. conversion rate 65 msps min. conversion rate 40 msps asd0400 rev v3.2 , 2010.04.23 confidential page 6 of 16
product specification asd0400 l80 avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, fs=80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, unless otherwise noted. parameter condition min typ max unit performance snr signal to noise ratio f in = 8 mhz 60.0 61.6 dbfs f in = 20 mhz 61.2 dbfs f in = 30 mhz 61.3 dbfs f in @ fs/2 61.3 dbfs sndr signal to noise and distortion ratio f in = 8 mhz 60.0 61.3 dbfs f in = 20 mhz 60.7 dbfs f in = 30 mhz 61.0 dbfs f in @ fs/2 59.0 dbfs sfdr spurious free dynamic range f in = 8 mhz 70 75 dbc f in = 20 mhz 75 dbc f in = 30 mhz 75 dbc f in @ fs/2 65 dbc hd2 second order harmonic distortion f in = 8 mhz -80 -90 dbc f in = 20 mhz -95 dbc f in = 30 mhz -90 dbc f in @ fs/2 -80 dbc hd3 third order harmonic distortion f in = 8 mhz -70 -75 dbc f in = 20 mhz -75 dbc f in = 30 mhz -75 dbc f in @ fs/2 -65 dbc enob effective number of bits f in = 8 mhz 9.7 9.9 bits f in = 20 mhz 9.8 bits f in = 30 mhz 9.8 bits f in @ fs/2 9.5 bits crosstalk signal crosstalk between channels, f in1 =8mhz, f in0 =9.9mhz -95.0 db power supply analog supply current 26.5 ma digital supply current digital core supply 6.1 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext enabled 9.5 ma output driver supply 2.5v output driver supply, sine wave input, f in = 1 mhz, ck_ext disabled 7.6 ma analog power 47.7 mw digital power ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 30.0 mw total power dissipation ovdd = 2.5v, 5pf load on output bits, f in = 1 mhz, ck_ext disabled 77.7 mw power down 9.1 w sleep mode 1 power dissipation, sleep mode one channel 46.1 m w sleep mode 2 power dissipation, sleep mode both channels 18.3 mw clock inputs max. conversion rate 80 msps min. conversion rate 65 msps asd0400 rev v3.2 , 2010.04.23 confidential page 7 of 16
product specification digital and timing specifications avdd=1.8v, dvdd=1.8v, dvddck=1.8v, ovdd=2.5v, conversion rate: max specified, 50% clock duty cycle, -1dbfs input signal, 5 pf capacitive load on data outputs, unless otherwise noted parameter condition min typ max unit clock inputs duty cycle 20 80 % high compliance cmos, lvds, lvpecl, sine wave input range differential input swing 0.4 vpp input range differential input swing, sine wave clock input 1.6 vpp input common mode voltage keep voltages within ground and voltage of ovdd 0.3 v ovdd -0.3 v input capacitance differential 2 pf timing t pd start up time from power down mode to active mode 900 clock cycles t slp start up time from sleep mode to active mode 20 clock cyles t ovr out of range recovery time 1 clock cycles t ap aperture delay 0.8 ns ? rms aperture jitter < 0.5 ps t lat pipeline delay 12 clock cycles t d output delay (see timing diagram). 5pf load on output bits 3.0 10.0 ns t dc output delay relative to ck_ext (see timing diagram) 1.0 6.0 ns logic inputs v hi high level input voltage. v ovdd 3.0v 2 v v hi high level input voltage. v ovdd = 1.7v C 3.0v 0.8 v ovdd v v li low level input voltage. v ovdd 3.0v 0 0.8 v v li low level input voltage. v ovdd = 1.7v C 3.0v 0 0.2 v ovdd v i hi high level input leakage current +/-10 a i li low level input leakage current +/-10 a c i input capacitance 3 pf logic outputs v ho high level output voltage v ovdd -0.1 v v lo low level output voltage 0.1 v c l max capacitive load. post-driver supply voltage equal to pre-driver supply voltagev ovdd = v ocvdd 5 pf c l max capacitive load. post-driver supply voltage above 2.25v (1) 10 pf (1) the outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum asd0400 rev v3.2 , 2010.04.23 confidential page 8 of 16
product specification timing diagram analog input clock input data output n-1 n n+1 n+2 n+3 n+4 n+5 n-13 n-12 n-11 n-10 n-9 n-8 t d t ap ck_ext t dc figure 2 : timing diagram absolute maximum ratings absolute maximum ratings are limiting values to be applied for short periods of time. exposure to absolute maximum rating conditions for an extended period of time may reduce device lifetime. table 1 : pin pin rating avdd avss -0.3v to +2.3v dvdd dvss -0.3v to +2.3v avss, dvssck, dvss, ovss dvss -0.3v to +0.3v ovdd ovss -0.3v to +3.9v ipx, inx, analog inputs and outputs avss -0.3v to +2.3v digital outputs ovss -0.3v to +3.9v ckp, ckn dvssck -0.3v to +3.9v digital inputs ovss -0.3v to +3.9v operating temperature -40 to +85 o c storage temperature -60 to +150 o c soldering profile qualification j-std-020 this device can be damaged by esd. even though this product is protected with state- of-the-art esd protection circuitry, damage may occur if the device is not handled with appropriate precautions. esd damage may range from device failure to performance degradation. analog circuitry may be more susceptible to damage as very small parametric changes can result in specification incompliance. asd0400 rev v3.2 , 2010.04.23 confidential page 9 of 16
product specification pin configuration and description 6 4 6 3 6 2 6 0 5 9 6 1 5 7 5 6 5 8 5 4 5 3 5 5 5 1 5 0 5 2 4 9 48 47 46 44 43 45 41 40 42 38 37 39 35 34 36 33 1 2 3 5 6 4 8 9 7 11 12 10 14 15 13 16 1 7 1 8 1 9 2 1 2 2 2 0 2 4 2 5 2 3 2 7 2 8 2 6 3 0 3 1 2 9 3 2 pin 0, exposed pad for thermal heat sink (bottom of package) pin 1 label d v s s s l p _ n _ 0 s l p _ n _ 1 c m _ e x t b c _ 1 o e _ n _ 0 c m _ e x t b c _ 0 d 0 _ 9 d 0 _ 8 o r n g _ 0 d 0 _ 6 o v s s d 0 _ 7 d 0 _ 5 d 0 _ 4 o v d d d 0 _ 3 d0_2 d0_1 d0_0 nc nc nc ovdd ovss ck_ext d1_9 d1_8 orng_1 d1_6 d1_5 d1_7 d1_4 d v s s d v d d c k _ e x t _ e n p d _ n o e _ n _ 1 d f r m t n c n c d v d d d 1 _ 0 o v s s n c d 1 _ 1 d 1 _ 2 o v d d d 1 _ 3 dvdd cm_ext avdd avss ip0 avss avss avdd in0 in1 avdd ip1 dvddck ckp dvssck ckn figure 3 : package drawing, qfn 64-pin table 2 : pin function pin # name description 1, 18, 23 dvdd digital and i/o-ring pre driver supply voltage, 1.8v 2 cm_ext common mode voltage output 3, 9, 12 avdd analog supply voltage, 1.8v 4, 5, 8 avss analog ground 6, 7 ip0, in0 analog input channel 0 (non-inverting, inverting) 10, 11 ip1, in1 analog input channel 1 (non-inverting, inverting) 13 dvssck clock circuitry ground 14 dvddck clock circuitry supply voltage, 1.8v 15 ckp clock input, non-inverting (format: lvds, lvpecl, cmos/ttl, sine wave) 16 ckn clock input, inverting. for cmos input on ckp, connect ckn to ground. 17, 64 dvss digital circuitry ground 19 ck_ext_en ck_ext signal enabled when low (zero). tristate when high. 20 dfrmt data format selection. 0: offset binary, 1: two's complement 21 pd_n full chip power down mode when low. all digital outputs reset to zero. after chip power up always apply power down mode before using active mode to reset chip. 22 oe_n_1 output enable channel 0. tristate when high asd0400 rev v3.2 , 2010.04.23 confidential page 10 of 16
product specification 24, 41, 58 ovdd i/o ring post-driver supply voltage. voltage range 1.7 to 3.6v 25, 40, 57 ovss ground for i/o ring 26 nc 27 nc 28 nc 29 d1_0 output data channel 1 (lsb) 30 d1_1 output data channel 1 31 d1_2 output data channel 1 32 d1_3 output data channel 1 33 d1_4 output data channel 1 34 d1_5 output data channel 1 35 d1_6 output data channel 1 36 d1_7 output data channel 1 37 d1_8 output data channel 1 38 d1_9 output data channel 1 (msb) 39 orng_1 out of range flag channel 1. high when input signal is out of range 42 ck_ext output clock signal for data synchronization. cmos levels 43 nc 44 nc 45 nc 46 d0_0 output data channel 0 (lsb) 47 d0_1 output data channel 0 48 d0_2 output data channel 0 49 d0_3 output data channel 0 50 d0_4 output data channel 0 51 d0_5 output data channel 0 52 d0_6 output data channel 0 53 d0_7 output data channel 0 54 d0_8 output data channel 0 55 d0_9 output data channel 0 (msb) 56 orng_0 out of range flag channel 0. high when input signal is out of range 59 oe_n_0 output enable channel 0. tristate when high 60, 61 cm_extbc_1, cm_extbc_0 bias control bits for the buffer driving pin cm_ext 00: off 01: 50ua 10: 500ua 11: 1ma 62, 63 slp_n_1, slp_n_0 sleep mode 00: sleep mode 01: channel 0 active 10: channel 1 active 11: both channels active recommended usage analog input the analog inputs to the asd0400 is a switched capacitor track-and-hold amplifier optimized for differential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. the cm_ext pin provides a voltage suitable as common mode voltage reference. the internal buffer for the cm_ext voltage can be switched off, and driving capabilities can be changed by using the cm_extbc control input. figure 4 shows a simplified drawing of the input network. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic asd0400 rev v3.2 , 2010.04.23 confidential page 11 of 16
product specification charging currents and may improve performance. the resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. track track track track hold hold inx ipx 2.1 pf 2.1 pf figure 4 : input configuration dc-coupling figure 5 shows a recommended configuration for dc- coupling. note that the common mode input voltage must be controlled according to specified values. preferably, the cm_ext output should be used as reference to set the common mode voltage. the input amplifier could be inside a companion chip or it could be a dedicated amplifier. several suitable single ended to differential driver amplifiers exist in the market. the system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the asd0400 input specifications. detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 5 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 6 shows a recommended configuration using a transformer. make figure 6 : transformer coupled input sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. this type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in figure 8 can be used. figure 7 shows ac-coupling using capacitors. resistors from the cm_ext output, r cm , should be used to bias the differential input signals to the correct voltage. the series capacitor, c i , form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. note that startup time from sleep mode and power down mode will be affected by this filter as the time asd0400 rev v3.2 , 2010.04.23 confidential page 12 of 16 figure 7 : ac coupled input ipx inx cm_ext 22 22 22 pf c i c i r cm r cm innx inpx figure 5 : dc coupled input with buffer ipx inx cm_ext input input amplifier 43 43 33 pf ipx inx cm_ext input 33 33 r t 47
product specification required to charge the series capacitors is dependent on the filter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of figure 8 can be used. the configuration in figure 8 is designed to figure 8 : alternative input network attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below nyquist. values of the series inductor will however depend on board design and conversion rate. in some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. this capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in the asd0400 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally. hence a wide common mode voltage range is accepted. differential clock sources as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the ckn pin should be connected to ground, and the cmos clock signal should be connected to ckp. for differential sine wave clock, the input amplitude must be at least +/- 800 mvpp. the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1 , snr jitter = 20 ? log 2 ? ? f in ? t ( 1 ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented on parallel cmos form. the voltage on the ovdd pin set the levels of the cmos outputs. the output drivers are dimensioned to drive a wide range of loads for ovdd above 2.25v, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. in applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the adc chip. the timing is described in the timing diagram section. note that the load or equivalent delay on ck_ext always should be lower than the load on data outputs to ensure sufficient timing margins. the digital outputs can be set in tristate mode by setting the oe_n signal high. the asd0400 employs digital offset correction. this means that the output code will be 4096 with shorted inputs. however, small mismatches in parasitics at the input can cause this to alter slightly. the offset correction also results in possible loss of codes at the edges of the full scale range. with no offset correction, the adc would clip in one end before the other, in practice resulting in code loss at the opposite end. with the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. when out of range flags are set, the code is forced to all ones for overrange and all zeros for underrange. data format selection the output data are presented on offset binary form when dfrmt is low (connect to ovss). setting dfrmt high (connect to ovdd) results in 2's complement output format. details are shown in table 3 . asd0400 rev v3.2 , 2010.04.23 confidential page 13 of 16 ipx inx cm_ext input 1:1 r t 68 120nh 120nh 33 33 220 22pf optional
product specification table 3 : data format description for 2vpp full scale range differential input voltage (ipx - inx) output data: dx_9 : dx_0 (dfrmt = 0, offset binary) output data: dx_9 : dx_0 (dfrmt = 1, 2's complement) 1.0 v 11 1111 1111 01 1111 1111 +0.24mv 10 0000 0000 00 0000 0000 -0.24mv 01 1111 1111 11 1111 1111 -1.0v 00 0000 0000 10 0000 0000 reference voltages the reference voltages are internally generated and buffered based on a bandgap voltage reference. no external decoupling is necessary, and the reference voltages are not available externally. this simplifies usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. operational modes the operational modes are controlled with the pd_n and slp_n pins. if pd_n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leakage current contributes to the power down dissipation. the startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. the slp_n bus can be used to power down each channel independently, or to set the full chip in sleep mode. in this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. however, sleep mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. the input clock should be kept running in all idle modes. however, even lower power dissipation is possible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to enabling active mode. startup initialization the asd0400 must be reset prior to normal operation. this is required every time the power supply voltage has been switched off. a reset is performed by applying power down mode. wait until a stable supply voltage has been reached, and pull the pd_n pin for the duration of at least one clock cycle. the input clock must be running continuously during this power down period and until active operation is reached. alternatively the pd pin can be kept low during power-up, and then be set high when the power supply voltage is stable. asd0400 rev v3.2 , 2010.04.23 confidential page 14 of 16
product specification package mechanical data qfn64 e 1.14 f a2 a3 1 b d d2 d 1 d d 2 a pin 1 id dia 0.20 a1 l g pin 0, exposed pad bottom view pin 1 id (top side) dia 0.50 0.45 1 64 16 17 32 33 48 49 1.14 figure 9 : qfn 64 package dimensions (millimeter unless otherwise noted) table 4 : dimensions millimeter inch symbol min typ max min typ max a 0.9 0.035 a1 0.00 0.01 0.05 0.00 0.0004 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 ref 0.008 ref b 0.2 0.25 0.3 0.008 0.010 0.012 d 9.00 bsc 0.354 bsc d1 8.75 bsc 0.344 bsc d2 3.79 3.99 4.19 0.149 0.157 0.165 l 0.3 0.4 0.5 0.012 0.016 0.020 e 0.50 bsc 0.020 bsc 1 0 12 0 12 f 1.9 0.075 g 0.24 0.42 0.6 0.0096 0.0168 0.024 asd0400 rev v3.2 , 2010.04.23 confidential page 15 of 16
product specification product information product status datasheet revision date asd0400 product specification v3.2 2010.04.23 ordering information ordering code temp. range package type package drawing msl, peak temp (1) transport media asd0400 l20-inr -40 to +85 c 64 pin qfn qfn64 level 2a tape and reel asd0400 l40-inr -40 to +85 c 64 pin qfn qfn64 level 2a tape and reel asd0400 l65-inr -40 to +85 c 64 pin qfn qfn64 level 2a tape and reel asd0400 l80-inr -40 to +85 c 64 pin qfn qfn64 level 2a tape and reel asd0400 l20-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd0400 l40-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd0400 l65-int -40 to +85 c 64 pin qfn qfn64 level 2a tray asd0400 l80-int -40 to +85 c 64 pin qfn qfn64 level 2a tray (1) msl, peak temp: the moisture sensitivity level rating classified according to the jedec industry standard and to peak solder temperature. datasheet status objective product specification: the values and functionality describe design targets only. specifications and functionality can be changed without notice preliminary product specification: the specifications are based on initial design results. specifications and functionality can be changed without notice. product specification: information is current as of publication data. products conform to specifications according to the terms of arctic silicon devices as standard warranty. production does not necessarily require all parameters to be tested. arctic silicon devices as vestre rosten 81 n-7075 tiller norway tel: +47 73 10 29 00 fax: +47 73 10 29 19 information provided in this document is believed to be accurate and reliable. however, no responsibility is assumed by arctic silicon devices as for its use. neither is any responsibility assumed for any infringement of patents or other third party rights that may result from the use of the product or information described herein. no license is implicitly or otherwise granted under any patent or patent right of arctic silicon devices as. arctic silicon devices as specifically disclaims any and all liability, including without limitation incidental or consequential damages. it is the responsibility of the user to ensure that in all respects the application in which arctic silicon devices as products are used is suited to the purpose of the end user. life support applications : products of arctic silicon devices as (asd) are not designed for use in life support appliances, devices or systems, where malfunction can result in personal injury. customers using or selling asd products for use in such applications do so at their own risk and agree to fully indemnify asd for any damages resulting from such improper use or sale. all rights reserved ?. reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. asd0400 rev v3.2 , 2010.04.23 confidential page 16 of 16 template rev. date: 2007.10.03

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