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publication# 080127 rev: f amendment: / 0 issue date: october 1999 am7942 subscriber line interface circuit distinctive characteristics programmable constant-current feed receive current gain = 200 programmable loop-detect threshold low standby power performs polarity reversal ground-key detector pin for external ground-key noise filter capacitor test relay driver option tip open state for ground-start lines ?19 v to ?58 v battery operation ideal for pbx and kts applications on-chip switching regulator for low-power dissipation can be used with or without the on-chip switching regulator two-wire impedance set by single external impedance on-hook transmission block diagram vtx vreg vbat 15474a-001 signal transmission input decoder and control ground-key detector ring relay driver test relay driver c1 c2 c3 c4 e1 gkfil rsn off-hook detector power-feed controller ring-trip detector switching regulator testout ringout rd rdc l two-wire a(tip) hpa hpb b(ring) bgnd da db chs chclk vcc vee agnd/dgnd cas det qbat interface
2 am7942 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am7942 j performance grade blank = standard specification ?1 = performance grading ?2 = performance grading temperature range c=commercial (0 c to 70 c)* package type j = 32-pin plastic leaded chip carrier (pl 032) subscriber line interface circuit valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on legerity?s standard military?grade products. c device number/description am7942 note: * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ?40 c to +85 c is guar- anteed by characterization and periodic sampling of production units. valid combinations am7942 ?1 ?2 jc
slic products 3 connection diagrams top view notes: 1. pin 1 is marked for orientation. 2. tp is a thermal conduction pin tied to substrate (qbat). tp testout l c4 vbat qbat chs chclk e1 ringout bgnd b(ring) a(tip) db gkfil 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 c1 c3 c2 tp agnd/dgnd det da rd hpb hpa vtx vee rsn 32-pin plcc cas rdc vreg vcc
4 am7942 data sheet pin descriptions notes: 1. all pins, except chclk, connect to vbat when using slic without a switching regulator. chclk is connected to agnd/ dgnd. 2. to prevent noise pickup by the detection circuits when using ground-key detect state (e1 = logical 1), a 3300 pf minimum bypass capacitor is recommended between the gkfil pin and ground. pin names type description agnd/dgnd gnd analog and digital ground. a(tip) output output of a(tip) power amplifier. bgnd gnd battery (power) ground. b(ring) output output of b(ring) power amplifier. c3 ? c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. c4 input test relay driver command. ttl compatible. a logic low enables the driver. cas capacitor anti-saturation pin for capacitor to filter reference voltage when operating in anti-saturation region. chclk input chopper clock. input to switching regulator (ttl compatible). freq = 256 khz (typ). see note 1. chs input chopper stabilization. (see note 1) connection for external chopper stabilizing components. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output switchhook detector. when enabled, a logic low indicates the selected detector is tripped. the detector is selected by the logic inputs (c3 ? c1, e1). the output is open-collector with a built-in 15 k ? pull-up resistor. e1 input ground-key enable. e1 = high connects the ground-key detector to det . e1 = low connects the off-hook or ring-trip detector to det . gkfil ? connection for external ground-key, noise-filter capacitor. see note 2. hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. l output (see note 1) switching regulator power transistor. connection point for filter inductor and anode of switching regulator power transistor. connection point for filter inductor and anode of catch diode. has up to 60 v of pulse waveform on it and must be isolated from sensitive circuits. keep the diode connections short because of the high currents and high di/dt. qbat battery quiet battery. (see note 1). filtered battery supply for the signal processing circuits. rd resistor detector resistor. detector threshold set and filter pin. rdc resistor dc feed resistor. connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). ringout output ring relay driver. open-collector driver with emitter internally connected to bgnd. rsn input receive summing node. the metallic current (ac and dc) between a(tip) and b(ring) is equal to 500 x the current into this pin. the networks that program receive gain, two-wire impedance, and feed current all connect to this node. testout output test relay driver. open collector driver with emitter internally connected to bgnd. tp thermal thermal pin. connection for heat dissipation. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. vbat battery battery supply. vcc power +5 v power supply. vee power ? 5 v power supply. vreg input regulated voltage. (see note 1.) provides negative power supply for power amplifiers. connection point for inductor, filter capacitor, and chopper stabilization. vtx output transmit audio. this output is a unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
slic products 5 absolute maximum ratings storage temperature . . . . . . . . . . . . ? 55 c to +150 c v cc with respect to agnd/dgnd . . . ? 0.4 v to +7.0 v v ee with respect to agnd/dgnd . . .+0.4 v to ? 7.0 v v bat with respect to agnd/dgnd . . . +0.4 v to ? 70 v note: rise time of v bat (dv/dt) must be limited to 27 v/ s or less when q bat bypass = 0.33 f. bgnd with respect to agnd/dgnd .+1.0 v to ? 3.0 v a(tip) or b(ring) to bgnd: continuous . . . . . . . . . . . . . . . . . . ? 70 v to +1.0 v 10 ms (f = 0.1 hz) . . . . . . . . . . . . . ? 70 v to +5.0 v 1 s (f = 0.1 hz) . . . . . . . . . . . . . . . ? 90 v to +10 v 250 ns (f = 0.1 hz) . . . . . . . . . . . . ? 120 v to +15 v current from a(tip) or b(ring) . . . . . . . . . . . . 150 ma voltage on ringout. . . . .bgnd to 70 v above q bat voltage on testout. . . . .bgnd to 70 v above q bat current through relay drivers . . . . . . . . . . . . . . 60 ma voltage on ring-trip inputs (da and db) . . . . . . . . . . . . . . . . . . . . . v bat to 0 v current into ring-trip inputs . . . . . . . . . . . . . . . . . 10 ma peak current into regulator switch (l pin). . . . . . . . . . . . . . . . . . . . . . . 150 ma switcher transient peak off voltage on l pin. . . . . . . . . . . . . . . . . . . . . . +1.0 v c4 ? c1, e1, chclk to agnd/dgnd . . . . . . . . . . . . ? 0.4 v to v cc + 0.4 v maximum power dissipation, t a (see note) . . . . .70 c in 32-pin plcc package. . . . . . . . . . . . . . . 1.74 w note: thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more information. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature . . . . . . . . . . . . . . 0 c to +70 c* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 v to 5.25 v v ee . . . . . . . . . . . . . . . . . . . . . . . . ? 4.75 v to ? 5.25 v v bat . . . . . . . . . . . . . . . . . . . . . . . . . . ? 19 v to ? 58 v agnd/dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v bgnd with respect to agnd/dgnd . . . . . . . . . . . . ? 100 mv to +100 mv load resistance on vtx to ground . . . . . . 10 k ? min the operating ranges define those limits between which the functionality of the device is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units. can be used without switching regulator components in this range of battery voltages, provided maximum power dissipation specifications are not exceeded.
6 am7942 data sheet electrical characteristics description test conditions (see note 1) min typ max unit note analog (v tx ) output impedance 3 ? 4 analog (v tx ) output offset 0 c to +70 c ? 1* ? 2 ? 35 ? 35 ? 30 +35 +35 +30 mv ? 40 c to +85 c ? 1* ? 2 ? 40 ? 40 ? 35 +40 +40 +35 4 analog (rsn) input impedance 300 hz to 3.4 khz 1 20 ? longitudinal impedance at a or b 35 overload level 4-wire 2-wire ? 2.5 +2.5 vpk 2 transmission performance, 2-wire impedance (see test circuit d) 2-wire return loss 300 hz to 3400 hz 26 db 4, 10 longitudinal balance (2-wire and 4-wire, see test circuit c); r l = 600 ? longitudinal to metallic l-t, l-4 200 hz to 1 khz normal polarity 0 c to +70 c normal polarity ? 40 c to +85 c reverse polarity 52 63 58 54 db 1, 2 1, 2, 4 1, 2 1 khz to 3.4 khz normal polarity 0 c to +70 c normal polarity ? 40 c to +85 c reverse polarity 52 58 54 54 1, 2 1, 2, 4 1, 2 longitudinal signal generation 4-l 300 hz to 800 hz ? 1* reverse polarity ? 2 40 40 42 longitudinal current capability per wire active state all* oht state all 28 18 marms insertion loss (2- to 4-wire and 4- to 2-wire, see test circuits a and b) bat = ? 48 v, r ldc = r lac = 600 ? ; bat = ? 24 v, r ldc = 300 ? , r lac = 600 ? gain accuracy 0 dbm, 1 khz 0 c to +70 c ? 1* ? 2 ? 0.15 ? 0.15 ? 0.10 +0.15 +0.15 +0.10 db 0 dbm, 1 khz ? 40 c to +85 c ? 1* ? 2 ? 0.20 ? 0.20 ? 0.15 +0.20 +0.20 +0.15 ? 4 ? variation with frequency 300 hz to 3400 hz relative to 1 khz ? 1* 0 c to +70 c ? 2 ? 0.15 ? 0.15 ? 0.10 +0.15 +0.15 +0.10 300 hz to 3400 hz relative to 1 khz ? 1* ? 40 c to +85 c ? 2 ? 0.20 ? 0.20 ? 0.15 +0.20 +0.20 +0.15 ? ? 4 note: *p.g. = performance grade
slic products 7 gain tracking 0 c to +70 c +7 dbm to ? 55 dbm reference: ? 0 dbm ? 0.10 +0.10 db ? 40 c to +85 c +7 dbm to ? 55 dbm reference: ? 0 dbm ? 0.15 +0.15 4 4 ? balance return signal (4- to 4-wire, see test circuit b) bat = ? 48 v, r ldc = r lac = 600 ? ; bat = ? 24 v, r ldc = 300 ? , r lac = 600 ? gain accuracy 0 dbm, 1 khz 0 c to +70 c ? 1* ? 2 ? 0.15 ? 0.15 ? 0.10 +0.15 +0.15 +0.10 db ? 3 ? 0 dbm, 1 khz ? 40 c to +85 c ? 1* ? 2 ? 0.20 ? 0.20 ? 0.15 +0.20 +0.20 +0.15 ? 3, 4 3, 4 variation with frequency 300 hz to 3400 hz relative to 1 khz 0 c to +70 c ? 0.10 +0.10 3 300 hz to 3400 hz relative to 1 khz ? 40 c to +85 c ? 0.15 +0.15 3 3 3, 4 gain tracking 0 c to +70 c +3 dbm to ? 55 dbm reference: 0 dbm ? 0.10 +0.10 3 ? 40 c to +85 c +3 dbm to ? 55 dbm reference: 0 dbm ? 0.15 ? 0.15 3, 4 group delay f = 1 khz 5.3 s 4, 12 total harmonic distortion (2- to 4-wire and 4- to 2-wire, see test circuits a and b) bat = ? 48 v, r ldc = r lac = 600 ? harmonic distortion 0 dbm ? 64 ? 50 db 300 hz to 3400 hz +7 dbm ? 55 ? 40 idle channel noise bat = ? 48 v, r ldc = r lac = 600 ? ; bat = ? 24 v, r ldc = 300 ? , r lac = 600 ? c-message weighted noise 2-wire, 0 c to +70 c 2-wire, ? 40 c to +85 c +7 +10 +12 dbrnc 4 4 4-wire, 0 c to +70 c 4-wire, ? 40 c to +85 c +7 +10 +12 4 4 psophometric weighted noise 2-wire, 0 c to +70 c 2-wire, ? 40 c to +85 c ? 83 ? 80 ? 78 dbmp ? 4 4-wire, 0 c to +70 c 4-wire, ? 40 c to +85 c ? 83 ? 80 ? 78 ? 4 note: *p.g. = performance grade electrical characteristics (continued) description test conditions (see note 1) min typ max unit note
8 am7942 data sheet single frequency out-of-band noise (see test circuit e) metallic 4 khz to 9 khz 9 khz to 1 mhz 256 khz and harmonics** ? 76 ? 76 ? 63 dbm 4 4, 5, 8 4, 5 longitudinal 1 khz to 15 khz above 15 khz 256 khz and harmonics** ? 70 ? 85 ? 57 4 4, 5, 8 4, 5 line characteristics (see figures 1a, 1b, 1c) short loops, active state battery = ? 24 v, r ldc = 300 ? battery = ? 43 v, r ldc = 600 ? battery = ? 48 v, r ldc = 600 ? 32.4 35.0 37.6 ma 4, 9 4 ? long loops, active state battery = ? 24 v, r ldc = 640 ? battery = ? 43 v, r ldc = 1300 ? battery = ? 48 v, r ldc = 1900 ? 20.0 23.0 18.0 4, 9 4 ? oht state battery = ? 24 v, r ldc = 600 ? battery = ? 48 v, r ldc = 600 ? 15.5 17.5 19.5 4, 9 ? loop current tip open state, r l = 0 disconnect state, r l = 0 1.0 i l lim (itip and iring) tip and ring shorted to gnd 70 105 power dissipation battery, normal loop polarity on-hook open circuit state battery = ? 24 v, w/o switching reg. battery = ? 48 v, with switching reg. 30 35 75 100 mw 9 ? on-hook oht state battery = ? 24 v, w/o switching reg. battery = ? 48 v, with switching reg. 100 175 135 225 9 ? on-hook active state battery = ? 24 v, w/o switching reg. battery = ? 48 v, with switching reg. 135 180 225 300 9 ? off-hook oht state r l = 50 ? battery = ? 24 v, w/o switching reg. battery = ? 48 v, with switching reg. 500 400 800 750 9 ? off-hook active state r l = 50 ? battery = ? 24 v, w/o switching reg. battery = ? 48 v, with switching reg. 800 800 1100 1000 9 ? supply currents, battery = ? 24 v or ? 48 v v cc on-hook supply current open circuit state oht state active state 3.0 6.0 7.5 4.5 10.0 12.0 ma 9 v ee on-hook supply current open circuit state oht state active state 1.0 2.2 2.7 2.3 3.5 6.0 v bat on-hook supply current open circuit state oht state active state 0.4 3.0 4.0 1.0 5.0 6.0 note: **applies only when switching regulator is used. electrical characteristics (continued) description test conditions (see note 1) min typ max unit note
slic products 9 power supply rejection ratio (v ripple = 50 mvrms) v cc 50 hz to 3.4 khz 3.4 khz to 50 khz 25 22 45 35 db 6 v ee 50 hz to 3.4 khz 3.4 khz to 50 khz 20 10 40 25 v bat 50 hz to 3.4 khz 3.4 khz to 50 khz 27 20 45 40 effective int. resistance cas to gnd 85 170 255 k ? 4 off-hook detector current threshold i det = 365/r d ? 20 +20 % ground-key detector thresholds, active state ground-key resistance threshold battery = ? 24 v, b(ring) to gnd battery = ? 48 v, b(ring) to gnd 1.0 2.0 2.2 5.0 4.5 10.0 k ? 9 ? ground-key current threshold b(ring) to gnd midpoint to gnd 9 9 ma 7 effective internal resistance gkfil to agnd/dgnd 18 36 54 k ? 4 ring-trip detector input bias current ? 5 ? 0.05 a offset voltage source resistance = 0 to 2 m ? ? 50 0 +50 mv 11 logic inputs (c4 ? c1, e0, e1, and chclk) input high voltage 2.0 v input low voltage 0.8 input high current all inputs except e1 ? 75 40 a input high current input e1 ? 75 45 input low current ? 0.4 ma logic output (det ) output low voltage i out = 0.8 ma 0.4 v output high voltage i out = ? 0.1 ma 2.4 relay driver outputs (ringout, testout) on voltage 25 ma sink +1.5 v off leakage v oh = +15 v 100 a electrical characteristics (continued) description test conditions (see note 1) min typ max unit note
10 am7942 data sheet relay driver schematics switching characteristics switching waveforms symbol parameter test conditions temperature range min typ max unit note tgkde e1 low to det high (e0 = 1) e1 low to det low (e0 = 1) ground-key detect state r l open, r g connected (see figure h) 0 c to +70 c ? 40 c to +85 c 0 c to +70 c ? 40 c to +85 c 3.8 4.0 1.1 1.6 s 4 tshde e1 high to det low (e0 = 1) e1 high to det high (e0 = 1) switchhook detect state r l = 600 ? , r g open (see figure g) 0 c to +70 c ? 40 c to +85 c 0 c to +70 c ? 40 c to +85 c 1.2 1.7 3.8 4.0 bgnd ringout testout 15474a-002 bgnd 2 1 0 t a = 70 c t a = 25 c 03060 current into ringout or testout (ma) on voltage at ringout or testout (v) det tgkde tshde tgkde tshde e1 e1 to det 15474a-003 note: all delays measured at 1.4 v levels.
slic products 11 notes: 1. unless otherwise noted, test conditions are bat = ? 48 v, v cc = +5 v, v ee = ? 5 v, r l = 600 ? , c hp = 0.33 f, r dc1 = r dc2 = 7.14 k ? , c dc = 0.47 f, r d = 35.4 k ? , c cas = 0.47 f, no fuse resistors, r t =120 k ? , and r rx = 60 k ? . switching regulator components: l = 1 mh, c fil = 0.47 f (see application circuit). 2. overload level is defined when thd = 1%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes the two-wire ac load impedance matches the programmed impedance. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. for frequencies below 12 khz, these tests are performed with a longitudinal impedance of 90 ? and metallic impedance of 300 ? . for frequencies greater than 12 khz, a longitudinal impedance of 90 ? and a metallic impedance of 135 ? is used. these tests are extremely sensitive to circuit board layout. please refer to application notes for details. 6. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 7. ? midpoint ? is defined as the connection point between two 300 ? series resistors connected between a(tip) and b(ring). 8. fundamental and harmonics from 256 khz switch regulator chopper are not included. 9. for ? 24 v battery, switching regulator is disabled. l, chs, and vreg pins connected to vbat pin; chclk pin connected to agnd/dgnd. 10. assumes the following z t network: 11. tested with 0 ? source impedance. 2 m ? is specified for system design purposes only. 12. group delay can be considerably reduced by using a z t network such as that shown in note 10 above. the network reduces the group delay to less than 2 s. the effect of group delay on linecard performance may be compensated for by using the qslac ? or dslac ? device. table 1. slic decoding det output state c3 c2 c1 two-wire status e1 = 0 e1 = 1 0 000 open circuit ring trip ring trip 1 001 ringing ring trip ring trip 2 010 active loop detector ground key 3 011 on-hook tx (oht) loop detector ground key 4 100 tip open loop detector ? 5 101 reserved loop detector ? 6 110 active polarity reversal loop detector ground key 7 111 oht polarity reversal loop detector ground key vtx rsn 60 k ? 60 k ? 150 pf
12 am7942 data sheet note: *r fuse = 20 ? ? 50 ? , user selectable. table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse re- sistors are r f , and z 2win is the desired 2-wire ac input im- pedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from v rx to the r sn . z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. r d and c d form the network connected from rd to ? 5 v, and i t is the threshold current between on hook and off hook. c cas is the regulator filter capacitor, and f c is the desired filter cut-off frequency. z t 200 z 2win 2r f ? ? () = z rx z l g42 l ------------- 200z t z t 200 z l 2r f + () + ------------------------------------------------- ? = r dc1 r dc2 500 i loop ------------- - = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ------------------------------- - ? = r d 365 i t -------- - c d 0.5 ms r d ---------------- - = , = c cas 1 3.4 10 5 f c ? ----------------------------- =
slic products 13 dc feed characteristics r dc1 + r dc2 = r dc = 14.28 k ? active state oht state notes: 1. constant-current region: active state: oht state: 2. anti-saturation turn-on (active state): a. battery independent: v ab = 35.5 v, (|v bat | > 46.2 v) b. battery tracking: v ab = 1.1 |v bat | ? 15, (|v bat | 46.2 v) v ab = 0.7 |v bat | + 3.5, (|v bat | < 46.2 v) 3. open circuit voltage: active state: v ab = 42.6, (|v bat | > 53 v) v ab = 0.7 |v bat | + 5.89, (|v bat | 53 v) oht state, v ab = 39.1, (|v bat | > 49.8 v) v ab = 0.7 |v bat | + 4.7, (|v bat | 49.8 v) 4. anti-saturation 1 region: active state: oht state: 5. anti-saturation 2 region: active state: oht state: i l 500 r dc ---------- - = i l 250 r dc --------- - = v ab 46.2 i l r dc 70.4 ---------- - ? = v ab 39.1 i l r dc 70.4 ---------- - ? = v ab 0.7 v bat 5.89 i l r dc 210 ---------- - ? + = v ab 0.7 v bat 4.7 i l r dc 210 ---------- - ? + = a. v a ? v b (v ab ) voltage vs. loop current (typical)
14 am7942 data sheet dc feed characteristics (continued) b. loop current vs. load resistance (typical) r dc1 + r dc2 = r dc = 14.28 k ? v bat = 47.3 v feed current programmed by r dc1 and r dc2 15474a-004 a b r l i l a b r dc1 r dc2 rdc c dc slic c. feed programming figure 1. dc feed characteristics rsn
slic products 15 test circuits vtx rsn agnd r t r rx r l 2 v l v ab v ab r l rsn agnd vtx v rx r rx i l2-4 = ? 20 log (v tx / v ab ) a. two- to four-wire insertion loss i l4-2 = ? 20 log (v ab / v rx ) b. four- to two-wire insertion loss and balance return signal vtx rsn agnd r t r rx vrx s2 open, s1 closed: brs = 20 log (v tx / v rx ) slic slic slic slic r l 2 b (ring) a (tip) b (ring) a (tip) r l 2 r l 2 v l s1 v l b (ring) a (tip) s2 1/ c << r l c l-t long. bal. = 20 log (v ab / v l ) l-4 long. bal. = 20 log (v tx / v l ) s2 closed, s1 open: 4-l long. sig. gen. = 20 log (v l / v rx ) c. longitudinal balance r r v m z in z d v s r t r rx b(ring) a (tip) rsn agnd vtx d. two-wire return loss test circuit note: z d is the desired impedance (e.g., the characteristic impedance of the line). r l = ? 20 log (2 v m / v s ) r t
16 am7942 data sheet test circuits (continued) 1/ c << 90 ? e. single-frequency noise slic b(ring) a(tip) 68 ? 68 ? 56 ? c c v n idc s m r l r l r e s e a(tip) b(ring) current feed or ground key f. ground-key detection center point test v cc 6.2 k ? 15 pf e1 a(tip) b(ring) g. loop-detector switching r l = 600 ? h. ground-key switching r g det r g : 2 k ? at v bat = ? 48 v 1 k ? at v bat = ? 24 v a(tip) b(ring)
slic products 17 physical dimensions pl032
18 am7942 data sheet revision summary revision c to revision d minor changes were made to the data sheet style and format to conform to legerity standards. ta b l e 1 ? some information in the table was revised, including the addition of the reserved status. revision d to revision e minor changes were made to the data sheet style and format to conform to legerity standards. in the pin description table, the tp pin description was inserted/changed to: ? thermal pin. connection for heat dissipation. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation." revision e to revision f the physical dimension (pl032) was added to the physical dimensions section. deleted the ceramic dip and plastic dip packages and references to them. updated the pin description table to correct inconsistencies. legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system cost of our customers' products. by combining process, design, systems architecture, and a complete set of software and hardware support tools with unparalleled factory and worldwide field applications support, legerity ensures its customers enjoy a smoother design experience. it is this commitment to our customers that places legerity in a class by itself.
the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with re- spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specificati ons and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intelle ctual property rights is granted by this publication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no li ability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerit y's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 1999 legerity, inc. all rights reserved. trademarks legerity, the legerity logo, and combinations thereof, dslac and qslac are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
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