View SGTL5000XNLA3R2_1139366.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary?subject to change without notice sgtl5000 low power stereo codec with headphone amplifier sgtl5000rm rev. 4 02/2009
freescale are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2008. all rights reserved. preliminary?subject to change without notice information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. document number: sgtl5000rm rev. 4, 02/2009 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 010 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor preliminary?subject to change without notice contents paragraph number title page number 1.0 overview ........................................................................................................ 1 1.1 description...........................................................................................................................1 1.2 benefits and advantages ..................................................................................................... 1 1.3 features .................................................................................................................... ............1 1.3.1 analog inputs............................................................................................................. ......1 1.3.2 analog outputs ................................................................................................................1 1.3.3 digital i/o ............................................................................................................... .........2 1.3.4 integrated digital processing...........................................................................................2 1.3.5 clocking/control .......................................................................................................... ...2 1.3.6 power supplies ............................................................................................................ ....2 1.3.7 package ................................................................................................................... .........2 2.0 electrical specifications ............................................................................... 3 2.1 absolute maximum ratings ................................................................................................3 2.2 recommended operating conditions ..................................................................................3 2.3 timing specifications ....................................................................................................... ...6 2.3.1 power up timing........................................................................................................... ..6 2.3.2 i2c ...................................................................................................................................6 2.3.3 spi....................................................................................................................... .............7 2.3.4 i2s....................................................................................................................... .............8 3.0 power consumption ................................................................................... 10 4.0 pinout & package info ............................................................................... 11 4.1 pinouts - 20- & 32-pin qfn packages ..............................................................................11 4.2 pin descriptions ............................................................................................................ .....12 4.3 packages.................................................................................................................... .........14 5.0 typical connection diagrams.................................................................... 17 5.1 typical connection diagram - 20-pin qfn ......................................................................17 5.2 typical connection diagram - 20-pin qfn - lowest power configuration ....................18 5.3 typical connection diagram - 20-pin qfn - lowest cost configuration .......................19 5.4 typical connection diagram - 32-pin qfn ......................................................................20 5.5 typical connection diagram - 32-pin qfn - lowest power configuration ....................21 5.6 typical connection diagram - 32-pin qfn - lowest cost configuration .......................22 6.0 device description ...................................................................................... 23 6.1 system block diagram w/ signal flow and gain map.....................................................23
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor preliminary?subject to change without notice contents paragraph number title page number 6.2 power .................................................................................................................................24 6.2.1 external power supplies................................................................................................24 6.2.2 internal power supplies .................................................................................................25 6.2.3 power schemes ............................................................................................................. .25 6.3 reset...................................................................................................................................25 6.4 clocking.............................................................................................................................26 6.4.1 synchronous sys_mclk input ...................................................................................26 6.4.2 using the pll - asynchronous sys_mclk input ......................................................26 6.5 audio switch (source select switch)...............................................................................27 6.6 analog input block.......................................................................................................... ..28 6.6.1 line inputs ............................................................................................................... ......28 6.6.2 microphone input .......................................................................................................... 28 6.6.3 adc ...............................................................................................................................28 6.7 analog outputs ..................................................................................................................29 6.7.1 dac ...............................................................................................................................29 6.7.2 headphone ................................................................................................................. ....29 6.7.3 line outputs .............................................................................................................. ....30 6.8 digital input & output...................................................................................................... .30 6.8.1 i2s, left justified and right justified modes................................................................30 6.8.2 pcm mode.................................................................................................................. ...31 6.9 digital audio processing ...................................................................................................3 2 6.9.1 dual input mixer .......................................................................................................... .33 6.9.2 sgtl surround............................................................................................................. .34 6.9.3 sgtl bass enhance ......................................................................................................35 6.9.4 7-band parametric eq / 5-band graphic eq / tone control........................................35 6.9.4.1 7-band parametric eq ...............................................................................................36 6.9.4.2 5-band graphic eq ...................................................................................................37 6.9.4.3 tone control ............................................................................................................ ..37 6.9.5 automatic volume control (avc) ................................................................................37 6.10 control ...............................................................................................................................38 6.10.1 i2c ...................................................................................................................... ...........38 6.10.2 spi...................................................................................................................... ............40 7.0 programming examples ............................................................................. 41 7.1 prototype for reading and writing a register...................................................................41 7.2 chip configuration ............................................................................................................41 7.2.1 initialization ............................................................................................................ .......42 7.2.1.1 chip powerup and supply configurations ................................................................42 7.2.1.2 system mclk and sample clock.............................................................................43 7.2.2 pll configuration......................................................................................................... 43
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor preliminary?subject to change without notice contents paragraph number title page number 7.2.3 input/output routing.....................................................................................................4 4 7.2.4 digital audio processor configuration .........................................................................44 7.2.4.1 dual input mixer .......................................................................................................4 4 7.2.4.2 sgtl surround..........................................................................................................4 5 7.2.4.3 sgtl bass enhance ..................................................................................................45 7.2.4.4 7-band parametric eq / 5-band graphic eq / tone control ...................................45 7.2.4.5 automatic volume control (avc) ............................................................................46 7.2.5 i2s configuration ......................................................................................................... .46 7.2.6 volume control............................................................................................................ ..46 7.3 end-user driven chip configuration.................................................................................47 7.3.1 volume and mute control..............................................................................................47 7.3.2 7-band peq preset selection ........................................................................................47 7.3.3 5-band geq volume change........................................................................................47 7.3.4 tone control - bass and treble change ........................................................................48 7.3.5 sgtl surround on/off .................................................................................................48 7.3.6 bass enhance on/off.....................................................................................................49 7.3.7 automatic volume control (avc) on/off....................................................................50 8.0 register descriptions .................................................................................. 51 8.1 chip_id - address = 0x0000 ...........................................................................................51 8.2 chip_dig_power - address = 0x0002.........................................................................51 8.3 chip_clk_ctrl - address = 0x0004 ...........................................................................52 8.4 chip_i2s_ctrl - address = 0x0006 ..............................................................................52 8.5 chip_sss_ctrl - address = 0x000a............................................................................53 8.6 chip_adcdac_ctrl - address = 0x000e ..................................................................54 8.7 chip_dac_vol - address = 0x0010 .............................................................................55 8.8 chip_pad_strength - address = 0x0014..................................................................56 8.9 chip_ana_adc_ctrl - address = 0x0020 ................................................................57 8.10 chip_ana_hp_ctrl - address = 0x0022....................................................................58 8.11 chip_ana_ctrl - address = 0x0024...........................................................................58 8.12 chip_linreg_ctrl - address = 0x0026.....................................................................59 8.13 chip_ref_ctrl - address = 0x0028 ............................................................................60 8.14 chip_mic_ctrl - address = 0x002a ...........................................................................60 8.15 chip_line_out_ctrl - address = 0x002c ...............................................................61 8.16 chip_line_out_vol - address = 0x002e..................................................................62 8.17 chip_ana_power - address = 0x0030 .......................................................................63 8.18 chip_pll_ctrl - address = 0x0032 ............................................................................64 8.19 chip_clk_top_ctrl - address = 0x0034 ..................................................................65 8.20 chip_ana_status - address = 0x0036.......................................................................66 8.21 chip_ana_test2 - address = 0x003a.........................................................................67
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor preliminary?subject to change without notice contents paragraph number title page number 8.22 chip_short_ctrl - address = 0x003c......................................................................68 8.23 dap_control - address = 0x0100 ..............................................................................69 8.24 dap_peq - address = 0x0102 .........................................................................................69 8.25 dap_bass_enhance - address = 0x0104..................................................................70 8.26 dap_bass_enhance_ctrl - address = 0x0106 .....................................................70 8.27 dap_audio_eq - address = 0x0108.............................................................................71 8.28 dap_sgtl_surround - address = 0x010a ..............................................................71 8.29 dap_filter_coef_access - address = 0x010c......................................................72 8.30 dap_coef_wr_b0_msb - address = 0x010e.............................................................72 8.31 dap_coef_wr_b0_lsb - address = 0x0110 ..............................................................73 8.32 dap_audio_eq_bass_band0 - address = 0x0116 .................................................73 8.33 dap_audio_eq_band1 - address = 0x0118 .............................................................74 8.34 dap_audio_eq_band2 - address = 0x011a ............................................................74 8.35 dap_audio_eq_band3 - address = 0x011c.............................................................74 8.36 dap_audio_eq_treble_band4 - address = 0x011e............................................75 8.37 dap_main_chan - address = 0x0120.........................................................................75 8.38 dap_mix_chan - address = 0x0122............................................................................75 8.39 dap_avc_ctrl - address = 0x0124.............................................................................76 8.40 dap_avc_threshold - address = 0x0126 ...............................................................76 8.41 dap_avc_attack - address = 0x0128 .......................................................................77 8.42 dap_avc_decay - address = 0x012a.........................................................................77 8.43 dap_coef_wr_b1_msb - address = 0x012c ............................................................78 8.44 dap_coef_wr_b1_lsb - address = 0x012e..............................................................78 8.45 dap_coef_wr_b2_msb - address = 0x0130 .............................................................78 8.46 dap_coef_wr_b2_lsb - address = 0x0132 ..............................................................79 8.47 dap_coef_wr_a1_msb - address = 0x0134.............................................................79 8.48 dap_coef_wr_a1_lsb - address = 0x0136 ..............................................................79 8.49 dap_coef_wr_a2_msb - address = 0x0138.............................................................79 8.50 dap_coef_wr_a2_lsb - address = 0x013a .............................................................80 9.0 revision history.......................................................................................... 82
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 1 preliminary?subject to change without notice 1.0 overview 1.1 description the low power stereo codec with headphone amp from freescale is designed to provide a complete audio solution for portable products needing line-in , mic-in, line-out, headphone-out, and digital i/o. deriving it?s architecture from best in class freescale integrated products that are currently on the market, the sgtl5000 is able to achieve ultra low power with very high performance a nd functionality, all in one of the smallest footprints available. target market s include portable media players, gps units and smart phones. features such as capless headphone design a nd an internal pll help lower overall system cost. 1.2 benefits and advantages ? high performance at low power ? 100db snr (-60db input) @ < 9.3 mw ? extremely low power modes ? 98db snr (-60db input) @ < 4 mw (1.62 v vdda, 3.0 v vddio, externally driven 1.2 v vddd) ? small pcb footprint ? 3 mm x 3 mm qfn ? audio processing ? allows for no cost system customization 1.3 features 1.3.1 analog inputs ? stereo line in ? support for external analog input ? codec bypass for low power ?mic ? mic bias provided (5x5mm qfn, 3x3mm qfn ta2) ? programmable mic gain ? adc ? 85db snr (-60db input) and -73db thd+n (vdda=1.8 v) 1.3.2 analog outputs ?line out ? 100db snr (-60db input) and -85db thd+n (vddio=3.3 v) ? hp output
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 2 freescale semiconductor preliminary?subject to change without notice ? 100db snr (-60db input) and -80db thd+n (vdda=1.8 v, 16 ohm load, dac to headphone) ? 45 mw max into 16 ohm load @ 3.3 v ? capless design 1.3.3 digital i/o ? i2s port to allow routing to application processor 1.3.4 integrated digital processing ? sgtl surround, sgtl bass, tone contro l/ parametric equalizer/graphic equalizer 1.3.5 clocking/control ? pll allows input of 8 mhz to 27 mhz system cl ock - standard audio clocks are derived from pll 1.3.6 power supplies ? designed to operate from 1.62 to 3.6 volts 1.3.7 package ? 3mm x 3mm 20 pin qfn ? 5mm x 5mm 32 pin qfn i2s interface headphone / line out w/ volume audio switch adc dac i2s_dout i2s_din i2s_sclk i2s_lrclk l i n e o u t _ r l i n e o u t _ l h p _ r hp_l i2c/spi control sys_mclk pll application processor headphone speaker amp/docking station/fmtx audio processing analog in (stereo line in, mic) linein_r linein_l mic_in mic_bias mp3/fm input mic in /speech recognition i2s interface headphone / line out w/ volume audio switch adc dac i2s_dout i2s_din i2s_sclk i2s_lrclk l i n e o u t _ r l i n e o u t _ l h p _ r hp_l i2c/spi control sys_mclk pll application processor headphone speaker amp/docking station/fmtx audio processing analog in (stereo line in, mic) linein_r linein_l mic_in mic_bias mp3/fm input mic in /speech recognition note: only i 2 c is supported in the 3 mm x 3 mm 20-pin qfn package option.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 3 preliminary?subject to change without notice 2.0 electrical specifications 2.1 absolute maximum ratings exceeding the absolute maximum ratings shown in table 2-1 could cause permanent damage to sgtl5000 and is not recommended. normal operation is not guaranteed at the absolute maximum ratings and extended exposure could affect long term reliability. 2.2 recommended operating conditions . table 2-1. absolute maximum ratings parameter min max unit storage temperature -55 125 c maximum digital voltage vddd 1.98 v maximum digital i/o voltage - vddio 3.6 v maximum analog supply voltage - vdda 3.6 v maximum voltage on any digital input gnd-0.3 vddio+0.3 v maximum voltage on any analog input gnd-0.3 vdda+0.3 v table 2-2. recommended operating conditions parameter symbol/pin(s) min max unit ambient operating temperature ta -40 85 c digital voltage (if supplied externally) vddd 1.1 2.0 v digital i/o voltage vddio 1.62 3.6 v analog output supply vdda 1.62 3.6 v
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 4 freescale semiconductor preliminary?subject to change without notice 2.3 operational specifications table 2-3. audio performance test conditions unless otherwise noted: vddio=1.8v, vdda = 1.8v, ta=25c, slave mode, fs = 48 khz, mclk = 256fs, 24 bit input. parameter min typical max unit line in input level .75 vrms line in input impedance 10 k line in -> adc -> i2s out snr (-60db input) 85 db thd+n -70 db frequency response +/-.11 db channel separation 79 db line in -> headphone_lineout (codec bypass mode) snr (-60db input) 98 db thd+n (10k ohm load) -87 db thd+n (16 ohm load) -87 db frequency response +/-.05 db channel separation (1 khz) 82 db i2s in -> dac -> line out output level .6 vrms snr (-60db input) 95 db thd+n -85 db frequency response +/-.12 db i2s in -> dac -> headphone out - 16 ohm load output power 17 mw snr (-60db input) 100 db thd+n -80 db frequency response +/-.12 db i2s in -> dac -> headphone out - 32 ohm load output power 10 mw snr (-60db input) 95 db thd+n -86 db frequency response +/-.11 db i2s in -> dac -> headphone out - 10k ohm load snr (-60db input) 96 db thd+n -84 db frequency response +/-.11 db psrr (200mvp-p @ 1 khz on vdda) 85 db
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 5 preliminary?subject to change without notice table 2-4. audio performance test conditions unless otherwise noted: vddio=3.3v, vdda =3.3v, ta=25c, slave mode, fs = 48 khz, mclk = 256fs, 24 bit input. adc tests were conducted with refbias = -37.5%, all other tests conducted with refbias = -50% parameter min typical max unit line in input level 1 vrms line in input impedance 10 k line in -> adc -> i2s out snr (-60db input) 90 db thd+n -72 db frequency response +/-.11 db channel separation 80 db line in -> headphone_lineout (codec bypass mode) snr (-60db input) 102 db thd+n (10k ohm load) -89 db thd+n (16 ohm load) -87 db frequency response +/-.05 db channel separation (1 khz) 81 db i2s in -> dac -> line out output level 1 vrms snr (-60db input) 100 db thd+n -88 db frequency response +/-.12 db i2s in -> dac -> headphone out - 16 ohm load output power 58 mw snr (-60db input) 98 db thd+n -86 db frequency response +/-.12 db i2s in -> dac -> headphone out - 32 ohm load output power 30 mw snr (-60db input) 100 db thd+n -88 db frequency response +/-.11 db i2s in -> dac -> headphone out - 10k ohm load snr (-60db input) 97 db thd+n -85 db frequency response +/-.11 db psrr (200mvp-p @ 1 khz on vdda) 89 db
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 6 freescale semiconductor preliminary?subject to change without notice 2.4 timing specifications 2.4.1 power up timing the sgtl5000 has an internal reset that is deasserted 8 sys_mclk cycles after all power rails have been brought up. after this time communication can start. * 1 s represents eight sys_mclk cycles at the minimum 8 mhz sys_mclk. 2.4.2 i2c this section provides timing for the sgtl5000 while in i2c mode (ctrl_mode = =0). table 2-5. power up timing symbol parameter min typical max unit tpc time from all supplies powered up and sys_mclk present to initial communication 1* s table 2-6. i2c bus timing symbol parameter min typical max unit fi2c_clk i2c serial clock frequency 400 khz ti2csh i2c start condition hold time 150 ns ti2cstsu i2c stop condition setup time 150 ns ti2cdsu i2c data input setup time to rising edge of ctrl_clk 125 ns ti2cdh i2c data input hold time from falling edge of ctrl_clk (sgtl5000 receiving data) 5n s ti2cdh i2c data input hold time from falling edge of ctrl_clk (sgtl5000 driving data) 360 ns ti2cclkl i2c ctrl_clk low time 300 ns ti2cclkh i2c ctrl_clk high time 100 ns vdda vddio vddd (if used) sys_mclk tpc ctrl_data ctrl_clk ctrl_adr0_cs initial communication figure 2-1. power up timing
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 7 preliminary?subject to change without notice 2.4.3 spi this section provides timing for the sgtl5000 while in spi mode (ctrl_mode = =1). table 2-7. spi bus timing symbol parameter min typical max unit fspi_clk spi serial clock frequency tbd mhz tspidsu spi data input setup time 10 ns tspidh spi data input hold time 10 ns tspiclkl spi ctrl_clk low time tbd ns tspiclkh spi ctrl_clk high time tbd ns tccs spi clock to chip select 60 ns tcsc spi chip select to clock 20 ns tcsl spi chip select low 20 ns tcsh spi chip select high 20 ns 1/fi2c_clk ti2csh ti2cclkh ti2cclkl ti2cdsu ti2cdh ctrl_clk ctrl_data ti2cstsu figure 2-2. i2c timing (ctrl_mode == 0)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 8 freescale semiconductor preliminary?subject to change without notice 2.4.4 i2s the following are the specifications and timing for i2s port. the timing applies to all formats. ta ble 2-8. symbol parameter min typical max unit flrclk frequency of i2s_lrclk tbd 96 khz fsclk frequency of i2s_sclk 32*flrclk, 64*flrclk khz ti2s_d i2s delay 10 ns ti2s_s i2s setup time 10 ns ti2s_h i2s hold time 10 ns 1/fspi_clk tspidh tspiclkh tspiclkl tspidsu ctrl_clk ctrl_data ctrl_ad0_cs tcsl tcsh tcsc tccs figure 2-3. spi timing
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 9 preliminary?subject to change without notice . 1/fsclk ti2s_s ti2s_d i2s_sclk i2s_lrclk in slave mode i2s_lrclk in master mode ti2s_h ti2s_d i2s_sclk i2s_din i2s_dout ti2s_s i2s_lrclk 1/flrclk figure 2-4. i2s interface timing
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 10 freescale semiconductor preliminary?subject to change without notice 3.0 power consumption vddd derived internally @ 1.2v, slave mode except for pll case, 32 ohm load on hp, conditions: -100db fs signal input, slave mode unless otherwise not ed, paths tested as indicated, unused paths turned off. a further 0.5-1.0mw reduction in power is expected with ta2 silicon. table 3-9. power consumption: vdda=1.8v, vddio=1.8v mode current consumption (ma) power (mw) vddd vdda vddio playback (i2s->dac->headphone) 2.54 .9 6.19 playback with dap ((i2s->dap->dac->headphone) 3.59 .9 8.08 playback/record (i2s->dac->headphone, adc->i2s) 3.71 1.10 8.67 record (adc->i2s) 2.29 1.06 6.02 analog playback, codec bypassed (linein->hp) 1.48 .89 4.27 standby, all analog power off .019 .002 0.038 playback with pll (i2s->dac->hp) 3.01 2.17 9.31 table 3-10. power consumption: vdda=3.3v, vddio=3.3v mode current consumption (ma) power (mw) vddd vdda vddio playback (i2s->dac->headphone) 3.45 .067 11.60 playback with dap ((i2s->dap->dac->headphone) 4.49 .067 15.03 playback/record (i2s->dac->headphone, adc->i2s) 4.67 .343 16.53 record (adc->i2s) 2.90 .296 10.56 analog playback, codec bypassed (linein->hp) 1.91 .039 6.43 standby, all analog power off .04 .002 0.139 playback with pll (i2s->dac->hp) 3.92 2.76 22.05
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 11 preliminary?subject to change without notice 4.0 pinout & package info 4.1 pinouts - 20- & 32-pin qfn packages figure 4-5. sgtl5000 20qfn pinout 20qfn pinout u? sgtl5000_20qfn u? sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 mic_bias 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 u1 sgtl5000_32qfn u1 sgtl5000_32qfn i2s_sclk 24 nc 22 li n ei n _l 14 cpfilt 18 vddio 20 nc 19 sys_mclk 21 i 2 s_dout 2 5 i 2 s_di n 2 6 hp_l 6 ctrl_data 2 7 n c 2 8 ctrl_clk 2 9 gnd 1 nc 8 hp_r 2 gnd 3 vdda 5 li n eout_l 1 2 li n eout_r 11 mic 15 nc 17 li n ei n _r 1 3 agnd 7 i2s_lrclk 23 vddd 3 0 ctrl_adr0_cs 3 1 ctrl_mode 32 hp_vgnd 4 n c 9 vag 10 mic_bias 16 gnd pad figure 4-6. sgtl5000 32qfn pinout
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 12 freescale semiconductor preliminary?subject to change without notice 4.2 pin descriptions table 4-11. 20 pin qfn pinout pin count pin name description notes 1 hp_r right headphone output analog 2 hp_vgnd headphone virtual ground analog 3 vdda analog voltage power 4 hp_l left headphone output analog 5 vag dac vag filter analog 6 lineout_r right line out analog 7 lineout_l left line out analog 8 linein_r right line in analog 9 linein_l left line in analog 10 mic microphone input analog 11 cpfilt charge pump filter analog 12 vddio digital i/o voltage power 13 sys_mclk system master clock digital 14 i2s_lrclk i2s frame clock digital 15 i2s_sclk i2s bit clock digital 16 i2s_dout i2s data output digital 17 i2s_din i2s data input digital 18 ctrl_data i2c mode: serial data (sda); spi mode: serial data input (mosi) digital 19 ctrl_clk i2c mode: serial clock (scl); spi mode: serial clock (sck) digital 20 vddd digital voltage power pad gnd ground. center pad of package is ground connection for part and must be connected to board ground. ground
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 13 preliminary?subject to change without notice table 4-12. 32 pin qfn pinout pin count pin name description notes 1 gnd ground ground 2 hp_r right headphone output analog 3 gnd ground ground 4 hp_vgnd headphone virtual ground analog 5 vdda analog voltage power 6 hp_l left headphone output analog 7 agnd analog ground ground 8 nc no connect digital 9 nc no connect digital 10 vag dac vag filter analog 11 lineout_r right line output analog 12 lineout_l left line output analog 13 linein_r right line input analog 14 linein_l left line input analog 15 mic microphone input analog 16 mic_bias mic bias analog 17 nc no connect - 18 cpfilt charge pump filter analog 19 nc no connect - 20 vddio digital i/o voltage power 21 sys_mclk system master clock digital 22 nc no connect - 23 i2s_lrclk i2s frame clock digital 24 i2s_sclk i2s bit clock digital 25 i2s_dout i2s data output digital 26 i2s_din i2s data input digital 27 ctrl_data i2c mode: serial data (sda); spi mode: serial data input (mosi) digital 28 nc no connect - 29 ctrl_clk i2c mode: serial clock (scl); spi mode: serial clock (sck) digital 30 vddd digital voltage power 31 ctrl_adr0_cs i2c mode: i2c address select 0; spi mode: spi chip select digital 32 ctrl_mode mode select for i2c or spi; when pulled low the control mode is i2c, when pulled high the control mode is spi digital pad gnd this pad should be soldered to ground. this is a suggestion for mechanical stability but is not required electrically. ground
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 14 freescale semiconductor preliminary?subject to change without notice 4.3 packages figure 4-7. sgtl5000 3mmx3mm 20qfn package
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 15 preliminary?subject to change without notice figure 4-8. sgtl5000 5mmx5mm 32qfn package (sheet 1)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 16 freescale semiconductor preliminary?subject to change without notice figure 4-9. sgtl5000 5mmx5mm 32qfn package (sheet 2)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 17 preliminary?subject to change without notice 5.0 typical connection diagrams typical connection diagrams are shown in this section that demonstrate the flexibility of the sgtl5000. both low cost and low power configurations are presented although it should be noted that all configurations offer a low cost design with high performance and low power. some design considerations for sgtl5000 are as follows: ? star the ground pins of the chip, vag ground, and all analog inputs/outputs to a single point, then to the ground plane ? use the widest, shortest trace possible for the hp_vgnd 5.1 typical connection diagram - 20-pin qfn figure 5-10. typical connection diagram - 20-pin qfn vdda (1.62v to 3.6v) vddio (1.62v to 3.6v) line_in_left line_in_right line_out_left line_out_right i2c_clk i2c_data i2s_sclk i2sdout i2s_din i2s_lrclk sys_mclk 20qfn typical connection diagram c? 1uf c? 1uf c? 0.1uf c? 0.1uf r? 2.2k r? 2.2k c? .1uf c? .1uf c? 0.1uf c? 0.1uf j? audio jack j? audio jack 2 5 1 4 3 c? 1uf c? 1uf c? 1uf c? 1uf r? 2.2k r? 2.2k x? mic x? mic 1 2 c? 1uf c? 1uf c? .1uf c? .1uf u? sgtl5000_20qfn u? sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 cpfilt 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 c? .1uf c? .1uf + c? 10uf 6.3v + c? 10uf 6.3v
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 18 freescale semiconductor preliminary?subject to change without notice 5.2 typical connection diagram - 20-pin qfn - lowest power configuration figure 5-11. typical connection diagram - 20-pin qfn - lowest power configuration vddio (=3.1v) vdda (=1.6v) vddd (=1.2v) line_in_left line_in_right line_out_left line_out_right i2c_clk i2c_data i2s_sclk i2sdout i2s_din i2s_lrclk sys_mclk 1. vddd is driven externally by 1.2v supply. 2. vdda is driven at 1.6v 3. vddio is driven at 3.1v c8 0.1uf c8 0.1uf c9 1uf c9 1uf c1 0.1uf c1 0.1uf u1 sgtl5000_20qfn u1 sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 cpfilt 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 + c11 10uf 6.3v + c11 10uf 6.3v j1 audio jack j1 audio jack 2 5 1 4 3 c2 220uf c2 220uf c12 1uf c12 1uf r1 2.2k r1 2.2k x1 mic x1 mic 1 2 c3 220uf c3 220uf c13 1uf c13 1uf c7 .1uf c7 .1uf c4 .1uf c4 .1uf c10 1uf c10 1uf c5 0.1uf c5 0.1uf r2 2.2k r2 2.2k c6 .1uf c6 .1uf
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 19 preliminary?subject to change without notice 5.3 typical connection diagram - 20-pin qfn - lowest cost configuration figure 5-12. typical connection diagram - 20-pin qfn - lowest cost configuration vdd (=3.1v to 3.6v) vdd (=3.1v to 3.6v) line_in_left line_in_right line_out_left line_out_right i2c_clk i2c_data i2s_sclk i2sdout i2s_din i2s_lrclk sys_mclk notes: 1. vddd is derived internally (no need for external cap) 2. vdda and vddio are supplied from same voltage that is between 3.1v and 3.6v. by using the same voltage this allows removal of power decoupling cap. by using a voltage above 3.1v the cap connected to cpfilt can be removed. 3. the above circuit shows a mic bias circuit derived from an external supply (vddio). c1 0.1uf c1 0.1uf r2 2.2k r2 2.2k c2 .1uf c2 .1uf c4 0.1uf c4 0.1uf j1 audio jack j1 audio jack 2 5 1 4 3 c5 1uf c5 1uf c8 1uf c8 1uf r1 2.2k r1 2.2k x1 mic x1 mic 1 2 c9 1uf c9 1uf u1 sgtl5000_20qfn u1 sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 cpfilt 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 c3 .1uf c3 .1uf + c7 10uf 6.3v + c7 10uf 6.3v c6 1uf c6 1uf
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 20 freescale semiconductor preliminary?subject to change without notice 5.4 typical connection diagram - 32-pin qfn figure 5-13. typical connection diagram - 32-pin qfn vddio vdda vddd ctrl_clk 6,7 i2s_sclk 7 ctrl_data 6,7 i2s_din 7 i2s_dout 7 sys_mclk i2s_lrclk 7 line_in_l 4 line_in_r 4 line_out_r 5 line_out_l 5 notes: 1. the above circuit shows vddd (pin 30) being derived internally. for lowest power operation vddd can be driven from an external 1.2v supply with .1uf of decoupling to ground. 2. if both vddio and vdda are below 3v, the cpfilt pin (pin 17) must be connected to a .1uf cap to ground. if either is above 3v, this cap is not needed. 3. the above shows i2c implementation as ctrl_mode (pin 32) is tied to ground). in addition, address 0 of the i2c address is 0 as ctrl_adr0_cs (pin 31) is tied to ground. 4. agnd (pin 7) should be "star" connected to the jack grounds for line in and line out and the ground side of the capacitor tied to vag. this node should via to the ground plane (or connected to ground) at a single point. 32qfn typical connection diagram solder pad to gnd j? audio jack j? audio jack 2 5 1 4 3 c? 0.1uf c? 0.1uf u? sgtl5000_32qfn u? sgtl5000_32qfn i2s_sclk 24 nc 22 linein_l 14 cpfilt 18 vddio 20 nc 19 sys_mclk 21 i2s_dout 25 i2s_din 26 hp_l 6 ctrl_data 27 nc 28 ctrl_clk 29 gnd 1 nc 8 hp_r 2 gnd 3 vdda 5 lineout_l 12 lineout_r 11 mic 15 nc 17 linein_r 13 agnd 7 i2s_lrclk 23 vddd 30 ctrl_adr0_cs 31 ctrl_mode 32 hp_vgnd 4 nc 9 vag 10 mic_bias 16 gnd pad c? 1uf c? 1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 1uf c? 1uf c? 1uf c? 1uf x? mic x? mic 1 2 c? 1uf c? 1uf r? 2.2k r? 2.2k c? 1uf c? 1uf c? 0.1uf c? 0.1uf
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 21 preliminary?subject to change without notice 5.5 typical connection diagram - 32-pin qfn - lowest power configuration figure 5-14. typical connection diagram - 32-pin qfn - lowest power configuration vddio (=3.1v) vdda (=1.6v) vddd (=1.2v) ctrl_clk 6,7 i2 s_sclk 7 ctrl_data 6,7 i2s_din 7 i2 s_dout 7 sys_mclk i2 s_lrclk 7 line_in _l 4 line_in _r 4 line_out_r 5 line_out_l 5 solder pad to gnd 1. vddd is driven externally by 1.2v supply. 2. vdda is driven at 1.6v 3. vddio is driven at 3.1v c 322 0uf c 322 0uf c 222 0uf c 222 0uf c5 0.1uf c5 0.1uf j1 audio jack j1 audio jack 2 5 1 4 3 c6 .1 uf c6 .1 uf c4 0.1uf c4 0.1uf c7 0.1uf c7 0.1uf x1 mic x1 mic 1 2 c8 1uf c8 1uf c1 0.1uf c1 0.1uf c9 1 uf c9 1 uf c11 1 uf c11 1 uf c10 1 uf c10 1 uf c12 1uf c12 1uf u1 sgtl5000_32qfn u1 sgtl5000_32qfn i2s_sclk 24 nc 22 li n ei n _l 14 cpfilt 18 vddio 20 nc 19 sys_mclk 21 i 2 s_dout 2 5 i 2 s_di n 2 6 hp_l 6 ctrl_data 2 7 n c 2 8 ctrl_clk 2 9 gnd 1 nc 8 hp_r 2 gnd 3 vdda 5 li n eout_l 1 2 li n eout_r 11 mic 15 nc 17 li n ei n _r 1 3 agnd 7 i2s_lrclk 23 vddd 3 0 ctrl_adr0_cs 3 1 ctrl_mode 32 hp_vgnd 4 n c 9 vag 10 mic_bias 16 gnd pad
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 22 freescale semiconductor preliminary?subject to change without notice 5.6 typical connection diagram - 32-pin qfn - lowest cost configuration figure 5-15. typical connection diagram - 32-pin qfn - lowest cost configuration vdd (=3.1v to 3.6v) vdd (=3.1v to 3.6v) ctrl_clk 6,7 i2 s_sclk 7 ctrl_data 6,7 i2s_din 7 i2 s_dout 7 sys_mclk i2 s_lrclk 7 line_in _l 4 line_in _r 4 line_out_r 5 line_out_l 5 notes: 1. vddd is derived internally (no need for external cap) 2. vdda and vddio are supplied from same voltage that is between 3.1v and 3.6v. by using the same voltage this allows removal of power decoupling cap. by using a voltage above 3.1v the cap connected to cpfilt can be removed. solder pad to gnd c2 .1uf c2 .1uf c8 1 uf c8 1 uf j1 audio jack j1 audio jack 2 5 1 4 3 u1 sgtl5000_32qfn u1 sgtl5000_32qfn i2s_sclk 24 nc 22 li n ei n _l 14 cpfilt 18 vddio 20 nc 19 sys_mclk 21 i 2 s_dout 2 5 i 2 s_di n 2 6 hp_l 6 ctrl_data 2 7 n c 2 8 ctrl_clk 2 9 gnd 1 nc 8 hp_r 2 gnd 3 vdda 5 li n eout_l 1 2 li n eout_r 11 mic 15 nc 17 li n ei n _r 1 3 agnd 7 i2s_lrclk 23 vddd 3 0 ctrl_adr0_cs 3 1 ctrl_mode 32 hp_vgnd 4 n c 9 vag 10 mic_bias 16 gnd pad c7 1 uf c7 1 uf c3 0.1uf c3 0.1uf c6 1 uf c6 1 uf c4 1uf c4 1uf c5 1 uf c5 1 uf c1 0.1uf c1 0.1uf x1 mic x1 mic 1 2
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 23 preliminary?subject to change without notice 6.0 device description the sgtl5000 is a low power stereo codec with integrat ed headphone amplifier. it is designed to provide a complete audio solution for portable products need ing line-in, mic-in, line-out, headphone-out, and digital i/o. deriving it?s architecture from best in class freescale integrated products that are currently on the market, the sgtl5000 is able to achieve ultra lo w power with very high performance and functionality, all in one of the smallest footprints available. ta rget markets include portable media players, gps units and smart phones. features such as capless headphone design and usb clocking mode (12 mhz sys_mclk input) help lower overall system cost. in summary, sgtl5000 accepts the following inputs: ? line input ? microphone input, with mic bias (mic bias only available in 32qfn version) ? digital i2s input in addition, sgtl5000 supports the following outputs: ? line output ? headphone output ? digital i2s output the following digital audio processing is included to allow for product differentiation: ? digital mixer ? sgtl surround ? sgtl bass enhancement ? tone control, parametric e qualizer, and graphic equalizer the sgtl5000 can accept an external standard master clock at a multiple of the sampling frequency (i.e. 256*fs, 385*fs, 512*fs). in addition it can take non-sta ndard frequencies and use the internal pll to derive the audio clocks. the device supports 8 khz, 11.025 khz, 16 khz, 22.5 khz, 24 khz, 32 khz, 44.1 khz, 48 khz, and 96 khz sampling frequencies. 6.1 system block diagram w/ signal flow and gain map figure 6-16 below shows a block diagram that highli ghts the signal flow and gain map for the sgtl5000.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 24 freescale semiconductor preliminary?subject to change without notice to guarantee against clipping it is important that the gain in a signal path in addition to the signal level does not exceed 0db at any point. 6.2 power the sgtl5000 has a flexible power architecture to allow the system designer to minimize power consumption and maximize performance at the lowest cost. 6.2.1 external power supplies the sgtl5000 requires 2 external power supplies: vdda and vddio. an optional third external power supply vddd may be provided externa lly to achieve lower power. a description for the different power supplies is as follows: ? vdda: this external power supply is used for the internal analog circuitry including adc, dac, line inputs, mic inputs, headphone outputs a nd reference voltages. vdda supply ranges are shown in section 2.2. a decoupling cap should be used on vdda as shown in the typical connection diagram in section 5.0. ? vddio: this external power supply controls the digital i/o levels as well as the output level of line outputs. vddio supply ranges are shown in section 2.2. a decoupling cap should be used on vddio as shown in the typical connection diagram in section 5.0. note that if vdda and vddio are derived from the same voltage, a single decoupling capacitor can be used to minimize cost. this capacitor should be placed closest to vdda. mic gain (0db, 20db, 30db, 40db ) mic_in audio switch i2s_din adc i2s_dout mix +6db tone control /geq/peq +12 db bass enhancement +6db surround avc +12db dac dac volume control -90db to 0db headphone volume control -52db to +12db ( chip_ana_hp_ctrl ) hp_out analog gain digital gain analog gain (0 to 22.5db) only gain is shown for the digital audio processing blocks. for complete description please see digital audio processing section. line out volume control ( chip_line_out_vol ) lineout line_in figure 6-16. system block diagram, signal flow and gain
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 25 preliminary?subject to change without notice ? vddd: this is a digital power supply that is used for internal digital circuitry. for a low cost design, this supply can be derived from an in ternal regulator and no external components are required. if no external supply is applied to vddd, the internal regulator will automatically be used. for lowest power, this supply can be driven at the lowest specified voltage given in section 2.2. if an external supply is used for vddd, a decoupling capacitor is recommended. vddd supply ranges are shown in section 2.2 for when externally driven. if the system drives vddd externally, an efficient switching supply should be used or no system power savings will be realized. 6.2.2 internal power supplies the sgtl5000 has two exposed internal power supplies, vag and chargepump. ? vag is the internal voltage reference for the adc and dac. after startup the voltage of vag should be set to vdda/2 by writing chip_ref_ctrl->vag_val . refer to programming section 7.2.1.1. the vag pin should have an ex ternal filter capacitor as shown in the typical connection diagram. ? chargepump: this power supply is used for internal analog switches. if vdda or vddio is greater than 2.7v, this supply is automatically driven from the highest of vddio and vdda. if both vddio and vdda are less than 3.1v, then the user should turn on the charge pump function to create the chargepump rail from vddio by writing chip_ana_power->vddc_chrgpmp_powerup register. refer to programming section 7.2.1.1. ? line_out_vag is the line output voltage reference. it should be set to vddio/2 by writing chip_line_out_ctrl->lo_vagcntrl . 6.2.3 power schemes the sgtl supports a flexible architecture and allo ws the system designer to minimize power or maximize bom savings. ? for maximum cost savings, all supplies can be run at the same voltage. ? alternatively for minimum power, the analog and digital supplies can be run at minimum voltage while driving the digital i/o voltage at the voltage needed by the system. ? to save power, independent supplies are provi ded for line outputs and headphone outputs. this allows for 1vrms line outputs while using minimal headphone power. ? for best power, vdda should be run at the lowe st possible voltage required for the maximum headphone output level. for highe st performance, vdda should be run at 3.3v. for most applications a lower voltage can be used for the best performance/power combination. 6.3 reset the sgtl5000 has an internal reset that is deassert ed 8 sys_mclks after all power rails have been brought up. after this time communication can st art. see section 2.4 for timing specification.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 26 freescale semiconductor preliminary?subject to change without notice 6.4 clocking clocking for the sgtl5000 is provided by a system master clock input (sys_mclk). sys_mclk should be synchronous to the sampling rate (fs) of the i2s port. alternatively any clock between 8 mhz and 27 mhz can be provided on sys_mclk and the sg tl5000 can use an internal pll to derive all internal and i2s clocks. this allows the system to use an available clock such as 12 mhz (common usb clock) for sys_mclk to reduce overall system costs. 6.4.1 synchronous sys_mclk input the sgtl5000 supports various combinations of sys_mclk frequency a nd sampling frequency as shown in table 6-13 . using a synchronous sys_mclk allows for lower power as the internal pll is not used. note: for a sampling frequency of 96 khz, only 256fs sys_mclk is supported. 6.4.2 using the pll - asynchronous sys_mclk input an integrated pll is provided in the sgtl5000 that allows any clock from 8 mhz to 27 mhz to be connected to sys_mclk. this can help save system costs as a clock available elsewhere in the system can be used to derive all audio clocks using the inte rnal pll. in this case the clock input to sys_mclk can be asynchronous with the sampling frequency needed in the system. for example a 12 mhz clock from the system processor could be used as the clock input to the sgtl5000. three register fields need to be configured to properly use the pll. they are chip_pll_ctrl->int_divisor , chip_pll_ctrl->frac_divisor and chip_clk_top_ctrl->input_freq_div2 . figure 6-17 shows a flowchart that shows how to determine the values to program in the register fields. table 6-13. synchronous mclk rates clock supported rates units system master clock (sys_mclk) 256*fs, 384*fs, 512*fs khz sampling frequency (fs) 8, 11.025, 16, 22.5, 32, 44.1, 48, 96 (see note, below.) khz
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 27 preliminary?subject to change without notice for example, when a 12 mhz digital signal is placed on mclk, for a 48 khz frame clock: chip_clk_top_ctrl->input_freq_div2 = 0 // sys_mclk<17 mhz chip_pll_ctrl->int_divisor = floor(196.608 mhz/12 mhz) = 16 (decimal) chip_pll_ctrl->frac_divisor = ((196.608 mhz/12 mhz) - 16) * 2048 = 786 (decimal) refer to pll programming note 7.2.2. 6.5 audio switch (source select switch) the audio switch is the central routing block that c ontrols the signal flow from input to output. any single input can be routed to any single or multiple outputs. any signal can be routed to the digital audio proces sor (dap). the output of the dap (an input to the audio switch) can in turn be routed to any physical output. the output of the dap can not be routed into itself. refer to section 6.9, digital audio pr ocessing, for dap information and configuration. it should be noted that the analog bypass from line input to headphone output does not go through the audio switch. sys_mclk>17mhz? chip_clk_top_ctrl->input_freq_div2 = 1 pll_input_freq = sys_mclk/2 sampling frequency = 44.1khz? pll_output_freq=180 .6336 mhz pll_output_freq=196.608mhz chip_clk_top_ctrl->input_freq_div2 = 0 pll_input_freq = sys_mclk chip_pll_ctrl->int_divisor = floor (pll_output_freq/input_freq chip_pll_ctrl->frac_divisor = ((pll_output_freq/input_freq) - int_divisor) * 2048 no yes no yes figure 6-17. pll programming flowchart
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 28 freescale semiconductor preliminary?subject to change without notice to configure a route, the chip_sss_ctrl register is used. each output from the source select switch has its own register field that is used to select what input is routed to that output. for example, to route the i2s digital input thro ugh the dap and then out to the dac (headphone) outputs write sss_ctrl->dap_select to 0x1 (selects i2s_in) and sss_ctrl->dac_select to 0x3 (selects dap output). 6.6 analog input block the analog input block contains a stereo line input and a microphone input with mic bias (in the 32qfn package). either input can be routed to the adc. the line input can also configured to bypass the codec and be routed the analog input directly to the headphone output. 6.6.1 line inputs one stereo line input is provided for connection to line sources such as an fm radio or mp3 input. the source should be connected to the left and right line inputs through series coupling capacitors. the suggested value is shown in the typical connection diagram in section 5.0. as detailed in section 6.6.3, the line input can be routed to the adc. the line input can also be routed to the headphone output by writing chip_ana_ctrl->select_hp . this selection bypasses the adc and audio switch a nd routes the line input directly to the headphone output to enable a very low power pass through. 6.6.2 microphone input one mono microphone input is provided for uses such as voice recording. mic bias is provided in the 32qfn package. the mic bias is can be programmed with the chip_mic_ctrl->bias_volt register field. values from 1.25v to 3.00v are supported in 0.25v steps. mic bias should be set less than 200mv from vdda, e.g. with vdda at 1.70v, mic bias should be set no greater than 1.50v. the microphone should be connected through a series coupling capacitor. the suggested value is shown in the typical connection diagram. the microphone has programmable gain through the chip_mic_ctrl->gain register field. values of 0db, +20db, +30db and +40db are available. 6.6.3 adc the sgtl5000 contains an adc which takes its input from either the line input or a microphone. the register field chip_ana_ctrl->select_adc controls this selection. the output of the adc feeds the audio switch.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 29 preliminary?subject to change without notice the adc has its own analog gain stage that provides 0 to +22.5db of gain in 1.5db steps. a bit is available that shifts this range down by 6db to effectively pr ovide -6db to +16.5db of gain. the adc gain is controlled in the chip_ana_adc_ctrl register. the adc has an available zero-cross detect (zcd) that will prevent any volume change until a zero-volt crossing of the audio signal is detected. this helps in eliminating pop or other a udio anomalies. if the adc is to be used, the chip reference bias current should not be set to -50% when in 3v mode. 6.7 analog outputs the sgtl5000 contains a single stereo dac that can be used to drive a headphone output and a line output. the dac receives its input from the audio sw itch. the headphone output and the line output can be driven at the same time from the dac. the headphone output can also be driven directly by the line input bypassing the adc and dac for a very low power mode of operation. the headphone output is powered by vdda while the line output is powered by vddio. this allows the headphone output to be run at the lowest possible vol tage while the line output can still meet line output level requirements. 6.7.1 dac the dac output is routed to the headphone and the dedicated line output. the dac output has a digital volume control from -90db to 0db in ~.5db step sizes. this volume is shared among headphone output and line output. the register chip_dac_vol controls the dac volume. 6.7.2 headphone stereo headphone outputs are provided which can be used to drive a headphone load or a line level output. the headphone output has its own independent analog volume control with a volume range of -52db to +12db in 0.5db step sizes. this volume control can be used in addition to the dac volume control. for best performance the dac volume control should be left at 0db until the headphone is brought to its lowest setting of -52db. the register chip_ana_hp_ctrl is used to control the headphone volume. the headphone output has an independent mute that is controlled by the register field chip_ana_ctrl->mute_hp . the line input is routed to the headphone output by writing chip_ana_ctrl->select_hp . this selection bypasses the adc and audio switch and routes the line input directly to the headphone output to enable a very low power pass through. when the lin e input is routed to the headphone output, only the headphone analog volume and mute will affect the headphone output. the headphone has an available zero cross detect (zcd ) which, as previously described, will prevent any volume change until a zero-volt crossing of the audio si gnal is detected. this helps in eliminating pop or other audio anomalies.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 30 freescale semiconductor preliminary?subject to change without notice 6.7.3 line outputs the sgtl5000 contains a stereo line output. the line out put has a dedicated gain stage that can be used to adjust the output level. the chip_line_out_vol controls the line level output gain. the line outputs also have a dedicated mute that is controlled by the register field chip_ana_ctrl->mute_lo. the lineout volume is intended as maximum output level adjustment. it is intended to be used to set the maximum output swing. it does not have the range of a typical volume control and does not have a zero cross detect (zcd). however the dac digital volum e could be used if volume control is desired 6.8 digital input & output one i2s (digital audio) port is provided which supports the following formats: i2s, left justified, right justified and pcm mode. 6.8.1 i2s, left justified and right justified modes i2s, left justified and right justified modes are st ereo interface formats. the i2s_sclk frequency, i2s_sclk polarity, i2s_din/dout data length, and i2s_lrclk polarity can all be change through the chip_i2s_ctrl register. for i2s, left justified and right justified formats the left subframe should always be presented first regardless of the chip_i2s_ctrl->lrpol setting. the i2s_lrclk and i2s_sclk can be programmed as master (driven to an external target) or slave (driven from an external source). when the clocks are in slave mode, they must be synchronous to sys_mclk. for this reason the sgtl5000 can only operate in synchronous mode (see section 6.4) while in i2s slave mode. in master mode, the clocks will be synchronous to sys_mclk or the output of the pll when the part is running in asynchronous mode. figure 6-18 shows functional examples of different common digital interface formats and their associated register settings.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 31 preliminary?subject to change without notice 6.8.2 pcm mode the i2s port can also be configured into a pcm mode (also known as dsp mode). this mode is provided to allow connectivity to external devices such as bluetooth modules. pcm mode differs from other interface formats presented in section 6.8.1 in that the frame clock (i2s_lrclk) does not represent a different channel when high or low, but is a bit-wide pul se that marks the start of a frame. data is aligned such that the left channel data is immediately followed by right channel data. zero padding is filled in for the remaining bits. the data and fram e clock may be configured to clock in on the rising or falling edge of bit clock. l n l (n-1) l01 l00 r n r (n-1) r01 r00 i2s_lrclk i2s_sclk i2s_din, dout i2s format (n = bit length) chip_i2s0_ctrl field values: (sclkfreq = 0; sclk_inv = 0; dlen = 1; i2s_mode = 0; lralign = 0; lrpol = 0) l n l n l (n-1) l 1 l 0 r n r (n-1) r 1 r 0 i2s_lrclk i2s_sclk i2s_din, dout left justified format (n = bit length) chip_i2s0_ctrl field values: (sclkfreq = 0; sclk_inv = 0; dlen = 1; i2s_mode = 0; lralign = 1; lrpol = 0) l n l (n-1) l n l (n-1) l 0 r n r (n-1) r0 i2s_lrclk i2s_sclk i2s_din, dout right justified format (n = bit length) chip_i2s0_ctrl field values: sclkfreq = 0; sclk_inv = 0; dlen = 1; i2s_mode = 1; lralign = 1; lrpol = 0) figure 6-18. i2s port supported formats
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 32 freescale semiconductor preliminary?subject to change without notice pcm format a signifies the data word beginning one sclk bit following the i2s_lrclk transition, as in i2s mode. pcm format b signifies the data word beginning after the i2s_lrclk transition, as in left justified. in slave mode, the pulse width of the i2s_lrclk doe s not matter. the pulse can range from one cycle high to all but one cycle high. in master mode, it will be driven one cycle high. figure 6-19 shows a functional drawing of the different formats in master mode. 6.9 digital audio processing the sgtl5000 contains a digital audio processing block (dap) attached to the source select switch. the digitized signal from the source select switch can be routed into the dap block for audio processing. the dap has the following 5 sub blocks: ? dual input mixer ? sgtl surround ? sgtl bass enhancement ? 7-band parameter eq / 5-band graphic eq / tone control (only one can be used at a time) ? automatic volume control (avc) the block diagram in figure 6-20 shows the sequence in which the signal passes through these blocks. l n l (n-1) l 0 r n r (n-1) r 0 i2s_lrclk i2s_sclk i2s_din, dout pcm format a chip_i2s0_ctrl = 0x01f4 (sclkfreq = 1; ms = 1; sclk_inv = 1; dlen = 3; i2s_mode = 2; lralign = 0) l n l (n-1) l 0 r n r (n-1) r 0 r 1 r 1 l n l (n -1 ) l 0 r n r (n-1) r 0 i2s_lrclk i2s_sclk i2s_din, dout pcm format b chip_i2s0_ctrl = 0x01f6 (sclkfreq = 1; ms = 1; sclk_inv = 1; dlen = 3; i2s_mode = 2; lralign = 1) l n l (n-1) l 0 r n r (n-1) r 0 figure 6-19. pcm formats
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 33 preliminary?subject to change without notice when the dap block is added in the route, it must be enabled separately to get audio through. it is recommended to mute the outputs before enabling/disabling the dap block to avoid any pops or clicks due to discontinuities in the output. refer to section 7.2.4 for programming examples on how to enable/disable the dap block. each sub-block of the dap can be individually disabl ed if its processing is not required. the sections below describes the dap sub-blocks and how to configure them. 6.9.1 dual input mixer the dual input digital mixer allows for two incoming st reams from the source select switch as shown in figure 6-21. automatic volume control (avc) sgtl surround sgtl bass enhance 7-band parametric eq 5-band graphic eq tone control from source select swtich to source select swtich dual input mixer set dap_control->dap_en to enable dap block only one of peq/geq/tc can be used at a time each dap sub-block can be configured in a pass -through mode main input mix input figure 6-20. digital audio processing block diagram
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 34 freescale semiconductor preliminary?subject to change without notice figure 6-21. dap - dual input mixer the dual input mixer can be enabled or configured in a pass-through mode (main channel will be passed through without any mixing). when enabled, the volume of the main and mix channels can be independently controlled before they are mixed together. the volume range allowed on each channel is 0% to 200% of the incoming signal level. the default is 100% (same as input signal level) volume on the main input and 0% (muted) on the mix input. please refer to section 7.2.4.1 for programming examples on how to enable/disable the mixer and also to set the main and mix channel volume. 6.9.2 sgtl surround sgtl surround is a royalty free virtual surround algorithm for stereo or mono inputs. it widens and deepens sound stage for music input. figure 6-22. dap - sgtl surround the sgtl surround can be enabled or configured in pass-through mode (input will be passed through without any processing). when enabling the surround, m ono or stereo input type must be selected based on the input signal. surround width may be adjusted for the size of the sound stage. main channel main channel volume dap_main_chan->vol mix channel volume dap_mix_chan->vol sum mixer output from source select switch from source select switch mix channel to sgtl surround block sgtl surround dap_sgtl_surround -> width_control ->select input from dual mixer output to sgtl bass enhance
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 35 preliminary?subject to change without notice please refer to section 7.2.4.2 and section 7.3.5 for a programming example on how to configure surround width and how to enable/disable surround. 6.9.3 sgtl bass enhance sgtl bass enhance is a royalty-free algorithm that enhances natural bass response of the audio. bass enhance extracts bass content from right and left cha nnels, adds bass and mixes this back up with the original signal. an optional complementary high pass filter is provided after the mixer. figure 6-23. dap - sgtl bass enhance the sgtl bass enhance can be enabled or configured in pass-through mode (input will be passed through without any processing). the cut-off frequency of the low-pass filter (lpf) can be selected based on the speakers frequency response. the cut-off frequency of the low-pass and high-pass filters are selectable between 80 hz to 225 hz. also, the input signal and bass enhanced signal ca n be individually adjusted for level before the two signals are mixed. please refer to section 7.2.4.3 and section 7.3.6 for a programming example on how to configure bass enhance and how to enable/disable this feature. 6.9.4 7-band parametric eq / 5-band graphic eq / tone control one 7-band parametric equalizer (p eq) and one 5-band graphic equalizer (geq) and a tone control (bass and treble control) blocks are implemented as mutua lly exclusive blocks. only one block can be used at a given time. please refer to section 7.2.4.4 for a programming example that shows how to select the desired eq mode. bass enhance low pass filter dap_bass_enhance ->cut_off dap_bass_enhance_ctrl ->bass _level dap_bass_enhance_ctrl ->lr_level input (from sgtl surround) high pass filter dap_bass_enhance_ctrl ->cutoff_hpf ->bypass _hpf output (to peq/geq/tc)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 36 freescale semiconductor preliminary?subject to change without notice 6.9.4.1 7-band parametric eq the 7-band peq allows the designer to compensate for speaker response and to provide the ability to filter out resonant frequencies caused by the physical system design. the system designer can create custom eq presets such rock, speech, classical etc. that allows the users the flexibility in customizing their audio. the 7-band peq is implemented using 7 cascaded second order iir filters. all filters are implemented using programmable biquad filters. figure 6-24 shows the transfer function and direct form 1 of the five coefficient biquadratic filter. figure 6-24. 5-coefficient biquad filter and transfer function if a band is enabled but is not being used (flat re sponse), then a value of 0.5 should be put in b 0 and all other coefficients should be set to 0.0. please note that the coefficients must be converted to hex values before writing to the registers. by default, all the filters are loaded with coefficients to give a flat response. in order to create eq presets such as rock, speech, classical etc., the coefficients must be calculated, converted to 20-bit hex values and written to the register s. note that coefficients are sample-rate dependent and separate coefficients must be generated for different sample rates. please contact freescale for assistance with generating the coefficients. please refer to section 7.3.2 for a programming example that shows how load the filter coefficients when the end-user changes the preset. peq can be disabled (pass-through mode) by writing 0 to dap_audio_eq->en bits. 1 ? z 1 ? z 1 ? z 1 ? z x(z) h(z)x(z) b 0 b 1 b 2 -a 1 -a 2 2 2 1 1 2 2 1 10 1 )( ? ? ? ? ++ ++ = zaza zbzbb zh direct form 1
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 37 preliminary?subject to change without notice 6.9.4.2 5-band graphic eq the 5-band graphic equalizer is implemented using 5 parallel second order iir filters. all filters are implemented using biquad filters whose coefficients are programmed to set the bands at specific frequency. the geq bands are fixed at 115 hz, 330 hz, 990 hz, 3000 hz, and 9900 hz. the volume on each band is independently adjustable in the ra nge of +12db to -11.75 db in 0.25db steps. please refer to section 7.3.3 for a programming example that shows how to change the geq volume 6.9.4.3 tone control tone control comprises treble and bass controls. th e tone control is implemented as one 2nd order low pass filter (bass) and one 2nd order high pass filter (treble). please refer to section section 7.3.4 for a programming example that shows how to change bass and treble values. 6.9.5 automatic volume control (avc) an automatic volume control (avc) block is provi ded to reduce loud signals and amplify low level signals for easier listening. the avc is designed to co mpress audio when the measured level is above the programmed threshold or to expand the audio to the programmed threshold when the measured audio is below the threshold. the threshold level is programmable with allowed range of 0db to -96db. figure 6-25 shows the avc block diagram and controls. figure 6-25. dap avc block diagram when the measured audio level is below threshold, the avc can apply a maximum gain of up to 12db. the maximum gain can be selected, either 0, 6 or 12db . when the maximum gain is set to 0db the avc acts as a limiter. in this case the avc will only take effect when the signal level is above the threshold. the rate at which the incoming signal is attenuated down to the threshold is called the attack rate. too high of an attack will cause an unnatural sound as the input signal is distorted. too low of an attack may cause saturation of the output as the incoming signal will not be compressed quickly enough. the attack rate is programmable with allowed ra nge of 0.05db/s to 200db/s. threshold level compare volume control if < threshold decay (0.05db/s to ~200db/s) dap_avc_decay dap_avc_threshold -> max_gain if > threshold attack (0.8db/s to ~3200db/s) dap_avc_attack input from dual input mixer dap_avc_threshold output to sgtl surround
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 38 freescale semiconductor preliminary?subject to change without notice when the signal is below the threshold, avc will adjust the volume up until either the threshold or the maximum gain is reached. the rate at which this volume is changed is called the decay rate. the decay rate is programmable with allowed range of 0.8db/s to 3200db/s. it is desirable to use very slow decay rate to avoid any distortion in the signal and prev ent the avc from entering a continuous attack-decay loop. please refer to section 7.2.4.5 and section 7.3.7 fo r a programming example that shows how to configure avc and how to enable/disable avc respectively. 6.10 control the sgtl5000 supports both i2c and spi control modes. the ctrl_mode pin chooses which mode will be used. when ctrl_mode is tied to ground, the control mode is i2c. when ctrl_mode is tied to vddio, the control mode is spi. regardless of the mode, the control interface is used for all communication with the sgtl5000 including startup configuration, routing, volume, etc. 6.10.1 i2c the i2c port is implemented according to the i2c specification v2.0. the i2c interface is used to read and write all registers. for the 32qfn version of the sgtl5000, the i2c device address is 0n01010(r/w) where n is determined by i2c_adr0_cs and r/w is the read/write bit from the i2c protocol. for the 20qfn version of the sgtl5000 the i2c address is always 0001010(r/w). the sgtl5000 is always the slave on all transactions which means that an external master will always drive ctrl_clk. in general an i2c transaction looks as follows. all locations are accessed with a 16 bit address. each location is 16 bits wide. an example i2c write transaction follows: ? start condition ? device address with the r/w bit cleared to indicate write ? send two bytes for the 16 bit register address (most significant byte first) ? send two bytes for the 16 bits of data to be written to the register (most significant byte first) ? stop condition an i2c read transaction is defined as follows: ? start condition ? device address with the r/w bit cleared to indicate write ? send two bytes for the 16 bit register address (most significant byte first) ? stop condition followed by start condition (or a single restart condition)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 39 preliminary?subject to change without notice ? device address with the r/w bit set to indicate read ? read two bytes from the addressed register (most significant byte first) ? stop condition figure 6-26 shows the functional i2c timing diagram. the protocol has an auto increment feature. instead of sending the stop condition after two bytes of data, the master may continue to send da ta byte pairs for writing, or it may send extra clocks for reading data byte pairs. in either case, the access address is incremented after every two bytes of data. a start or stop condition from the i2c master interrupts the current command. for reads, unless a new address is written, a new start condition with r/w=0 reads from the current address and continues to auto increment. the following diagrams describe the different access formats. the gray fields are from the i2c master, and the white fields are the sgtl5000 responses. data[n] corresponds to the data read from the address sent, data[n+1] is the data from the next register, and so on. s = start condition sr = restart condition a = ack n = nack p = stop condition ta2 silicon will allow for up to a 3.6v i2c signal level, regardle ss of the vddio level. table 6-14. write single location table 6-15. write auto increment table 6-16. read single location table 6-17. read auto increment s device address w (0) a addr byte 1 a addr byte 0 a data byte 1 a data byte 0 a p s device address w (0) a start addr byte 1 a start addr byte 0 a data [n] byte 1 a data [n] byte 0 a data [n+1] byte 1 a data [n+1] byte 0 a p s device address w (0) a addr byte 1 a addr byte 0 a sr device address r (1) adata byte 1 adata byte 0 n p s device address w (0) a start addr byte 1 a start addr byte 0 a sr device address r (1) adata [n] byte 1 adata [n] byte 0 adata [n+1] byte 1 adata [n+1] byte 0 n p i2c addr ess a15 a8 a7 a0 d15 d 8 d7 d0 r/w ack ack ack ack ack start condition stop condition figure 6-26. functional i2c diagram
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 40 freescale semiconductor preliminary?subject to change without notice table 6-18. read continuing auto increment 6.10.2 spi serial peripheral interface (spi) is a communications protocol supported by the sgtl5000. the sgtl5000 is always a slave. the ctrl_ad0_cs is used as the slave select (ss) when the master wants to select the sgtl5000 for communication. ctrl_clk is connected to master?s sclk and ctrl_data is connected to master?s mosi line. the part only supports allows spi write operations and does not support read operations. figure 6-27 below shows the functional timing diagram of the spi communication protocol as supported by sgtl5000 chip. note that on the rising edge of the ss, the chip latches to previous 32 bits of data. it interprets the latest 16-bits as register value and 16-bits preceding it as register address. figure 6-27. functional timing diagram of spi protocol s device address ra data [n+2] byte 1 adata [n+2] byte 0 adata [n+3] byte 1 adata [n+3] byte 0 n p ss sck addr 15 addr 14 addr 8 addr 7 addr 6 addr 0 31 15 mosi val 15 val 14 val 8 val 7 val 6 val 0 23 70 16-bits register address 16-bits register value on rising edge of ss, latch the last 32 bits of data
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 41 preliminary?subject to change without notice 7.0 programming examples this section provides programming examples that show how to configure the chip. the registers can be written/read by using i2c communication protocol. the chip also supports spi communication protocol but only register write operation is supported. 7.1 prototype for reading and writing a register the generic register read write prototype will be used throughout this section as shown below. the i2c or spi implementation will be specific to the i2c/spi hardware used in the system. // this prototype writes a value to the entire register. all // bit-fields of the register will be written. write register registervalue // this prototype writes a value only to the bit-field specified. // in the actual implementation, the other bit-fields should be // masked to prevent them from being written. also, the // actual implementation should left-shift the bitfieldvalue // by appropriate number to match the starting bit location of // the bitfield. modify register -> bitfield, bitfieldvalue //bitfield location // example implementation // modify dap_en (bit 0) bit to value 1 to enable dap block modify( dap_control_reg, 0xfffe, 1 << dap_en_startbit ); // example implementation of modify void modify( unsigned short usregister, unsigned short usclearmask, unsigned short ussetvalue ) { unsigned short usdata; // 1) read current value readregister( usregister, &usdata ); // 2) clear out old bits usdata = usdata & usclearmask; // 3) set new bit values usdata = usdata | ussetvalue; // 4) write out new value created writeregister( usregister, usdata ); } 7.2 chip configuration all outputs (lineout, hp_out, i2s_out) are mute d by default on powerup. to avoid any pops/clicks, the outputs should remain muted during these chip conf iguration steps. refer to section 7.2.6 for volume and mute control.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 42 freescale semiconductor preliminary?subject to change without notice 7.2.1 initialization 7.2.1.1 chip powerup and supply configurations after the power supplies for chip is turned on, fo llowing initialization sequence should be followed. please note that certain steps may be optional or different values may need to be written based on the power supply voltage used and desired configuration. the initialization sequence below assumes vddio = 3.3v and vdda = 1.8v. //--------------- power supply configuration---------------- // note: this next 2 write calls is needed only if vddd is // internally driven by the chip // configure vddd level to 1.2v (bits 3:0) write chip_linreg_ctrl 0x0008 // power up internal linear regulator (set bit 9) write chip_ana_power 0x7260 // note: this next write call is needed only if vddd is // externally driven // turn off startup power supplies to save power (clear bit 12 and 13) write chip_ana_power 0x4260 // note: the next 2 write calls is needed only if both vdda and // vddio power supplies are less than 3.1v. // enable the internal oscillator for the charge pump (set bit 11) write chip_clk_top_ctrl 0x0800 // enable charge pump (set bit 11) write chip_ana_power 0x4a60 // note: the next 2 modify calls is only needed if both vdda and // vddio are greater than 3.1v // configure the chargepump to use the vddio rail (set bit 5 and bit 6) write chip_linreg_ctrl 0x006c //------ reference voltage and bias current configuration---------- // note: the value written in the next 2 write calls is dependent // on the vdda voltage value. // set ground, adc, dac reference voltage (bits 8:4). the value should // be set to vdda/2. this example assumes vdda = 1.8v. vdda/2 = 0.9v. // the bias current should be set to 50% of the nominal value (bits 3:1) write chip_ref_ctrl 0x004e // set lineout reference voltage to vddio/2 (1.65v) (bits 5:0) and bias current // (bits 11:8) to the recommended value of 0.36ma for 10kohm load with 1nf // capacitance write chip_line_out_ctrl 0x0322 //----------------other analog block configurations------------------ // configure slow ramp up rate to minimize pop (bit 0) write chip_ref_ctrl 0x004f // enable short detect mode for headphone left/right // and center channel and set short detect current trip level // to 75ma write chip_short_ctrl 0x1106 // enable zero-cross detect if needed for hp_out (bit 5) and adc (bit 1)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 43 preliminary?subject to change without notice write chip_ana_ctrl 0x0133 //----------------power up inputs/outputs/digital blocks------------- // power up lineout, hp, adc, dac write chip_ana_power 0x6aff // power up desired digital blocks // i2s_in (bit 0), i2s_out (bit 1), dap (bit 4), dac (bit 5), // adc (bit 6) are powered on write chip_dig_power 0x0073 //--------------------set lineout volume level----------------------- // set the lineout volume level based on voltage reference (vag) // values using this formula // value = (int)(40*log(vag_val/lo_vagcntrl) + 15) // assuming vag_val and lo_vagcntrl is set to 0.9v and 1.65v respectively, the // left lo vol (bits 12:8) and right lo volume (bits 4:0) value should be set // to 5 write chip_line_out_vol 0x0505 7.2.1.2 system mclk and sample clock // configure sys_fs clock to 48 khz // configure mclk_freq to 256*fs modify chip_clk_ctrl->sys_fs 0x0002 // bits 3:2 modify chip_clk_ctrl->mclk_freq 0x0000 // bits 1:0 // configure the i2s clocks in master mode // note: i2s lrclk is same as the system sample clock modify chip_i2s_ctrl->ms 0x0001 // bit 7 7.2.2 pll configuration these programming steps are needed only when the pll is used. please refer to section 6.4.2 for details on when to use the pll. to avoid any pops/clicks, the outputs should be muted during these chip configuration steps. refer to section 7.2.6 for volume and mute control. // power up the pll modify chip_ana_power->pll_powerup 0x0001 // bit 10 modify chip_ana_power->vcoamp_powerup 0x0001 // bit 8 // note: this step is required only when the external sys_mclk // is above 17 mhz. in this case the external sys_mclk clock // must be divided by 2 modify chip_clk_top_ctrl->input_freq_div2 0x0001 // bit 3 sys_mclk_input_freq = sys_mclk_input_freq/2; // pll output frequency is different based on the sample clock // rate used. if (sys_fs_rate == 44.1 khz) pll_output_freq = 180.6336mhz else pll_output_freq = 196.608mhz
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 44 freescale semiconductor preliminary?subject to change without notice // set the pll dividers int_divisor = floor(pll_output_freq/sys_mclk_input_freq) frac_divisor = ((pll_output_freq/sys_mclk_input_freq) - int_divisor)*2048 modify chip_pll_ctrl->int_divisor int_divisor // bits 15:11 modify chip_pll_ctrl->frac_divisor frac_divisor // bits 10:0 7.2.3 input/output routing to avoid any pops/clicks, the outputs should be muted during these chip configuration steps. refer to section 7.2.6 for volume and mute control. a few example routes are shown below: // example 1: i2s_in -> dap -> dac -> lineout, hp_out // route i2s_in to dap modify chip_sss_ctrl->dap_select 0x0001 // bits 7:6 // route dap to dac modify chip_sss_ctrl->dac_select 0x0003 // bits 5:4 // select dac as the input to hp_out modify chip_ana_ctrl->select_hp 0x0000 // bit 6 // example 2: mic_in -> adc -> i2s_out // set adc input to mic_in modify chip_ana_ctrl->select_adc 0x0000 // bit 2 // route adc to i2s_out modify chip_sss_ctrl->i2s_select 0x0000 // bits 1:0 // example 3: linein -> hp_out // select linein as the input to hp_out modify chip_ana_ctrl->select_hp 0x0001 // bit 6 7.2.4 digital audio processor configuration to avoid any pops/clicks, the outputs should be muted during these chip configuration steps. refer to section 7.2.6 for volume and mute control. // enable dap block // note: dap will be in a pass-through mode if none of dap // sub-blocks are enabled. modify dap_control->dap_en 0x0001 // bit 0 7.2.4.1 dual input mixer these programming steps are needed only if dual input mixer feature is used. // enable dual input mixer modify dap_control->mix_en 0x0001 // bit 4 // note: this example assumes mix level of main and mix // channels as 100% and 50% respectively
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 45 preliminary?subject to change without notice // configure main channel volume to 100% (no change from input // level) write dap_main_chan 0x4000 // configure mix channel volume to 50% (attenuate the mix // input level by half) write dap_mix_chan 0x4000 7.2.4.2 sgtl surround the sgtl surround on/off function will be typically controlled by the end-user. end-user driven programming steps are shown in section 7.3. the default width_control of 4 should be appr opriate for most applications. this optional programming step shows how to configure a different width value. // configure the surround width // (0x0 = least width, 0x7 = most width). this example shows // a width setting of 5 modify dap_sgtl_surround->width_control 0x0005 // bits 6:4 7.2.4.3 sgtl bass enhance the sgtl bass enhance on/off function will be typically controlled by the end-user. end-user driven programming steps are shown in section 7.3. the default lr_level value of 0x0005 results in no change in the input signa l level and bass_level value of 0x001f adds some harmonic boost to the main signal. the default settings should work for most applications. this optional programming step shows how to configure a different value. // gain up the input signal level modify dap_bass_enhance_ctrl->lr_level 0x0002 // bits 7:4 // add harmonic boost modify dap_bass_enhance_ctrl->bass_level 0x003f); // bits 6:0 7.2.4.4 7-band parametric eq / 5-band graphic eq / tone control only one audio eq block can be used at a given time. the psuedocode in this section shows how to select each block. some parameters of the audio eq will typically be controlled by end-user. e nd-user driven programming steps are shown in section 7.3. // 7-band peq mode // select 7-band peq mode and enable 7 peq filters write dap_audio_eq 0x0001 write dap_peq 0x0007 // tone control mode write dap_audio_eq 0x0002 // 5-band geq mode write dap_audio_eq 0x0003
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 46 freescale semiconductor preliminary?subject to change without notice 7.2.4.5 automatic volume control (avc) the avc on/off function will be typically controlled by the end-user. end-user driven programming steps are shown in section 7.3. the default configuration of the avc should work fo r most applications. however, the following example shows how to change the configuration if needed. // configure threshold to -18db write dap_avc_threshold 0x0a40 // configure attack rate to 16db/s write dap_avc_attack 0x0014 // configure decay rate to 2db/s write dap_avc_decay 0x0028 7.2.5 i2s configuration by default the i2s port on the chip is configured for 24-bits of data in i2s format with sclk set for 64*fs. this can be modified by setting various bit-fields in chip_i2s_ctrl register. 7.2.6 volume control the outputs should be unmuted after a ll the configuration is complete. //---------------- input volume control--------------------- // configure adc left and right analog volume to desired default. // example shows volume of 0db write chip_ana_adc_ctrl 0x0000 // configure mic gain if needed. example shows gain of 20db modify chip_mic_ctrl->gain 0x0001 // bits 1:0 //---------------- volume and mute control--------------------- // configure hp_out left and right volume to minimum, unmute // hp_out and ramp the volume up to desired volume. write chip_ana_hp_ctrl 0x7f7f modify chip_ana_ctrl->mute_hp 0x0000 // bit 5 // code assumes that left and right volumes are set to same value // so it only uses the left volume for the calculations uscurrentvolleft = 0x7f; usnewvolleft = usnewvol & 0xff; usnumsteps = usnewvolleft - uscurrentvolleft; if (usnumsteps == 0) return; // ramp up for (int i = 0; i < usnumsteps; i++ ) { ++uscurrentvolleft; uscurrentvol = (uscurrentvolleft << 8) | (uscurrentvolleft); write chip_ana_hp_ctrl uscurrentvol; } // lineout and dac volume control
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 47 preliminary?subject to change without notice modify chip_ana_ctrl->mute_lo 0x0000 // bit 8 // configure dac left and right digital volume. example shows // volume of 0db write chip_dac_vol 0x3c3c modify chip_adcdac_ctrl->dac_mute_left 0x0000 // bit 2 modify chip_adcdac_ctrl->dac_mute_right 0x0000 // bit 3 // unmute adc modify chip_ana_ctrl->mute_adc 0x0000 // bit 0 7.3 end-user driven chip configuration end-users will control features like volume up/down, audio eq parameters such as bass and treble. this will require programming the chip without introducing any pops/clicks or any disturbance to the output. this section shows examples on how to program these features. 7.3.1 volume and mute control refer to section 7.2.6 for examples on how to pr ogram volume when end-user changes the volume or mutes/unmutes output. note that the dac volume ramp is automatically handled by the chip. 7.3.2 7-band peq preset selection this programming example shows how to load the filter coefficients when the end-user changes peq presets such as rock, speech, classical etc. // load the 5 coefficients for each band and write them to // appropriate filter address. repeat this for all enabled // filters (this example shows 7 filters) for (i = 0; i < 7; i++) { // note that each 20-bit coefficient is broken into 16-bit msb // (unsigned short usxxmsb) and 4-bit lsb (unsigned short // usxxlsb) write dap_coef_wr_b0_lsb usb0msb[i] write dap_coef_wr_b0_msb usb0lsb[i] write dap_coef_wr_b1_lsb usb1msb[i] write dap_coef_wr_b1_msb usb1lsb[i] write dap_coef_wr_b2_lsb usb2msb[i] write dap_coef_wr_b2_msb usb2lsb[i] write dap_coef_wr_a1_lsb usa1msb[i] write dap_coef_wr_a1_msb usa1lsb[i] write dap_coef_wr_a2_lsb usa2msb[i] write dap_coef_wr_a2_msb usa2lsb[i] // set the index of the filter (bits 7:0) and load the // coefficients modify dap_filter_coef_access->index (0x0101 + i) // bit 8 } 7.3.3 5-band geq volume change this programming example shows how to program the geq volume when end-user changes the volume on any of the 5 bands.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 48 freescale semiconductor preliminary?subject to change without notice geq volume should be ramped in 0.5 db steps in order to avoid any pops. the example assumes that volume is ramped on band 0. other bands can be programmed similarly. // read current volume set on band 0 uscurrentvol = read dap_audio_eq_bass_band0 // convert the new volume to hex value usnewvol = 4*dnewvoldb + 47; // calculate the number of steps usnumsteps = abs(usnewvol - uscurrentvol); if (usnumsteps == 0) return; for (int i = 0; i++; usnumsteps ) { if (usnewvol > uscurrentvol) ++uscurrentvol; else --uscurrentvol; write dap_audio_eq_bass_band0 uscurrentvol; } 7.3.4 tone control - bass and treble change this programming example shows how to program the tone control bass and treble when end-user changes it on the fly. tone control bass and treble volume should be ramped in 0.5 db steps in order to avoid any pops. the example assumes that treble is changed to a new value. bass can be programmed similarly. // read current treble value uscurrentval = read dap_audio_eq_treble_band4 // convert the new treble value to hex value usnewval = 4*dnewvaldb + 47; // calculate the number of steps usnumsteps = abs(usnewval - uscurrentval); if (usnumsteps == 0) return; for (int i = 0; i++; usnumsteps ) { if (usnewval > uscurrentval) ++uscurrentval; else --uscurrentval; write dap_audio_eq_treble_band4 uscurrentval; } 7.3.5 sgtl surround on/off this programming example shows how to program the surround when end-user turns it on/off on his device.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 49 preliminary?subject to change without notice the surround width should be ramped up to highest va lue before enabling/disabling the surround to avoid any pops. // read current surround width value // width_control bits 6:4 usoriginalval = (read dap_sgtl_surround >> 4) && 0x0003; usnextval = usoriginalval; // ramp up the width to maximum value of 7 for (int i = 0; i++; (7 - usoriginalval) { ++usnextval; modify dap_sgtl_surround->width_control usnextval; } // enable (to disable, write 0x0000) surround // select bits 1:0 modify dap_sgtl_surround->select 0x0003; // ramp down the width to original value for (int i = 0; i++; (7 - usoriginalval) { --usnextval; modify dap_sgtl_surround->width_control usnextval; } 7.3.6 bass enhance on/off this programming example shows how to program the bass enhance on/off when end-user turns it on/off on his device. the bass level should be ramped down to the lowest bass before bass enhance feature is turned on/off. // read current bass level value // bass_level bits 6:0 usoriginalval = read dap_bass_enhance_ctrl && 0x007f; usnextval = usoriginalval; // ramp bass level to lowest bass (lowest bass = 0x007f) usnumsteps = abs(0x007f - usoriginalval); for (int i = 0; i++; usnumsteps ) { ++usnextval; modify dap_bass_enhance_ctrl->bass_level usnextval; } // enable (to disable, write 0x0000) bass enhance // en bit 0 modify dap_bass_enhance->en 0x0001; // ramp bass level back to original value for (int i = 0; i++; usnumsteps ) { --usnextval; modify dap_bass_enhance_ctrl->bass_level usnextval; }
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 50 freescale semiconductor preliminary?subject to change without notice 7.3.7 automatic volume control (avc) on/off this programming example shows how to program the avc on/off when end-user turns it on/off on his device. // enable avc (to disable, write 0x0000) modify dap_avc_ctrl->en 0x0001 // bit 0
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 51 preliminary?subject to change without notice 8.0 register descriptions 8.1 chip_id - address = 0x0000 8.2 chip_dig_power - address = 0x0002 1514131211109876543210 partid revid bits field rw reset definition 15:8 partid ro 0xa0 sgtl5000 part id - 0xa0 - 8 bit identifier for sgtl5000 7:0 revid ro 0x00 sgtl5000 revision id - 0xhh - revision number for sgtl5000. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd adc_powerup dac_powerup dap_powerup rsvd i2s_out_powerup i2s_in_powerup bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6 adc_powerup rw 0x0 enable/disable the adc block, both digital and analog 0x0 = disable 0x1 = enable 5 dac_powerup rw 0x0 enable/disable the dac block, both analog and digital 0x0 = disable 0x1 = enable 4 dap_powerup rw 0x0 enable/disable the dap block 0x0 = disable 0x1 = enable 3:2 rsvd rw 0x0 reserved 1 i2s_out_powerup rw 0x0 enable/disable the i2s data output 0x0 = disable 0x1 = enable 0 i2s_in_powerup rw 0x0 enable/disable the i2s data input 0x0 = disable 0x1 = enable
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 52 freescale semiconductor preliminary?subject to change without notice 8.3 chip_clk_ctrl - address = 0x0004 8.4 chip_i2s_ctrl - address = 0x0006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd rate_mode sys_fs mclk_freq bits field rw reset definition 15:6 rsvd ro 0x0 reserved 5:4 rate_mode rw 0x0 sets the sample rate mode. mclk_freq is still specified relative to the rate in sys_fs 0x0 = sys_fs specifies the rate 0x1 = rate is 1/2 of the sys_fs rate 0x2 = rate is 1/4 of the sys_fs rate 0x3 = rate is 1/6 of the sys_fs rate 3:2 sys_fs rw 0x2 sets the internal system sample rate 0x0 = 32 khz 0x1 = 44.1 khz 0x2 = 48 khz 0x3 = 96 khz 1:0 mclk_freq rw 0x0 identifies incoming sys_mclk frequency and if the pll should be used 0x0 = 256*fs 0x1 = 384*fs 0x2 = 512*fs 0x3 = use pll the 0x3 (use pll) setting must be used if the sys_mclk is not a standard multiple of fs (256, 384 or 512). this setting can also be used if sys_mclk is a standard multiple of fs. before this field is set to 0x3 (use pll), the pll must be powered up by setting chip_ana_power->pll_powerup and chip_ana_power->vcoamp_powerup. also, the pll dividers must be calculated based on the external mclk rate and chip_pll_ctrl register must be set (see chip_pll_ctrl register description details on how to calculate the divisors). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd sclkfreq ms sclk_inv dlen i2s_mode lralign lrpol bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 sclkfreq rw 0x0 sets frequency of i2s_sclk when in master mode (ms=1). when in slave mode (ms=0), this field must be set appropriately to match sclk input rate. 0x0 = 64fs 0x1 = 32fs - not supported for rj mode (i2s_mode = 1)
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 53 preliminary?subject to change without notice 8.5 chip_sss_ctrl - address = 0x000a 7 ms rw 0x0 configures master or slave of i2s_lrclk and i2s_sclk. 0x0 = slave: i2s_lrclk and i2s_sclk are inputs 0x1 = master: i2s_lrclk and i2s_sclk are outputs note: if the pll is used (chip_clk_ctrl->mclk_freq==0x3), the sgtl5000 must be a master of the i2s port (ms==1) 6 sclk_inv rw 0x0 sets the edge that data (input and output) is clocked in on for i2s_sclk 0x0 = data is valid on rising edge of i2s_sclk 0x1 = data is valid on falling edge of i2s_sclk 5:4 dlen rw 0x1 i2s data length 0x0 = 32 bits (only valid when sclkfreq=0), not valid for right justified mode 0x1 = 24 bits (only valid when sclkfreq=0) 0x2 = 20 bits 0x3 = 16 bits 3:2 i2s_mode rw 0x0 sets the mode for the i2s port 0x0 = i2s mode or left justified (use lralign to select) 0x1 = right justified mode 0x2 = pcm format a/b 0x3 = reserved 1 lralign rw 0x0 i2s_lrclk alignment to data word. not used for right justified mode 0x0 = data word starts 1 i2s_sclk delay after i2s_lrclk transition (i2s format, pcm format a) 0x1 = data word starts after i2s_lrclk transition (left justified format, pcm format b) 0 lrpol rw 0x0 i2s_lrclk polarity when data is presented. 0x0 = i2s_lrclk = 0 - left, 1 - right 1x0 = i2s_lrclk = 0 - right, 1 - left the left subframe should be presented first regardless of the setting of lrpol. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd dap_mix_lrswap dap_lrswap dac_lrswap rsvd i2s_lrswap dap_mix_select dap_select dac_select rsvd i2s_select bits field rw reset definition 15 rsvd rw 0x0 reserved 14 dap_mix_lrswap rw 0x0 dap mixer input swap 0x0 = normal operation 0x1 = left and right channels for the dap mixer input will be swapped. 13 dap_lrswap rw 0x0 dap input swap 0x0 = normal operation 0x1 = left and right channels for the dap input will be swapped 12 dac_lrswap rw 0x0 dac input swap 0x0 = normal operation 0x1 = left and right channels for the dac will be swapped 11 rsvd rw 0x0 reserved bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 54 freescale semiconductor preliminary?subject to change without notice 8.6 chip_adcdac_ctrl - address = 0x000e 10 i2s_lrswap rw 0x0 i2s_dout swap 0x0 = normal operation 0x1 = left and right channels for the i2s_dout will be swapped 9:8 dap_mix_select rw 0x0 select data source for dap mixer 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = reserved 7:6 dap_select rw 0x0 select data source for dap 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = reserved 5:4 dac_select rw 0x1 select data source for dac 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = dap 3:2 rsvd rw 0x0 reserved 1:0 i2s_select wo 0x0 select data source for i2s_dout 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = dap 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd vol_busy_dac_right vol_busy_dac_left rsvd vol_ramp_en vol_expo_ramp rsvd dac_mute_right dac_mute_left adc_hpf_freeze adc_hpf_bypass bits field rw reset definition 15:14 rsvd ro 0x0 reserved 13 vol_busy_dac_right ro 0x0 volume busy dac right 0x0 = ready 0x1 = busy - this indicates the channel has not reached its programmed volume/mute level 12 vol_busy_dac_left ro 0x0 volume busy dac left 0x0 = ready 0x1 = busy - this indicates the channel has not reached its programmed volume/mute level 11:10 rsvd ro 0x0 reserved bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 55 preliminary?subject to change without notice 8.7 chip_dac_vol - address = 0x0010 9 vol_ramp_en rw 0x1 volume ramp enable 0x0 = disables volume ramp. new volume settings will take immediate effect without a ramp 0x1 = enables volume ramp this field affects dac_vol. the volume ramp effects both volume settings and mute. when set to 1 a soft mute is enabled. 8 vol_expo_ramp rw 0x0 exponential volume ramp enable 0x0 = linear ramp over top 4 volume octaves 0x1 = exponential ramp over full volume range this bit only takes effect if vol_ramp_en is 1. 7:4 rsvd rw 0x0 reserved 3 dac_mute_right rw 0x1 dac right mute 0x0 = unmute 0x1 = muted if vol_ramp_en = 1, this is a soft mute. 2 dac_mute_left rw 0x1 dac left mute 0x0 = unmute 0x1 = muted if vol_ramp_en = 1, this is a soft mute. 1 adc_hpf_freeze rw 0x0 adc high pass filter freeze 0x0 = normal operation 0x1 = freeze the adc high-pass filter offset register. the offset will continue to be subtracted from the adc data stream. 0 adc_hpf_bypass rw 0x0 adc high pass filter bypass 0x0 = normal operation 0x1 = bypassed and offset not updated 1514131211109876543210 dac_vol_right dac_vol_left bits field rw reset definition 15:8 dac_vol_right rw 0x3c dac right channel volume set the right channel dac volume with 0.5017 db steps from 0 to -90 db 0x3b and less = reserved 0x3c = 0 db 0x3d = -0.5 db 0xf0 = -90 db 0xfc and greater = muted if vol_ramp_en = 1, there will be an automatic ramp to the new volume setting. bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 56 freescale semiconductor preliminary?subject to change without notice 8.8 chip_pad_strength - address = 0x0014 7:0 dac_vol_left rw 0x3c dac left channel volume set the left channel dac volume with 0.5017 db steps from 0 to -90 db 0x3b and less = reserved 0x3c = 0 db 0x3d = -0.5 db 0xf0 = -90 db 0xfc and greater = muted if vol_ramp_en = 1, there will be an automatic ramp to the new volume setting. 1514131211109876543210 rsvd i2s_lrclk i2s_sclk i2s_dout ctrl_data ctrl_clk bits field rw reset definition 15:14 rsvd rw 0x0 reserved 9:8 i2s_lrclk rw 0x1 i2s lrclk pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 7:6 i2s_sclk rw 0x1 i2s sclk pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 5:4 i2s_dout rw 0x1 i2c dout pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 3:2 ctrl_data rw 0x3 i2c data pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 57 preliminary?subject to change without notice 8.9 chip_ana_adc_ctrl - address = 0x0020 1:0 ctrl_clk rw 0x3 i2c clk pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd adc_vol_m6db adc_vol_right adc_vol_left bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 adc_vol_m6db rw 0x0 adc volume range reduction this bit shifts both right and left analog adc volume range down by 6db. 0x0 = no change in adc range 0x1 = adc range reduced by 6db 7:4 adc_vol_right rw 0x0 adc right channel volume right channel analog adc volume control in 1.5db steps. 0x0 = 0db 0x1 = +1.5db ... 0xf = +22.5db this range will be -6db to +16.5db if adc_vol_m6db is set to 1. 3:0 adc_vol_left rw 0x0 adc left channel volume left channel analog adc volume control in 1.5db steps. 0x0 = 0db 0x1 = +1.5db ... 0xf = +22.5db this range will be -6db to +16.5db if adc_vol_m6db is set to 1. bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 58 freescale semiconductor preliminary?subject to change without notice 8.10 chip_ana_hp_ctrl - address = 0x0022 8.11 chip_ana_ctrl - address = 0x0024 this is an analog control register that includes mute s, input selects, and zero-cross-detectors for the adc, headphone, and lineout. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd hp_vol_right rsvd hp_vol_left bits field rw reset definition 15 rsvd ro 0x0 reserved 14:8 hp_vol_right rw 0x18 headphone right channel volume right channel headphone volume control with 0.5db steps. 0x00 = +12db 0x01 = +11.5db 0x18 = 0db ... 0x7f = -51.5db 7 rsvd ro 0x0 reserved 6:0 hp_vol_left rw 0x18 headphone left channel volume left channel headphone volume control with 0.5db steps. 0x00 = +12db 0x01 = +11.5db 0x18 = 0db ... 0x7f = -51.5db 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mute_lo rsvd select_hp en_zcd_hp mute_hp rsvd select_adc en_zcd_adc mute_adc bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 mute_lo rw 0x1 lineout mute 0x0 = unmute 0x1 = mute 7 rsvd ro 0x0 reserved 6 select_hp rw 0x0 select the headphone input. 0x0 = dac 0x1 = line in
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 59 preliminary?subject to change without notice 8.12 chip_linreg_ctrl - address = 0x0026 this register controls the vddd linear regulator and the charge pump. 5 en_zcd_hp rw 0x0 enable the headphone zero cross detector (zcd) 0x0 = hp zcd disabled 0x1 = hp zcd enabled 4 mute_hp rw 0x1 mute the headphone outputs 0x0 = unmute 0x1 = mute 3 rsvd ro 0x0 reserved 2 select_adc rw 0x0 select the adc input. 0x0 = microphone 0x1 = line in 1 en_zcd_adc rw 0x0 enable the adc analog zero cross detector (zcd) 0x0 = adc zcd disabled 0x1 = adc zcd enabled 0 mute_adc rw 0x1 mute the adc analog volume 0x0 = unmute 0x1 = mute 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd vddc_man_assn vddc_assn_ovrd rsvd d_programming bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6 vddc_man_assn rw 0x0 determines chargepump source when vddc_assn_ovrd is set. 0x0 = vdda 0x1 = vddio 5 vddc_assn_ovrd rw 0x0 chargepump source assignment override 0x0 = chargepump source is automatically assigned based on higher of vdda and vddio 0x1 = the source of chargepump is manually assigned by vddc_man_assn if vddio and vdda are both the same and greater than 3.1v, vddc_assn_ovrd and vddc_man_assn should be used to manually assign vddio as the source for chargepump. 4 rsvd rw 0x0 reserved 3:0 d_programming rw 0x0 sets the vddd linear regulator output voltage in 50 mv steps. must clear pwd_linreg_d bit to enable this linear regulator. 0x0=1.60 0xf=0.85 bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 60 freescale semiconductor preliminary?subject to change without notice 8.13 chip_ref_ctrl - address = 0x0028 this register controls the bandgap reference bias voltage and currents. 8.14 chip_mic_ctrl - address = 0x002a this register controls the microphone gain and the internal microphone biasing circuitry. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd vag _val bias_ctrl small_pop bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8:4 vag_val rw 0x0 analog ground voltage control these bits control the analog ground voltage in 25mv steps. this should usually be set to vdda/2 or lower for best performance (maximum output swing at minimum thd). this vag reference is also used for the dac and adc voltage reference. so changing this voltage scales the output swing of the dac and the output signal of the adc. 0x00 = 0.800v 0x1f = 1.575v 3:1 bias_ctrl rw 0x0 bias control these bits adjust the bias currents for all of the analog blocks. by lowering the bias current a lower quiescent power is achieved. it should be noted that this mode can affect performance by 3-4db. 0x0 = nominal 0x1-0x3=+12.5% 0x4=-12.5% 0x5=-25% 0x6=-37.5% 0x7=-50% 0 small_pop rw 0x0 vag ramp control setting this bit slows down the vag ramp from ~200ms to ~400ms to reduce the startup pop, but increases the turn on/off time. 0x0 = normal vag ramp 0x1 = slowdown vag ramp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd bias_resistor rsvd bias_volt rsvd gain bits field rw reset definition 15:10 rsvd ro 0x0 reserved
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 61 preliminary?subject to change without notice 8.15 chip_line_out_ctrl - address = 0x002c 9:8 bias_resistor rw 0x0 mic bias output impedance adjustment controls an adjustable output impedance for the microphone bias. if this is set to zero the micbias block is powered off and the output is high impedance. 0x0 = powered off 0x1 = 2kohm 0x2 = 4kohm 0x3 = 8kohm 7 rsvd ro 0x0 reserved 6:4 bias_volt rw 0x0 mic bias voltage adjustment controls an adjustable bias voltage for the microphone bias amp in 250mv steps. this bias voltage setting should be no more than vdda-200mv for adequate power supply rejection. 0x0 = 1.25v ... 0x7 = 3.00v 3:2 rsvd ro 0x0 reserved 1:0 gain rw 0x0 mic amplifier gain sets the microphone amplifier gain. at 0db setting the thd can be slightly higher than other paths- typically around ~65db. at other gain settings the thd will be better. 0x0 = 0db 0x1 = +20db 0x2 = +30db 0x3 = +40db 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd out_current rsvd lo_vagcntrl bits field rw reset definition 15:12 rsvd ro 0x0 reserved 11:8 out_current rw 0x0 controls the output bias current for the lineout amplifiers. the nominal recommended setting for a 10kohm load with 1nf load cap is 0x3. there are only 5 valid settings: 0x0=0.18ma 0x1=0.27ma 0x3=0.36ma 0x7=0.45ma 0xf=0.54ma 7:6 rsvd ro 0x0 reserved bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 62 freescale semiconductor preliminary?subject to change without notice 8.16 chip_line_out_vol - address = 0x002e 5:0 lo_vagcntrl rw 0x0 lineout amplifier analog ground voltage controls the analog ground voltage for the lineout amplifiers in 25mv steps. this should usually be set to vddio/2. 0x00 = 0.800v ... 0x1f = 1.575v ... 0x23 = 1.675 0x24-0x3f are invalid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd lo_vol_right rsvd lo_vol_left bits field rw reset definition 15:13 rsvd ro 0x0 reserved 12:8 lo_vol_right rw 0x4 lineout right channel volume controls the right channel lineout volume in 0.5db steps. higher codes have more attenuation. see programming information for left channel. 7:5 rsvd ro 0x0 reserved 4:0 lo_vol_left rw 0x4 lineout left channel output level the lo_vol_left is used to normalize the output level of the left line output to full scale based on the values used to set line_out_ctrl -> lo_vagcntrl and chip_ref_ctrl -> vag_val. in general this field should be set to: 40*log((vag_val)/(lo_vagcntrl)) + 15 ta b l e 8 - 1 9 shows suggested values based on typical vddio and vdda voltages. after setting to the nominal voltage, this field can be used to adjust the output level in +/-.5db increments by using values higher or lower than the nominal setting. table 8-19. line out output level values vdda vag_val vddio lo_vagcntrl lo_vol_* 1.8v 0.9 3.3v 1.55 0x06 1.8v 0.9 1.8v 0.9 0x0f 3.3v 1.55 1.8v 0.9 0x19 3.3v 1.55 3.3v 1.55 0x0f bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 63 preliminary?subject to change without notice 8.17 chip_ana_power - address = 0x0030 this register contains all of the powerdown cont rols for the analog blocks. the only other powerdown controls are bias_resistor in the mic_ctrl register and the en_zcd control bits in ana_ctrl. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd dac_mono linreg_simple_powerup startup_powerup vddc_chrgpmp_powerup pll_powerup linreg_d_powerup vcoamp_powerup vag_powerup adc_mono reftop_powerup headphone_powerup dac_powerup capless_headphone_powerup adc_powerup lineout_powerup bits field rw reset definition 15 rsvd rw 0x0 reserved 14 dac_mono rw 0x1 while dac_powerup is set, this allows the dac to be put into left only mono operation for power savings. 0x0 = mono (left only) 0x1 = stereo 13 linreg_simple_powerup rw 0x1 power up the simple (low power) digital supply regulator. after reset, this bit can be cleared if vddd is driven externally or the primary digital lingered is enabled with linreg_d_powerup 0x0 = power down 0x1 = power up 12 startup_powerup rw 0x1 power up the circuitry needed during the power up ramp and reset. after reset this bit can be cleared if vddd is coming from an external source. 0x0 = power down 0x1 = power up 11 vddc_chrgpmp_powerup rw 0x0 power up the vddc chargepump block. if neither vdda or vddio is 3v or larger this bit should be cleared before analog blocks are powered up. 0x0 = power down 0x1 = power up note that for charge pump to function, either the pll must be powered on and programmed correctly (refer to chip_clk_ctrl->mclk_freq description) or the internal oscillator (set clk_top_ctrl->enable_int_osc) must be enabled 10 pll_powerup rw 0x0 pll power up 0x0 = power down 0x1 = power up when cleared, the pll will be turned o ff. this must be set before chip_clk_ctrl -> mclk_freq is programmed to 0x3. the chip_pll_ctrl register must be configured correctly before setting this bit.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 64 freescale semiconductor preliminary?subject to change without notice 8.18 chip_pll_ctrl - address = 0x0032 this register may only be changed after reset, and before pll_powerup is set. 9 linreg_d_powerup rw 0x0 power up the primary vddd linear regulator. 0x0 = power down 0x1 = power up 8 vcoamp_powerup rw 0x0 power up the pll vco amplifier. 0x0 = power down 0x1 = power up 7 vag_powerup rw 0x0 power up the vag reference buffer. setting this bit starts the power up ramp for the headphone and lineout. the headphone (and/or lineout) powerup should be set before clearing this bit. when this bit is cleared the powerdown ramp is started. the headphone (and/or lineout) powerup should stay set until the vag is fully ramped down (200-400ms after clearing this bit). 0x0 = power down 0x1 = power up 6 adc_mono rw 0x1 while adc_powerup is set, this allows the adc to be put into left only mono operation for power savings. this mode is useful when only using the microphone input. 0x0 = mono (left only) 0x1 = stereo 5 reftop_powerup rw 0x1 power up the reference bias currents 0x0 = power down 0x1 = power up this bit can be cleared when the part is a sleep state to minimize analog power. 4 headphone_powerup rw 0x0 power up the headphone amplifiers 0x0 = power down 0x1 = power up 3 dac_powerup rw 0x0 power up the days 0x0 = power down 0x1 = power up 2 capless_headphone_powerup rw 0x0 power up the capless headphone mode 0x0 = power down 0x1 = power up 1 adc_powerup rw 0x0 power up the adcs 0x0 = power down 0x1 = power up 0 lineout_powerup rw 0x0 power up the lineout amplifiers 0x0 = power down 0x1 = power up 1514131211109876543210 int_divisor frac_divisor bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 65 preliminary?subject to change without notice 8.19 chip_clk_top_ctrl - address = 0x0034 miscellaneous controls for the clock block. bits field rw reset definition 15:11 int_divisor rw 0xa this is the integer portion of the pll divisor. to determine the value of this field, use the following calculation: int_divisor = floor(pll_output_freq/input_freq) pll_output_freq = 180.6336 mhz if system sample rate is 44.1 khz else pll_output_freq = 196.608 mhz if system sample rate is not 44.1 khz input_freq = frequency of the external mclk provided if chip_clk_top_ctrl->input_freq_div2 = 0x0 else input_freq = (frequency of the external mclk provided/2) if chip_clk_top_ctrl->input_freq_div2 = 0x1 10:0 frac_divisor rw 0x0 this is the fractional portion of the pll divisor. to determine the value of this field, use the following calculation: frac_divisor = ((pll_output_freq/input_freq) - int_divisor)*2048 pll_output_freq = 180.6336 mhz if system sample rate is 44.1 khz else pll_output_freq = 196.608 mhz if system sample rate is not 44.1 khz input_freq = frequency of the external mclk provided if chip_clk_top_ctrl->input_freq_div2 = 0x0 else input_freq = (frequency of the external mclk provided/2) if chip_clk_top_ctrl->input_freq_div2 = 0x1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd enable_int_osc rsvd input_freq_div2 rsvd bits field rw reset definition 15:12 rsvd ro 0x0 reserved 11 enable_int_osc rw 0x0 setting this bit enables an internal oscillator to be used for the zero cross detectors, the short detect recovery, and the charge pump. this will allow the i2s clock to be shut off while still operating an analog signal path. this bit can be kept on when the i2s clock is enabled, but the i2s clock is more accurate so it is preferred to clear this bit when i2s is present. 10:4 rsvd rw 0x0 reserved 3 input_freq_div2 rw 0x0 sys_mclk divider before pll input 0x0 = pass through 0x1 = sys_mclk is divided by 2 before entering pll this must be set when the input clock is above 17 mhz. this has no effect when the pll is powered down.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 66 freescale semiconductor preliminary?subject to change without notice 8.20 chip_ana_status - address = 0x0036 status bits for analog blocks. 8.21 chip_ana_test2 - address = 0x003a 2:0 rsvd rw 0x0 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd lrshort_sts cshort_sts rsvd pll_is_locked rsvd bits field rw reset definition 15:10 rsvd ro 0x0 reserved 9 lrshort_sts ro 0x0 this bit is high whenever a short is detected on the left or right channel headphone drivers. 0x0 = normal 0x1 = short detected 8 cshort_sts ro 0x0 this bit is high whenever a short is detected on the capless headphone common/center channel driver. 0x0 = normal 0x1 = short detected 7:5 rsvd ro 0x0 reserved 4 pll_is_locked ro 0x0 this bit goes high after the pll is locked. 0x0 = pll is not locked 0x1 = pll is locked 3:0 rsvd ro 0x0 reserved 1514131211109876543210 rsvd lineout_to_vdda spare monomode_dac vco_tune_again lo_pass_mastervag invert_dac_sample_clock invert_dac_data_timing dac_extend_rtz dac_double_i dac_dis_rtz dac_classa invert_adc_sample_clock invert_adc_data_timing adc_lessi adc_ditheroff bits field rw reset definition 15 rsvd ro 0x0 reserved bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 67 preliminary?subject to change without notice 8.22 chip_short_ctrl - address = 0x003c this register contains controls for the headphone short detectors. 14 lineout_to_vdda rw 0x0 changes the lineout amplifier power supply from vddio to vdda. typically lineout should be on the higher power supply. this bit is useful when vdda is ~3.3v and vddio is ~1.8v. 13 spare rw 0x0 spare registers to analog. 12 monomode_dac rw 0x0 copy the left channel dac data to the right channel. this allows both left and right to play from mono dac data. 11 vco_tune_again rw 0x0 when toggled high then low forces the pll vco to retune the number of inverters in the ring oscillator loop. 10 lo_pass_mastervag rw 0x0 tie the main analog vag to the lineout vag. this can improve snr for the lineout when both are the same voltage. 9 invert_dac_sample_clock rw 0x0 change the clock edge used for the dac output sampling. 8 invert_dac_data_timing rw 0x0 change the clock edge used for the digital to analog dac data crossing. 7 dac_extend_rtz rw 0x0 extend the return-to-zero time for the dac. 6 dac_double_i rw 0x0 double the output current of the dac amplifier when it is in class a mode. 5 dac_dis_rtz rw 0x0 turn off the return-to-zero in the dac. in mode cases this will hurt the sndr of the dac. 4 dac_classa rw 0x0 turn off the class ab mode in the dac amplifier. this mode should normally not be used. the output current will not be high enough to support a full scale signal in this mode. 3 invert_adc_sample_clock rw 0x0 change the clock edge used for the adc sampling. 2 invert_adc_data_timing rw 0x0 change the clock edge used for the analog to digital adc data crossing 1 adc_lessi rw 0x0 drops adc bias currents by 20% 0 adc_ditheroff rw 0x0 turns off the adc dithering. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd lvladjr rsvd lvladjl rsvd lvladjc mode_lr mode_cm bits field rw reset definition 15 rsvd ro 0x0 reserved bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 68 freescale semiconductor preliminary?subject to change without notice 14:12 lvladjr rw 0x0 these bits adjust the sensitivity of the right channel headphone short detector in 25ma steps.this trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. this short detect trip point is also effected by the bias current adjustments made by chip_ref_ctrl -> bias_ctrl and by chip_ana_test1 -> hp_iall_adj. 0x3=25ma 0x2=50ma 0x1=75ma 0x0=100ma 0x4=125ma 0x5=150ma 0x6=175ma 0x7=200ma 11 rsvd ro 0x0 reserved 10:8 lvladjl rw 0x0 these bits adjust the sensitivity of the left channel headphone short detector in 25ma steps.this trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. this short detect trip point is also effected by the bias current adjustments made by chip_ref_ctrl -> bias_ctrl and by chip_ana_test1 -> hp_iall_adj. 0x3=25ma 0x2=50ma 0x1=75ma 0x0=100ma 0x4=125ma 0x5=150ma 0x6=175ma 0x7=200ma 7 rsvd ro 0x0 reserved 6:4 lvladjc rw 0x0 these bits adjust the sensitivity of the capless headphone center channel short detector in 50ma steps. this trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. this short detect trip point is also effected by the bias current adjustments chip_ref_ctrl -> bias_ctrl and by chip_ana_test1 -> hp_iall_adj. 0x3=50ma 0x2=100ma 0x1=150ma 0x0=200ma 0x4=250ma 0x5=300ma 0x6=350ma 0x7=400ma 3:2 mode_lr rw 0x0 these bits control the behavior of the short detector for the capless headphone central channel driver. this mode should be set prior to powering up the headphone amplifier. when a short is detected the amplifier output switches to class a mode internally to avoid excessive currents. 0x0 = disable short detector, reset short detect latch, software view non-latched short signal 0x1 = enable short detector and reset the latch at timeout (every ~50ms) 0x2 = this mode is not used/invalid 0x3 = enable short detector with only manual reset (have to return to 0x0 to reset the latch) bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 69 preliminary?subject to change without notice 8.23 dap_control - address = 0x0100 8.24 dap_peq - address = 0x0102 1:0 mode_cm rw 0x0 these bits control the behavior of the short detector for the capless headphone central channel driver. this mode should be set prior to powering up the headphone amplifier. when a short is detected the amplifier output switches to class a mode internally to avoid excessive currents. 0x0 = disable short detector, reset short detect latch, software view non-latched short signal 0x1 = enable short detector and reset the latch at timeout (every ~50ms) 0x2 = enable short detector and auto reset when output voltage rises (preferred mode) 0x3 = enable short detector with only manual reset (have to return to 0x0 to reset the latch) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd mix_en rsvd dap_en bits field rw reset definition 15:5 rsvd ro 0x0 reserved 4 mix_en rw 0x0 enable/disable the dap mixer path 0x0 = disable 0x1 = enable when enabled, dap_en must also be enabled to use the mixer. 3:1 rsvd ro 0x0 reserved 0 dap_en rw 0x0 enable/disable digital audio processing (dap) 0x0 = disable. when disabled, no audio will pass-through. 0x1 = enable. when enabled, audio can pass-through dap even if none of the dap functions are enabled. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd en bits field rw reset definition 15:3 rsvd ro 0x0 reserved 2:0 en rw 0x0 set to enable the peq filters 0x0 = disabled 0x1 = 1 filter enabled 0x2 = 2 filters enabled ..... 0x7 = cascaded 7 filters dap_audio_eq->en bit must be set to 1 in order to enable the peq bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 70 freescale semiconductor preliminary?subject to change without notice 8.25 dap_bass_enhance - address = 0x0104 8.26 dap_bass_enhance_ctrl - address = 0x0106 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd bypass_hpf rsvd cutoff rsvd en bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 bypass_hpf rw 0x0 bypass high pass filter 0x0 = enable high pass filter 0x1 = bypass high pass filter 7 rsvd ro 0x0 reserved 6:4 cutoff rw 0x4 set cut-off frequency 0x0 = 80 hz 0x1 = 100 hz 0x2 = 125 hz 0x3 = 150 hz 0x4 = 175 hz 0x5 = 200 hz 0x6 = 225 hz 3:1 rsvd ro 0x0 reserved 0 en rw 0x0 enable/disable bass enhance 0x0 = disable 0x1 = enable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd lr_level rsvd bass_level bits field rw reset definition 15:14 rsvd ro 0x0 reserved 13:8 lr_level rw 0x5 left/right mix level control 0x00= +6db for main channel ...... 0x3f= least l/r channel level 7 rsvd ro 0x0 6:0 bass_level rw 0x1f bass harmonic level control 0x00= most harmonic boost ...... 0x7f=least harmonic boost
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 71 preliminary?subject to change without notice 8.27 dap_audio_eq - address = 0x0108 8.28 dap_sgtl_surround - address = 0x010a 8.29 dap_filter_coef_access - address = 0x010c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd en bits field rw reset definition 15:2 rsvd ro 0x0 reserved 1:0 en rw 0x0 selects between peq/geq/tone control and enables it. 0x0 = disabled. 0x1 = enable peq. note: dap_peq->en bit must also be set to the desired number of filters (bands) in order for the peq to be enabled. 0x2 = enable tone control 0x3 = enable 5 band geq 1514131211109876543210 rsvd width_control rsvd select bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:4 width_cont rol rw 0x4 sgtl surround width control - the width control changes the perceived width of the sound field. 0x0 = least width ...... 0x7 = most width 3:2 rsvd ro 0x0 reserved 1:0 select rw 0x0 sgtl surround selection 0x0 = disabled 0x1 = disabled 0x2 = mono input enable 0x3 = stereo input enable 1514131211109876543210 rsvd wr index
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 72 freescale semiconductor preliminary?subject to change without notice 8.30 dap_coef_wr_b0_msb - address = 0x010e bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 wr wo 0x0 when set, the coefficients written in the ten coefficient data registers will be loaded into the filter specified by index 7:0 index rw 0x0 specifies the index for each of the seven bands of the filter coefficient that needs to be written to. each filter has 5 coefficients that need to be loaded into the 10 coefficient registers (msb,lsb) before setting the index and wr bit. steps to write coefficients: 1. write the five 20-bit coefficient values to dap_coef_wr_xx_msb and dap_coef_wr_xx_lsb registers (xx= b0,b1,b2,a1,a2) 2. set index of the coefficient from the table below. 3. set the wr bit to load the coefficient. note: steps 2 and 3 can be performed with a single write to dap_filter_coef_access register. coefficient address: band 0 = 0x00 band 1 = 0x01 band 2 = 0x02 band 3 = 0x03 band 4 = 0x04 ... band 7 = 0x06 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit_19 bit_18 bit_17 bit_16 bit_15 bit_14 bit_13 bit_12 bit_11 bit_10 bit_9 bit_8 bit_7 bit_6 bit_5 bit_4 bits field rw reset definition 15 bit_19 wo 0x0 most significant 16-bits of the 20-bit filter coefficient that needs to be written 14 bit_18 wo 0x0 13 bit_17 wo 0x0 12 bit_16 wo 0x0 11 bit_15 wo 0x0 10 bit_14 wo 0x0 9 bit_13 wo 0x0 8 bit_12 wo 0x0 7 bit_11 wo 0x0 6 bit_10 wo 0x0 5b i t _ 9w o0 x 0 4b i t _ 8w o0 x 0 3b i t _ 7w o0 x 0 2b i t _ 6w o0 x 0 1b i t _ 5w o0 x 0 0b i t _ 4w o0 x 0
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 73 preliminary?subject to change without notice 8.31 dap_coef_wr_b0_lsb - address = 0x0110 8.32 dap_audio_eq_bass_band0 - address = 0x0116 115 hz 8.33 dap_audio_eq_band1 - address = 0x0118 330 hz 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd bit_3 bit_2 bit_1 bit_0 bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3 bit_3 wo 0x0 least significant 4 bits of the 20-bit filter coefficient that needs to be written. 2 bit_2 wo 0x0 1 bit_1 wo 0x0 0 bit_0 wo 0x0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets tone control bass/geq band0 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets geq band1 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 74 freescale semiconductor preliminary?subject to change without notice 8.34 dap_audio_eq_band2 - address = 0x011a 990 hz 8.35 dap_audio_eq_band3 - address = 0x011c 3000 hz 8.36 dap_audio_eq_treble_band4 - address = 0x011e 9900 hz 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets geq band2 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets geq band3 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 75 preliminary?subject to change without notice 8.37 dap_main_chan - address = 0x0120 sets the main channel volume level. 8.38 dap_mix_chan - address = 0x0122 sets the mix channel volume level. 8.39 dap_avc_ctrl - address = 0x0124 6:0 volume rw 0x2f sets tone control treble/geq band4 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 vol bits field rw reset definition 15:0 vol rw 0x8000 dap main channel volume 0xffff = 200% 0x8000 (default) = 100% 0x0000 = 0% 1514131211109876543210 vol bits field rw reset definition 15:0 vol rw 0x0000 dap mix channel volume 0xffff = 200% 0x8000 = 100% 0x0000 (default) = 0% 1514131211109876543210 rsvd rsvd max_gain rsvd lbi_response rsvd hard_limit_en rsvd en bits field rw reset definition 15 rsvd ro 0x0 reserved 14 rsvd rw 0x1 reserved. bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 76 freescale semiconductor preliminary?subject to change without notice 8.40 dap_avc_threshold - address = 0x0126 8.41 dap_avc_attack - address = 0x0128 13:12 max_gain rw 0x1 maximum gain that can be applied by the avc in expander mode. 0x0 = 0db gain 0x1 = 6db of gain 0x2 = 12db of gain 11:10 rsvd ro 0x0 reserved 9:8 lbi_response rw 0x1 integrator response 0x0 = 0ms lbi 0x1 = 25ms lbi 0x2 = 50ms lbi 0x3 = 100ms lbi 7:6 rsvd ro 0x0 reserved 5 hard_limit_en rw 0x0 enable hard limiter mode 0x0 = hard limit disabled. avc compressor/expander is enabled. 0x1 = hard limit enabled. the signal is limited to the programmed threshold. (signal saturates at the threshold) 4:1 rsvd ro 0x0 reserved 0 en rw 0x0 enable/disable avc 0x0 = disable 0x1 = enable 1514131211109876543210 thresh bits field rw reset definition 15:0 thresh rw 0x1473 avc threshold value threshold is programmable. use the following formula to calculate hex value: hex value = ((10^(threshold_db/20))*0.636)*2^15 threshold can be set in the range of 0db to -96 db example values: 0x1473 = set threshold to -12db 0x0a40 = set threshold to -18db 1514131211109876543210 rsvd rate bits field rw reset definition 15:12 rsvd ro 0x0 reserved bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 77 preliminary?subject to change without notice 8.42 dap_avc_decay - address = 0x012a 8.43 dap_coef_wr_b1_msb - address = 0x012c 11:0 rate rw 0x28 avc attack rate this is the rate at which the avc will apply attenuation to the signal to bring it to the threshold level. avc attack rate is programmable. to use a custom rate, use the formula below to convert from db/s to hex value: hex value = (1 - (10^(-(rate_dbs/( 20*sys_fs)))) * 2^19 where, sys_fs is the system sample rate configured in chip_clk_ctrl register. example values: 0x28 = 32db/s 0x10 = 8db/s 0x05 = 4db/s 0x03 = 2db/s 1514131211109876543210 rsvd rate bits field rw reset definition 15:12 rsvd ro 0x0 reserved 11:0 rate rw 0x050 avc decay rate this is the rate at which the avc releases the attenuation previously applied to the signal during attack. avc decay rate is programmable. to use a custom rate, use the formula below to convert from db/s to hex value: hex value = (1 - (10^(-(rate_dbs/( 20*sys_fs)))) * 2^23 where, sys_fs is the system sample rate configured in chip_clk_ctrl register. example values: 0x284 = 32db/s 0x0a0 = 8db/s 0x050 = 4db/s 0x028 = 2db/s 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20-bit filter coefficient that needs to be written bits field rw reset definition
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 78 freescale semiconductor preliminary?subject to change without notice 8.44 dap_coef_wr_b1_lsb - address = 0x012e 8.45 dap_coef_wr_b2_msb - address = 0x0130 8.46 dap_coef_wr_b2_lsb - address = 0x0132 8.47 dap_coef_wr_a1_msb - address = 0x0134 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20-bit filter coefficient that needs to be written. 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20-bit filter coefficient that needs to be written 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20-bit filter coefficient that needs to be written. 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20-bit filter coefficient that needs to be written
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 freescale semiconductor 79 preliminary?subject to change without notice 8.48 dap_coef_wr_a1_lsb - address = 0x0136 8.49 dap_coef_wr_a2_msb - address = 0x0138 8.50 dap_coef_wr_a2_lsb - address = 0x013a 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20-bit filter coefficient that needs to be written. 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20-bit filter coefficient that needs to be written 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20-bit filter coefficient that needs to be written.
sgtl 5000 - low power stereo codec with headphone amplifier, rev. 4 82 freescale semiconductor preliminary?subject to change without notice 9.0 revision history for questions or issues, please go to http://www.freescale.com and log in. enter a service request and reference stmp host support in the title or description. revision description 1.0 2 september 2008 - initial internal release. 2.0 25 november 2008 - update to the freescale style and format. - initial public release. 3.0 7 january 2009 - update to the chip_sss_ctrl register bit fields. 4.0 13 february 2009 - update to the supported sampling frequencies.

▲Up To Search▲

Price & Availability of SGTL5000XNLA3R2

	To Download SGTL5000XNLA3R2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .