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low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 19 http://www.cypress.com approved product c9815 product features ? meets intel?s 133mhz/sdram chipset specification ? 3 copies of cpu clock (cpu[0:1] and cpu2_itp) ? 9 copies of sdram clock (sdram[0:7] and dclk) ? 7 copies of pci clock ? 3 copies of 3v66 clock ? 2 copies of ioapic clock ? 1 ref clock ? 1 usb clock (non ssc) ? 1 dot clock (non ssc) ? cypress spread spectrum for best emi reduction ? smbus support with read back ? 56 pin ssop package block diagram fig.1 frequency table (mhz) sel2 sel1 sel0 cpu sdram pci x 0 0 tri-state x 0 1 test mode 0 1 0 66.6 mhz 100 mhz* 33.3 0 1 1 100 mhz 100 mhz* 33.3 1 1 0 133.3 mhz 133.3 mhz 33.3 1 1 1 133.3 mhz 100 mhz* 33.3 table 1 note: the following clocks remain fixed frequencies except in test mode: 3v66=66.6mhz, usb/dot=48mhz, ref=14.318mhz and ioapic=33.3mhz. *smbus programmable to 133 mhz, byte 3, bit 0 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 xin vdd sel1 xout vss vss 3v66_0 3v66_1 3v66_2(agp) pci0(ich) pci1 vss pci3 vss vdd pci2 pci4 pci5 vdd vdda vssa vss vdd dclk vss sdram7 sdram6 sdram5 vdds vss sdram2 vdds sdram0 vss cpu2(itp) cpu1 sdram4 sdram3 sdram1 vss vddc cpu0 vddi ioapic1 ioapic0 vss pci6 c 9 8 1 5 25 26 27 ref/sel2 usb dot 28 vdd sel0 sdata sclk pd# 49 50 51 52 53 54 55 56 vdd vddc vdds vdd vdd vddi vdd vdd vdd pll1 rin i2c-clk i2c-data apic s1 pwr_dwn# s0 cpu sdram 3v66 pci s2 pll2 rin 48 pd# i2c-clk i2c-data 300k 36pf 36pf 3 9 2 8 2 1 1 1 xin xout cpu(0:2) sdram(0:7), dclk 3v66(0:2) pci(0:6) ioapic(0:1) sdata sclk pd# sel0 sel1 dot usb ref / sel2
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 19 http://www.cypress.com approved product c9815 pin description pin no. pin name pwr i/o description 1 sel2/ref vdd i/o this is a bi-directional pin (see app. note, p.5). at power up, it is an input pin sel2 for selecting the cpu/sdram frequencies (see table 1 p.1). when the power reaches the rail, the state of sel2 is latched, and this pin becomes ref, a buffer output of the signal applied at xin, typically 14.318mhz. this pin has an internal pull-down. typical 50k ? (range 20k ? to 70k ? ) 3 xin vdd i on-chip reference oscillator input pin. requires either an external parallel resonant crystal (nominally 14.318 mhz) or externally generated reference signal 4 xout vdd o on-chip reference oscillator pin. drives an external parallel resonant crystal. when an externally generated reference signal is used at xin, this pin remains unconnected. 12,13,15, 16,18,19, 20 pci0_ich pci(1..6) vdd o 3.3v pci clock outputs. they are synchronous to cpu clocks. see fig.3, page4. 7, 8, 9 3v66(0:2) vdd o 3.3v fixed 66.6 mhz clock outputs. see fig.3 page 4. 25 usb vdd o 3.3v fixed 48 mhz clock outputs 26 dot vdd o 3.3v fixed 48 mhz clock outputs 28, 29 sel(0,1) vdd i 3.3v lvttl inputs for logic selection. this pin has an internal pull-up. typical 250k ? (range 200k ? to 500k ? ) 30 sdata vdd i/o serial data input pin. conforms to the smbus specification of a slave receive/transmit device. this pin is an input when receiving data. it is an open drain output when acknowledging or transmitting data. see smbus function description, pp.6,7,8. 31 sclk vdd i serial clock input pin. conforms to the smbus specification. 32 pd# vdd i 3.3v lvttl compatible input. when held low, the device enters a power down mode. see description page 3. this pin has an internal pull-up. typical 250k ? (range 200k ? to 500k ? ) 34 dclk vdd o 3.3v sdram feedback clock. see table1, p.1 for frequency selection. see fig.3, page 4 for timing relationship. 36,37,39,40, 42,43,45, 46 sdram(7..0) vdds o 3.3v sdram dimm clocks. see table1, p.1 for frequency selection. see fig.3, page 4 for timing relationship. 49, 50, 52 cpu(2)_itp,c pu(1,0) vddc o 2.5v host clock outputs. see table 1 p. 1 for frequency selection. 54, 55 ioapic(1,0) vddi o 2.5v ioapic clock outputs. see fig.3 p.4 for timing relationship. 2,10, 11, 21, 27, 33 vdd - 3.3v common power supply 22 vdda - analog circuitry 3.3v power supply 23 vssa - analog circuitry power supply ground pins. 51, 53 vddc, vddi - 2.5v power supply ? s 5, 6,14, 17, 24, 35, 41, 47, 48, 56 vss - common ground pins. 38, 44 vdds - 3.3v power support for sdram clock output drivers. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 19 http://www.cypress.com approved product c9815 test mode function test mode functionality sel2 sel1 sel0 cpu sdram 3v66 pci usb/dot ref ioapic x 0 1 tclk/2 tclk/2 tclk/3 tclk/6 tclk/2 tclk tclk/6 table 2 note : tclk is a test clock over driven on the xin input during test mode. power management functions power management on this device is controlled by a single pin, pd# (pin32). when pd# is high (default) the device is in normal running mode and all signals are active. when pd# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3v and 2.5v except for vdda/pin 27) may be removed. when in power down, all outputs are synchronously stopped in a low state (see fig.2 below), all pll ? s are shut off, and the crystal oscillator is disabled. when the device is shutdown, the i 2 c function is also disabled. power management timing 100mhz pci 33mhz sdram 33mhz undefined cpu 66mhz 30ns 0ns ioapic 3v66 100mhz 20ns 10ns 40ns 50ns pwrdn# ref usb 14 . 3mhz 48mhz undefined undefined fig.2 power management current pd# , sel2, sel1, sel0 maximum 2.5 volt current consumption (vddc = vddi =2.625) maximum 3.3 volt current consumption (vdd = vdda = vdds = 3.465 v) 0xxx (power down) 10ma 10ma 1010 (66mhz) 70 ma 280 ma 1011 (100mhz) 100 ma 280 ma 1101 (133mhz) 133 ma 365 ma table 3 when exiting the power down mode, the designer must supply power to the vdd pins first, a minimum of 200ms before releasing the pd# pin high.
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 19 http://www.cypress.com approved product c9815 ioapic clock synchronization and phase alignment this device incorporates ioapic clock synchronization. with this feature, the ioapic clocks are derived from the cpu clock. the ioapic clock lags the cpu clock by the specified 1.5 to 3.5 nsec. figure 3 shows the relationship between the cpu and ioapic clocks. clock phase relationships fig.3 0ns 10ns 20ns 30ns 40ns 66mhz 100mhz 133mhz cpu clock sdram clock 3v66 clock pci clock 100mhz 66mhz 33mhz cpu clock cpu clock 1.5~3.5ns sync 7.5ns 5ns 5ns 2.5ns ioapic clock 33mhz sdram clock 133mhz 0ns 3.75ns 3.75ns 0ns 0ns
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 19 http://www.cypress.com approved product c9815 group timing relationships and tolerances cpu = 66.6 mhz, sdram = 100 mhz offset (ns) tolerance (ps) conditions cpu to sdram 2.5 500 sdram leads cpu to 3v66 7.5 500 180 degrees phase shift sdram to 3v66 0 500 when rising edges line-up 3v66 to pci 1.5-3.5 500 3v66 leads pci to ioapic 0 1000 cpu = 100 mhz, sdram = 100 mhz offset (ns) tolerance (ps) conditions cpu to sdram 5 500 180 degrees phase shift cpu to 3v66 5 500 cpu leads sdram to 3v66 0 500 when rising edges line-up 3v66 to pci 1.5-3.5 500 3v66 leads pci to ioapic 0 1000 cpu = 133.3 mhz, sdram = 100 mhz offset (ns) tolerance (ps) conditions cpu to sdram 0 500 when rising edges line-up cpu to 3v66 0 500 sdram to 3v66 0 500 when rising edges line-up 3v66 to pci 1.5-3.5 500 3v66 leads pci to ioapic 0 1000 cpu = 133.3 mhz, sdram = 133.3 mhz offset (ns) tolerance (ps) conditions cpu to sdram 3.75 500 180 degrees phase shift cpu to 3v66 0 500 sdram to 3v66 3.75 500 3v66 to pci 1.5-3.5 500 3v66 leads pci to ioapic 0 1000
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 19 http://www.cypress.com approved product c9815 power on bi-directional pins power up condition: pin1 is a power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. during power-up of the device, this pin is in input mode (see fig 4, below), therefore; it is considered input select pin, sel2 internal to the ic. after a settling time, the selection data is latch into the internal control register and this pin becomes a clock output. - hi-z inputs toggle outputs ower supply amp select data is latched into register, then pin becomes a ref clock output signal. ref / sel2 (pin 1) vdd rail strapping resistor options: the power up bi-directional pin has a large value pull- down (50k ?+/?20 k ?) , therefore, a selection ? 0 ? is the default. if the system uses a slow power supply (over 10ms settling time), then it is recommended to use an external pull-down (rdn) in order to insure a low selection. in this case, the designer may choose one of two configurations, see fig.5a and 5b. fig. 5a represents an additional pull down resistor 5k ? connected from the pin to the power line, which allows a faster down to a high level. if a selection ? 1 ? is desired, then a jumper is placed on jp1 to a 1 k ? resistor as shown in fig.5a. please note the selection resistors (rup and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 5b represent a single resistor 5k ? connected to a 3-way jumper, jp2. when a ? 1 ? selection is desired, a jumper is placed between leads1 and 3. when a ? 0 ? selection is desired, a jumper is placed between leads 1 and 2. load load fig. 5a fig. 5b vdd vdd rup 1k rd imi c9815 bidirectional jp1 jumper jp2 3 w ay jumper rsel 5k rd imi c9815 bidirectional rdn 5k 1 2 3 fig.4
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 19 http://www.cypress.com approved product c9815 2-wire smbus control interface the 2-wire control interface implements a read/write slave only interface according to smbus specification. (see fig. 6 below). the device can be read back by using standard smbus command bytes. sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2-wire control interface allows each clock output to be individually enabled or disabled. 100 kbits/second (standard mode) data transfer is supported. during normal data transfer, the sdata signal only changes when the sclk signal is low, and is stable when sclk is high. there are two exceptions to this. a high to low transition on sdata while sclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is an 8-bit address. the lsb address byte = 0 in write mode. the device will respond to transfers of 10 bytes (max) of data. the device will generate an acknowledge (low) signal on the sdata wire following reception of each byte. data is transferred msb first at a max rate of 100kbits/s. this device will also respond to a d3 address which sets it in a read mode. it will not respond to any other control interface conditions, and previously set control registers are retained. start condition transmit receive stop condition start condition transmit receiv stop condition 1 8 ack msb 00 0 data 0 1 lsb command byte 1 clk 1 byte n 88 8 byte 0 byte count ack ack ack ack (don ? t care) (don ? t care) (valid) (valid) fig.6a (write) (valid) data 1 0 (valid) 0 11 8 byte n (valid) byte count clk lsb ack 8 ack ack 8 0 byte1 1 ack ack msb 8 1 (valid) byte 0 fig.6b (read) figure 6 smbus communications waveforms
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 19 http://www.cypress.com approved product c9815 serial control registers note: the pin# column lists the relevant pin number where applicable. the @pup column gives the default state at power up. following the acknowledge of the address byte, two additional bytes must be sent: 1) ? command code ? byte, and 2) ? byte count ? byte. although the data (bits) in these two bytes are considered ? don ? t care ? ; they must be sent and will be acknowledged. after the command code and the count bytes have been acknowledged, the sequence described below (byte 0, byte 1, and byte 2) will be valid and acknowledged. byte 0: cpu clock register (1=enable, 0=disable) bit @pup pin# description 7 0 - reserved 6 0 - reserved 5 0 - reserved 4 0 - reserved 3 0 - spread spectrum mode 21 26dot 11 25usb 0 1 49 cpu2_itp byte 2: pci clock register (1=enable, 0=disable) bit @pup pin# description 7 1 9 3v66-2 (agp) 61 20pci6 51 19pci5 41 18pci4 31 16pci3 21 15pci2 11 13pci1 0 0 - reserved byte 1: sdram clock register (1=enable, 0=disable) bit @pup pin# description 7 1 36 sdram7 6 1 37 sdram6 5 1 39 sdram5 4 1 40 sdram4 3 1 42 sdram3 2 1 43 sdram2 1 1 45 sdram1 0 1 46 sdram0 byte 3: reserved register bit @pup pin# description 7 0 - reserved 6 0 - reserved 5 0 - reserved 4 0 - reserved 3 0 - reserved 2 0 - reserved 1 0 - reserved 0 0 - 0 = sdram runs at 100mhz 1= sdram runs at 133.3mhz byte 4: reserved register byte 5: sscg control register bit @pup pin# description 7 0 - spread mode (0=down, 1=center) 6 0 - selects spread bandwidth. ref. table 4 5 0 - selects spread bandwidth. ref. table 4 4 0 - reserved 3 0 - reserved 2 0 - reserved 1 0 - reserved 0 0 - reserved
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 9 of 19 http://www.cypress.com approved product c9815 smbus test circuitry fig.7 note: buffer is 7407 with vcc @ 5.0 v spread spectrum clock generation (sscg) spread spectrum is a modulation technique applied here for maximum efficiency in minimizing electro-magnetic interference radiation generated from repetitive digital signals mainly clocks. a clock accumulates em energy at the center frequency it is generating. spread spectrum distributes this energy over a small frequency bandwidth therefore distributing an even amount of energy over a wider spectrum. this technique is achieved by modulating the clock either down (fig.8a) or around the center (fig.8b) of its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). in this device, spread spectrum is enabled by setting smbus byte0, bit3 = 1. the default of the device at power up keeps the spread spectrum disabled, it is therefore, important to have smbus accessibility to turn-on the spread spectrum function. once the spread spectrum is enabled, the spread bandwidth option is selected by sst(0:2) in smbus byte 5, bits 5, 6 & 7 following tables 4a, and 4b below. in down spread mode the center frequency is shifted down from its rested (non-spread) value by ? of the total spread %. (eg.: assuming the center frequency is 100mhz in non-spread mode; when down spread of ? 0.5% is enabled, the center frequency shifts to 99.75mhz.). 2.2 k device under test sdata datain sclk dataout clock + 5v + 5v + 5v 2.2 k 2.2 k
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 10 of 19 http://www.cypress.com approved product c9815 in center spread mode, the center frequency remains the same as in the non-spread mode. down spread figure 8a center spread figure 8b spread spectrum selection tables i2c byte5 bit[7:5] spread % 000 - 0.5 001 - 0.7 010 - 1.0 011 - 0.25 table 4a i2c byte5 bit[7:5] spread % 100 0.25 101 0.35 110 0.5 111 +/- 0.125 table 4b maximum ratings maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65 o c to + 150 o c operating temperature: 0 o c to +85 o c maximum esd protection 2kv maximum power supply: 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 11 of 19 http://www.cypress.com approved product c9815 dc parameters (all outputs loaded per table 5 below) (vdd=vdds = 3.3v 5 %, vddc = vddi = 2.5 5%, ta = 0 o to +85 o c) characteristic symbol min typ max units conditions input low voltage vil1 - - 1.0 vdc input high voltage vih1 2.0 - - vdc note 1 input low voltage vil2 - - 1.0 vdc input high voltage vih2 2.2 - - vdc note 2 input low current (@vil = vss) iil1 -66 -5 a input high current (@vil =vdd) iih1 5 a for internal pull up resistors, note 6 input low current (@vil = vss) iil2 a input high current (@vil = vdd) iih2 a for internal pull down resistors, note 6 tri-state leakage current ioz - - 10 a dynamic supply current idd3.3v - - 280 ma sel2 = 0, sel1 = sel0 = 1 dynamic supply current idd2.5v - - 100 ma sel2 = 0, sel1 = sel0 = 1 static supply current isdd - - 10 ma sel1 = sel0 = x, pd# = 0 input pin capacitance cin - - 5 pf output pin capacitance cout - - 6 pf pin inductance lpin - - 7 nh crystal pin capacitance cxtal 32 34 38 pf measured from pin to ground. note 5 crystal dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v crystal startup time txs - - 40 s from stable 3.3v power supply. note1: applicable to input signals: sel(0:1), pd# (pull up), sel2 (pull down) note2: applicable to sdata, and sclk. note3: although internal pull-up resistors have a typical value of 250k, this value may vary between 200k and 500k. note5: although the device will reliably interface with crystals of a 17pf ? 20pf c l range, it is optimized to interface with a typical c l = 18pf crystal specifications. note6: internal pull up and pull down resistors have a typical value of 50k (it may vary between 30k and 70k). clock name max load (in pf) cpu(0:2), ioapic(0:1), ref, usb 20 pci(0:6), sdram(0:7), dclk, 3v66(0:2) 30 dot 15 table 5.
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 12 of 19 http://www.cypress.com approved product c9815 ac parameters 133 mhz host 100 mhz host 66 mhz host symbol parameter min max min max min max units tperiod cpu(0:2) period 5,8 7.5 8.0 10.0 10.5 14.75 15.25 ns thigh cpu(0:2) high time 10 1.87 - 3.0 - 5.2 - ns tlow cpu(0:2) low time 11 1.67 - 2.8 - 5.0 - ns tr / tf cpu(0:2) rise and fall times 7 0.4 1.6 0.4 1.6 0.4 1.6 ns tskew cpu0 to cpu skew 6,9 - 175 - 175 - 175 ps tccj cpu(0:2) cycle to cycle jitter 6,9 - 250 - 250 - 250 ps tperiod sdram(0:7) and dclk period 5,6 7.5 8.0 10.0 10.5 10.0 10.5 ns thigh sdram(0:7) and dclk high time 10 1.87 - 3.0 - 3.0 - ns tlow sdram(0:7) and dclk low time 11 1.67 - 2.8 - 2.8 - ns tr / tf sdram(0:7) and dclk rise and fall times 7 0.4 1.6 0.4 1.6 0.4 1.6 ns tskew sdram(0:7) and dclk skew 6,9 - 250 - 250 - 250 ps tccj sdram(0:7), dclk cycle to cycle jitter 6,9 - 250 - 250 - 250 ps tperiod ioapic(0:1) period 5,6 30.0 - 30.0 - 30.0 - ns thigh ioapic(0:1) high time 10 12.0 - 12.0 - 12.0 - ns tlow ioapic(0:1) low time 11 12.0 - 12.0 n/s 12.0 - ns tr / tf ioapic(0:1) rise and fall times 7 0.4 1.6 0.4 1.6 0.4 1.6 ns tccj ioapic(0:1) cycle to cycle jitter 6,9 - 500 - 500 - 500 ps tperiod 3v66-(0:2) period 5,6 15.0 16.0 15.0 16.0 15.0 16.0 ns thigh 3v66-(0:2) high time 10 5.25 - 5.25 - 5.25 - ns tlow 3v66-(0:2) low time 11 5.05 - 5.05 - 5.05 - ns tr / tf 3v66-(0:2) rise and fall times 7 0.5 2.0 0.5 2.0 0.5 2.0 ns tskew (any 3v66) to (any 3v66) skew 6,9 - 175 - 175 - 175 ps tccj 3v66-(0:2) cycle to cycle jitter 6,9 - 500 - 500 - 500 ps tperiod pci(0:6) period 5,6 30.0 - 30.0 - 30.0 - ns thigh pci(0:6) period 10 12.0 - 12.0 - 12.0 - ns tlow pci(0:6) low time 11 12.0 - 12.0 - 12.0 - ns tr / tf pci(0:6) rise and fall times 7 0.5 2.0 0.5 2.0 0.5 2.0 ns tskew (any pci) to (any pci) skew 6,9 - 500 - 500 - 500 ps tccj pci(0:6) cycle to cycle jitter 6,9 - 500 - 500 - 500 ps tperiod dot & usb period (conforms to +167ppm max) 5,6 20.8299 20.8333 20.8299 20.8333 20.829 20.833 ns tr / tf dot & usb rise and fall times 7 1.0 4.0 1.0 4.0 1.0 4.0 ns tccj dot & usb cycle to cycle jitter 6,9 - 500 - 500 - 500 ps
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 13 of 19 http://www.cypress.com approved product c9815 133 mhz host 100 mhz host 66 mhz host symbol parameter min max min max min max units tperiod ref period 5,6 69.8413 71.0 69.8413 71.0 69.8413 71.0 ns tr / tf ref rise and fall times 7 1.0 4.0 1.0 4.0 1.0 4.0 ns tccj ref cycle to cycle jitter 6 - 1000 - 1000 - 1000 ps tpzl, tpzh output enable delay (all outputs) 8 1.0 10.0 1.0 10.0 1.0 10.0 ns tplz, tphz output disable delay (all outputs) 13 1.0 10.0 1.0 10.0 1.0 10.0 ns tstable all clock stabilization from power-up 12 33 3ms tduty duty cycle for all outputs 14 45 55 45 55 45 55 % note 5: this parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818mhz note 6: all outputs loaded as per table 5, page 11. probes are placed on the pins and taken at 1.5v levels for 3.3v signals and at 1.25v for 2.5v signals (figs. 9a and 9b). note 7: probes are placed on the pins, and measurements are acquired between 0.4v and 2.4v for 3.3v signals and between 0.4v and 2.0v for 2.5v signals (see fig.9a and fig.9b) note 8: measured from when both sel1 and sel0 are switched to high (enable). note 9: this measurement is applicable with spread on or spread off. note 10: probes are placed on the pins, and measurements are acquired at 2.4v for 3.3v signals and at 2.0v for 2.5v signals, (see figs. 9a & 9b) note 11: probes are placed on the pins, and measurements are acquired at 0.4v. note 12: the time specified is measured from when all vdd ? s reach their respective supply rail (3.3v and 2.5v) till the frequency output is stable and operating within the specifications note 13: measured from when both sel1 and sel0 are switched to low (disable). note 14: device designed for typical duty cycle of 50%.
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 14 of 19 http://www.cypress.com approved product c9815 output buffer characteristics ( vdd=vdds=3.3v 5%, vddc=vddi=2.5 5%, ta=0 to 85 o c) cpu and ioapic characteristic symbol min typ max units conditions pull-up current ioh 1 -15 -31 -51 ma vout =vddc - 0.5v (or vddi ? 0.5v) pull-up current ioh 2 -26 -58 -101 ma vout = 1.2 v pull-down current iol 1 12 24 40 ma vout = 0.4 v pull-down current iol 2 27 56 93 ma vout = 1.2 v pci, 3v66 and dot characteristic symbol min typ max units conditions pull-up current ioh 1 -20 -25 -33 ma vout =vdd - 1.0 v pull-up current ioh 2 -30 -54 -184 ma vout = 1. 5 v pull-down current iol 1 9.4 18 38 ma vout = 0.4 v pull-down current iol 2 28 55 148 ma vout = 1.5 v usb and ref characteristic symbol min typ max units conditions pull-up current ioh 1 -12 -20 -30 ma vout =vdd - 1.0 v pull-up current ioh 2 -27 -43 -92 ma vout = 1. 5 v pull-down current iol 1 9 13 27 ma vout = 0.4 v pull-down current iol 2 26 39 79 ma vout = 1.5 v buffer characteristics for sdram characteristic symbol min typ max units conditions pull-up current ioh 1 -30 -40 -60 ma vout =vdd - 1. 0 v pull-up current ioh 2 -68 -110 -188 ma vout = 1. 4 v pull-down current iol 1 23 34 53 ma vout = 0.4 v pull-down current iol 1 64 98 159 ma vout = 1.5 v
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 15 of 19 http://www.cypress.com approved product c9815 test and measurement condition fig.9a fig.9b - - 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc 0.4v 2.0v 1.25v 2.5v 0v 2.5v signals tdc tr tf probe output under test load cap - -
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 16 of 19 http://www.cypress.com approved product c9815 suggested oscillator crystal parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance t c - - +/-100 ppm note 1 t s - - +/- 100 ppm stability (t a -10 to +60c) note 1 t a - - 5 ppm aging (first year @ 25c) note 1 operating mode - - - - parallel resonant, note 1 load capacitance c xtal - 20 - pf the crystal ? s rated load. note 1 effective series resistance (esr) r esr - 40 - ohms note 2 note1: for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifications note 2: larger values may cause this device to exhibit oscillator startup problems to obtain the maximum accuracy, the total circuit loading capacitance should be equal to c xtal . this loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (c ftg ), any circuit traces (c pcb ), and any onboard discrete load capacitors (c disc ). the following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal. c l = (c xinpcb + c xinftg + c xindisc ) x (c xoutpcb + c xoutftg + c xoutdisc ) (c xinpcb + c xinftg + c xindisc ) + (c xoutpcb + c xoutftg + c outdisc ) where: c xtal = the load rating of the crystal c xoutftg = the clock generators xin pin effective device internal capacitance to ground c xoutftg = the clock generators xout pin effective device internal capacitance to ground c xinpcb = the effective capacitance to ground of the crystal to device pcb trace c xoutpcb = the effective capacitance to ground of the crystal to device pcb trace c xindisc = any discrete capacitance that is placed between the xin pin and ground c xoutdisc = any discrete capacitance that is placed between the xout pin and ground c xinpcb c xoutpcb c xoutdisc c xindisc c xinftg c xoutftg xin xout clock generator
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 17 of 19 http://www.cypress.com approved product c9815 suggested oscillator crystal parameters (cont.) as an example, and using this formula for this datasheet ? s device, a design that has no discrete loading capacitors (c disc ) and each of the crystal to device pcb traces has a capacitance (c pcb ) to ground of 4pf (typical value) would calculate as: c l = (4pf + 36pf + 0pf) x (4pf + 36pf + 0pf) = 40 x 40 = 1600 = 20pf (4pf + 36pf + 0pf) + (4pf + 36pf + 0pf) 40 + 40 80 therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20pf. package drawing and dimensions 56 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.203 0.305 0.406 a2 0.088 - 0.092 2.24 - 2.34 b 0.008 - 0.0135 0.203 - 0.343 c 0.005 - 0.010 0.127 - 0.254 d 0.720 0.725 0.730 18.29 18.42 18.54 e 0.291 0.295 0.299 7.39 7.49 7.60 e 0.025 bsc 0.635 bsc h 0.395 - 0.420 10.03 - 10.67 l 0.020 - 0.040 0.508 - 1.016 a0 o -8 o 0 o -8 o b e a a 1 a 2 e a l c d h
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 18 of 19 http://www.cypress.com approved product c9815 ordering information part number package type production flow C9815DY 56 pin ssop commercial, 0 to 85 o c marking: example: cypress C9815DY date code, lot # C9815DY package y = ssop revision device number notice cypress semiconductor corporation reserves the right to make changes to its products in order to improve design, performance or reliability. cypress semiconductor corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by cypress semiconductor corporation for the use of its products in the life supporting and medical applications.
low emi clock generator for intel ? 133mhz/2dimm chipset systems cypress semiconductor corporation 525 los coches st. document#: 38-07054 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 19 of 19 http://www.cypress.com approved product c9815 document title: c9815 low emi clock generator for intel ? 133 mhz/2dimm chipset systems document number: 38-07054 rev. ecn no. issue date orig. of change description of change ** 107062 06/11/01 ika convert from imi to cypress

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