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a d s 8 0 9 12-bit pipelined a/d core reference and mode select reference ladder and driver timing circuitry error correction logic 3-state outputs t&h d0 d11 +v s ads809 clk clk oe sel2 refb v ref reft vdrv in 1vp-p 1vp-p cm (+2.5v) sel1 dv ovr in 12-bit, 80mhz sampling analog-to-digital converter features dynamic range: snr: 65db at 10mhz f in sfdr: 68db at 10mhz f in premium track-and-hold: low jitter: 0.25ps rms differential or single-ended inputs selectable full-scale input range flexible clocking: differential or single-ended accepts sine or square wave clocking down to 0.5vp-p variable threshold level description the ads809 is a high-dynamic range 12-bit, 80mhz pipelined analog-to-digital (a/d) converter. it includes a high-band- width linear track-and-hold that has a low jitter of only 0.25ps rms, leading to excellent snr performance. the clock input can accept a low level differential sine wave or square wave signal down to 0.5vp-p, further improving the snr perfor- mance. it also accepts a single-ended clock signal and has flexible threshold levels. the ads809 has a 2vp-p differential input range (1vp-p 2 inputs) for optimum signal-to-noise ratio. the differential operation gives the lowest even-order harmonic compo- nents. a lower input voltage of 1.5vp-p or 1vp-p can also be selected using the internal references, further optimizing sfdr. alternatively, a single-ended input range can be used by tying the in input to the common-mode voltage if desired. the ads809 also provides an over-range flag that indicates when the input signal has exceeded the converter s full-scale range. this flag can also be used to reduce the gain of the front end signal conditioning circuitry. it also employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. the ads809 is available in a small tqfp-48 powerpad terminally-en- hanced package. applications basestation wideband radios: cdma, gsm, tdma, 3g, amps, nmt test instrumentation ccd imaging ads809 sbas170b november 2000 revised june 2002 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2000, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a registered trademark of texas instruments.
ads809 2 sbas170b www.ti.com electrical characteristics at t a = full specified temperature range, differential input range = 1v to 2v, sampling rate = 80mhz, v s = +5v, and internal reference, unless otherwise noted. ads809y parameter conditions min typ max units resolution 12 tested bits specified temperature range ambient air 40 to +85 c analog input standard differential input range (1vp-p 2, +10dbm) 1 2 v single-ended input voltage 1vp-p 2 3 v common-mode voltage 2.5 v optional input ranges selectable 1vp-p or 1.5vp-p v analog input bias current 1 a track-mode input bandwidth 3dbfs 1 ghz input impedance static, no clock 1.25 || 9 m ? || pf conversion characteristics sample rate 1m 80m samples/s data latency 5 clk cyc dynamic characteristics differential linearity error (largest code error) f = 1mhz 0.7 +1.7/ 1.0 lsb f = 10mhz 0.7 lsb no missing codes tested integral nonlinearity error, f = 1mhz 4.0 6.0 lsbs spurious-free dynamic range (1) f = 1mhz 71 dbfs (2) f = 10mhz 65 68 dbfs f = 31mhz 67 dbfs 2-tone intermodulation distortion f in = 19.4mhz and 20.4mhz ( 7db each tone) 77 dbfs signal-to-noise ratio (snr) f = 1mhz 65.5 dbfs f = 10mhz 65 dbfs f = 31mhz 63 dbfs signal-to-(noise + distortion) (sinad) f = 2.2mhz 64 dbfs f = 10mhz 63 dbfs f = 31mhz 61 dbfs output noise input ac-grounded 0.13 lsbs rms aperture delay time 3ns aperture jitter 0.25 ps rms overvoltage recovery time 2ns full-scale step acquisition time 5ns +v s ....................................................................................................... +6v analog input .......................................................... ( 0.3v) to (+v s + 0.3v) logic input ............................................................ ( 0.3v) to (+v s + 0.3v) case temperature ......................................................................... +100 c junction temperature .................................................................... +150 c storage temperature ..................................................................... +150 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. absolute maximum ratings (1) electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity ads809y tqfp-48 php 40 c to +85 c ads809y ads809y/250 tape and reel, 250 " """" ads809y/2k5 tape and reel, 2500 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information
ads809 3 sbas170b www.ti.com electrical characteristics (cont.) at t a = full specified temperature range, differential input range = 1v to 2v, sampling rate = 80mhz, v s = +5v, and internal reference, unless otherwise noted. ads809y parameter conditions min typ max units digital inputs logic family +3v/+5v compatible cmos convert command start conversion rising edge of convert clock high level input current (v in = 5v) (3) 100 a low level input current (v in = 0v) 10 a high level input voltage +2.0 v low level input voltage +1.0 v input capacitance 5pf digital outputs logic family +3v/+5v compatible cmos logic coding straight offset binary low output voltage (i ol = 50 a to 1.6ma) vdrv = 3v +0.2 v high output voltage, (i oh = 50 a to 0.5ma) +2.5 v low output voltage, (i ol = 50 a to 1.6ma) vdrv = 5v +0.2 v high output voltage, (i oh = 50 a to 1.6ma) +2.5 v 3-state enable time oe = low 20 40 ns 3-state disable time oe = high 2 10 ns output capacitance 5pf accuracy (internal reference, = 2v, unless otherwise noted) zero error (midscale) at 25 c 0.5 %fs zero error drift (midscale) 12 ppm/ c gain error (4) at 25 c 1.5 %fs gain error drift (4) 38 ppm/ c gain error (5) at 25 c 0.75 %fs gain error drift (5) 20 ppm/ c power-supply rejection of gain ? v s = 5% 68 db internal ref tolerance (v refp v refn ) deviation from ideal 10 40 mv reference input resistance 660 ? power-supply requirements supply voltage: +v s operating +4.75 +5.0 +5.25 v supply current: +i s operating 170 ma output driver supply current (vdrv) 12 ma power dissipation: vdrv = 5v internal reference 925 mw vdrv = 3v internal reference 900 945 mw vdrv = 5v external reference 905 mw vdrv = 3v external reference 880 mw power down operating 20 mw thermal resistance, ja tqfp-48 28.8 c/w notes: (1) spurious-free dynamic range refers to the magnitude of the largest harmonic. (2) dbfs means db relative to full scal e. (3) a 50k ? pull-down resistor is inserted internally. (4) includes internal reference. (5) excludes internal reference.
ads809 4 sbas170b www.ti.com 26 vdrv output bit driver voltage supply 27 gnd ground 28 i oe output enable: hi = high impedance; lo or floating: normal operation 29 i pd power down: hi = power down; lo = normal 30 i btc hi = binary two s complement; lo = straight binary 31 gnd ground 32 sel2 reference select 2: see table on page 5 33 sel1 reference select 1: see table on page 5 34 v ref internal reference voltage 35 gnd ground 36 gnd ground 37 gnd ground 38 gnd ground 39 refb bottom reference voltage bypass 40 cm common-mode voltage (mid-scale) 41 reft top reference voltage bypass 42 gnd ground 43 gnd ground 44 i in complementary analog input 45 gnd ground 46 i in analog input 47 +v s supply voltage 48 +v s supply voltage 1 byp bypass point 2+v s supply voltage 3+v s supply voltage 4+v s supply voltage 5 gnd ground 6 i clk clock input 7i clk complementary clock input 8 gnd ground 9 gnd ground 10 o ovr over range indicator 11 o dv data valid pulse: hi = data valid 12 nc no connection 13 nc no connection 14 o d11 data bit 11, (msb) 15 o d10 data bit 10 16 o d9 data bit 9 17 o d8 data bit 8 18 o d7 data bit 7 19 o d6 data bit 6 20 o d5 data bit 5 21 o d4 data bit 4 22 o d3 data bit 3 23 o d2 data bit 2 24 o d1 data bit 1 25 o d0 data bit 0, (lsb) 36 35 34 33 32 31 30 29 28 27 26 25 gnd gnd v ref sel1 sel2 gnd btc pd oe gnd vdrv d0 (lsb) +v s +v s in gnd in gnd gnd reft cm refb gnd gnd nc d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 1 2 3 4 5 6 7 8 9 10 11 12 byp +v s +v s +v s gnd clk clk gnd gnd ovr dv nc 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 ads809y nc = no connection pin i/o designator description pin i/o designator description pin descriptions pin diagram
ads809 5 sbas170b www.ti.com desired internal full-scale range sel1 sel2 v ref 1vp-p v ref gnd 0.5v 1.5vp-p gnd +v s 0.75v 2vp-p gnd gnd 1.0v reference and full-scale range select for external reference operation, tie v ref to +v s and apply reft and refb externally. internal voltage buffer of cm is powered up. the full-scale input range is equal to 2x the reference value (reft refb). timing diagram symbol description min (1) typ max (1) units t conv convert clock period 12.5 1 sns t h clock pulse high 6.2 t conv /2 ns t l clock pulse low 6.2 t conv /2 ns t a aperture delay 4.6 6.1 ns t dv data valid pulse delay (2) 10 12 ns t 1 data hold time, c l = 0pf 4 5.8 ns t 2 new data delay time, c l = 15pf max 9 11 ns notes: (1) timing values based on simulation at room temperature. min/max values provided for design estimation only. (2) measured from the 50% point of the clock to the time when signals are within valid logic levels. t a t conv t h n 5n 4n 3n 2n 1 n n + 1 data bits out data valid pulse clock n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 analog in t l t 1 t dv 5 clock cycles t 2
ads809 6 sbas170b www.ti.com typical characteristics at t a = full specified temperature range, differential input range = 1v to 2v, sampling rate = 80mhz, and internal reference, unless otherwise noted. 0 20 40 60 80 100 120 spectral performance (differential, 2vp-p) frequency (mhz) 0 5 10 15 20 25 30 35 40 amplitude (dbfs) f in = 1mhz ( 1.0dbfs) sfdr = 70.1dbfs snr = 65.4dbfs sinad = 63.8dbfs 80 75 70 65 60 55 50 dynamic performance vs sampling frequency (2vp-p, differential) sampling frequency (mhz) 30 40 50 60 70 80 90 sfdr, snr and sinad (dbfs) sfdr f in = 10mhz snr sinad 0 20 40 60 80 100 120 spectral performance (differential, 1.5vp-p) frequency (mhz) 0 5 10 15 20 25 30 35 40 amplitude (dbfs) f in = 10mhz ( 1.0dbfs) sfdr = 68.9dbfs snr = 63.2dbfs 0 20 40 60 80 100 120 spectral performance (differential, 1vp-p) frequency (mhz) 0 5 10 15 20 25 30 35 40 amplitude (dbfs) f in = 10mhz ( 1.0dbfs) sfdr = 69.6dbfs snr = 60.7dbfs 0 20 40 60 80 100 120 2-tone intermodulation distortion frequency (mhz) 0 5 10 15 20 25 30 35 40 amplitude (dbfs) f 1 = 19.4mhz f 2 = 20.4mhz imd(3) = 77.2dbfs 0 20 40 60 80 100 120 spectral performance (differential, 2vp-p) frequency (mhz) 0 5 10 15 20 25 30 35 40 amplitude (dbfs) f in = 10mhz ( 1.0dbfs) sfdr = 68.3dbfs snr = 65.1dbfs sinad = 63.0dbfs
ads809 7 sbas170b www.ti.com typical characteristics (cont.) at t a = full specified temperature range, differential input range = 1v to 2v, sampling rate = 80mhz, and internal reference, unless otherwise noted. 80 75 70 65 60 55 50 dynamic performance vs sampling frequency (2vp-p, differential) sampling frequency (mhz) 30 40 50 60 70 80 90 sfdr, snr and sinad (dbfs) f in = 20mhz sfdr snr sinad 75 70 65 60 55 50 dynamic performance vs input frequency input frequency (mhz) 010 5 15202530 40 35 45 sfdr, snr and sinad (dbfs) ( 1.0dbfs) snr sfdr sinad 80 75 70 65 60 55 50 dynamic performance vs input frequency input frequency (mhz) 010 5 15202530 40 35 45 sfdr, snr and sinad (dbfs) ( 6.0dbfs) snr sfdr sinad 180 160 140 120 100 80 60 40 20 0 supply currents vs sampling frequency sampling frequency (mhz) 20 30 40 50 60 70 80 90 supply currents (ma) vdrv v s 1 0.8 0.6 0.4 0.3 0 0.2 0.4 0.6 0.8 1 differential linearity error code 0 1024 2048 3072 4096 dle (lsb) 3 2 1 0 1 2 3 integral linearity error ile (lsb) code 0 1024 2048 3072 4096
ads809 8 sbas170b www.ti.com 250k 200k 150k 100k 50k 0 output noise histogram (2vp-p, grounded input) code n 1 n n + 1 n + 2 counts n 2 80 70 60 50 40 30 20 10 0 10 20 swept power snr analog input level (dbfs) 60 50 40 30 20 10 0 snr (dbc, dbfs) 80 70 dbfs dbc typical characteristics (cont.) at t a = full specified temperature range, differential input range = 1v to 2v, sampling rate = 80mhz, and internal reference, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 swept power sfdr analog input level (dbfs) 60 50 40 30 20 10 0 sfdr (dbc, dbfs) 80 70 dbc dbfs 75 70 65 60 55 50 dynamic performance vs temperature temperature ( c) 60 40 20 sfdr 0 20 40 60 80 100 sfdr, snr, and sinad (dbfs) snr sinad f in = 10mhz ( 1.0dbfs) 180 160 140 120 100 80 60 40 20 0 supply current vs temperature temperature ( c) 60 40 20 0 20 40 60 80 100 supply current (ma) vdrv v s
ads809 9 sbas170b www.ti.com application information theory of operation the ads809 is a high-speed, high performance, cmos a/d converter built with a fully differential, 9-stage pipeline architecture. each stage contains a low-resolution quantizer and digital error correction logic, ensuring excellent differen- tial linearity and no missing codes at the 12-bit level. the conversion process is initiated by a rising edge of the external convert clock. once the signal is captured by the input track-and-hold amplifier, the bits are sequentially en- coded starting with the msb. this process results in a data latency of five clock cycles, after which the output data is available as a 12-bit parallel word either coded in a straight binary or binary two s complement format. the analog input of the ads809 consists of a differential track-and-hold circuit, as shown in figure 1. the differential topology produces a high level of ac-performance at high sampling rates. it also results in a very high usable input bandwidth that is especially important for if, or undersampling applications. both inputs (in, in ) require external biasing up to a common-mode voltage that is typically at the mid-supply level (+v s /2). this is because the on-resistance of the cmos switches is lowest at this voltage, minimizing the effects of the signal dependent non-linearity of r on . the track-and- hold circuit can also convert a single-ended input signal into a fully differential signal for the quantizer. for ease of use, the ads809 incorporates a selectable voltage reference, a versatile clock input, and a logic output driver designed to interface to 3v or 5v logic. particularly suited for communication systems that digitize wideband signals. features on the ads809, like the input range selector or the option of an external reference, provide the needed flexibility to accommodate a wide range of applications. in any case, the analog interface/driver require- ments should be carefully examined before selecting the appropriate circuit configuration. the circuit definition should include considerations on the input frequency spectrum and amplitude, single-ended versus differential driver configura- tion, as well as the available power supplies. differential versus single-ended the ads809 input structure allows it to be driven either single-ended or differentially. differential operation of the ads809 requires an input signal that consists of an in-phase and a 180 out-of-phase component simultaneously applied to the inputs (in, in ). differential signals offer a number of advantages, that in many applications, will be instrumental in achieving the best harmonic performance of the ads809: the signal amplitude is half of that required for the single- ended operation, and is therefore less demanding to achieve while maintaining good linearity performance from the signal source. the reduced signal swing allows for more headroom of the interface circuitry, and therefore a wider selection of the best suitable driver amplifier. even-order harmonics are minimized. improves the noise immunity based on the converter s common-mode input rejection. for the single-ended mode, the signal is applied to one of the inputs while the other input is biased with a dc voltage to the required common-mode level. both inputs are identical in terms of their impedance and performance except that apply- ing the signal to the complementary input ( in ) instead of the in-input will invert the orientation of the input signal relative to the output code. for example, if the input driver operates in inverting mode, using in as the signal input, it will restore the phase of the signal to its original orientation. time- domain applications may benefit from a single-ended inter- face configuration and a reduced circuit complexity. driving the ads809 with a single-ended signal will result in a trade- off of the excellent distortion performance, while maintaining a good signal-to-noise ratio (snr). the trade-off of the differential input configuration over the single-ended is its increase in circuit complexity. in either case, the selection of the driver amplifier should be such that the amplifier s perfor- mance will not degrade the a/d converter s performance. input full-scale range versus performance employing dual supply amplifiers and ac-coupling will usually yield the best results. dc-coupling and/or single-supply am- plifiers impose additional design constrains due to their head- room requirements, especially when selecting the 2vp-p input range. the full-scale input range of the ads809 is defined either by the settings of the reference select pins (sel1, sel2) or by an external reference voltage (see table i). t&h c in c in s 1 s 2 s 3 s 4 s 6 s 5 in in tracking phase: s 1 , s 2 , s 3 , s 4 closed; s 5 , s 6 open hold phase: s 1 , s 2 , s 3 , s 4 open; s 5 , s 6 closed ads809 figure 1. simplified circuit of input track-and-hold amplifier. driving the analog inputs types of applications the analog input of the ads809 can be configured in various ways and driven with different circuits, depending on the application and the desired level of performance. offering a high dynamic range at high input frequencies, the ads809 is
ads809 10 sbas170b www.ti.com by choosing between the three different signal input ranges, tradeoffs can be made between noise and distortion perfor- mance. for maximizing the snr, which is important for time- domain applications, the 2vp-p range may be selected. this range may also be used with low-level ( 6dbfs to 40dbfs) to high frequency inputs (multi-tone). the 1.5vp- p range may be considered for achieving a combination of both low noise and distortion performance. here, the snr number is typically 3db down compared to the 2vp-p range, while an improvement in the distortion performance of the driver amplifier may be realized due to the reduced output power level required. the third option, 1vp-p fsr, may be considered mainly for applications requiring dc-coupling and/ or single-supply operation of the driver and the converter. input biasing (v cm ) the ads809 operates from a single +5v supply, and requires each of the analog inputs to be externally biased to a common- mode voltage of typically +2.5v. this allows a symmetrical signal swing while maintaining sufficient headroom to either supply rail. communication systems are usually ac-coupled in-between signal processing stages, making it convenient to set individual common-mode voltages and allow optimizing the dc operating point for each stage. other applications (e.g., imaging) process only unipolar or dc-restored signals. in this case, the common-mode voltage may be shifted such that the full-input range of the converter is utilized. it should be noted that the cm pin is internally buffered. however, it is recommended to keep the loading of this pin to a minimum to avoid an increase in the converter s non- linearity. also, the dc voltage at the cm pin is not exactly +2.5v, but is subject to the tolerance of the top and bottom references as well as the resistor ladder. input impedance the input of the ads809 is of a capacitive nature and the driving source needs to provide the slew current to charge or discharge the input sampling capacitor while the track-and- hold amplifier is in track mode, see figure 1. this effectively results in a dynamic input impedance that is a function of the sampling frequency. figure 2 depicts the differential input impedance of the ads809 as a function of the input frequency. for applications that use op amps to drive the a/d converter, it is recommended to add a series resistor between the amplifier output and the converter inputs. this will isolate the converter s capacitive input from the driving source and avoid gain peaking, or instability. furthermore, it will create a first-order, low-pass filter in conjunction with the specified input capacitance of the ads809. its cutoff frequency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. however, the optimum values of this rc network depend on a variety of factors, including the ads809 s sampling rate, the selected op amp, the interface configuration, and the particular application (time domain versus frequency domain). generally, increas- ing the size of the series resistor and/or capacitor will improve the signal-to-noise ratio, however, depending on the signal source, large resistor values may reduce the harmonic distortion performance. in any case, the use of the rc network is optional but optimizing the values to adapt to the specific application is encouraged. input driver configurations the following section provides some principal circuit sugges- tions on how to interface the analog input signal to the ads809. a first example of a typical analog interface circuit is shown in figure 3. here, it is assumed that the input signal is already available in differential form, e.g.: coming from a preceding mixer stage. the differential driver performs an impedance transformation as well as amplifying the signal to match the selected full-scale input range of the ads809 (for example, 2vp-p). the common-mode voltage (v cm ) for the converter input is established by connecting the inputs to the midpoints of the resistor divider. the input signal is ac- coupled through capacitors c in to the inputs of the converter that are set to a v cm of approximately +2.5v dc . figure 2. differential input impedance versus input frequency. differential driver ads809 0.1 f 0.1 f reft refb in in 1k ? 1k ? 1k ? c in c in 1k ? v cm = +2.5v v in v in note: reference bypassing omitted for clarity. figure 3. ac coupling allows for easy dc biasing of the ads809 inputs while the input signal is applied by the differential input driver. 1000 100 10 1 0.1 0.01 0.1 1 10 100 1000 ads809 input impedance vs input frequency f in (mhz) z in (k ? ) some differential driver circuits may allow setting an appro- priate common-mode voltage directly at the driver input. this will simplify the interface to the ads809 and eliminate the external biasing resistors and the coupling capacitors. texas instruments offers a line of fully differential high-speed ampli- fiers. the ths4150, for example, may be used for input
ads809 11 sbas170b www.ti.com frequencies from dc to approximately 10mhz, for which the part maintains good distortion performance providing a 2vp- p (max) output swing on 5v supplies. combining a differen- tial driver circuit with a step-up transformer can lead to significant improvement of the distortion performance (see figure 6). transformer coupled interface circuits if the application allows for ac-coupling, but requires a signal conversion from a single-ended source to drive the ads809 differentially, using a transformer offers a number of advantages. as a passive component, it does not add to the total noise, plus using a step-up transformer, further signal amplification can be realized. as a result, the signal swing out of the amplifier driving the transformer can be reduced, leading to more headroom for the amplifier and improved distortion performance. one possible interface solution that uses a transformer is given in figure 4. the input signal is assumed to be an intermediate frequency (if) and bandpass filtered prior to the if amplifier dedicated if amplifiers, for example the rf2312 or mar-6, are fixed-gain broadband amplifiers and feature a very high bandwidth, a low-noise figure, and a high intercept point at the expense of high quiescent currents of 50-120ma. the if amplifier may be ac-coupled or directly connected to the primary side of the transformer. a variety of miniature rf transformers are readily available from different manufacturers, i.e.: mini-circuits, coilcraft, or trak. for the selection, it is important to carefully examine the application requirements and determine the correct model, the desired impedance ratio, and frequency characteristics. furthermore, the appropriate model must support the tar- geted distortion level and should not exhibit any core satura- tion at full-scale voltage levels. since the transformer does not appreciably load the ladder, its center tap can be directly tied to the cm pin of the converter, as shown in figure 4. the value of termination resistor (r t ) should be chosen to satisfy the termination requirements of the source impedance (r s ). it can be calculated using the equation r t = n 2 r s to ensure proper impedance matching. transformer coupled, single-ended to differential configuration for applications in which the input frequency is limited to about 40mhz (i.e.: baseband), the wideband, current-feedback, op- erational amplifier opa685 may be used. as shown in figure 5, the opa685 is configured for the noninverting mode, amplifies the single-ended input signal, and drives the primary of a rf transformer. to maintain the very low distortion performance of the opa685, it may be advantageous to reduce the full-scale input range (fsr) of the ads809 from 2vp-p to 1.5vp-p or 1vp-p (refer to the paragraph reference for details on selecting the converter s full-scale range). the circuit also shows the use of additional rc low-pass filter placed in series with each converter input. this optional filter can be used to set a defined corner frequency and attenuate some of the wideband noise. the actual component values would need to be tuned for the individual application require- ments. as a guideline, resistor values are typically in the range of 10 ? to 100 ? , capacitors in the range of 10pf to 200pf. in any case, the r in and c in values should have a low tolerance. this will ensure that the ads809 sees closely matched source impedances. figure 4. driving the ads809 with a low distortion rf amplifier and a transformer suited for if sampling applications. r in r in c in c in 4.7 f 0.1 f r t 0.1 f 1:n xfmr r s if amp optional bandpass filter v in (if) + ads809 in in cm +5v +v s v s v cm +2.5v r in r in c in c in 2.2 f 0.1 f r t 0.1 f 1:n xfmr r s r g opa685 r 1 r 2 v in + ads809 in in cm +5v v +v v cm +2.5v figure 5. converting a single-ended input signal into a differential signal using a rf transformer.
ads809 12 sbas170b www.ti.com ac-coupled, differential interface with gain the interface circuit example presented in figure 6 employs two opa685s, (current feedback op amp), optimized for gains of 8v/v or higher. the input transformer (t1) converts the single-ended input signal to a differential signal required at the amplifier s inverting inputs, that are tuned to provide a 50 ? impedance match to an assumed 50 ? source. to achieve the 50 ? input match at the primary of the 1:2 transformer, the secondary input must see a 200 ? load impedance. both amplifiers are configured for the inverting mode resulting in close gain and phase matching of the differential signal. this technique, along with a highly sym- metrical layout, is instrumental in achieving a substantial reduction of the 2nd-harmonic, while retaining excellent 3rd- order performance. a common-mode voltage (v cm ) is ap- plied to the noninverting inputs of the opa685. additional series of 43.2 ? resistors isolate the output of the op amps from the capacitive load presented by the 22pf capacitors and the input capacitance of the ads809. this 43.2 ? /22pf combination sets a pole at approximately 167mhz and rolls off some of the wideband noise. reference reference operation integrated into the ads809 is a bandgap reference circuit including some logic that provides a +0.5v, +0.75v, or +1v reference output by selecting the corresponding pin-strap configuration. table i gives a complete overview of the possible reference options and pin configurations. +5v 5v opa685 22pf 22pf +5v 5v 600 ? opa685 t1 1:2 50 ? source noise figure 11.8db v cm v cm 600 ? 100 ? 100 ? 43.2 ? power supply decoupling not shown. 43.2 ? v i v o a/d converter input v o v i = 12v/v (21.6db) dis dis figure 6. wideband differential a/d converter driver. desired full-scale range, connect connect voltage at v ref voltage at reft voltage at refb fsr (differential) sel1 (pin 33) sel2 (pin 32) (pin 34) (pin 41) (pin 39) 2vp-p (+10dbm) gnd gnd +1.0v +3v +2v 1.5vp-p (+7.5dbm) gnd +v s +0.75v +2.875v +2.125v 1vp-p v ref gnd +0.5v +2.75v +2.25v external reference > +3.5v +2.75v to +4.5v +0.5v to +2.25v table i. reference pin configurations and corresponding voltage on the reference pins.
ads809 13 sbas170b www.ti.com figure 7 shows the basic model of the internal reference circuit. the functional blocks are a 1v bandgap voltage reference, a selectable gain amplifier, the drivers for the top and bottom reference (reft, refb), and the resistive refer- ence ladder. the ladder resistance measures approximately 660 ? between the reft and refb pin. the ladder is split into two equal segments, establishing a common-mode volt- age at the ladder midpoint, labeled cm . the ads809 requires solid bypassing for all reference pins to keep the effect of clock feedthrough to a minimum and to achieve the specified level of performance. figure 7 also demonstrates the recommended decoupling scheme. all 0.1 f capacitors should be located as close to the pins as possible. when operating the ads809 from the internal reference, the effective full-scale input span for each of the inputs, in and in , is determined by the voltages at reft and refb pins, given as: input span (differential) = 2x (reft refb), in vp-p = 2 v ref the top and bottom reference outputs may be used to provide up to 1ma (sink or source) of current to external circuits. degradation of the differential linearity (dnl) and, consequently, of the dynamic performance of the ads809 may occur if this limit is exceeded. using external references for even more design flexibility, the ads809 can be oper- ated with an external reference. the utilization of an external reference voltage may be considered for applications requiring higher accuracy, im- proved temperature stability, or a continuous adjustment of the converter s full-scale range. especially in multichannel applications, the use of a common external reference offers the benefit of improving the gain matching between convert- ers. selection between internal or external reference opera- tion is controlled through the v ref pin. the internal reference will become disabled if the voltage applied to the v ref pin exceeds +3.5v dc . once selected, the ads809 requires two reference voltages a top-reference voltage applied to the reft pin and a bottom-reference voltage applied to the refb pin (see table i). as illustrated in figure 8, a micropower reference (ref1004) and a dual, single-supply amplifier may be used to generate a precision external reference. note that the function of the range select pins, sel1 and sel2, are disabled while the converter is in external mode. range select and gain amplifier to p reference driver bottom reference driver +1v dc bandgap reference ads809 reft cm refb 0.1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f byp sel1 sel2 pd v ref 330 ? 330 ? 1 figure 7. internal reference circuit of the ads809 and recommended bypass scheme. r 3 r 4 r 1 r 2 + + 2.2 f 0.1 f 0.1 f + 2.2 f 0.1 f 10 f reft refb ads809 1/2 opa2234 1/2 opa2234 4.7k ? +5v 5v ref1004 +2.5v figure 8. example for an external reference circuit using a dual, single-supply op amp.
ads809 14 sbas170b www.ti.com clk clk ads809 0.1 f 1:1 square wave clock source figure 11. connecting a ground referenced square wave clock source to the ads809 using a rf transformer. digital inputs and outputs clock input unlike most a/d converters, the ads809 contains an inter- nal clock conditioning circuitry. this enables the converter to adapt to a variety of application requirements and differ- ent clock sources. some interface examples are given in the following section. with no input signal connected to either clock pin, the threshold level is set to about +1.6v by the on-chip resistive voltage divider, as shown in figure 9. the parallel combination of r 1 || r 2 and r 3 || r 4 sets the input impedance of the clock inputs (clk, clk ) to approximately 2.7k ? single-ended or 5.4k ? differentially. the associated ground-referenced input capacitance is approximately 5pf for each input. if a logic voltage other than the nominal +1.6v is desired, the clock inputs can be externally driven to establish an alternate threshold voltage. r 1 8.5k ? ads809 r 3 8.5k ? +5v r 2 4k ? clk clk r 4 4k ? applying a single-ended clock signal will provide satisfactory results in many applications. however, unbalanced high- speed logic signals often introduce a high amount of distur- bances, such as ringing or ground bouncing. also, a high amplitude may cause the clock signal to have unsymmetrical rise and fall times, potentially effecting the converter distor- tion performance. proper termination practice and a clean pcb layout will help to keep those effects to a minimum. to take full advantage of the excellent distortion performance of the ads809, it is recommended to drive the clock inputs differentially. a low-level, differential clock improves the digi- tal feedthrough immunity and minimizes the effect of modu- lation between the signal and the clock. figure 11 illustrates a simple method of converting a square wave clock from single-ended to differential using a rf transformer. small surface-mount transformers are readily available from sev- eral manufacturers (e.g.: model adt1-1 by mini-circuits). a capacitor in series with the primary side may be inserted to block any dc voltage present in the signal. since the clock inputs are self-biased, the secondary side connects directly to the two clock inputs of the converter. clk clk ads809 47nf ttl/cmos clock source (3v/5v) figure 9. the differential clock inputs are internally biased. figure 10. single-ended ttl/cmos clock source. the ads809 can be interfaced to standard ttl or cmos logic and accepts 3v or 5v compliant logic levels. in this case, the clock signal should be applied to the clk-input, while the complementary clock input ( clk ) should be bypassed to ground by a low-inductance ceramic chip capacitor, as shown in figure 10. depending on the quality of the signal, inserting a series, damping resistor may be beneficial to reduce ringing. when digitizing at high sam- pling rates (f s > 50mhz), the clock should have a 50% duty cycle (t h = t l ) to maintain a good distortion performance. the clock inputs of the ads809 can be connected in a number of ways. however, the best performance is obtained when the clock input pins are driven differentially. when operating in this mode, the clock inputs accommodate signal swings ranging from 2.5vp-p down to 0.5vp-p differentially. this allows direct interfacing of clock sources, such as voltage-controlled crystal oscillators (vcxo) to the ads809. the advantage here is the elimination of external logic usually necessary to convert the clock signal into a suitable logic (ttl or cmos) signal, that otherwise would create an additional source of jitter. in any case, a very low-jitter clock is fundamental to preserving the excellent ac performance of the ads809. the converter itself is specified for a very low 0.25ps (rms) jitter, characterizing the outstanding capability of the internal clock and track-and-hold circuitry. generally, as the input frequency increases, the clock jitter becomes more dominant in maintaining a good snr. this is particu- larly critical in if sampling applications where the sampling frequency is lower than the input frequency (or undersampling). the following equation can be used to calculate the achievable snr for a given input frequency and clock jitter (t ja in ps rms): snr ft in ja = ( ) 20 1 2 10 log
ads809 15 sbas170b www.ti.com clk clk ads809 1:1 r t rf sine source depending on the nature of the clock source s output imped- ance, an impedance matching might become necessary. for this, a termination resistor (r t ) may be installed, as shown in figure 12. to calculate the correct value for this resistor, consider the impedance ratio of the selected transformer and the differential clock input impedance of the ads809, which is approximately 5.4k ? . it is not recommended to employ any type of differential ttl logic that suffers from mismatch in delay time and slew-rate leading to performance degradation. alternatively, a low jitter ecl or pecl clock may be ac-coupled directly to the clock inputs using small (0.1 f) capacitors. output enable ( oe ) the digital outputs of the ads809 can be set to high impedance (tri-state), exercising the output enable pin ( oe ). for normal operation, this pin must be at a logic low potential while a logic high voltage disables the outputs. even though this function effects the output driver stage, the threshold voltages for the oe pin do not depend on the output driver supply (vdrv), but are fixed (see specifica- tions, digital inputs ). operating the oe function dynamically (i.e.: high speed multiplexing, should be avoided, as it will corrupt the conversion process. power down (pd) a power-down of the ads809 is initiated by taking the pd pin high. this shuts down portions within the converter and reduces the power dissipation to about 20mw. the remain- ing active blocks include the internal reference, ensuring a fast reactivation time. during power-down, data in the con- verter pipeline will be lost and new valid data will be subject to the specified pipeline delay. in case the pd pin is not used, it should be tied to ground or a logic low level. over range indicator (ovr) if the analog input voltage exceeds the full-scale range set by the reference voltages, an over range condition exists. the ads809 incorporates a function, that monitors the input voltage and detects any such out-of-range condition. the current state can be read at the over range indicator pin (ovr). this output is low when the input voltage is within the defined input range. it will change to high if the applied signal exceeds the full-scale range. it should be noted that the ovr output is updated along with the data output, corresponding to the particular sampled analog input volt- age. therefore, the ovr data is subject to the same pipeline delay as the digital data (5 clock cycles). output loading it is recommended to keep the capacitive loading on the data output lines as low as possible, preferably below 15pf. higher capacitive loading will cause larger dynamic currents to flow as the digital outputs are changing. for example, with a typical output slew-rate of 0.8v/ns and a total capacitive loading of 10pf (including 4pf output capacitance, 5pf input capacitance of external logic buffer, and 1pf pc-board parasitics), a bit transition can cause a dynamic current of (10pf 0.8v/1ns = 8ma). those high current surges can figure 12. applying a sinusoidal clock to the ads809. minimum sampling rate the pipeline architecture of the ads809 uses the switched capacitor technique in its internal track-and-hold stages. with each clock cycles charges representing the captured signal level are moved within the a/d converter pipeline core. the high sampling speed necessitates the use of very small capacitor values. in order to hold the droop errors low, the capacitors require a minimum refresh rate . therefore, the sampling clock on the ads809 should not drop below the specified minimum of 1mhz. data output format (btc) the ads809 makes two data output formats available, either the straight offset binary code (sob) or the binary two s complement code (btc). the selection of the output coding is controlled through the btc pin. applying a logic high will enable the btc coding, while a logic low will enable the sob code. the btc output format is widely used to interface to microprocessors and such. the two code structures are identical with the exception that the msb is inverted for the btc format, as shown in tables ii and iii. single-ended binary two s input (in) straight offset complement (in biased to v cm ) binary (sob) (btc) +fs 1lsb 1111 1111 1111 0111 1111 1111 ( in = cmv + fsr/2) +1/2 fs 1100 0000 0000 0100 0000 0000 bipolar zero 1000 0000 0000 0000 0000 0000 (in = cmv) 1/2 fs 0100 0000 0000 1100 0000 0000 fs 0000 0000 0000 1000 0000 0000 (in = cmv fsr / 2) table ii. coding table for single-ended input configuration with in tied to the common-mode voltage (cmv). binary two s straight offset complement differential input binary (sob) (btc) +fs 1lsb 1111 1111 1111 0111 1111 1111 (in = +3v, in = +2v) +1/2 fs 1100 0000 0000 0100 0000 0000 bipolar zero 1000 0000 0000 0000 0000 0000 (in = in = cmv) 1/2 fs 0100 0000 0000 1100 0000 0000 fs 0000 0000 0000 1000 0000 0000 (in = +2v, in = +3v) table iii. coding table for differential input configuration and 2vp-p full-scale input range.
ads809 16 sbas170b www.ti.com figure 13. recommended supply decoupling scheme. feed back to the analog portion of the ads809 and adversely affect the performance. external buffers, or latches, close to the converter s output pins may be used to minimize the capacitive loading. they also provide the added benefit of isolating the ads809 from any digital activities on the bus from coupling back high-frequency noise. power supplies when defining the power supplies for the ads809, is it highly recommended to consider linear supplies instead of switch- ing types. even with good filtering, switching supplies may radiate noise that could interfere with any high frequency input signal and cause unwanted modulation products. at its full conversion rate of 80mhz, the ads809 requires typically 170ma of supply current on the +5v supply (+v s ). note that this supply voltage should stay within a 5% tolerance. the ads809 does not require separate analog and digital sup- plies, but only one single +5v supply to be connected to all its +v s pins. this is with the exception of the output driver supply pin, denoted vdrv (see the following section). digital output driver supply (vdrv) a dedicated supply pin, denoted vdrv, provides power to the logic output drivers of the ads809, and may be operated with a supply voltage in the range of +3.0v to +5.0v. this can simplify interfacing to various logic families, in particular low- voltage cmos. it is recommended to operate the ads809 with a +3.0v supply voltage on vdrv. this will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line that may affect the ac performance of the converter. the analog supply (+v s ) and driver supply (vdrv) may be tied together, with a ferrite bead or inductor between the supply pins. each of the these supply pins must be bypassed separately with at least one 0.1 f ceramic chip capacitor, forming a pi-filter. the recommended operation for the ads809 is +5v for the +v s pins and +3.0v on the output driver pin (vdrv). layout and decoupling considerations proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high- frequency designs. achieving optimum performance with a fast sampling converter, like the ads809, requires careful attention to the pc-board layout to minimize the effect of board parasitics and optimize component placement. a multilayer board usually ensures best results and allows convenient component placement. the ads809 should be treated as an analog component with the +v s pins connected to clean analog supplies. this will ensure the most consistent results, since digital supplies often carry a high level of switching noise that could couple into the converter and degrade the performance. as men- tioned previously, the driver supply pins (vdrv) should also be connected to a low-noise supply. supplies of adjacent digital circuits may carry substantial current transients. the supply voltage must be thoroughly filtered before connecting to the vdrv supply of the converter. all ground connections on the ads809 are internally bonded to the metal flag (bottom of package) that forms a large ground plane. all ground pins should directly connect to an analog ground plane that covers the pc-board area under the converter. because of its high sampling frequency, the ads809 gener- ates high-frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. if not sufficiently bypassed, this will add noise to the conversion process. figure 13 shows the recommended supply decoupling scheme for the ads809. all +v s pins may be connected together and bypassed with a combination of 10nf to 0.1 f ceramic chip capacitors (0805, low esr) and a 10 f tantalum tank capacitor. a similar approach may be used on the driver supply pins, vdrv. in order to minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. where double-sided component mounting is allowed, they are best placed directly under the package. in addition, larger bipolar decoupling capacitors (2.2 f to 10 f), effective at lower frequencies, should also be used on the main supply pins. they can be placed on the pc-board in proximity (< 0.5") of the a/d converter. +v s 2, 47, 48 35, 36, 37, 38 42, 43, 45 gnd ads809 0.1 f 0.01 f 0.01 f 0.01 f +v s 3, 4 5, 8, 31 gnd 0.1 f vdrv 26 9, 27 gnd 0.1 f +3v, +5v +5v if the analog inputs to the ads809 are driven differentially, it is especially important to optimize towards a highly symmetri- cal layout. small trace length differences may create phase shifts compromising a good distortion performance. for this reason, the use of two single op amps (rather than one dual amplifier) enables a more symmetrical layout and a better match of parasitic capacitances. the pin orientation of the ads809 package follows a flow-through design with the analog inputs located on one side of the package while the digital outputs are located on the opposite side of the quad- flat package. this provides a good physical isolation be-
ads809 17 sbas170b www.ti.com tween the analog and digital connections. while designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog portion. also, try to match trace length for the differential clock signal (if used) to avoid mismatches in propagation delays. single- ended clock lines must be short and should not cross any other signal traces. short-circuit traces on the digital outputs will minimize ca- pacitive loading. trace length should be kept short to the receiving gate (< 2") with only one cmos gate connected to one digital output. if possible, the digital data outputs should be buffered (with a 74lcx571, for example). dynamic perfor- mance may also be improved with the insertion of series resistors at each data output line. this sets a defined time constant and reduces the slew rate that would otherwise flow, due to the fast edge rate. the resistor value may be chosen to result in a time constant of 15% to 25% of the used data rate. layout of pcb with powerpad thermally enhanced packages the ads809 is housed in a 48-lead powerpad thermally enhanced package. to make optimum use of the thermal efficiencies designed into the powerpad package, the pcb must be designed with this technology in mind. please refer to slma004 powerpad brief powerpad made easy (refer to our web site at www.ti.com), which addresses the specific considerations required when integrating a powerpad pack- age into the pcb design. for more detailed information, including thermal modeling and repair procedures, please see slma002 technical brief powerpad thermally en- hanced package (www.ti.com).
ads809 18 sbas170b www.ti.com mpqf051 january 1998 php (s-pqfp-g48) powerpad ? plastic quad flatpack thermal pad (see note d) gage plane 0,13 nom 0,25 0,45 0,75 seating plane 4146927/a 01/98 0,17 0,27 24 25 13 12 sq 36 37 7,20 6,80 48 1 5,50 typ sq 8,80 9,20 1,05 0,95 1,20 max 0,50 m 0,08 0,08 0 C 7 0,05 0,15 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. the package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. this pad is electrically and thermally connected to the backside of the die and possibly selected leads. e. falls within jedec ms-026 package drawing
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