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? semiconductor components industries, llc, 2004 february, 2004 ? rev. 5 1 publication order number: ncp1010/d ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 self-supplied monolithic switcher for low standby- power offline smps the ncp101x series integrates a fixed?frequency current?mode controller and a 700 v voltage mosfet. housed in a pdip?7 package, the ncp101x of fers everything needed to build a rugged and low?cost power supply, including soft?start, frequency jittering, short?circuit protection, skip?cycle, a maximum peak current setpoint and a dynamic self?supply (no need for an auxiliary winding). unlike other monolithic solutions, the ncp101x is quiet by nature: during nominal load operation, the part switches at one of the available frequencies (65?100?130 khz). when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so?called skip cycle mode and provides excellent efficiency at light loads. because this occurs at typically 1/4 of the maximum peak value, no acoustic noise takes place. as a result, standby power is reduced to the minimum without acoustic noise generation. short?circuit detection takes place when the feedback signal fades away, e.g. in true short?circuit conditions or in broken optocoupler cases. external disabling is easily done either simply by pulling the feedback pin down or latching it to ground through an inexpensive scr for complete latched?off. finally soft?start and frequency jittering further ease the designer task to quickly develop low?cost and robust offline power supplies. for improved standby performance, the connection of an auxiliary winding stops the dss operation and helps to consume less than 100 mw at high line. in this mode, a built?in latched overvoltage protection prevents from lethal voltage runaways in case the optocoupler would brake. these devices are available in ec onomical 8?pin dual?in?line and 4?pin sot?223 packages. features ? built?in 700 v mosfet with typical rds (on) of 11 and 22 ? large creepage distance between high?voltage pins ? current?mode fixed frequency operation: 65 khz100 khz?130 khz ? skip?cycle operation at low peak currents only: no acoustic noise! ? dynamic self?supply, no need for an auxiliary winding ? internal 1.0 ms soft?start ? latched overvoltage protection with auxiliary winding operation ? frequency jittering for better emi signature ? auto?recovery internal output short?circuit protection ? below 100 mw standby power if auxiliary winding is used ? internal temperature shutdown ? direct optocoupler connection ? spice models available for transient analysis typical applications ? low power ac/dc adapters for chargers ? auxiliary power supplies (usb, appliances, tvs, etc.) pdip?7 case 626a ap suffix 1 8 marking diagrams http://onsemi.com p101xapyy awl yyww 1 see detailed ordering and shipping information in the package dimensions section on page 22 of this data sheet. ordering information sot?223 case 318e st suffix 1 4 101xy alyw 1 4 x = current limit (0, 1, 2, 3, 4) yy = 06 (65 khz), 10 (100 khz), 13 (130 khz) y = oscillator frequency a (65 khz), b (100 khz), c (130 khz) a = assembly location wl, l = wafer lot yy, y = year ww, w = work week
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 2 1 vcc 8 gnd 2 nc 3 nc 4 fb 7 nc 5 drain (top view) pin connections pdip?7 sot?223 (top view) 1 2 3 4 vcc fb drain gnd indicative maximum output power from ncp1014 rdson?ip 230 vac 100?250 vac 11 ?450 ma dss 14 w 6.0 w 11 ?450 ma auxiliary winding 19 w 8.0 w 1. informative values only, with: tamb = 50 c, fswitching = 65 khz, circuit mounted on minimum copper area as recommended. figure 1. typical application example 27 3 45 18 100?250 vac + + ncp101x vout + gn d quick selection table ncp1010* ncp1011* ncp1012 ncp1013 ncp1014 rds (on) [ ] 22 11 ipeak [ma] 100 250 250 350 450 freq [khz] 65 100 130 65 100 130 65 100 130 65 100 130 65 100 * versions 65, 130 khz of ncp1010 and 65, 100 khz of ncp1011 will be released in q1, 2004.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 3 pin function description pin no. (sot?223) pin no. (pdip?7) pin name function description 1 1 vcc powers the internal circuitry this pin is connected to an external capacitor of typically 10 f. the natural ripple superimposed on the v cc participates to the frequency jittering. for improved standby performance, an auxiliary v cc can be connected to pin 1. the v cc also includes an active shunt which serves as an opto fail?safe protection. ? 2 nc ? ? ? 3 nc ? ? 2 4 fb feedback signal input by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 5 drain drain connection the internal drain mosfet connection. ? ? ? ? ? ? 7 nc ? this unconnected pin ensures adequate creepage distance. 4 8 gnd the ic ground ? 60, 100 or 130 khz clock overload? uvlo management nc nc vcc fb drain nc gnd figure 2. simplified internal circuit architecture 2 1 3 4 iv cc i? vclamp* 4 v 18 k error flag armed? emi jittering v cc startup source drain flip?flop dcmax = 65% reset reset high when v cc 3 v driver s q r ? + iref = 7.4 ma iv cc set q v cc 8 rsense 250 ns l.e.b. 7 5 ? + + - soft?start startup sequence overload ? + 0.5 v drain *vclamp = vcc off + 200 mv (8.7 v typical)
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 4 maximum ratings rating symbol value unit power supply voltage on all pins, except pin 5 (drain) v cc ?0.3 to 10 v drain voltage ? ?0.3 to 700 v drain current peak during transformer saturation i ds(pk) 2 x i lim max a maximum current into pin 1 when activating the 8.7 v active clamp i_v cc 15 ma thermal resistance, junction?to?air pdip?7 r ja 100 c/w maximum junction temperature t jmax 150 c storage temperature range ? ?60 to +150 c esd capability, hbm model (all pins except hv) ? 2.0 kv esd capability, machine model ? 200 v
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 8.0 v unless otherwise noted.) rating pin symbol min typ max unit supply section and v cc management v cc increasing level at which the current source turns?off 1 vcc off 7.9 8.5 9.1 v v cc decreasing level at which the current source turns?on 1 vcc on 6.9 7.5 8.1 v v cc decreasing level at which the latch?off phase ends 1 vcc latch 4.4 4.7 5.1 v v cc decreasing level at which the internal latch is released 1 vcc reset ? 3.0 ? v internal ic consumption, mosfet switching at 65 khz 1 icc1 ? 0.92 1.1 (note 1) ma internal ic consumption, mosfet switching at 100 khz 1 icc1 ? 0.95 1.15 (note 1) ma internal ic consumption, mosfet switching at 130 khz 1 icc1 ? 0.98 1.2 (note 1) ma internal ic consumption, latch?off phase, v cc = 6.0 v 1 icc2 ? 290 ? a active zener voltage positive offset to vcc off 1 vclamp 140 200 300 mv latch?off current ncp1012/13/14 ncp1010/11 1 ilatch 6.3 5.8 7.4 7.3 9.2 9.0 ma power switch circuit power switch circuit on?state resistance ncp1012/13/14 (id = 50 ma) t j = 25 c t j = 125 c ncp1010/11 (id = 50 ma) t j = 25 c t j = 125 c 5 rds (on) ? 11 19 22 38 16 24 35 50 power switch circuit and startup breakdown voltage (id (off) = 120 a, t j = 25 c) 5 bvdss 700 ? ? v power switch and startup breakdown voltage off?state leakage current t j = 25 c (vds = 700 v) t j = 125 c (vds = 700 v) 5 5 ids(off) ? ? 50 30 ? ? a switching characteristics (rl = 50 , vds set for idrain = 0.7 x ilim) turn?on time (90%?10%) turn?off time (10%?90%) 5 5 ton toff ? ? 20 10 ? ? ns internal start?up current source high?voltage current source, v cc = 8.0 v ncp1012/13/14 ncp1010/11 1 ic1 5.0 5.0 8.0 8.5 10 10.3 ma high?voltage current source, v cc = 0 1 ic2 ? 10 ? ma current comparator t j = 25 c (note 1) maximum internal current setpoint, ncp1010 5 ipeak (22) 90 100 110 ma maximum internal current setpoint, ncp1011 5 ipeak (22) 225 250 275 ma maximum internal current setpoint, ncp1012 5 ipeak (11) 225 250 275 ma maximum internal current setpoint, ncp1013 5 ipeak (11) 315 350 385 ma maximum internal current setpoint, ncp1014 5 ipeak (11) 405 450 495 ma default internal current setpoint for skip cycle operation, percentage of max ip ? i lskip ? 25 ? % propagation delay from current detection to drain off state ? t del ? 125 ? ns leading edge blanking duration ? t leb ? 250 ? ns 1. see characterization curves for temperature evolution.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 6 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 8.0 v unless otherwise noted.) rating pin symbol min typ max unit internal oscillator oscillation frequency, 65 khz version, t j = 25 c (note 2) ? f osc 59 65 71 khz oscillation frequency, 100 khz version, t j = 25 c (note 2) ? f osc 90 100 110 khz oscillation frequency, 130 khz version, t j = 25 c (note 2) ? f osc 117 130 143 khz frequency dithering compared to switching frequency (with active dss) ? f dither ? 3.3 ? % maximum duty?cycle ? dmax 62 67 72 % feedback section internal pull?up resistor 4 rup ? 18 ? k internal soft?start (guaranteed by design) ? ts s ? 1.0 ? ms skip cycle generation default skip mode level on fb pin 4 vskip ? 0.5 ? v temperature management temperature shutdown ? tsd ? 150 ? c hysteresis in shutdown ? ? ? 50 ? c 2. see characterization curves for temperature evolution.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 7 figure 3. ic1 @ v cc = 8.0 v, fb = 1.5 v vs. temperature ?10.0 ?9.0 ?8.0 ?7.0 ?6.0 ?5.0 ?4.0 ?3.0 ?2.0 ?25 0 25 50 75 100 125 temperature ( c) ic1 ( ma) figure 4. icc1 @ v cc = 8.0 v, fb = 1.5 v vs. temperature 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 ?25 0 25 50 75 100 125 temperature ( c) icc1 (ma) figure 5. icc2 @ v cc = 6.0 v, fb = open vs. temperature 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40 ?25 0 25 50 75 100 125 temperature ( c) icc2 (ma) figure 6. v cc off, fb = 1.5 v vs. temperature 8.20 8.30 8.40 8.50 8.60 8.70 8.80 8.90 9.00 ?25 0 25 50 75 100 125 temperature ( c) vcc?off ( v ) figure 7. v cc on, fb = 3.5 v vs. temperature 7.00 7.10 7.20 7.30 7.40 7.50 7.60 7.70 7.80 7.90 8.00 ?25 0 25 50 75 100 125 temperature ( c) vcc?on ( v) figure 8. duty cycle vs. temperature 65 66 66 67 67 68 68 ?25 0 25 50 75 100 125 temperature ( c) duty?cycle (%)
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 8 figure 9. ilatch, fb = 1.5 v vs. temperature 7.00 7.20 7.40 7.60 7.80 8.00 8.20 8.40 8.60 8.80 9.00 ?25 0 25 50 75 100 125 temperature ( c) i_latch (ma) figure 10. ipeak?rr, v cc = 8.0 v, fb = 3.5 v vs. temperature 300 320 340 360 380 400 420 440 460 480 500 ?25 0 25 50 75 100 125 temperature ( c) ipeak (ma) figure 11. frequency vs. temperature 40 60 80 100 120 140 160 ?25 0 25 50 75 100 125 temperature ( c) fosc (khz) 100 khz 130 khz figure 12. on resistance vs. temperature, ncp1012/1013 0.00 5.00 10.00 15.00 20.00 25.00 ?25 0 25 50 75 100 12 5 temperature ( c) rds on ( )
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 9 application information introduction the ncp101x offers a complete current?mode control solution (actually an enhanced ncp1200 controller section) together with a high?voltage power mosfet in a monolithic structure. the component integrates everything needed to build a rugged and low?cost switch?mode power supply (smps) featuring low standby power. the quick selection table details the differences between references, mainly peak current setpoints and operating frequency. no need for an auxiliary winding: on semiconductor very high voltage integrated circuit technology lets you supply the ic directly from the high?voltage dc rail. we call it dynamic self?supply (dss). this solution simplifies the transformer design and ensures a better control of the smps in difficult output conditions, e.g. constant current operations. however, for improved standby performance, an auxiliary winding can be connected to the v cc pin to disable the dss operation. short?circuit protection: by permanently monitoring the feedback line activity, the ic is able to detect the presence of a short?circuit, immediately reducing the output power for a total system protection. once the short has disappeared, the controller resumes and goes back to normal operation. fail?safe optocoupler and ovp: when an auxiliary winding is connected to the v cc pin, the device stops its internal dynamic self?supply and takes its operating power from the auxiliary winding. a 8.7 v active clamp is connected between v cc and ground. in case the current injected in this clamp exceeds a level of 7.4 ma (typical), the controller immediately latches off and stays in this position until the user cycle v cc down to 3.0 v (e.g. unplugging the converter from the wall). by adjusting a limiting resistor in series with the v cc terminal, it becomes possible to implement an over voltage protection function, latching off the circuit in case of broken optocoupler or feedback loop problems. low standby?power: if smps naturally exhibits a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping unneeded switching cycles, the ncp101x drastically reduces the power wasted during light load conditions. an auxiliary winding can further help decreasing the standby power to extremely low levels by invalidating the dss operation. typical measurements show results below 80 mw @ 230 vac for a typical 7.0 w universal power supply. no acoustic noise while operating: instead of skipping cycles at high peak currents, the ncp101x waits until the peak current demand falls below a fixed 1/4 of the maximum limit. as a result, cycle skipping can take place without having a singing transformer you can thus select cheap magnetic components free of noise problems. spice model: a dedicated model to run transient cycle?by?cycle simulations is available but also an averaged version to help you closing the loop. ready?to?use templates can be downloaded in orcad's pspice, and intusoft's isspice4 from on semiconductor web site, ncp101x related section. dynamic self?supply when the power supply is first powered from the mains outlet, the internal current source (typically 8.0 ma) is biased and charges up the v cc capacitor from the drain pin. once the voltage on this v cc capacitor reaches the vcc off level (typically 8.5 v), the current source turns off and pulses are delivered by the output stage: the circuit is awake and activates the power mosfet. figure 13 details the internal circuitry. figure 13. the current source regulates v cc by introducing a ripple vref off = 8.5 v vref on = 7.5 v vref latch = 4.7 v* - + internal supply + vref vcc off +200 mv (8.7 v typ.) v cc + cv cc startup source drain *in fault condition being loaded by the circuit consumption, the voltage on the v cc capacitor goes down. when the dss controller detects that v cc has reached 7.5 v (vcc on ), it activates the internal current source to bring v cc toward 8.5 v and stops again: a cycle takes place whose low frequency depends on the v cc capacitor and the ic consumption. a 1.0 v ripple takes place on the v cc pin whose average value equals (vcc off + vcc on )/2. figure 14 portrays a typical operation of the dss.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 10 figure 14. the charge/discharge cycle over a 10 f v cc capacitor vcc 8.5 v 7.5 v device internally pulses startup period 8.00 6.00 4.00 2.00 0 as one can see, the v cc capacitor shall be dimensioned to offer an adequate startup time, i.e. ensure regulation is reached before v cc crosses 7.5 v (otherwise the part enters the fault condition mode). if we know that v = 1.0 v and icc1 (max.) is 1.1 ma (for instance we selected an 11 device switching at 65 khz), then the v cc capacitor can be calculated using: c icc1 tstartup v (eq. 1) . let's suppose that the smps needs 10 ms to startup, then we will calculate c to offer a 15 ms period. as a result, c should be greater than 20 f thus the selection of a 33 f/16 v capacitor is appropriate. short circuit protection the internal protection circuitry involves a patented arrangement that permanently monitors the assertion of an internal error flag. this error flag is, in fact, a signal that instructs the controller that the internal maximum peak current limit is reached. this naturally occurs during the startup period (vout is not stabilized to the target value) or when the optocoupler led is no longer biased, e.g in a short?circuit condition or when the feedback network is broken. when the dss normally operates, the logic checks for the presence of the error flag every time v cc crosses vcc on . if the error flag is low (peak limit not active) then the ic works normally. if the error signal is active, then the ncp101x immediately stops the output pulses, reduces its internal current consumption and does not allow the startup source to activate: v cc drops toward ground until it reaches the so?called latch?off level, where the current source activates again to attempt a new restart. if the error has gone, the ic automatically resumes its operation. if the default is still there, the ic pulses during 8.5 v down to 7.5 v and enters a new latch?off phase. the resulting burst operation guarantees a low average power dissipation and lets the smps sustain a permanent short?circuit. figure 15 presents the corresponding diagram. figure 15. simplified ncp101x short?circuit detection circuitry ? + 4 v fb division max ip flag v cc vcc on signal to latch reset current sense information clamp active? the protection burst duty?cycle can easily be computed through the various timing events as portrayed by figure 16.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 11 figure 16. ncp101x facing a fault condition (vin = 150 vdc) tstart ts w tlatch 1 v ripple latch?off level the rising slope from the latch?off level up to 8.5 v is expressed by: tstart v1 c ic1 . the time during which the ic actually pulses is given by tsw v2 c icc1 . finally, the latch?off time can be derived using the same formula topology: tlatch v3 c icc2 . from these three definitions, the burst duty?cycle can be computed: dc tsw tstart tsw tlatch (eq. 2) . dc v2 icc1
v2 icc1 v1 ic1 v3 icc2 (eq. 3) . feeding the equation with values extracted from the parameter section gives a typical duty?cycle of 13%, precluding any lethal thermal runaway while in a fault condition. dss internal dissipation the dynamic self?supplied pulls energy out from the drain pin. in flyback?based converters, this drain level can easily go above 600 v peak and thus increase the stress on the dss startup source. however, the drain voltage evolves with time and its period is small compared to that of the dss. as a result, the averaged dissipation, excluding capacitive losses, can be derived by: p dss icc1 vds(t) . (eq. 4) . figure 17 portrays a typical drain?ground waveshape where leakage effects have been removed. figure 17. a typical drain?ground waveshape where leakage effects are not accounted for. vds(t) vin vr toff dt ton t ts w by looking at figure 17, the average result can easily be derived by additive square area calculation: vds(t) vin(1 d) vr toff tsw (eq. 5) by developing equation 5, we obtain: vds(t) vin vin ton tsw vr toff tsw (eq. 6)
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 12 toff can be expressed by: toff ip lp vr (eq. 7) where ton can be evaluated by: ton ip lp vin (eq. 8) . plugging equations 7 and 8 into equation 6 leads to vds(t) vin and thus, p dss vin icc1 (eq. 9) . the worse case occurs at high line, when vin equals 370 vdc. with icc1 = 1.1 ma (65 khz version), we can expect a dss dissipation around 407 mw. if you select a higher switching frequency version, the icc1 increases and it is likely that the dss consumption exceeds that number. in that case, we recommend to add an auxiliary winding in order to of fer more dissipation room to the power mosfet. please read application note aevaluating the power capability of the ncp101x memberso to help in selecting the right part/configuration for your application. lowering the standby power with an auxiliary winding the dss operation can bother the designer when a) its dissipation is too high b) extremely low standby power is a must. in both cases, one can connect an auxiliary winding to disable the self?supply. the current source then ensures the startup sequence only and stays in the off state as long as v cc does not drop below vcc on or 7.5 v. figure 18 shows that the insertion of a resistor (rlimit) between the auxiliary dc level and the v cc pin is mandatory a) not to damage the internal 8.7 v active zener diode during an overshoot for instance (absolute maximum current is 15 ma) b) to implement the fail?safe optocoupler protection as offered by the active clamp. please note that there cannot be bad interaction between the clamping voltage of the internal zener and vcc off since this clamping voltage is actually built on top of vcc off with a fixed amount of offset (200 mv typical). self?supplying controllers in extremely low standby applications often puzzles the designer. actually, if a smps operated at nominal load can deliver an auxiliary voltage of an arbitrary 16 v (vnom), this voltage can drop to below 10 v (vstby) when entering standby. this is because the recurrence of the switching pulses expands so much that the low frequency refueling rate of the v cc capacitor is not enough to keep a constant auxiliary voltage. figure 19 portrays a typical scope shot of a smps entering deep standby (output unloaded). so care must be taken when calculating rlimit 1) to not trigger the v cc over current latch [by injecting 6.3 ma (min. value) into the active clamp] in normal operation but 2) not to drop too much voltage over rlimit when entering standby. otherwise the dss could reactivate and the standby performance would degrade. we are thus able to bound rlimit between two equations: vnom vclamp itrip rlimit vstby vcc on icc1 (eq. 10) where: vnom is the auxiliary voltage at nominal load. vstdby is the auxiliary voltage when standby is entered. itrip is the current corresponding to the nominal operation. it thus must be selected to avoid false tripping in overshoot conditions. icc1 is the controller consumption. this number slightly decreases compared to icc1 from the spec since the part in standby does almost not switch. vcc on is the level above which vauxiliary must be maintained to keep the dss in the off mode. it is good to shoot around 8.0 v in order to offer an adequate design margin, e.g. to not reactivate the startup source (which is not a problem in itself if low standby power does not matter). since rlimit shall not bother the controller in standby, e.g. keep vauxiliary to around 8.0 v (as selected above), we purposely select a vnom well above this value. as explained before, experience shows that a 40% decrease can be seen on auxiliary windings from nominal operation down to standby mode. let's select a nominal auxiliary winding of 20 v to offer sufficient margin regarding 8.0 v when in standby (rlimit also drops voltage in standby ). plugging the values in equation 10 gives the limits within which rlimit shall be selected: 20 8.7 6.3m rlimit 12 8 1.1m , that is to say : (eq. 11) 1.8 k rlimit 3.6 k if we design a power supply delivering 12 v, then the ratio between auxiliary and power must be: 12/20 = 0.6. the ovp latch will activate when the clamp current exceeds 6.3 ma. this will occur when vauxiliary grows?up to: 8.7 v + 1.8 k x (6.4m + 1.1m) = 22.2 v for the first boundary or 8.7 v + 3.6 k x (6.4m +1.1m) = 35.7 v for second boundary. on the power output, it will respectively give 22.2 x 0.6 = 13.3 v and 35.7 x 0.6 = 21.4 v. as one can see, tweaking the rlimit value will allow the selection of a given overvoltage output level. theoretically predicting the auxiliary drop from nominal to standby is an almost impossible exercise since many parameters are involved, including the converter time constants. fine tuning of rlimit thus requires a few iterations and experiments on a breadboard to check vauxiliary variations but also output voltage excursion in fault. once properly adjusted, the fail?safe protection will preclude any lethal voltage runaways in case a problem would occur in the feedback loop.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 13 figure 18. a more detailed view of the ncp101x offers better insight on how to properly wire an auxiliary winding. startup source drain + - ? + vcc on = 8.5 v vcc off = 7.5 v + v cc rlimit + - + i > 7.4m (typ.) + + cvcc caux laux ground + vclamp = 8.7 v typ. permanent latch d1 figure 19. the burst frequency becomes so low that it is difficult to keep an adequate level on the auxiliary vcc . . . 30 ms when an ovp occurs, all switching pulses are permanently disabled, the output voltage thus drops to zero. the v cc cycles up and down between 8.54.7 v and stays in this state until the user unplugs the power supply and forces v cc to drop below 3.0 v (vcc reset ). below this value, the internal ovp latch is reset and when the high voltage is reapplied, a new startup sequence can take place in an attempt to restart the converter. lowering the standby power with skip?cycle skip cycle offers an efficient way to reduce the standby power by skipping unwanted cycles at light loads. however, the recurrent frequency in skip often enters the audible range and a high peak current obviously generates acoustic noise in the transformer. the noise takes its origins in the resonance of the transformer mechanical structure which is excited by the skipping pulses. a possible solution, successfully implemented in the ncp1200 series, also authorizes skip cycle but only when the power demand as dropped below a given level. at this time, the peak current is reduced and no noise can be heard. figure 20 pictures the peak current evolution of the ncp101x entering standby.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 14 figure 20. low peak current skip cycle guarantees noise?free operation 100% peak current at nominal power 25% skip cycle current limit full power operation involves the nominal switching frequency and thus avoids any noise when running. experiments carried on a 5.0 w universal mains board unveiled a standby power of 300 mw @ 230 vac with the dss activated and dropped to less than 100 mw when an auxiliary winding is connected. frequency jittering for improved emi signature by sweeping the switching frequency around its nominal value, it spreads the energy content on adjacent frequencies rather than keeping it centered in one single ray. this offers the benefit to artificially reduce the measurement noise on a standard emi receiver and pass the tests more easily. the emi sweep is implemented by routing the v cc ripple (induced by the dss activity) to the internal oscillator. as a result, the switching frequency moves up and down to the dss rhythm. typical deviation is 3.3% of the nominal frequency. w ith a 1.0 v peak?to?peak ripple, the frequency will equal 65 khz in the middle of the ripple and will increase as v cc rises or decrease as v cc ramps down. figure 21 portrays the behavior we have adopted. figure 21. the v cc ripple is used to introduce a frequency jittering on the internal oscillator sawtooth. here, a 65 khz version was selected. v cc ripple vcc off 67.15 khz 65 khz 62.85 khz vcc on internal sawtooth
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 15 soft?start the ncp101x features an internal 1.0 ms soft?start activated during the power on sequence (pon). as soon as v cc reaches vcc off , the peak current is gradually increased from nearly zero up to the maximum internal clamping level (e.g. 350 ma). this situation lasts 1.0 ms and further to that time period, the peak current limit is blocked to the maximum until the supply enters regulation. the soft?start is also activated during the over current burst (ocp) sequence. every restart attempt is followed by a soft?start activation. generally speaking, the soft?start will be activated when v cc ramps up either from zero (fresh power?on sequence) or 4.7 v, the latch?off voltage occurring during ocp. figure 22 portrays the soft?start behavior. the time scales are purposely shifted to offer a better zoom portion. figure 22. soft?start is activated during a start?up sequence or an ocp condition. 0 v (fresh pon) or 4.7 v (overload) v cc 8.5 v current sense max ip 1.0 ms non?latching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the internal skip level (vskip), the output pulses are disabled. as soon as fb is relaxed, the ic resumes its operation. figure 23 depicts the application example. figure 23. a non?latching shutdown where pulses are stopped as long as the npn is biased. on/off 27 3 45 18 drain + cv cc
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 16 full latching shutdown other applications require a full latching shutdown, e.g. when an abnormal situation is detected (over temp or overvoltage). this feature can easily be implemented through two external transistors wired as a discrete scr. when the ovp level exceeds the zener breakdown voltage, the npn biases the pnp and fires the equivalent scr, permanently bringing down the fb pin. the switching pulses are disabled until the user unplugs the power supply. figure 24. two bipolars ensure a total latch?off of the smps in presence of an ovp 27 3 45 18 drain + cv cc bat54 10 k 10 k ovp rhold 12 k rhold ensures that the scr stays on when fired. the bias current flowing through rhold should be small enough to let the v cc ramp up (8.5 v) and down (7.5 v) when the scr is fired. the npn base can also receive a signal from a temperature sensor. typical bipolars can be mmbt2222 and mmbt2907 for the discrete latch. the mmbt3946 features two bipolars npn+pnp in the same package and could also be used. power dissipation and heatsinking the ncp101x welcomes two dissipating terms, the dss current?source (when active) and the mosfet. thus, ptot = p dss + p mosfet . when the pdip?7 package is surrounded by copper, it becomes possible to drop its thermal resistance junction?to?ambient, r j?a down to 75 c/w and thus dissipate more power. the maximum power the device can thus evacuate is: pmax tjmax tambmax r j ? a (eq. 12) which gives around 1.0 w for an ambient of 50 c. the losses inherent to the mosfet rds (on) can be evaluated using the following formula: pmos 1 3 ip 2 drds (on) (eq. 13) , where ip is the worse case peak current (at the lowest line input), d is the converter operating duty?cycle and rds (on) , the mosfet resistance for tj = 100 c. this formula is only valid for discontinuous conduction mode (dcm) operation where the turn?on losses are null (the primary current is zero when you restart the mosfet). figure 25 gives a possible layout to help dropping the thermal resistance. when measured on a 35 m (1 oz.) copper thickness pcb, we obtained a thermal resistance of 75 c/w. figure 25. a possible pcb arrangement to reduce the thermal resistance junction?to?ambient
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 17 design procedure the design of an smps around a monolithic device does not differ from that of a standard circuit using a controller and a mosfet. however, one needs to be aware of certain characteristics specific of monolithic devices: 1. in any case, the lateral mosfet body?diode shall never be forward biased, either during start?up (because of a large leakage inductance) or in normal operation as shown by figure 26. figure 26. the drain?source wave shall always be positive . . . 1.004m 1.011m 1.018m 1.025m 1.032m ? 50.0 50.0 150 250 350 > 0 !! as a result, the flyback voltage which is reflected on the drain at the switch opening cannot be larger than the input voltage. when selecting components, you thus must adopt a turn ratio which adheres to the following equation: n (vout vf) vin min (eq. 14) . for instance, if you operate from a 120 v dc rail and you deliver 12 v, we can select a reflected voltage of 100 vdc maximum: 120100 > 0. therefore, the turn ratio np:ns must be smaller than 100/(12 + 1) = 7.7 or np:ns < 7.7. we will see later on how it affects the calculation. 2. a current?mode architecture is, by definition, sensitive to subharmonic oscillations. subharmonic oscillations only occur when the smps is operating in continuous conduction mode (ccm) together with a duty?cycle greater than 50%. as a result, we recommend to operate the device in dcm only, whatever duty?cycle it implies (max. = 65%). however, ccm operation with duty?cycles below 40% is possible. 3. lateral mosfets have a poorly dopped body?diode which naturally limits their ability to sustain the avalanche. a traditional rcd clamping network shall thus be installed to protect the mosfet. in some low power applications, a simple capacitor can also be used since vdrain max vin n (vout vf) ip lf ctot (eq. 15) , where lf is the leakage inductance, ctot the total capacitance at the drain node (which is increased by the capacitor you will wire between drain and source), n the np:ns turn ratio, vout the output voltage, vf the secondary diode forward drop and finally, ip the maximum peak current. worse case occurs when the smps is very close to regulation, e.g. the vout target is almost reached and ip is still pushed to the maximum. taking into account all previous remarks, it becomes possible to calculate the maximum power that can be transferred at low line. when the switch closes, vin is applied across the primary inductance lp until the current reaches the level imposed by the feedback loop. the duration of this event is called the on time and can be defined by: ton lp ip vin (eq. 16) at the switch opening, the primary energy is transferred to the secondary and the flyback voltage appears across lp, resetting the transformer core with a slope of n (vout vf) lp . toff, the off time is thus: toff lp ip n (vout vf) (eq. 17) if one wants to keep dcm only, but still need to pass the maximum power, we will not allow a dead?time after the core is reset, but rather immediately restart. the switching time can be expressed by: tsw toff ton lp ip
1 vin 1 n (vout vf) (eq. 18)
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 18 the flyback transfer formula dictates that: pout 1 2 lpip 2 fsw (eq. 19) which, by extracting ip and plugging into equation 19, leads to: tsw lp 2 pout fswlp
1 vin 1 n (vout vf) (eq. 20) extracting lp from equation 20 gives: lp critical (vin vr) 2 2 fsw [pout (vr 2 2vrvin vin 2 )] (eq. 21) , with vr = n . (vout + vf) and the efficiency. if lp critical gives the inductance value above which dcm operation is lost, there is another expression we can write to connect lp, the primary peak current bounded by the ncp101x and the maximum duty?cycle that needs to stay below 50%: lpmax dcmax vinmin tsw ipmax (eq. 22) where v inmin corresponds to the lowest rectified bulk voltage, hence the longest ton duration or largest duty?cycle. ip max is the available peak current from the considered part, e.g. 350 ma typical for the ncp1013 (however, the minimum value of this parameter shall be considered for reliable evaluation). combining equations 21 and 22 gives the maximum theoretical power you can pass respecting the peak current capability of the ncp101x, the maximum duty?cycle and the discontinuous mode operation: pmax : tsw 2 vinmin 2 vr 2 (eq. 23) fsw (2 lpmax vr 2 4 lpmax vr vinmin 2 lpmax vinmin 2 ) from equation 22 we obtain the operating duty?cycle d ip lp vin tsw (eq. 24) which lets us calculate the rms current circulating in the mosfet: idrms ip d 3 (eq. 25) . from this equation, we obtain the average dissipation in the mosfet: pavg 1 3 ip 2 drds (on) (eq. 26) to which switching losses shall be added. if we stick to equation 23, compute lp and follow the above calculations, we will discover that a power supply built with the ncp101x and operating from a 100 vac line minimum will not be able to deliver more than 7.0 w continuous, regardless of the selected switching frequency (however the transformer core size will go down as fswitching is increased). this number grows up significantly when operated from a single european mains (18 w). application note aevaluating the power capability of the ncp101x memberso details how to assess the available power budget from all the ncp101x series. example 1, a 12 v 7.0 w smps operating on a large mains with ncp101x: vin = 100 vac to 250 vac or 140 vdc to 350 vdc once rectified, assuming a low bulk ripple efficiency = 80% vout = 12 v, iout = 580 ma fswitching = 65 khz ip max = 350 ma 10% = 315 ma applying the above equations leads to: selected maximum reflected voltage = 120 v with vout = 12 v, secondary drop = 0.5 v np:ns = 1:0.1 lp critical = 3.2 mh ip = 292 ma duty?cycle worse case = 50% idrain rms = 119 ma p mosfet = 354 mw at rdson = 24 (tj > 100 c) p dss = 1.1 ma x 350 v = 385 mw, if dss is used secondary diode voltage stress = (350 x 0.1) + 12 = 47 v (e.g. a mbrs360t3, 3.0 a/60 v would fit) example 2, a 12 v 16 w smps operating on narrow european mains with ncp101x: vin = 230 vac 15%, 276 vdc for vin min to 370 vdc once rectified efficiency = 80% vout = 12 v, iout = 1.25 a fswitching = 65 khz ip max = 350 ma 10% = 315 ma applying the equations leads to: selected maximum reflected voltage = 250 v with v out = 12 v, secondary drop = 0.5 v np:ns = 1:0.05 lp = 6.6 mh ip = 0.305 ma duty?cycle worse case = 0.47 idrain rms = 121 ma p mosfet = 368 mw at rdson = 24 (tj > 100 c) p dss = 1.1 ma x 370 v = 407 mw, if dss is used below an ambient of 50 c. secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 v (e.g. a mbrs340t3, 3.0 a/40 v) please note that these calculations assume a flat dc rail whereas a 10 ms ripple naturally affects the final voltage available on the transformer end. once the bulk capacitor has been selected, one should check that the resulting ripple (min vbulk?) is still compatible with the above calculations. as an example, to benefit from the largest operating range, a 7.0 w board was built with a 47 f bulk capacitor which ensured discontinuous operation even in the ripple minimum waves.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 19 mosfet protection as in any flyback design, it is important to limit the drain excursion to a safe value, e.g. below the mosfet bvdss which is 700 v. figure 27 presents possible implementations: figure 27. different options to clamp the leakage spike + ncp101x cvcc hv 1 8 2 3 4 7 5 + cvcc hv rclamp cclamp d 1 8 2 3 4 7 5 + cvcc hv d 1 8 2 3 4 7 5 + c dz 17a 17b 17c ncp101x ncp101x figure 27a : the simple capacitor limits the voltage according to equation 15. this option is only valid for low power applications, e.g. below 5.0 w, otherwise chances exist to destroy the mosfet. after evaluating the leakage inductance, you can compute c with equation 15. typical values are between 100 pf and up to 470 pf. large capacitors increase capacitive losses figure 27b : the most standard circuitry called the rcd network. you calculate rclamp and cclamp using the following formulae: rclamp 2 vclamp (vclamp (vout vf sec) n) lleak ip 2 fsw (eq. 27) cclamp vclamp vripple fsw rclamp (eq. 28) vclamp is usually selected 50?80 v above the reflected value n x (vout + vf). the diode needs to be a fast one and a mur160 represents a good choice. one major drawback of the rcd network lies in its dependency upon the peak current. worse case occurs when ip and vin are maximum and vout is close to reach the steady?state value. figure 27c : this option is probably the most expensive of all three but it offers the best protection degree. if you need a very precise clamping level, you must implement a zener diode or a tvs. there are little technology differences behind a standard zener diode and a tvs. however, the die area is far bigger for a transient suppressor than that of zener. a 5.0 w zener diode like the 1n5388b will accept 180 w peak power if it lasts less than 8.3 ms. if the peak current in the worse case (e.g. when the pwm circuit maximum current limit works) multiplied by the nominal zener voltage exceeds these 180 w, then the diode will be destroyed when the supply experiences overloads. a transient suppressor like the p6ke200 still dissipates 5.0 w of continuous power but is able to accept surges up to 600 w @ 1.0 ms. select the zener or tvs clamping level between 40 to 80 volts above the reflected output voltage when the supply is heavily loaded.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 20 typical application examples a 6.5 w watt ncp1012?based flyback converter figure 28 shows a converter built with a ncp1012 delivering 6.5 w from a universal input. the board uses the dynamic self?supply and a simplified zener?type feedback. this configuration was selected for cost reasons and a more precise circuitry can be used, e.g. based on a tl431: figure 28. an ncp1012?based flyback converter delivering 6.5 watts 1 2 j1 cee7.5/2 d1 d2 d3 d4 1n4007 1n4007 10 /16 v e1 10 /400 v e2 2 3 7 2 1 gnd gnd gnd vcc hv fb gnd ic1 ncp1012 r2 150 k d5 u160 5 4 4 8 c2 2n2/y 4 8 7 6 5 tr1 1 e3 470 /25 v d6 b150 r3 100 r r4 180 r 2 1 zd1 11 v j2 czm5/2 ic2 pc817 c1 2.2 nf 1n4007 1n4007 r1 47 r the converter built according to figure 29 layouts, gave the following results: ? efficiency at vin = 100 vac and pout = 6.5 w = 75.7% ? efficiency at vin = 230 vac and pout = 6.5 w = 76.5% figure 29. the ncp1012?based pcb layout . . . and its associated component placement a 7.0 watt ncp1013?based flyback converter featuring low standby power figure 30 depicts another typical application showing a ncp1013?65 khz operating in a 7.0 w converter up to 70 c of ambient temperature. we can grow?up the output power since an auxiliary winding is used, the dss is disabled, and thus offering more room for the mosfet. in this application, the feedback is made via a tlv431 whose low bias current (100 a min) helps to lower the no?load standby power.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 21 figure 30. a typical converter delivering 7.0 w from a universal mains 1 8 2 3 4 7 5 v cc nc nc fb gnd nc d vbulk c2 47 f/ 450 v + 1n4148 d4 r2 3.3 k + c10 33 f/25 v r4 22 ncp1013p06 + 100 f/10 v c3 c9 1 nf c8 10 nf 400 v r7 100 k/ 1 w d3 mur160 t1 12 v @ 0.6 a gnd d2 mbrs360t3 + + 100 f/16 v c7 + c6 c8 470 f/16 v r5 39 k r3 1 k ic1 sfh6156?2 c4 100 nf ic2 tlv431 r6 4.3 k c5 2.2 nf y1 type t1 aux l2 22 h measurements have been taken from a demonstration board implementing figure 30's sketch and the following results were achieved, with either the auxiliary winding in place or through the dynamic self?supply: vin = 230 vac, auxiliary winding, pout = 0, pin = 60 mw vin = 100 vac, auxiliary winding, pout = 0, pin = 42 mw vin = 230 vac, dynamic self?supply, pout = 0, pin = 300 mw vin = 100 vac, dynamic self?supply, pout = 0, pin = 130 mw pout = 7.0 w, = 81% @ 230 vac, with aux winding pout = 7.0 w, = 81.3 @ 100 vac, with aux winding for a quick evaluation of figure 30 application example, the following transformers are available from coilcraft: a9619?c, lp = 3.0 mh, np:ns = 1:0.1, 7.0 w application on universal mains, including auxiliary winding, ncp1013?65khz. a0032?a, lp = 6.0 mh, np:ns = 1:0.055, 10 w application on european mains, dss operation only, ncp1013?65 khz. coilcraft 1102 silver lake road cary il 60013 email: info@coilcraft.com tel.: 847?639?6400 fax.: 847?639?1469
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 22 ordering information device order number frequency (khz) package type shipping 2 r ds(on) ( ) ipk (ma) ncp1010ap065 65 ncp1010ap100 100 100 ncp1010ap130 130 23 ncp1011ap065 65 23 ncp1011ap100 100 ncp1011ap130 130 250 ncp1012ap065 65 pdip 7 50 units / rail 250 ncp1012ap100 100 pdip?7 50 units / rail ncp1012ap133 130 ncp1013ap065 65 11 ncp1013ap100 100 11 350 ncp1013ap133 130 ncp1014ap065 65 450 ncp1014ap100 100 450 ncp1010st65t3 65 ncp1010st100t3 100 100 ncp1010st130t3 130 23 ncp1011st65t3 65 23 ncp1011st100t3 100 ncp1011st130t3 130 250 ncp1012st65t3 65 sot 223 4000 units / ta p e & reel 250 ncp1012st100t3 100 sot?223 4000 units / tape & reel ncp1012st130t3 130 ncp1013st65t3 65 11 ncp1013st100t3 100 11 350 ncp1013st130t3 130 ncp1014st65t3 65 450 ncp1014st100t3 100 450 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 23 package dimensions pdip?7 ap suffix case 626a?01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. package contour optional (round or square corners). 4. dimension l to center of lead when formed parallel. 5. dimensions a and b are datums. 14 5 8 f note 3 ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 b a sot?223 st suffix case 318e?04 issue k h s f a b d g l 4 123 0.08 (0003) c m k j dim a min max min max millimeters 0.249 0.263 6.30 6.70 inches b 0.130 0.145 3.30 3.70 c 0.060 0.068 1.50 1.75 d 0.024 0.035 0.60 0.89 f 0.115 0.126 2.90 3.20 g 0.087 0.094 2.20 2.40 h 0.0008 0.0040 0.020 0.100 j 0.009 0.014 0.24 0.35 k 0.060 0.078 1.50 2.00 l 0.033 0.041 0.85 1.05 m 0 10 0 10 s 0.264 0.287 6.70 7.30 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch.
ncp1010, ncp1011, ncp1012, ncp1013, ncp1014 http://onsemi.com 24 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1010/d the products described herein (ncp1010, 1011, 1012, 1013, 1014), may be covered by one or more of the following u.s. patents: 6 ,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357, 6,633,193. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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