uc1860 uc2860 uc3860 resonant mode power supply controller features 3mhz vfo linear over 100:1 range 5mhz error amplifier with controlled output swing programmable one shot timer down to 100ns precision 5v reference dual 2a peak totem pole outputs programmable output sequence programmable under voltage lockout very low start up current programmable fault management & restart delay uncommitted comparator description the uc1860 family of control ics is a versatile system for resonant mode power supply control. this device easily implements frequency modulated fixed-on-time control schemes as well as a number of other power supply control schemes with its various dedicated and programmable features. the uc1860 includes a precision voltage reference, a wide-bandwidth er- ror amplifier, a variable frequency oscillator operable to beyond 3mhz, an oscillator-triggered one-shot, dual high-current totem-pole output drivers, and a programmable toggle flip-flop. the output mode is easily pro- grammed for various sequences such as a, off, b, off; a & b, off; or a, b, off. the error amplifier contains precision output clamps that allow pro- gramming of minimum and maximum frequency. the device also contains an uncommitted comparator, a fast comparator for fault sensing, programmable soft start circuitry, and a programm able restart delay. hic-up style response to faults is easily achieved. in addi- tion, the uc1860 contains programmable under voltage lockout circuitry that forces the output stages low and minimizes supply current during start-up conditions. block diagram absolute maximum ratings supply voltage (pin 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v output current, source or sink (pins 17 & 20) dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a pulse (0.5 m s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0a power ground voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2v inputs (pins 1, 2, 3, 4, 8, 9, 11, 12, 13, 14, 21, 22, 23 & 24) . . . . . . . . . . . . . . . . . . . . . . -0.4 to 6v error amp output current, source or sink (pin 5) . . . . . . . . 2ma i vfo current (pin 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ma comparator output current (pin 15) . . . . . . . . . . . . . . . . . . 5ma comparator output voltage (pin 15) . . . . . . . . . . . . . . . . . . 15v soft start or restart delay sink current (pins 22 & 23) . . . 5ma power dissipation at t a = 50c (dip) . . . . . . . . . . . . . . . 1.25w power dissipation at t a = 50 c (plcc) . . . . . . . . . . . . . . . . 1w lead temperature (soldering, 10 seconds) . . . . . . . . . . . 300c note: all voltages are with respect to signal ground and all currents are positive into the specified terminal. pin numbers refer to the dip. refer to packaging section of databook for thermal limitations and considerations of packages. 10/93
uc1860 uc2860 uc3860 electrical characteristics: parameter conditions min typ max units reference section output voltage t a = 25c, i o = 0 4.95 5.00 5.05 v i o = 0, over temp 4.93 5.07 v line regulation 10 v cc 20v 2 15 mv load regulation 0 i o 10ma 2 25 mv output noise voltage* 10hz f 10khz 50 m v rms short circuit current v ref = 0v -150 -15 ma error amplifier section input offset voltage 2.8 v cm 4.5v 1 8 mv input bias current 50 500 na open loop gain dv o = 1.5v 60 80 db psrr 10 v cc 20v 70 100 db output low (v o -vi vfo ) -0.1 i o 0.1ma -8 0 8 mv output high (v o -vi vfo ) -0.5 i o 0.5ma 1.9 2 2.1 v unity gain bandwidth* r in = 2k 4 5 mhz oscillator section nominal frequency* 1.0 1.5 2.0 mhz df/di osc * 100 i vfo 500 m a 2 3 4 ghz/a *guaranteed by design but not 100% tested. unless otherwise stated, all specifications apply for -55c t a 125c for the uc1860, -25c t a 85c for the uc2860, 0 t a 70c for the uc3860, v cc = 12v, c vfo = 330pf, i vfo = 0.5ma, c = 330pf, and r = 2.7k, t a = t j. dil - 24 (top view) j or n package plcc-28, lcc-28 (top view) q or l package pin package function function pin s gnd 1 i vfo 2 c vfo 3 rc 4 v ref 5 cmp in (-) 6 cmp in (+) 7 trig 8 osc dsbl 9 cmp out 10 n/c 11, 12 out a 13 pgnd 14 n/c 15 v cc 16 out b 17 n/c 18, 19 mode 20 sft strt 21 rst dly 22 uvlo 23 flt (-) 24 flt (+) 25 ea in (+) 26 ea in (-) 27 ea out 28 connection diagram 2
uc1860 uc2860 uc3860 electrical characteristics: parameter conditions min typ max units oscillator section (contd) trig in threshold 1.0 1.4 1.8 v trig in open circuit voltage 0.7 0.9 1.1 v trig in delta (v th -v oc ) 0.3 0.5 0.7 v trig in input resistance dv t rig = v oc to v th 51225k w minimum trig in pulse width* 3 10 ns osc. disable threshold 1.0 1.4 1.8 v one shot timer on time* 150 200 250 ns clamp frequency* i vfo = 1.5ma 2.8 3.7 4.6 mhz dead time* i vfo =1.5ma 35 70 100 ns output stage output low saturation 20ma 0.2 0.4 v 200ma 0.5 2.2 v output high saturation -20ma 1.5 2.0 v -200ma 1.7 2.5 v rise/fall time* c load = 1nf 1530ns uvlo low saturation 20ma 0.8 1.5 v output mode low input 0.4 v output mode high input 2.0 v under voltage lockout section v cc comparator threshold on 16 17.3 18.5 v off 9.5 10.5 12 v uvlo comparator threshold on 3.6 4.2 4.8 v hysteresis 0.2 0.4 0.6 v uvlo input resistance uvlo = 4/v cc = 8 102350k w v ref comparator threshold v cc = uvlo = v ref 4.5 4.9 v supply current i cc v cc = 12v, v osc dsbl = 3v 30 40 ma i start uvlo pin open v cc = v cc (on) -0.3v 0.3 0.5 ma fault comparator input offset voltage - 0.3 v cm 3v 2 10 mv input bias current v cm = 0v 100 200 m a input offset current v cm = 0v 10 30 m a propagation delay to output* 50mv input 100 150 ns uncommitted comparator input offset voltage -0.3 v cm 3v 2 10 mv input bias current v cm = 0v 100 200 m a input offset current v cm = 0v 10 30 m a output low voltage i o = 2ma 0.3 0.5 v propagation delay to sat* 50mv input, 2.5k load to 5v 50 100 ns soft start/restart control section saturation voltage (2 pins) i sink = 100 m a0.20.5v charge current (2 pins) 2 5 10 m a restart delay threshold 2.8 3.0 3.2 v *guaranteed by design but not 100% tested. unless otherwise stated, all specifications apply for -55c t a 125c for the uc1860, -25 t a 85c for the uc2860, 0 t a 70c for the uc3860, v cc = 12v, c vfo = 330pf, i vfo = 0.5ma, c = 330pf, and r = 2.7k, t a = t j. 3
uc1860 uc2860 uc3860 error amplifier the error amplifier is a high gain, low offset, high bandwidth de- sign with precise limits on its output swing. the bandwidth of the amplifier is externally determined by the resistance seen at the inverting input. unity gain bandwidth is approximately: frequency (0db) = 1/(2 p * r in (-) * c comp ) the input common mode range of the amplifier is from 2.8 to 4.5v. as long as one pin is within this range, the other can go as low as zero. the output swing with respect to the l vfo pin is limited from zero to 2v. note that pulling sft strt ( soft start) low will lower the ref- erence of the upper clamp. the lower clamp, however, will dominate should the upper clamp reference drop below the lower reference. under voltage lockout section the under voltage lockout consists of three comparators that monitor v cc , uvlo and v ref . the v ref comparator makes sure that the reference voltage is sufficiently high before op- eration begins. when the uvlo comparator is low, the outputs are driven low, the fault latch is reset, the soft start pin is dis- charged, and the toggle flip-flop is loaded for output a. the v cc comparator is used for off-line applications by leaving the uvlo pin open. in this application the supply current is typically less than 0.3ma during start-up. the uvlo comparator is used for dc to dc applications or to gate the chip on and off. to utilize its hysteretic threshold by an external resistive divider, the internal impedance of the pin must be accounted for. to run from a 5v external s upply, uvlo, v cc , and v ref are tied together. i cc vs v cc 4
uc1860 uc2860 uc3860 variable frequency oscillator the vfo block is controlled through 4 pins: c vfo , l vfo , osc dsbl (oscillator disable), and trig (trigger input). os- cillator frequency is approximately: frequency = i vfo /(c vfo * 1v) with a fixed capacitor and low voltage applied to trig and osc dsbl, frequency is linearly modulated by varying the current into the l vfo pin. the trig and osc dsbl inputs are used to modify vfo op- eration. if osc dsbl is held high, the oscillator will com- plete the current cycle but wait until osc dsbl is returned low to initiate a new cycle. if a pulse is applied to trig dur- ing a cycle, the oscillator will immediately initiate a new cycle. osc dsbl has priority over trig, but if a trigger pulse is received while osc dsbl is high, the vfo will remember the trigger pulse and start a new cycle as soon as osc dsbl goes low. normally low trigger pulses are used to synchronize the oscillator to a faster clock. normally high trigger pulses can also be used to synchronize to a slower clock. one shot timer the one shot timer performs three functions and is pro- grammed by the rc pin. the first function is to control output driver pulse width. secondly, it clocks the toggle flip-flop. thirdly, it establishes the maximum allowable fre- quency for the vfo. one shot operation is initiated at the beginning of each oscillator cycle. the rc pin, pro- grammed by an external resistor and capacitor to ground, is charged to approximately 4.3v and then allowed to dis- charge. the lower threshold is approximately 80% of the peak. on time is approximately: t(on) = 0.2 * r * c. after crossing the lower threshold, the resistor continues to discharge the capacitor to approximately 3v, where it waits for the next oscillator cycle. maximum frequency vs r on time vs r vfo frequency vs i vfo 5
uc1860 uc2860 uc3860 fault management section during uvlo, the fault management section is initialized. the latch is reset, and both sft strt (soft start) and rst dly (restart delay) are pulled low. when sft strt is low, it low- ers the upper clamp of the error amplifier. as sft strt in- creases in voltage, the upper clamp increases from a value equal to the lower clamp until it is 2v more positive. a capacitor to ground from the sft strt pin will control the start rate. uncommitted comparator the uncommitted comparator, biased from the reference voltage, operates independently from the rest of the chip. the open collector output is capable of sinking 2ma. the inputs are valid in the common mode range of -0.3 to 3.0v. as long as one of the inputs is within this range, the other can be as high as 5v. the high speed fault comparator will work over the input common mode range of -0.3 to 3.0v. when a fault is sensed, the one shot is immediately terminated, sft strt is pulled low, and rst dly is allowed to go high. three modes of fault disposition can easily be implemented. if rst dly is externally held low, then a detected fault will shut the chip down permanently. if the rst dly pin is left open, a fault will simply cause an interruption of opera- tion. if a capacitor is connected from rst dly to ground, then hic-up operation is implemented. the hic-up time is: t (off) = 600 kohm * c(rst dly). input bias current input voltage 6
uc1860 uc2860 uc3860 open loop laboratory test fixture the open loop laboratory test fixture is designed to allow familiarization with the operating characteristics of the uc3860. note the pin numbers apply to the dlp. to get started, preset all the options as follows: adjust the error amplifier variable resistor pot (r1) so the wiper is at a high potential. open the l vfo resistor switch (s1). throw the trig switch (s2) to ground. throw the osc dsbl switch (s3) to ground. throw the uncommitted comparator switch (s4) to ground. throw the uvlo switch (s5) to the resistive divider. throw the out mode switch (s6) to ground. open the restart delay switch (s7). throw the fault switch (s8)to ground. in this configuration, the chip will operate for vcc greater than 12v. adjustment of the following controls allows ex- amination of specific features. r1 adjusts the output of the error amp. notice the voltage at pin 5 is limited from 0 to 2v above the voltage at pin 7. s1 changes the error amp output to vfo gain. with s1 open, the maximum frequency is determined by the error amp output. with s1 closed, the one shot will set the maximum frequency. s2 demonstrates the trigger. an external trigger signal may be applied. when the switch is set to the resistive di- vider, the chip will operate in consecutive mode (ie: a,b, off,...) s3 allows input of an external logic signal to disable the oscillator. s4 demonstrates the uncommitted comparator. when set to output a, the comparator will accelerate the discharge of pin 9, shortening the output pulse. s5 shorted to ground will disable the chip and the outputs will be low. if the switch is open, the v cc start and stop thresholds are 17 and 10v. switched to the resistive di- vider, the thresholds are approximately 12 and 10v. s6 sets the mode of the toggle flip-flop. when grounded, the outputs operate alternately. switched to 5v, the out- puts switch in unison. (note: if s6 and s2 are set for uni- son operation and triggered consecutive outputs, the chip will free run at the maximum frequency determined by the one shot.) s7 open allows the chip to restart immediately after a fault sense has been removed. when grounded, it causes the chip to latch off indefinitely. this state can be reset by uvlo, v cc , or opening the switch. connected to i m f pro- grams a hic-up delay time of 600 ms. s8 allows the simulation of a fault state. when flipped to the rc network, the comparator monitors scaled average voltage of output b. adjusting frequency will cause the comparator to sense a fault and the chip will enter fault sequence. 7
uc1860 uc2860 uc3860 output stage the two totem pole output stages can be programmed by mode to operate alternately or in unison. when mode is low the outputs alternate. during uvlo, the outputs are low. extreme care needs to be exercised in the application of these outputs. each output can source and sink transient currents of 2a or more and is designed for high values of dl/dt. this dictates the use of a ground plane, shielded in- terconnect cables, schottky diode clamps from the output pins to pwr gnd (power ground), and some series resis- tance to provide damping. pwr gnd should not exceed 0.2v from signal ground. bypass note the reference should be bypassed with a 0.1 m f ceramic capacitor from the v ref pin directly to the ground plane near the signal ground pin. the timing capacitors on c vfo and rc should be treated likewise. v cc , however, should be bypassed with a ceramic capacitor from the v cc pin to the section of ground plane that is connected to power ground. any required bulk reservoir capacitor should parallel this one. the two ground plane sections can then be joined at a single point to optimize noise re- jection and minimize dc drops. output saturation voltage vs load current output saturation voltage vs load current output rise & fall time vs load capacitance unitrode integrated circuits 7 continental bl vd. merrimack, nh 03054 tel. 603-424-2410 fax 603-424-3460 8
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