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ae2.0e fujitsu semiconductor data sheet 1 (3/2004) memory mobile fcram tm cmos 128m bit (8m word x 16 bit) mobile phone application specific memory mb82dbr08163a -70l cmos 8,388,608-word x 16 bit fast cycle random access memory with low power sram interface programmable page mode & burst mode n n n n description the fujitsu mb82dbr08163a is a cmos fast cycle random access memory (fcram) with asynchronous static random access memory (sram) interface containing 134,217,728 storages accessible in a 16-bit format. the mb82dbr08163a adopts asynchronous page mode and synchronous burst mode for fast memory access as user configurable options. the mb82dbr08163a is suited for mobile applications such as cellular handset and pda. n n n n features notice: fcram is a trademark of fujitsu limited, japan ? fast access cycle time t ce = 70ns max ? 8 words page read access capability t pa a = 20ns max ? burst read/write access capability t ac = 11ns max ? low voltage operating condition v dd = +2.6 to +3.1v ?v ddq = +1.65v to +1.95v ? wide operating temperature t a = -30c to +85c ? byte control by ub and lb ? low power consumption i dda1 = 35ma max i dds1 =300 m a max ? various power down mode sleep, 16m-bit and 32m-bit partial
2 (ae2.0e) mb82dbr08163a -70l preliminary n n n n pin description n n n n block diagram pin name description a 22 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) clk clock input adv address valid input (low active) wait wait signal output dq 16-9 upper byte data input/output dq 8-1 lower byte data input/output v dd power supply v ddq i/o power supply v ss ground a22 to a3 y controller memory cell array 134,217,728bit dq16 to dq9 dq8 to dq1 v dd v ddq v ss we ub ce2 lb burst address counter ce 1 oe x controller serial to parallel converter address controller memory core controller mode controller command decoder adv bus controller i/o buffer a2 to a0 parallel to serial clk address latch & buffer wait read amp write amp burst controller
3 (ae2.0e) mb82dbr08163a -70l preliminary n n n n function truth table asynchronous operation (page mode) notes l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance *1: should not be kept this logic condition longer than 1 m s. please contact local fujitsu representative for the relaxation of 1 m s limitation. *2: power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to "power down" in functional description for the details. *3: "l" for address pass through and "h" for address latch on the rising edge of adv . *4: oe can be v il during write operation if the following conditions are satisfied; (1) write pulse is initiated by ce 1 (refer to ce 1 controlled write timing), or cycle time of the previous operation cycle is satisfied. (2) oe stays v il during write cycle. *5: can be either v il or v ih but must be valid before read or write. *6: output is either valid or high-z depending on the level of ub and lb input. mode note ce2 ce 1clkadv we oe lb ub a22-0 dq8-1 dq16-9 wait standby (deselect) hhxxxxxx xhigh-zhigh-zhigh-z output disable *1 hl x *3 h h x x *5 high-z high-z high-z output disable (no read) x*3 hl h h valid high-z high-z high-z read (upper byte) x *3 h l valid high-z output valid high-z read (lower byte) x *3 l h valid output valid high-z high-z read (word) x *3 l l valid output valid output valid high-z page read x *3 l/h l/h valid *6 *6 high-z no write x *3 l *4 h h h valid invalid invalid high-z write (upper byte) x *3 h l valid invalid input valid high-z write (lower byte) x *3 l h valid input valid invalid high-z write (word) x *3 l l valid input valid input valid high-z power down *2lxxxxxxx xhigh-zhigh-zhigh-z
4 (ae2.0e) mb82dbr08163a -70l preliminary n n n n function truth table (continued) synchronous operation (burst mode) notes l = v il , h = v ih , x can be either v il or v ih , = valid edge, = positive edge of low pulse, high-z = high impedance *1: should not be kept this logic condition longer than 4 m s. please contact local fujitsu representative for the relaxation of 4 m s limitation. *2: power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to "power down" in functional description for the details. *3: valid clock edge shall be set on either positive or negative edge through cr set. clk must be started and stable prior to memory access. *4: can be either v il or v ih except for the case the both of oe and we are v il . it is prohibited to bring the both of oe and we to v il *5: when device is operating in "we single clock pulse control" mode, we is dont care once write operation is determined by we low pulse at the beginning of write access together with address latching. write suspend feature is not supported in "we single clock pulse control" mode *6: can be either v il or v ih but must be valid before read or write is determined. and once ub and lb inputs are determined, they must not be changed until the end of burst. *7: once valid address is determined, input address must not be changed during adv =l. *8: if oe =l, output is either invalid or high-z depending on the level of ub and lb input. if we =l, input is invalid. if oe =we =h, output is high-z. *9: output is either valid or high-z depending on the level of ub and lb input. *10: input is either valid or invalid depending on the level of ub and lb input. *11: output is either high-z or invalid depending on the level of oe and we input. *12: keep the level from previous cycle except for suspending on last data. refer to "wait output function" in functional description for the details. *13: wait output is driven in high level during write operation. mode note ce2 ce 1clkadv we oe lb ub a22-0 dq8-1 dq16-9 wait standby (deselect) h h x x x x x x x high-z high-z high-z start address latch *1 l *3 *4 x *4 x *6 x *6 x *7 valid *8 high-z *8 high-z *11 high-z advance burst read to next address *1 *3 h h l x *9 output valid *9 output valid output valid burst read suspend *1 *3 h high-z high-z *12 high advance burst write to next address *1 *3 *5 l h *10 input valid *10 input valid *13 high burst write suspend *1 *3 *5 h input invalid input invalid *12 high te r m i n a t e burst read x h x high-z high-z high-z te r m i n a t e burst write x x h high-z high-z high-z power down *2l xxxxxxx xhigh-zhigh-zhigh-z
5 (ae2.0e) mb82dbr08163a -70l preliminary n n n n state diagram notes assuming all the parameters specified in ac characteristics are satisfied. refer to the func- tional description, ac characteristics, and timing diagram for details. asynchronous operation (page mode) synchronous operation (burst mode) common state cr set power down standby standby standby output disable write read power up pause time ce2=l ce2=h ce 1=l ce 1=h ce2=ce 1=h ce 1=l & oe =l ce 1=l & we =l ce 1=h ce 1=h oe =l we =h oe =h we =l address change or byte control byte control byte control @oe =l standby write read ce2=ce 1=h ce 1=l, adv low pulse, & oe =l ce 1=h adv low pulse adv low pulse (@bl=8 or 16, and after burst operation is completed) ce 1=h read suspend oe =h we =l adv low pulse initial/standby state asynchronous operation synchronous operation power down ce2=l ce2=h @m=0 @m=1 write suspend we =h oe =l ce 1=l, adv low pulse, & we =l ce 1=h ce 1=h
6 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description this device supports asynchronous page read & normal write operation and synchronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as user configurable option. power-up it is required to follow the power-up timing to start executing proper device operation. refer to power-up timing. after power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. configuration register the configuration register (cr) is used to configure the type of device function among optional features. each selection of features is set through cr set sequence after power-up. if cr set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration cr set sequence the cr set requires total 6 read/write operations with unique address. between each read/write operation requires that device being in standby mode. following table shows the detail sequence. the first cycle is to read from most significant address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written into the different address, the cr set is cancelled and the data written by the second or third cycle is valid as a normal write operation. the forth and fifth cycle is to write to msb. the data of forth and fifth cycle is dont-care. if the forth or fifth cycle is written into different address, the cr set is also cancelled but write data may not be written as normal write operation. the last cycle is to read from specific address key for mode selection. and read data (rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in memory cell array may be lost. so, it should perform the cr set sequence prior to regular read/ write operation if necessary to change from default configuration. cycle # operation address data 1st read 7fffffh (msb) read data (rda) 2nd write 7fffffh rda 3rd write 7fffffh rda 4th write 7fffffh x 5th write 7fffffh x 6th read address key read data (rdb)
7 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) address key the address key has the following format. notes *1: a22, a21, a8, and a6 to a0 must be all "1" in any cases. *2: it is prohibited to apply this key. *3: if m=0, all the registers must be set with appropriate key input at the same time. *4: if m=1, ps must be set with appropriate key input at the same time. except for ps, all the other key inputs must be "1". *5: burst read & single write is not supported at we single clock pulse control. address pin register name function key description note a22-a21 1 unused bits muse be 1 *1 a20-a19 ps partial size 00 32m partial 01 16m partial 10 reserved for future use *2 11 sleep [default] a18-a16 bl burst length 000 reserved for future use *2 001 reserved for future use *2 010 8 words 011 16 words 100 reserved for future use *2 101 reserved for future use *2 110 reserved for future use *2 111 continuous a15 m mode 0 synchronous mode (burst read / write) *3 1 asynchronous mode [default] (page read / normal write) *4 a14-a12 rl read latency 000 reserved for future use *2 001 3 clocks 010 4 clocks 011 5 clocks 1xx reserved for future use *2 a11 bs burst sequence 0 reserved for future use *2 1 sequential a10 sw single write 0 burst read & burst write 1 burst read & single write *5 a9 ve valid clock edge 0 falling clock edge 1 rising clock edge a8 1 unused bits muse be 1 *1 a7 wc write control 0 we single clock pulse control without write suspend function *5 1 we level control with write suspend function a6-a0 1 unused bits muse be 1 *1
8 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) power down the power down is low power idle state controlled by ce2. ce2 low drives the device in power down mode and maintains low power idle state as long as ce2 is kept low. ce2 high resume the device from power down mode. this device has three power down modes, sleep, 16m partial, and 32m partial. the selection of power down mode is set through cr set sequence. each mode has following data retention features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to perform cr set sequence to set to sleep mode after power-up in case of asynchronous operation. mode data retention size retention address sleep [default] no n/a 16m partial 16m bit 000000h to 0fffffh 32m partial 32m bit 000000h to 1fffffh
9 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) burst read/write operation synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. configuration register set is required to perform burst read & write operation after power-up. once cr set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding rl and bl that is set through cr set sequence together with operation mode. in order to perform synchronous burst read & write operation, it is required to control new signals, clk, adv and wait that low power srams dont have. address adv clk dq valid ce 1 oe wait high-z high-z rl bl q 2 q bl q 1 we high address adv clk dq valid ce 1 oe wait high-z high-z rl-1 bl d 2 d bl d 1 we high burst read operation burst write operation
10 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) clk input function the clk is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. the clk input increments device internal address counter and the valid edge of clk is referred for latency counts from address latch, burst write data latch, and burst read data out. during synchronous operation mode, clk input must be supplied except for standby state and power down state. clk is dont care during asynchronous operation. adv input function the adv is input signal to indicate valid address presence on address inputs. it is applicable to synchronous operation as well as asynchronous operation. adv input is active during ce 1=l and ce 1=h disables adv input. all addresses are determined on the positive edge of adv . during synchronous burst read/write operation, adv =h disables all address inputs. once adv is brought to high after valid address latch, it is inhibited to bring adv low until the end of burst or until burst operation is terminated. adv low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. during asynchronous operation, adv =h also disables all address inputs. adv can be tied to low during asynchronous operation and it is not necessary to control adv to high. wait output function the wait is output signal to indicate data bus status when the device is operating in synchronous burst mode. during burst read operation, wait output is enabled after specified time duration from oe =l. wait output low indicates data out at next clock cycle is invalid, and wait output becomes high one clock cycle prior to valid data out. during oe read suspend, wait output doesnt indicate data bus status but carries the same level from previous clock cycle (kept high) except for read suspend on the final data output. if final read data out is suspended, wait output become high impedance after specified time duration from oe =h. during burst write operation, wait output is enabled to high level after specified time duration from we =l and kept high for entire write cycles including we write suspend. the actual write data latching starts on the appropriate clock edge with respect to valid clock edge, read latency and burst length. during we write suspend, wait output doesnt indicate data bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data in is suspended, wait output become high impedance after specified time duration from we =h. this device doesnt incur additional delay against crossing device-row boundary or internal refresh operation. therefore, the burst operation is always started after fixed latency with respect to read latency. and there is no waiting cycle asserted in the middle of burst operation except for burst suspend by oe brought to high or we brought to high. thus, once wait output is enabled and brought to high, wait output keep high level until the end of burst or until the burst operation is terminated. when the device is operating in asynchronous mode, wait output is always in high impedance.
11 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) latency read latency (rl) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. it is set through cr set sequence after power- up. once specific rl is set through cr set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to rl-1. the burst operation is always started after fixed latency with respect to read latency set in cr. address adv clk valid q1 q2 q3 d1 d2 d3 d4 0 12 345 rl=3 q4 d5 dq [out] dq [in] ce 1 oe or we wait wait 6 q5 d5 q1 q2 d1 d2 d3 rl=4 q3 d4 dq [out] dq [in] wait wait q4 d5 q1 d1 d2 rl=5 q2 d3 dq [out] dq [in] wait wait q3 d4 high-z high-z high-z high-z high-z high-z
12 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) address latch by adv the adv indicates valid address presence on address inputs. during synchronous burst read/write operation mode, all the address are determined on the positive edge of adv when ce 1=l. the specified minimum value of adv =l setup time and hold time against valid edge of clock where rl count begin must be satisfied for appropriate rl counts. valid address must be determined with specified setup time against either the negative edge of adv or negative edge of ce 1 whichever comes late. and the determined valid address must not be changed during adv =l period. burst length burst length is the number of word to be read or write during synchronous burst read/write operation as the result of a single address latch cycle. it can be set on 8, 16 words boundary or continuous for entire address through cr set sequence. the burst type is sequential that is incremental decoding scheme within a boundary address. starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (=0). after completing read data out or write data latch for the set burst length, operation automatically ended except for continuous burst length. when continuous burst length is set, read/write is endless unless it is terminated by the positive edge of ce 1. single write single write is synchronous write operation with burst length =1. the device can be configured either to "burst read & single write" or to "burst read & burst write" through cr set sequence. once the device is configured to "burst read & single write" mode, the burst length for synchronous write operation is always fixed 1 regardless of bl values set in cr, while burst length for read is in accordance with bl values set in cr. write control the device has two types of we signal control method, "we level control" and "we single clock pulse control", for synchronous write operation. it is configured through cr set sequence. address adv clk valid 0 12 345 ce 1 we 6 d1 d2 rl=5 d3 dq [in] wait d4 we d1 d2 d3 dq [in] wait d4 high-z t wld high-z t wsck t ckwh t wlth t wlth we level control we single clock pulse control t clth
13 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) burst read suspend burst read operation can be suspended by oe high pulse. during burst read operation, oe brought to high suspends burst read operation. once oe is brought to high with the specified set up time against clock where the data being suspended, the device internal counter is suspended, and the data output become high impedance after specified time duration. it is inhibited to suspend the first data out at the beginning of burst read. oe brought to low resumes burst read operation. once oe is brought to low, data output become valid after specified time duration, and internal address counter is reactivated. the last data out being suspended as the result of oe =h and first data out as the result of oe =l are from the same address. burst write suspend burst write operation can be suspended by we high pulse. during burst write operation, we brought to high suspends burst write operation. once we is brought to high with the specified set up time against clock where the data being suspended, device internal counter is suspended, data input is ignored. it is inhibited to suspend the first data input at the beginning of burst write. we brought to low resumes burst write operation. once we is brought to low, data input become valid after specified time duration, and internal address counter is reactivated. the write address of the cycle where data being suspended and the first write address as the result of we =l are the same address. burst write suspend function is available when the device is operating in we level controlled burst write only. q 2 dq oe clk q 1 t ac t ckqx t olz t ac q 2 t ckqx t ac q 3 t ckqx t ac t ckoh t osck t ckoh t osck t ohz wait t cktv q 4 dq we d 1 t dhck t dsck t dsck d 2 t dhck t dsck t dsck d 3 t dhck t dsck t dsck t ckwh t wsck t ckwh t wsck d 2 d 4 wait high clk
14 (ae2.0e) mb82dbr08163a -70l preliminary n n n n functional description (continued) burst read termination burst read operation can be terminated by ce 1 brought to high. if bl is set on continuous, burst read operation is continued endless unless terminated by ce 1=h. it is inhibited to terminate burst read before first data out is completed. in order to guarantee last data output, the specified minimum value of ce 1=l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. burst write termination burst write operation can be terminated by ce 1 brought to high. if bl is set on continuous, burst write operation is continued endless unless terminated by ce 1=h. it is inhibited to terminate burst write before first data in is completed. in order to guarantee last write data being latched, the specified minimum values of ce 1=l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. address adv dq oe clk valid ce 1 wait q 1 q 2 t chtz t ac t ckqx t ckclh t trb t ckoh t chz high-z t ohz address adv dq we clk valid ce 1 wait t ckclh t trb t ckwh t chtz high-z d 2 d 1 t dhck t dhck t dsck t dsck t chck
15 (ae2.0e) mb82dbr08163a -70l preliminary n n n n absolute maximum ratings (see warning below.) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions (see warning below.) (referenced to v ss ) notes *1: maximum dc voltage on input and i/o pins is v ddq +0.2v. during voltage transitions, inputs may positive overshoot to v ddq +1.0v for periods of up to 5 ns. *2: minimum dc voltage on input or i/o pins is -0.3v. during voltage transitions, inputs may negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage of v ddq supply relative to v ss v ddq -0.5 to +2.6 v voltage at any pin relative to v ss v in , v out -0.5 to +2.6 v short circuit output current i out + 50 ma storage temperature t stg -55 to +125 o c parameter notes symbol min. max. unit supply voltage v dd 2.6 3.1 v i/o supply voltage v ddq 1.65 1.95 v ground v ss 00v high level input voltage *1 v ih v ddq *0.8 v ddq +0.2 v low level input voltage *2 v il -0.3 v ddq *0.2 v ambient temperature t a -30 85 c
16 (ae2.0e) mb82dbr08163a -70l preliminary n n n n dc characteristics (under recommended operating conditions unless otherwise noted) note *1,*2,*3 notes *1: all voltages are referenced to vss. *2: dc characteristics are measured after following power-up timing. *3: i out depends on the output load conditions. parameter symbol test conditions min. max. unit input leakage current i li v in = v ss to v ddq -1.0 +1.0 m a output leakage current i lo v out = v ss to v ddq , output disable -1.0 +1.0 m a output high voltage level v oh v ddq = v ddq (min), i oh = C0.5ma 1.4 v output low voltage level v ol i ol = 1ma 0.4 v v dd power down current i ddps v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce2 0.2v sleep 10 m a i ddp16 16m partial 120 m a i ddp32 32m partial 150 m a v dd standby current i dds v dd = v dd max., v ddq = v ddq max., v in (including clk)= v ih or v il , ce 1 = ce2 = v ih 1.5ma i dds1 v dd = v dd max., v ddq = v ddq max., v in (including clk) 0.2v or v in (including clk) 3 v ddq C 0.2v, ce 1 = ce2 3 v ddq C 0.2v 300 m a i dds2 v dd = v dd max., v ddq = v ddq max., tck=min. v in 0.2v or v in 3 v ddq C 0.2v, ce 1 = ce2 3 v ddq C 0.2v 350 m a v dd active current i dda1 v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma t rc / t wc = minimum 35ma i dda2 t rc / t wc = 1 m s 5ma v dd page read current i dda3 v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma, t prc = min. 15ma v dd burst access current i dda4 v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce 1 = v il and ce2= v ih , t ck = t ck min., bl = continuous, i out =0ma, 30ma
17 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (under recommended operating conditions unless otherwise noted) asynchronous read operation (page mode) notes *1: maximum value is applicable if ce 1 is kept at low without change of address input of a3 to a22. if needed by system operation, please contact local fujitsu representative for the relaxation of 1 m s limitation. *2: address should not be changed within minimum t rc . *3: the output load 50pf with 50ohm termination to v ddq *0.5 v. *4: the output load 5pf without any other load. *5: applicable to a3 to a22 when ce 1 is kept at low. *6: applicable only to a0, a1 and a2 when ce 1 is kept at low for the page address access. *7: in case page read cycle is continued with keeping ce 1 stays low, ce 1 must be brought to high within 4 m s. in other words, page read cycle must be closed within 4 m s. *8: t vpl is specified from the negative edge of either ce 1 or adv whichever comes late. *9: applicable when at least two of address inputs among applicable are switched from previous state. *10: t rc (min) and t prc (min) must be satisfied. parameter symbol value unit notes min. max. read cycle time t rc 70 1000 ns *1, *2 ce 1 access time t ce 70ns *3 oe access time t oe 40ns *3 address access time t aa 70ns*3, *5 adv access time t av 70 ns *3 lb , ub access time t ba 30ns *3 page address access time t paa 20ns*3, *6 page read cycle time t prc 20 1000 ns *1, *6, *7 output data hold time t oh 5ns *3 ce 1 low to output low-z t clz 5ns *4 oe low to output low-z t olz 0ns *4 lb , ub low to output low-z t blz 0ns *4 ce 1 high to output high-z t chz 20ns *3 oe high to output high-z t ohz 20ns *3 lb , ub high to output high-z t bhz 20ns *3 address setup time to ce 1 low t asc C5 ns address setup time to oe low t aso 10 ns adv low pulse width t vpl 10 ns *8 address hold time from adv high t ahv 5ns address invalid time t ax 10ns*5, *9 address hold time from ce 1 high t chah C5 ns *10 address hold time from oe high t ohah C5 ns ce 1 high pulse width t cp 15 ns
18 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (continued) asynchronous write operation notes *1: maximum value is applicable if ce 1 is kept at low without any address change. if the relaxation is needed by system operation, please contact local fujitsu representative for the relaxation of 1 m s limitation. *2: minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wrc , t wr or t br ). *3: write pulse is defined from high to low transition of ce 1, we or lb / ub , whichever occurs last. *4: t vpl is specified from the negative edge of either ce 1 or adv whichever comes late. *5: write recovery is defined from low to high transition of ce 1, we or lb / ub , whichever occurs first. *6: if oe is low after minimum t ohcl , read cycle is initiated. in other word, oe must be brought to high within 5ns after ce1 is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. *7: if oe is low after new address input, read cycle is initiated. in other word, oe must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol value unit notes min. max. write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0ns *3 adv low pulse width t vpl 10 ns *4 address hold time from adv high t ahv 5ns ce 1 write pulse width t cw 45 ns *3 we write pulse width t wp 45 ns *3 lb , ub write pulse width t bw 45 ns *3 ce 1 write recovery time t wrc 15 ns *5 we write recovery time t wr 15 1000 ns *5 lb , ub write recovery time t br 15 1000 ns *5 data setup time t ds 15 ns data hold time t dh 0ns oe high to ce 1 low setup time for write t ohcl C5 ns *6 oe high to address setup time for write t oes 0ns *7 lb , ub write pulse overlap t bwo 30 ns ce 1 high pulse width t cp 15 ns
19 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (continued) synchronous operation - clock input (burst mode) notes *1: clock period is defined between valid clock edges. *2: clock rise/fall time is defined between v ih min. and v il max. synchronous operation - address latch (burst mode) notes *1: t ascl is applicable if ce 1 brought to low after adv is brought to low under the condition where t vlcl is satisfied. the both of t ascl and t asvl must be satisfied if t vlcl is not satisfied. *2: t vpl is specified from the negative edge of either ce 1 or adv whichever comes late. *3: applicable to the 1st valid clock edge. parameter symbol value unit notes min. max. clock period rl=5 t ck 13 ns *1 rl=4 18 ns *1 rl=3 30 ns *1 clock high time t ckh 4ns clock low time t ckl 4ns clock rise/fall time t ckt 3ns *2 parameter symbol value unit notes min. max. address setup time to adv low t asvl C5 ns *1 address setup time to ce 1 low t ascl C5 ns *1 address hold time from adv high t ahv 5ns adv low pulse width t vpl 10 ns *2 adv low setup time to clk t vsck 5ns *3 adv low setup time to ce 1 low t vlcl 5ns *1 ce 1 low setup time to clk t clck 5ns *3 adv low hold time from clk t ckvh 1ns *3 burst end adv high hold time from clk t vhvl 13 ns
20 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (continued) synchronous read operation (burst mode) notes *1: the output load 50pf with 50ohm termination to v ddq *0.5 v. *2: the output load 5pf without any other load. *3: once they are determined, they must not be changed until the end of burst. *4: defined from the low to high transition of ce 1 to the high to low transition of either adv or ce 1 whichever occurs late. parameter symbol value unit notes min. max. burst read cycle time t rcb 8000ns clk access time t ac 11ns *1 output hold time from clk t ckqx 3ns *1 ce 1 low to wait low t cltl 520ns *1 oe low to wait low t oltl 020ns *1 adv low to wait low t vltl 020ns *1 clk to wait valid time t cktv 11ns *1 wait valid hold time from clk t cktx 3ns *1 ce 1 low to output low-z t clz 5ns *2 oe low to output low-z t olz 0ns *2 lb , ub low to output low-z t blz 0ns *2 ce 1 high to output high-z t chz 20ns *1 oe high to output high-z t ohz 20ns *1 lb , ub high to output high-z t bhz 20ns *1 ce 1 high to wait high-z t chtz 20ns *1 oe high to wait high-z t ohtz 20ns *1 oe low setup time to 1st data-out t olq 30 ns ub , lb setup time to 1st data-out t blq 26 ns *3 oe setup time to clk t osck 5ns oe hold time from clk t ckoh 5ns burst end ce 1 low hold time from clk t ckclh 5ns burst end ub , lb hold time from clk t ckbh 5ns burst terminate recovery time bl=8,16 t trb 26 ns *4 bl=continuous 70 ns *4
21 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (continued) synchronous write operation (burst mode) notes *1: defined from the valid input edge to the high to low transition of either adv , ce 1, or we , whichever occurs last. and once they are determined, they must not be changed until the end of burst. *2: the output load 50pf with 50ohm termination to v ddq *0.5 v. *3: defined from the valid clock edge where last data-in being latched at the end of burst write to the high to low transition of either adv or ce 1 whichever occurs late for the next access. *4: defined from the low to high transition of ce 1 to the high to low transition of either adv or ce 1 whichever occurs late for the next access. parameter symbol value unit notes min. max. burst write cycle time t wcb 8000ns data setup time to clock t dsck 5ns data hold time from clk t dhck 3ns we low setup time to 1st data in t wld 30 ns ub , lb setup time for write t bs C5 ns *1 we setup time to clk t wsck 5ns we hold time from clk t ckwh 5ns ce 1 low to wait high t clth 520ns *2 we low to wait high t wlth 020ns *2 ce 1 high to wait high-z t chtz 20ns *2 we high to wait high-z t whtz 20ns *2 burst end ce 1 low hold time from clk t ckclh 5ns burst end ce 1 high setup time to next clk t chck 5ns burst end ub , lb hold time from clk t ckbh 5ns burst write recovery time t wrb 26 ns *3 burst terminate recovery time bl=8,16 t trb 26 ns *4 bl=continuous t trb 70 ns *4
22 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (continued) power down parameters notes *1: applicable also to power-up. *2: applicable when partial mode is set. other timing parameters notes *1: some data might be written into any address location if t chwx (min) is not satisfied. *2: except for clock input transition time. *3: the input transition time (t t ) at ac testing is shown in below. if actual t t is longer than specified values, it may violate ac specification of some timing parameters. parameter symbol value unit note min. max. ce2 low setup time for power down entry t csp 20 ns *1 ce2 low hold time after power down entry t c2lp 70 ns *1 ce 1 high hold time following ce2 high after power down exit [sleep mode only] t chh 300 m s*1 ce 1 high hold time following ce2 high after power down exit [not in sleep mode] t chhp 1 m s*2 ce 1 high setup time following ce2 high after power down exit t chs 0ns*1 parameter symbol value unit note min. max. ce 1 high to oe invalid time for standby entry t chox 10 ns ce 1 high to we invalid time for standby entry t chwx 10 ns *1 ce2 high hold time after power-up t c2hl 50 m s ce 1 high hold time following ce2 high after power-up t chh 300 m s input transition time (except for clk) t t 125ns*2, *3
23 (ae2.0e) mb82dbr08163a -70l preliminary n n n n ac characteristics (continued) ac test conditions ac measurement output load circuit symbol description test setup value unit note v ih input high level v ddq * 0.8 v v il input low level v ddq * 0.2 v v ref input timing measurement level v ddq * 0.5 v t t input transition time async. between v il and v ih 5ns sync. 3 ns device under test v dd v ddq *0.5v v ss out 0.1 m f 50pf 50ohm v ddq v ss 0.1 m f
24 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams asynchronous read timing #1-1 (basic timing) see note. note: this timing diagram assumes ce2=h and we =h. asynchronous read timing #1-2 (basic timing) see note. note: this timing diagram assumes ce2=h and we =h. t ce valid data output address ce 1 dq (output) oe t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb / ub t oe t ba t blz adv low t ce valid data output address ce 1 dq (output) oe t chz t rc t olz t cp t asc t asc t ohz t oh t bhz lb / ub t oe t ba t blz adv address valid t ahv t vpl t av
25 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous read timing #2 (oe & address access) see note. notes: this timing diagram assumes ce2=h, adv =l and we =h. asynchronous read timing #3 (lb / ub byte access) see note. note: this timing diagram assumes ce2=h, adv =l and we =h. t aa valid data output address ce 1 dq (output) lb / ub t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe t ax low t aa t ohah t aso t aa valid data output address ce 1, oe dq1-8 (output) ub t bhz t ba t rc t blz address valid valid data output t bhz t oh lb t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output
26 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous read timing #4 (page address access after ce 1 control access) see note. notes: this timing diagram assumes ce2=h and we =h. asynchronous read timing #5 (random and page address access) see note. notes *1: this timing diagram assumes ce2=h, adv =l and we =h. *2: either or both lb and ub must be low when both ce 1 and oe are low. valid data output (normal access) address (a2-a0) ce 1 dq (output) oe t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa address (a22-a3) address valid lb / ub t paa t oh t prc t paa t prc t oh address valid address valid t rc adv t asc valid data output (normal access) address (a2-a0) ce 1 dq (output) oe t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a22-a3) address valid lb / ub t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso
27 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous write timing #1-1 (basic timing) see note. notes: this timing diagram assumes ce2=h and adv =l. asynchronous write timing #1-2 (basic timing) see note. notes: this timing diagram assumes ce2=h. t as valid data input address ce 1 dq (input) we t dh t ds t wc t wrc t wp t cw lb , ub t as t bw address valid t as t as t br oe t ohcl t as t as t wr adv low t as valid data input address ce 1 dq (input) we t dh t ds t wc t wrc t wp t cw lb , ub t as t bw address valid t as t as t br oe t ohcl t as t as t wr adv t vpl t ahv
28 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous write timing #2 (we control) see note. note: this timing diagram assumes ce2=h and adv =l. asynchronous write timing #3-1 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h, adv =l and oe =h. t as address we ce 1 t wc t wr t wp lb , ub address valid t as t wr t wp valid data input dq (input) t dh t ds oe t oes t ohz t wc valid data input t dh t ds low address valid t ohah t as address we ce 1 t wc t br t wp lb address valid t as t br t wp valid data input dq1-8 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq9-16 (input)
29 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous write timing #3-2 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h, adv =l and oe =h. asynchronous write timing #3-3 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h, adv =l and oe =h. t as address we ce 1 t wc t wr t bw lb address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq9-16 (input) t as address we ce 1 t wc t br t bw lb address valid t as t br t bw valid data input dq1-8 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq9-16 (input)
30 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous write timing #3-4 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h, adv =l and oe =h. t as address we ce 1 t wc t br t bw lb address valid t as t br t bw dq1-8 (input) t dh t ds ub t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo
31 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous read / write timing #1-1 (ce 1 control) see note. notes *1: this timing diagram assumes ce2=h and adv =l. *2: write address is valid from either ce 1 or we of last falling edge. asynchronous read / write timing #1-2 (ce 1 / we / oe control) see note. notes *1: this timing diagram assumes ce2=h and adv =l. *2: oe can be fixed low during write operation if it is ce 1 controlled write at read-write-read se- quence. read data output address ce 1 dq we t wc t cw oe t ohcl ub , lb t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh read data output address ce 1 dq we t wc t wp oe t ohcl ub , lb t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
32 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) asynchronous read / write timing #2 (oe , we control) see note. notes *1: this timing diagram assumes ce2=h and adv =l. *2: ce 1 can be tied to low for we and oe controlled operation. asynchronous read / write timing #3 (oe , we , lb , ub control) see note. notes *1: this timing diagram assumes ce2=h and adv =l. *2: ce 1 can be tied to low for we and oe controlled operation. read data output address ce 1 dq we t wc t wp oe ub , lb t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah read data output address ce 1 dq we t wc t bw oe ub , lb t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes
33 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) clock input timing see note. notes *1: stable clock input must be required during ce 1=l. *2: t ck is defined between valid clock edges. *3: t ckt is defined between v ih min. and v il max. address latch timing (synchronous mode) see note. notes *1: case #1 is the timing when ce 1 is brought to low after adv is brought to low. case #2 is the timing when adv is brought to low after ce 1 is brought to low. *2: t vpl is specified from the negative edge of either ce 1 or adv whichever comes late. at least one valid clock edge must be input during adv =l. *3: t vsck and t clck are applied to the 1st valid clock edge during adv =l. clk t ck t ckh t ckl t ckt t ckt t ck clk adv address ce 1 t ahv t vpl t asvl valid case #1 case #2 t vsck t ahv t vpl t vlcl valid t vsck t clck t ascl low t ckvh t ckvh
34 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous read timing #1 (oe control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. t ahv address adv dq we oe lb , ub clk valid ce 1 t asvl t vpl t clck t ascl wait q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t ckvh t ckvh
35 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous read timing #2 (ce 1 control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl t clck t ascl wait q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cltl t ckbh t asvl t cktx t ckvh t ckvh
36 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous read timing #3 (adv control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl wait q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx low low t cktx t vltl t vltl t ckvh t ckvh
37 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous write timing #1 (we level control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl t clck t ascl wait high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t ckvh t ckvh t asvl
38 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous write timing #2 (we single clock pulse control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl t clck t ascl wait high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckclh valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t chtz t wlth t wsck t ckwh t ckwh t wsck t ckvh t ckvh
39 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous write timing #3 (adv control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl wait high rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb valid t asvl t ahv t vpl t vsck t bs t wrb t vsck t vhvl t ckbh high t ckvh t ckvh
40 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous write timing #4 (we level control, single write) see note. notes *1: this timing diagram assumes ce2=h, the valid clock edge on rising edge and single write operation. *2: write data is latched on the valid clock edge. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl t clck t ascl wait high high-z rl=5 t bs d 1 t dhck t dsck t wcb t ckwh t wld valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t wlth t ckvh t ckvh
41 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous read to write timing #1(ce 1 control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl t clck t ascl wait t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t vhvl t ckbh t ckbh t wcb t clth t ckvh
42 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous read to write timing #2(adv control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl wait t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t vhvl t ckbh t ckbh t wlth t ckvh t vsck
43 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous write to read timing #1 (ce 1 control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. d bl address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl t clck t ascl wait t vsck t cp rl=5 t ckclh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t cltl t clz t wrb t ckbh t cktx t chtz high-z t ckvh
44 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) synchronous write to read timing #2 (adv control) see note. note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. d bl address adv dq we oe lb , ub clk valid ce 1 t asvl t ahv t vpl wait low t vsck rl=5 t ckwh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t oltl t olz t olq t wrb t blq t ckbh t cktx t whtz high-z t ckvh
45 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) power-up timing #1 see note. notes *1: v ddq shall be applied and reach the specified minimum level prior to v dd applied. *2: the both of ce 1 and ce2 shall be brought to high together with v ddq prior to v dd applied. otherwise power-up timing#2 must be applied for proper operation. *3: the t chh specifies after v dd reaches specified minimum level and applicable to both ce 1 and ce2. power-up timing #2 see note. notes *1: v ddq shall be applied and reach specified minimum level prior to v dd applied. *2: the t c2hl specifies from ce2 low to high transition after v dd reaches specified minimum level. if ce2 became high prior to v dd reached specified minimum level, t c2hl is defined from v dd minimum. *3: ce 1 shall be brought to high prior to or together with ce2 low to high transition. ce 1 v ddq 0v ce2 t chh *3 v dd 0v *2 v dd min *1,*2 v ddq min *1 *2 ce 1 v ddq v ddq min *1 0v ce2 t chh v dd 0v v dd min *1 t c2hl *2 t chs t csp t c2lp t c2hl *2 *3
46 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) power down entry and exit timing see note. note: this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. standby entry timing after read or write see note. note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce 1 low to high transition. t csp ce 1 power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z t chox ce 1 oe we active (read) standby active (write) standby t chwx
47 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) configuration register set timing #1 (asynchronous operation) see note. notes *1: the all address inputs must be high from cycle #1 to #5. *2: the address key must confirm the format specified in functional description. if not, the operation and data are not guaranteed. *3: after t cp or t rc following cycle #6, the configuration register set is completed and returned to the normal operation. t cp and t rc are applicable to returning to asynchronous mode and to synchronous mode respectively. address ce 1 dq* 3 we t rc oe lb , ub rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb t cp * 3 (t rc )
48 (ae2.0e) mb82dbr08163a -70l preliminary n n n n timing diagrams (continued) configuration register set timing #2 (synchronous operation) see note. notes *1: the all address inputs must be high from cycle #1 to #5. *2: the address key must confirm the format specified in functional description. if not, the operation and data are not guaranteed. *3: after t trb following cycle #6, the configuration register set is completed and returned to the normal operation. address adv dq we oe lb , ub clk ce 1 rda msb rda msb rda msb x msb x msb rdb key t rcb t wcb t wcb t wcb t wcb t rcb t trb t trb t trb t trb t trb cycle#1 cycle#2 cycle#3 cycle#4 cycle#5 cycle#6 t trb rl rl-1 rl-1 rl-1 rl-1 rl
49 (ae2.0e) mb82dbr08163a -70l preliminary n n n n bonding pad bonding pad layout please contact local fujitsu representative for pad layout and pad coordinate information. bonding pad description pin name description a 22 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) clk clock input adv address valid input (low active) wait wait signal output dq 16-9 upper byte data input/output dq 8-1 lower byte data input/output v dd power supply v ddq i/o power supply v ss ground test/open test/open (this pad should be left open. do not use.)
50 (ae2.0e) mb82dbr08163a -70l preliminary n n n n package for engineering samples ball assignment ball description pin name description a 22 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) clk clock input adv address valid input (low active) wait wait signal output dq 8-1 lower byte data input/output dq 16-9 upper byte data input/output v dd power supply v ddq i/o power supply v ss ground nc no connection (top view) abcdefghjklm 8 nc nc a15 a21 a22 a16 nc v ss nc nc 7 nc nc a11 a12 a13 a14 nc dq16 dq8 dq15 nc nc 6 a8 a19 a9 a10 dq7 dq14 dq13 dq6 5we ce2 a20 dq5 v dd nc 4 clk adv wait dq4 v ddq dq12 3lb ub a18 a17 dq2 dq10 dq11 dq3 2 nc a7a6a5a4v ss oe dq1 dq9 nc nc 1ncnc a3a2a1a0ncce 1ncnc (bga-71p-m03)
51 (ae2.0e) mb82dbr08163a -70l preliminary n n n n package for engineering samples (continued) package view note: this is for engineering sample only. package dimensions note: this is for engineering sample only. (bga-71p-m03) 71-pin plastic fbga package c 2003 fujitsu limited b71003s-c-1-1 11.000.10(.433.004) 7.000.10 (.276.004) index-mark area a b c d e f g h j k l m 1 2 3 4 5 6 7 8 s 1.09 +0.11 C0.10 +.004 C .004 .043 (.015.004) 0.390.10 (stand off) (seated height) 0.20(.008) s b 0.10(.004) s 0.10(.004) s a s 0.20(.008) ref 0.80(.031) b ref 0.40(.016) ref 0.80(.031) a ref 0.40(.016) ab s m ?0.08(.003) 71-?0.45 +0.10 C 0.05 +.004 C .002 71-?.018 71-pin plastic fbga (bga-71p-m03) dimensions in mm (inch)
52 (ae2.0e) mb82dbr08163a -70l preliminary fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0403 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third- party?s intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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