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| 1 gsps direct digital synthesizer AD9858 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . features 1 gsps intern a l clock speed up to 2 gh z in put clock (selec t able di vide -by - 2) integrated 10 - b it d/a convert e r phase no ise < 1 45 dbc/hz @ 1 khz o ffset o u tput freq ue nc y = 10 0 mh z (dac o u tput) 32-bit programmable frequen c y register simplified 8-bi t parallel and s p i? serial control interface automatic freq uency sweepin g capability 4 freq uenc y pr o f iles 3.3 v power supply power dissipati o n 2 w typical integrated programmable charge pump and phase frequ e ncy detector with fast lock circu i t isolated charge pump supply up to 5 v integrated 2 ghz mixer applic ati o ns vhf/uhf lo synthesis tuners instrumentation agile clock syn t hesis cellular base st ation hopping synthesizer radar sonet/sdh clock synthesis general description the AD9858 is a dir e c t dig i tal s y n t h e sizer (d ds) f e a t ur in g a 10-b i t d a c o p era t in g u p t o 1gs p s. th e ad98 58 us es ad van c e d d d s t e c h n o log y , co u p le d wi th a n in t e r n al hig h s p e e d , hig h p e r f o r ma n c e d/ a co n v er ter to fo r m a dig i t a l l y p r o g ra mma b l e, c o m p l e te h i g h f r e q u e nc y s y n t h e s i z e r c a p a bl e o f ge ne r a t i ng a f r eq uen c y-a g ile a n alog o u t p u t sin e wa v e a t u p t o 400+ mh z. the AD9858 is desig n e d t o p r o v ide f a s t f r eq uen c y h o p p i n g and f i ne tu n i ng re s o lut i on ( 3 2 - b i t f r e q u e nc y tu n i ng word ) . t h e f r e q uen c y t u ni ng a nd con t r o l w o r d s a r e lo ade d in to t h e ad985 8 via p a ral l e l (8-b i t ) o r s e r i al lo adin g f o r m a t s. the AD9858 co n t a i n s an i n t e g r a t e d ch a r ge pum p (cp) an d phas e f r e q ue n c y det e c t o r (p fd) fo r syn t h e sis a p p l ica t ion s r e q u ir in g th e co m b in a t ion o f a hig h sp e e d dds a l o n g wi t h phas e-lo ck e d lo op ( p l l ) f u nc t i on s . a n an a l o g m i x e r i s a l s o prov i d e d on - c h i p f o r a p plic a t ion s r e quir in g t h e com b ina t ion o f a dd s, pll, a nd mixer , s u c h as f r eq uen c y tra n s l a t io n lo o p s, t u n e rs, a n d s o on. the AD9858 als o f e a t ur es a di vide-b y-2 on the c l o c k in p u t, a l lo win g t h e exter n a l clo c k t o b e as hig h as 2 g h z. the AD9858 is s p ecif ie d t o o p era t e o v er th e exten d ed ind u s t r i a l t e m p era t ur e ra ng e o f C40c t o +85c. func tio n a l block di agram analog multiplier phase accumulator div lo if rf pd cp cpiset reset daciset i out i out fud synclk refclk refclk profile select i/o port (ser/par) digital pll delta frequency wo rd delta frequency ram p rate frequency accum ulator reset frequency tuning wo rd phase accum ulator reset sync phase offset adj ust dac dac clock charge pump power- down logic phase detector timing and control logic phase-to- amplitude conversion m 8 2 control registers n AD9858 15 frequency accumulator 32 32 14 32 15 10 m u x 03166-a - 001 fi g u r e 1 .
AD9858 rev. a | page 2 of 32 table of contents features .......................................................................................... 1 applications ................................................................................... 1 general description ..................................................................... 1 functional block diagram .......................................................... 1 AD9858electrical specifications ................................................ 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration ............................................................................. 7 pin function descriptions .............................................................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 15 overview ..................................................................................... 15 component blocks ..................................................................... 15 modes of operation ................................................................... 17 synchronization .......................................................................... 19 programming the AD9858 ........................................................ 21 AD9858 application suggestions ............................................. 29 evaluation boards ...................................................................... 30 outline dimensions ....................................................................... 31 war n i ng ....................................................................................... 31 ordering guide .......................................................................... 31 revision history 11/03data sheet changed from a rev. 0 to a rev. a changes to specifications........................................................ 5 moved esd caution to ..................................................................... 6 moved pin configuration to ............................................................ 7 moved pin function description to ............................................... 8 changes to equations........................................................................ 19 changes to delta frequency ramp rate word (dfrrw) .......... 27 AD9858 rev. a | page 3 of 32 AD9858electrical specifications table 1. unless otherwise noted, v dd = 3.3 v 5%, cpv dd = 5 v 5%, r set = 2 k?, c piset = 2.4 k?, reference clock frequency = 1 ghz. parameter temp test level min typ max unit ref clock input characteristics 1, 2 reference clock frequency range (divider off) full vi 10 1000 mhz reference clock frequency range (divider on) full vi 20 2000 mhz duty cycle @ 1 ghz 25c v 42 50 58 % input capacitance 25c v 3 pf input impedance 25c iv 1500 ? input sensitivity full vi C20 +5 dbm dac output characteristics resolution full 10 bits full-scale output current full 5 20 40 ma gain error full vi C10 +10 % fs output offset full vi 15 a differential nonlinearity full vi 0.5 1 lsb integral nonlinearity full vi 1 1.5 lsb output impedance full vi 100 k? voltage compliance range full vi av dd C 1.5 av dd + 0.5 v wideband sfdr (dc to nyquist) 40 mhz f out full v 60 dbc 100 mhz f out full v 54 dbc 180 mhz f out full v 53 dbc 360 mhz f out full v 50 dbc 180 mhz f out (700 mhz refclk) full iv 52 dbc narrow-band sfdr3 3 40 mhz f out (15 mhz) full v 82 dbc 40 mhz f out (1 mhz) full v 87 dbc 40 mhz f out (50 khz) full v 88 dbc 100 mhz f out (15 mhz) full v 81 dbc 100 mhz f out (1 mhz) full v 82 dbc 100 mhz f out (50 khz) full v 86 dbc 180 mhz f out (15 mhz) full v 74 dbc 180 mhz f out (1 mhz) full v 84 dbc 180 mhz f out (50 khz) full v 85 dbc 360 mhz f out (15 mhz) full v 75 dbc 360 mhz f out (1 mhz) full v 85 dbc 360 mhz f out (50 khz) full v 86 dbc 180 mhz f out (15 mhz) (700 mhz refclk) full v 65 dbc 180 mhz f out (1 mhz) (700 mhz refclk) full v 80 dbc 180 mhz f out (50 khz) (700 mhz refclk) full v 84 dbc output phase noise characteristics (@ 103 mhz i out ) @ 1 khz offset full v C147 dbc/hz @ 10 khz offset full v C150 dbc/hz @ 100 khz offset full v C152 dbc/hz output phase noise characteristics (@ 403 mhz i out ) @ 1 khz offset full v C133 dbc/hz @ 10 khz offset full v C137 dbc/hz @ 100 khz offset full v C140 dbc/hz AD9858 rev. a | page 4 of 32 parameter temp test level min typ max unit output phase noise characteristics (@ 100 mhz i out with 700 mhz refclk) @ 100 hz offset full v C125 dbc/hz @ 1 khz offset full v C140 dbc/hz @ 10 khz offset full v C148 dbc/hz @ 100 khz offset full v C150 dbc/hz @ 1 mhz offset full v C150 dbc/hz @ 10 mhz offset full v C150 dbc/hz phase detector and charge pump phase detector frequency full vi 150 mhz phase detector frequency (divide-by-4 enabled) 4 full vi 400 mhz charge pump sink and source current 5 full vi 4 ma fast lock current (acquisition only) full vi 7 ma open-loop current (acquisition only) full vi 30 ma sink and source current absolute accuracy 6 full v 2.5 % sink and source current matching 6 full v 1 % input sensitivity pd in and div in (50 ?) 7 full iv C15 0 dbm input impedence pd in and div in (single-ended) full v 1 k? phase noise @ 100 mhz input frequency @ 10 khz offset full v 110 dbc/hz @ 100 khz offset full v 140 dbc/hz @ 1 mhz offset full v 148 dbc/hz charge pump output range 8 full v cpv dd v mixer if out 9 full v 400 mhz f rf full vi 2 ghz f lo full vi 2 ghz conversion gain full vi 0.0 3.5 db lo level full vi C10 +5 dbm rf level full vi C20 dbm input ip3 full vi 5 9 dbm 1 db input compression power 10 full vi C3 dbm input impedance (single-ended) lo full v 1 k? rf full v 1 k? logic inputs logic 1 voltage full vi 2.0 v logic 0 voltage full vi 0.8 v logic 1 current full vi 12 a logic 0 current full vi 12 a input capacitance full v 3 pf power supply p diss (worst-case conditionseverything on p fd input frequency 150 mhz) full vi 2 2.5 w p diss (dac and dds core only worst-case) full vi 1.7 2 w p diss (power-down mode) full vi 65 100 mw p diss mixer only full vi 60 75 mw p diss pfd and cp (@ 100 mhz) only full vi 350 435 mw AD9858 rev. a | page 5 of 32 parameter temp test level min typ max unit timing characteristics serial control bus maximum frequency full iv 10 mhz minimum clock pulse width low (t pwl ) full iv 5.5 ns minimum clock pulse width high (t pwh ) full iv 15 ns maximum clock rise/fall time full iv 1 ms minimum data setup time (t ds ) full iv 7 ns mimimum data hold time (t dh ) full iv 0 ns maximum data valid time (t dv ) full iv 20 ns parallel control bus wr minimum low time full iv 3 ns wr minimum high time full iv 6 ns wr minimum period full iv 9 ns address to wr setup (t asu ) full iv 3 ns address to wr setup (t ahu ) full iv 0 ns data to wr setup (t dsu ) full iv 3.5 ns data to wr hold (t dhu ) full iv 0 ns miscellaneous timing specifications refclk to synclk full v 2.5 ns fud to synclk setup time full iv 4 ns fud to synclk hold time full iv 0 ns refclk to synclk delay full iv 2.5 3 ns fud rising edge to frequency change single tone mode 25c iv 83 sysclk cycles linear sweep mode 25c iv 99 sysclk cycles fud rising edge to phase offset change 25c iv 83 sysclk cycles 1 the reference clock input is configured to accept a differential or si ngle-ended sine wave input or a 3 v cmos-level pulse inp ut. 2 refclk input is internally dc biased. ac coupling should be used. 3 reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest. 4 pd inputs sent @ 400 mhz, with divide-by-4 enabled. 5 the charge pump current is programmable in eight discrete steps, minimum va lue assumes current sharing. 6 for 0.75 v < v cp < cpv dd C 0.75 v. 7 these differential inputs are internally dc biased. ac coupling should be used. 8 the charge pump supply voltage can range from 4.75 v to 5.25 v. 9 output interface is differential open collector. 10 for 1 db output compression; input power measured at 50 ?. AD9858 r e v. a | pa ge 6 o f 3 2 absolute maximum ratings table 2. p a r a m e t e r r a t i n g av dd 4 v dv dd 4 v cpv dd 6 v digital input voltage C0.7 v to +v dd digital output c u rrent 5 ma storage temperature C65c to +150c operating temperature C40c to +85c ja epad solder ed 25c/w a b s o l u te m a x i m u m r a t i n g s a r e limi t i n g va l u e s , to b e a p plie d indivi d u a l ly , and b e yo nd w h ich t h e s e r v ice a b i li ty o f t h e cir c ui t m a y b e i m pa i r e d . f u n c ti o n al o p era b ili t y un d e r a n y o f th es e co ndi t i on s is n o t n e cess a r i l y im plie d . e x p o sur e o f a b s o l u t e m a xi m u m ra tin g co n d i ti o n s f o r e x t e n d ed pe ri od s o f ti m e m a y af fe c t d e v i c e rel i a b i l it y . table 3. ex plan ation of test l e vels i 100% productio n tested. iii sample tested only. iv parameter is guaranteed by design and charact e rization testing. v parameter is a typical va lue only. vi devices are 100 % production tested at 25c and guaranteed by design and char acterization test ing for industrial operating temperature range. esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. AD9858 r e v. a | pa ge 7 o f 3 2 pin conf iguration 84 83 82 81 80 79 78 77 76 95 94 93 92 91 90 89 88 87 86 85 1 0 0 9 99 89 7 96 26 28 29 30 31 32 33 38 39 34 35 36 37 42 40 41 43 44 45 46 47 48 49 50 13 dvdd d7 d6 d5 d4 dgnd dgnd dvdd dvdd d3 d2 d1 d0 addr5 addr4 addr3 rd/cs dvdd dvdd dgnd dv dd dv dd agnd agnd av dd refclk av dd refclk av dd av dd agnd agnd av dd agnd agnd agnd av dd av dd lo lo av dd agnd av dd agnd ps1 s y nclk fud ps0 dgnd dgnd r eset dv dd dv dd av dd spselec t agnd av dd av dd agnd iout agnd iout iout agnd iout dacis e t av dd dacbp nc a ddr2/iorese t addr1/sdo addr0/sdio wr/sclk dvdd dgnd avdd nc agnd avdd div div avdd agnd cpgnd cpvdd cp cp cpfl cpgnd cpvdd cpiset rf rf agnd nc nc pfd pfd if if ad9 8 5 8 top v i e w ( n o t to s cal e) nc = no connect 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 031 66-a - 044 f i g u re 2. 10 0-l e ad e p a d (sv - 10 0) pin conf ig ur at i o n AD9858 rev. a | page 8 of 32 pin function descriptions table 4. pin function descript ions100-lead epad (sv-100) pin no. mnemonic i/o description 1 to 4, 9 to 12 d7 to d0 i parallel port data. note that the functionality of these pins is valid only when the i/o port is configured as a parallel port. 5, 6, 21, 28, 95, 96 dgnd digitial ground. 7, 8, 20, 23 to 27, 93, 94 dvdd digital supply voltage. 13 to 18 addr5 to addr0 i when the i/o port is configured as a parallel po rt, these pins serve as a 6-bit address select for accessing the on-chip registers (see the iore set, sdo, and sdio pins below for serial port mode). 16 ioreset i note that this is valid only for serial programmin g mode. active high input signal that resets the serial i/o bus controller. it is intended to serve as a means of recovering from an unresponsive serial bus caused by improper programming protocol . asserting an i/o reset does not affect the contents of previously programmed registers nor does it invoke their default values. 17 sdo o note that this is valid only for serial prog ramming mode. when operating the i/o port as a 3-wire serial port, this pin serves as a unidirecti onal serial data output pi n. when operated as a 2-wire serial port, this pin is unused. 18 sdio i or i/o note that this is valid only for serial prog ramming mode. when operating the i/o port as a 3-wire serial port, this pin is the serial data inpu t. when operated as a 2-wire serial port, this pin is the bidirectional serial data pin. 19 wr /sclk i when the i/o port is configured for parallel pr ogramming mode, this pin functions as an active low write pulse ( wr ). when configured for serial progra mming mode, this pin functions as the serial data clock (sclk). 22 rd / cs i when the i/o port is configured for parallel pr ogramming mode, this pin functions as an active low read pulse ( rd ). when configured for serial progra mming mode, this pin functions as an active low chip select ( cs ) that allows multiple devices to share the serial bus. 29, 30, 37 to 39, 41, 42, 49, 50, 52, 69, 74, 80, 85, 87, 88 agnd i analog ground. 31, 32, 35, 36, 40, 43, 44, 47, 48, 51, 70, 73, 77, 86, 89, 90 avdd i analog supply voltage. 33 refclk i reference clock complementary in put. (note that when the refc lk port is operated in single- ended mode, refclk should be decoupled to avdd with a 0.1 f capacitor. 34 refclk i reference clock input. 45 lo i mixer local oscillator (lo) complementary input. note that when the lo port is operated in single-ended mode, lo should be decoupled to avdd with a 0.1 f capacitor. 46 lo i mixer local oscillator (lo) input. 53 rf i analog mixer rf compleme ntary input. note that when the rf port is operated in single-ended mode, rf should be decoupled to avdd with a 0.1 f capacitor. 54 rf i analog mixer rf input. 55 if o analog mixer if output. 56 if o analog mixer if complementary output. 57 pfd i phase frequency detector complementary input . note that when the pfd port is operated in single-ended mode, pfd should be decoupled to avdd with a 0.1 f capacitor. 58 pfd i phase frequency detector input. 59, 60, 75, 76 nc no connection. 61 cpiset i charge pump output current control. a resistor connected from cpiset to cpgnd establishes the reference current for the charge pump. 62, 67 cpvdd i charge pump supply voltage. 63, 68 cpgnd i charge pump ground. 64 cpfl o charge pump fast lock output. 65, 66 cp o charge pump output. AD9858 rev. a | page 9 of 32 pin no. mnemonic i/o description 71 div i phase frequency detector feedback input. 72 div i phase frequency detector feedback complement ary input. note that when the div port is operated in single-ended mode, div should be decoupled to avdd with a 0.1 f capacitor. 78 dacbp dac baseline decoupling pin, typically bypassed to pin 77 with a 0.1 f capacitor. 79 daciset i a resistor connected from daciset to ag nd establishes the reference current for the dac. 81, 82 iout o dac output. 83, 84 iout o dac complementary output. 91 spselect i i/o port serial/parallel programming mode sele ct pin. logic 0: serial programming mode. logic 1: parallel programming mode. 92 reset i active high hardware reset pin. assertion of the reset pin forces the AD9858 to its default operating conditions. 97, 98 ps0, ps1 i used to select one of the four internal pr ofiles. these pins are synchronous to the synclk output. 99 fud i frequency update. the rising edge transfers the co ntents of the internal buffer registers to the memory registers. this pin is synchronous to the synclk output. 100 synclk o clock output pin that serves as a synchroniz er for external hardware. synclk runs at refclk/8. AD9858 rev. a | page 10 of 32 typical perf orm ance cha r acte ristics ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 start 0hz 50mhz/ stop 500mhz 5khz 5khz 50s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.04dbm 26.05210421mhz 03166-a - 002 1 f i gure 3. wideb a n d sfdr, 2 6 m h z f ou t ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 start 0hz 50mhz/ stop 500mhz 5khz 5khz 50s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.72dbm 65.13026052mhz 03166-a - 003 1 f i gure 4. wideb a n d sfdr, 6 5 m h z f ou t ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 start 0hz 50mhz/ stop 500mhz 5khz 5khz 50s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.39dbm 126.25250501mhz 03166-a - 004 1 f i gure 5. wideb a n d sfdr, 1 2 6 mh z f ou t ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 26.1mhz 50khz/ span 500khz 200hz 200hz 64s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.73dbm 26.10050100mhz 03166-a - 006 1 f i g u re 6. n a r r ow-b and sfdr , 2 6 m h z f ou t , 1 m h z b w ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 65.1mhz 200khz/ span 2mhz 500hz 500hz 40s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.58dbm 65.10200401mhz 03166-a - 007 1 f i g u re 7. n a r r ow-b and sfdr , 6 5 m h z f ou t , 1 m h z b w ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 126.1mhz 200khz/ span 2mhz 500hz 500hz 40s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.27dbm 126.10200401mhz 03166-a - 008 1 f i g u re 8. n a r r ow-b and sfdr , 1 2 6 m h z f ou t , 1 mh z b w AD9858 rev. a | page 11 of 32 ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 start 0hz 50mhz/ stop 500mhz 5khz 5khz 50s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] ?1.25dbm 375.75150301mhz 03166-a - 005 1 f i gure 9. wideb a n d sfdr, 3 7 5 mh z f ou t ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 216.1mhz 100khz/ span 1mhz 300hz 300hz 56s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt 03166-a - 010 f i gure 10. na rro w - band sf dr , 2 0 1 m h z f ou t , 1 mh z bw , 1 gh z c l o c k , d i v i de r o ff ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 216.1mhz 100khz/ span 1mhz 300hz 300hz 56s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt 03166-a - 012 f i gure 11. na rro w - band sf dr , 2 0 1 m h z f ou t , 1 mh z bw , 2 gh z c l o c k , d i v i de r o n ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 375.1mhz 500khz/ span 5mhz 500hz 500hz 100s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] ?1.35dbm 375.10501002mhz 03166-a - 009 1 f i gure 12. na rro w - band sf dr , 3 7 5 m h z f ou t , 1 m h z bw ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 start 0hz 50mhz/ stop 500mhz 5khz 5khz 50s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.12dbm 216.43286573mhz 03166-a - 011 1 f i gure 13. wideb a n d sfdr, 2 0 1 mh z f ou t , 1 g h z c l ock , d i vi der o ff ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 start 0hz 50mhz/ stop 500mhz 5khz 5khz 50s rf att unit 20db db a 1ap ref lvl 5dbm rbw vbw swt marker 1 [t1] 1.12dbm 216.43286573mhz 03166-a - 013 1 f i gure 14. wideb a n d sfdr, 2 0 1 mh z f ou t , 2 g h z c l o c k , d i v i der o n AD9858 rev. a | page 12 of 32 ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?170 ?100 ?110 ?120 ?130 ?140 ?150 ?160 10 10m 1m 100k 10k frequency (hz) ph a se n o ise, l( f ) ( d b c /h z) 1k 100 03166-a - 014 f i g u re 15. r e s i dua l p h as e n o is e , 1 03 m h z f ou t , 1 g h z refclk ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 170 ? 100 ?110 ? 120 ? 130 ? 140 ? 150 ? 160 10 10m 100m 1m 100k 10k 1k 100 03166-a - 016 frequency (hz) p has e no i s e , l(f) (dbc / h z) f i g u re 16. f r ac t i on al d i v i d e r l o op r e s i dual p h as e no is e , f in = 11 5 m h z, f ou t = 1 5 50 m h z, l oop bw = 5 0 kh z ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 150khz/ span 1.55mhz 1khz 1khz 3.8s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] 0.0db 0.00000000hz 03166-a - 018 1 f i g u re 17. f r ac t i on al d i v i d e r l o op sf dr , f in = 9 6 .9 mh z , f ou t = 155 0 mhz, bw = 1 . 5 m h z ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?170 ?100 ? 110 ?120 ?130 ?140 ?150 ?160 10 10m 1m 100k 10k 1k 100 03166-a - 015 frequency (hz) ph a se n o ise, l( f ) ( d b c /h z) f i g u re 18. r e s i dua l p h as e n o is e , 4 03 m h z f ou t , 1 g h z refclk ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 170 ? 100 ?110 ? 120 ? 130 ? 140 ? 150 ? 160 10 10m 100m 1m 100k 10k 1k 100 031 66-a - 019 frequency (hz) p has e no i s e , l(f) (dbc / h z) f i g u re 19. t r ans l at i o n l o op r e s i d u a l phas e n o is e f lo = 1 5 00 m h z, f out = 15 5 0 mh z, l o o p bw = 50 k h z ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 150khz/ span 1.5mhz 2khz 2khz 940s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] ?56.76db 423.84769539khz 03166-a - 021 1 1 f i g u re 20. f r ac t i on al d i v i d e r l o op sf dr , f in = 9 7 .3 mh z , f ou t = 155 0 mhz, bw = 1 . 5 m h z AD9858 rev. a | page 13 of 32 ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 15mhz/ span 150mhz 5khz 5khz 15s rf att unit 10db dbm a 1ap ? ref lvl 0dbm rbw vbw swt delta 1 [t1] 0.0db 0.00000000hz 03166-a - 017 1 f i g u re 21. f r ac t i on al d i v i d e r l o op sf dr , f in = 9 6 .9 mh z , f ou t = 155 0 mhz, bw = 15 0 mhz ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 150khz/ span 1.5mhz 1khz 500khz 7.6s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] ?81.10db 57.11422845khz 03166-a - 022 1 f i g u re 22. t r ans l at i o n l o op sfdr , f lo = 1 4 59 m h z, f ou t = 155 0 mhz, bw = 1 . 5 m h z ? ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 15mhz/ span 150mhz 10khz 500hz 75s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] ?96.36db ? 42.98597194mhz 03166-a - 023 1 1 f i g u re 23. t r ans l at i o n l o op sfdr , f lo = 1 4 59 m h z, f ou t = 155 0 mhz, bw = 15 0 mhz ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 15mhz/ span 150mhz 5khz 5khz 15s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] ?64.55db ?1.20240481mhz 03166-a - 020 1 1 f i g u re 24. f r ac t i on al d i v i d e r l o op sf dr , f in = 9 7 .3 mh z , f ou t = 155 0 mhz, bw = 15 0 mhz ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 150khz/ span 1.5mhz 1khz 500hz 7.6s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] ?60.67db ?57.11422846khz 03166-a - 045 1 1 f i g u re 25. t r ans l at i o n l o op sfdr , f lo = 1 4 10 m h z, f ou t = 155 0 mhz, bw = 1 . 5 m h z ?1 0 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ? 100 center 1.55ghz 15mhz/ span 150mhz 5khz 5khz 15s rf att unit 10db dbm a 1ap ref lvl 0dbm rbw vbw swt delta 1 [t1] ?64.55db ?1.20240481mhz 03166-a - 046 1 1 f i g u re 26. t r ans l at i o n l o op sfdr , f lo = 1 4 10 m h z, f ou t = 155 0 mhz, bw = 15 0 mhz AD9858 rev. a | page 14 of 32 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 900 675 450 225 1125 03166-a - 025 ref clock (mhz) p o we r drawn (w) f i gure 27. sup p l y current v s . r e fclk ( f ou t = r e fclk /5) 600 3.1v 3.3v 3.5v 500 300 400 200 100 0 0 7 0 140 210 280 350 420 03166-a - 024 f out (mhz) s u p p l y curre nt (ma) f i gure 28. sup p l y current v s . f ou t ( 1 g h z re fcl k ) AD9858 rev. a | page 15 of 32 theory of operation overview the AD9858 dir e c t dig i t a l sy n t h e sizer (d ds) is a f l exi b le device t h a t c a n a ddr ess a wi de r a n g e o f a p plic a t io ns. t h e d e vice co n s ists o f a n nc o wi t h a 32- b i t phas e acc u m u l a t o r , 14-b i t phas e o f fs et ad j u s t m e n t , a p o w e r ef f i cien t d d s co r e , a nd a on e g i ga-s am ples p e r s e co nd (1 gs p s ) 10-b i t dig i t a l - to -a na lo g co n v er t e r . th e AD9858 in co r p o r a t es addi tiona l ca p a b i li ties f o r a u t o ma t e d f r eq ue n c y s w ee p i n g . t h e d e v i ce al so o f f e r s a n a n al og mixer ca p a b l e of o p era t in g a t 2 gh z, a phas e - f r e q uen c y det e c t o r (p fd), a nd a p r ogra mma b le c h a r g e p u m p (cp) wi th ad van c e d fa st-l o c k c a p a b i li ty . t h es e rf b u i l d i ng b l o c ks c a n b e us e d fo r va r i o u s f r e q uen c y syn t h e sis lo o p s o r as n e e d e d in sys t em desig n . the AD9858 can dir e c t l y g e n e r a t e f r eq uen c ies u p t o 400+ mh z w h en dr i v en a t a 1 ghz i n t e r n a l clo c k sp e e d . t h is clo c k can b e der i v e d f r o m an ext e r n al c l o c k s o ur ce o f u p t o 2 gh z b y usin g t h e on-ch i p divi de-b y-2 fe a t ur e . the o n -chi p m i xer a n d p f d/cp ma k e p o s s i b le a va r i ety o f syn t h e sizer co nf igura t io n s c a p a bl e of ge ne r a t i ng f r e q u e nc i e s i n t h e 1 g h z to 2 g h z r a nge or h i g h e r . the AD9858 o f f e rs th e ad van t a g es o f a d d s wi t h the addi tio n al f l exi b ili t y t o w o rk in con c er t wi th a n alog f r e q uen c y sy n t h e sis te ch ni qu e s ( p l l , mi x i ng ) to ge ne r a te pre c i s i o n f r e q u e nc y sig n als wi t h hig h f r e q uen c y r e s o l u tio n , fast f r e q uen c y h o p p i n g , f a st s e tt l i ng t i m e , an d a u tom a te d f r e q u e nc y s w e e pi ng ca p a b i li ties. w r i t in g da t a t o i t s o n -c hi p dig i t a l r e g i s t ers tha t co n t r o l al l o p era t io ns o f the de vic e easil y c o nf igur es th e AD9858. the AD9858 o f f e rs a c h o i ce o f bo t h s e r i al an d p a ral l e l p o r t s f o r co n t r o l l in g t h e de vice . f o ur us er p r o f i l es ca n b e s e le c t e d b y a p a ir o f ext e r n al p i n s . th es e p r o f i l es al lo w in dep e n d e n t s e t t in g o f t h e f r e q uen c y t u nin g w o rd and t h e phas e o f fs et ad j u s t men t w o r d f o r eac h o f f o ur s e lec t a b le co nf igura t io n s . the AD9858 can b e p r og ra mmed t o o p er a t e in sin g le-t on e m o de o r in f r eq uen c y-sw e e p i n g m o de . t o s a v e o n p o w e r co n s um p t io n, t h er e is als o a p r og ra mma b l e f u l l -s le ep m o de , d u r i n g whic h mos t o f th e de vic e is p o w e r e d do wn t o r e d u ce cu rr e n t f l o w . the o p er a t io n of a dds is des c r i b e d in de t a i l i n a t u to r i a l av a i l a b l e f r o m a n a l o g d e v i c e s at ww w . a n a l o g . c o m / d d s . componen t blocks dds cor e the d d s co r e gen e r a t e s t h e n u m e r i c val u es t h a t r e p r es en t a si n u so i d in t h e d i gi t a l d o m a in . de pen d i n g o n th e o p e r a t in g m o de o f th e dds, this sin u s o id ma y be c h an ged in f r eq uen c y , phas e , o r p e rha p s m o d u l a t e d b y a n info r m a t ion ca r r y i n g sig n a l . the f r e q uen c y o f t h e o u t p u t si g n al is det e r m i n e d b y a us er - pro g r a m m e d f r e q u e nc y tu n i ng word ( f t w ) . t h e re l a t i on of t h e output f r e q u e nc y of t h e d e v i c e t o t h e s y ste m cl o c k ( s y s c l k ) i s d e t e rm i n ed b y t h e f o l l o w i n g eq u a t i o n : () n o sysclk ftw f 2 = wher e f o r th e AD9858, n = 32. f o r a m o r e det a i l e d expla n a t ion o f a dds co r e , co n s u l t t h e dd s tut o r i a l a t w w w . a n a l o g .co m /dds . dac o u tp ut the AD9858 inco r p o r a t es a n in t e g r a t ed 10 -b i t c u r r en t o u t p u t d a c . t w o c o m p l e me n t ar y output s prov i d e a c o mbi n e d f u l l - s c ale o u t p u t c u r r en t (i ou t ). dif f er en t i a l o u t p u t s r e d u ce t h e a m o u n t o f co mm on- m o d e n o is e t h a t mig h t b e p r es en t a t t h e d a c output , of f e r i ng t h e a d v a n t age of an i n c r e a s e d s i g n a l - t o - n o is e r a t i o . th e f u l l -s cale c u r r en t is con t r o l l e d b y m e a n s o f an ext e r n al r e sis t o r (r set ) co nn e c te d b e twe e n t h e d a cis e t pin an d an a l o g g r ou n d . t h e f u l l - s c a l e c u r r e n t i s prop or t i on a l to t h e re s i stor v a lu e a s f o l l ow s : out set i r / 19 . 39 = the maxi m u m f u l l -s cale o u t p ut c u r r en t o f t h e co m b in e d d a c o u t p u t s is 40 ma, b u t limi t i n g t h e o u t p u t t o 20 ma p r o v ides the b e s t s p ur io us-f r e e d y namic ra ng e (s fd r) p e r f o r ma n c e . the d a c o u t p u t com p lian ce ra n g e is (a v dd C 1.5 v) t o (a v dd + 0.5 v). v o l t a g es de v e l op e d b e yo nd t h is ra n g e c a us e excessi v e d a c disto r t i o n and c o u l d p o te n t i a l l y da m a ge t h e d a c output c i r c u i t r y . prop e r a tte n t i o n s h ou l d b e p a i d to t h e lo ad t e r m ina t ion t o k e ep t h e o u t p u t v o lt a g e w i t h in t h is co m p lian ce ra ng e . w h e n t e r m i n a t ing t h e dif f er en t i al o u t p u t s in t o a t r an sfo r m e r , t h e cen t er t a p sh o u ld b e a t t a ch e d t o a v dd . pll frequency synthesizer the p ll f r e q ue n c y syn t h e sizer is a g r o u p o f indep e n d e n t syn t h e sis b l o c ks , desig n e d t o b e us e d wi t h the d d s t o exp a nd t h e ra n g e o f syn t h e sis a p pli c a t ion s . th es e b l o c ks a r e a dig i t a l p h ase-f r eq uen c y det e c t o r (p fd) tha t dr i v es a cha r g e p u m p (cp). th e cha r g e p u m p i n co r p ora t es fast-lo c ki ng log i c, des c r i b e d b e lo w . b a s e d on sy ste m r e q u ir e m e n ts , t h e us er s u p p lies an ext e r n al lo o p f i l t er a nd o n e o r m o r e v c os. a hig h sp e e d a n a l og m i xer is in cl ude d fo r t r a n sla t ion s y n t h e sis lo o p s. u s in g t h e dif f er en t b l o c ks in t h e p ll f r e q ue n c y syn t h e s i zer in co n j u n c t io n w i t h t h e d d s, t h e us er ca n cr e a t e t r a n s l a t io n lo o p s ( a l s o k n ow n a s of f s e t l o op s ) , f r ac t i on a l d i v i d e r l o op s , a s wel l a s tradi t io nal p ll lo o p s t o m u l t i p ly th e o u t p u t o f t h e d d s in fr e q u e n c y . AD9858 rev. a | page 16 of 32 phase-frequency detector the phas e dete c t o r has tw o i n pu ts, pd in and div in . b o t h a r e a n alog in p u ts tha t c a n be op era t ed in dif f er en t i a l o r sin g le- en d e d m o de. b o t h a r e desig n e d to o p er a t e a t f r e q uen c ies u p to 150 mh z, al t h oug h sig n als o f u p t o 400 mh z c a n be a c co mm o d a t e d o n th e i n p u t s w h en th e d i v i d e -b y- 4 fun c ti o n s a r e us e d . th e ex p e c t e d i n p u t l e ve l fo r b o t h t h e pd an d d i v in p u ts is in t h e ra n g e o f 800 mv p-p (dif f e r e n t ial), 400 mv p - p (sin g l e-e n de d). a p r o g r a mma b l e divider t h a t o f fers di visio n ra tios o f m, n = {1, 2, 4} imm e dia t e l y f o l l o w s th e in p u t. th e divisio n ra t i o is co n t r o l l ed b y mea n s o f th e con t r o l fu n c ti o n r e gi s t er . cha r ge pump the cha r g e p u m p o u t p u t r e fer e n c e c u r r en t is det e r m i n e d b y a n ext e r n al r e sis t o r (~2.4 k?), whic h es tab l ish e s a 500 a max i m u m in ter n a l b a s e li n e c u r r en t (i cp0 ). th e b a s e li ne c u r r en t is s c ale d t o p r o v ide t h e a p p r o p r i a t e dr i v e c u r r en t fo r t h e cp s va r i o u s o p er a t i n g mo des (f r e q u en c y dete c t mo de, wi de clo s e d - l o op , an d f i n a l c l o s e d - l o o p ) . t h e am ou n t of s c a l i n g i n e a ch m o de is p r og ra mma b l e b y m e an s o f t h e val u es s t o r e d i n t h e co n t r o l f u n c t i on r e g i s t er , g i ving t h e us er maxi m u m f l exi b i l i t y o f th e pll s f r e q ue n c y lo c k in g ca p a b i li ty . the cp p o la r i ty ca n be conf igur ed as ei t h er p o si ti v e o r nega t i v e wi t h r e s p ec t t o t h e pd in p u t. w h en the cp p o lar i ty is p o si ti v e , if th e d i v i n p u t lea d s th e p d in p u t , th e c h a r g e p u m p a t t e m p ts t o de cr e a s e t h e v o l t a g e a t t h e v c o co n t r o l n o de . i f t h e d i v i n p u t la gs t h e pd in p u t, th e c h a r g e p u m p w o rks t o in cr eas e the v o l t a g e a t t h e v c o co n t r o l n o de . w h e n t h e cp p o la r i ty is n e ga ti v e , th e o p posi t e occur s . th i s allo w s th e use r t o d e f i n e ei ther in p u t as t h e f e e d back p a t h . this als o al lo ws th e AD9858 t o acco mm o d a t e g r o u n d -r efer en ce d o r s u p p l y - r efer en ce d v c os. this f u nc t i o n a l i t y is def i n e d b y t h e cha r ge p u m p p o l a r i t y (cp p ) b i t in the co n t r o l f u n c tio n r e gis t er . w h en cp p = 0 (d e f a u l t ), th e c h a r g e p u m p i s se t u p f o r o p e r a t i o n wi th a g r o u n d -r ef er enced v c o . w h en cp p = 1, th e c h a r g e p u m p is s e t u p fo r a s u p p l y -r efer en ce d v c o . i n te r n a l to t h e c p , t h e i cp0 c u r r en t is s c ale d t o p r o v ide dif f er en t o u t p ut dr i v e c u r r en t val u es fo r t h e va r i o u s m o des o f o p era t ion. i n i t s n o r m a l o p er a t in g m o de, t h e f i na l clo s e d -l o o p m o de can be p r og ra mm e d t o s c ale i cp0 b y 1, 2, 3, o r 4 . s e t t in g th e cha r g e p u m p c u r r en t of fs et b i t, cfr < 1 3 >, a p plies a 2 ma o f fs et t o t h e p r og ra mm e d c h a r g e p u m p c u r r en t, al lo wing s c aler val u es o f i cp 0 o f 5, 6, 7, o r 8. t h e wide c l os ed-l o o p m o de can b e p r og ra mm e d to s c a l e i cp0 b y 0, 2, 4, 6, 8 , 10, 12, o r 14. th e f r eq uen c y det e c t m o de can be p r og ra mm e d t o s c ale i cp0 b y 0, 20, 40, o r 60. th e dif f er en t m o des o f o p er a t io n, c o n t r o l l e d b y t h e fast-lo c k i n g lo g i c, a r e dis c uss e d i n t h e n e x t s e c t io n the cp has a n i n de p e n d e n t s e t o f p o w e r p i n s t h a t c a n op era t e a t u p t o 5.25 v . w h i l e t h e de vic e can o p era t e f r o m g r o u nd t o ra i l , t h e v o l t a g e co m p li an ce sh ou ld b e k e p t i n t h e ra n g e o f 0.5 v to 4 . 5 v to e n su re t h e b e st ste a dy -st a te p e r f or manc e. t h e co m b in a t ion o f p r o g ra mma b l e o u t p ut c u r r en t, p r o g ra mma b l e p o la r i ty , wid e c o m p li an ce ra n g e, a nd p r o p r i et ar y fast-lo c k ca p a b i li ty o f fers t h e f l exi b i l i t y ne ces s a r y fo r t h e dig i t a l p ll t o o p era t e w i t h i n a b r o a d ra n g e o f p ll a p plic a t io ns. fast-locking logic the charge p u m p i n cl u d es a f a st-l o c k i ng a l gor i t h m t h a t hel p s to ove r c o me t h e t r a d it i o n a l l i m i t a t i ons of pl l s w i t h re g a rd to f r e q u e nc y s w i t c h i n g t i m e . t h e f a st - l o c k i ng a l go r i t h m wor k s i n co n j u n c t io n w i t h t h e lo o p f i l t er s h own i n f i gur e 29 t o p r o v ide ext r em e l y fast f r e q uen c y s w i t chi n g p e r f o r ma n c e. b a s e d o n t h e er r o r s e en b e tw e e n t h e fe e d b a ck s i g n al an d t h e r e f e r e n c e si gn al , th e fas t - l oc k i n g alg o ri th m p u t s th e c h a r g e p u m p i n t o on e o f t h r e e s t a t es: f r e q uen c y det e c t m o de , a wide clo s e d -lo o p m o de, a nd a f i na l clo s e d -lo o p m o d e . i n t h e f r e q uen c y dete c t m o de, t h e fe e d b a ck and r e fer e n c e sig n a l s a r e r e g i s t er in g s u bst a n t ial phas e and f r e q uen c y er r o rs. r a t h er t h an o p e r a t in g in a co n t in uo us c l osed - l oo p f e e d ba ck m o de , th e cha r g e p u m p s u p p lies a f i xe d c u r r en t o f t h e co r r e c t p o la r i ty t o th e v c o co n t r o l n o de th a t d r i v e s th e loo p t o w a r d s f r eq ue n c y lo c k . on c e f r e q uen c y lo c k is de t e c t e d , th e f a s t -lo c kin g log i c s h if ts t h e p a r t i n t o on e o f t h e clos e d -lo o p m o des. i n t h e clos e d - lo o p m o des, e i t h er wide o r f i na l, t h e cha r ge p u m p su p p lies c u r r en t t o t h e l o o p f i l t er as dire c t e d b y t h e phas e-f r e q ue n c y de te c t or pf d . t h e f r e q u e nc y - d e te c t mo d e i s i n te nde d to b r i n g t h e sy s t e m t o a l e vel o f f r e q ue nc y lo ck f r om w h i c h t h e in t e r m e d ia r y c l ose d - l o o p syst em ca n q u ickl y a c hi e v e p h ase lo c k . the le ve l o f f r e q uen c y lo c k acc u rac y a i m e d f o r is typ i cal l y r e f e r r ed t o as the lo c k ra n g e . o n ce t h e f r eq uenc y is wi thin t h e lo ck ra n g e , t h e t i me r e q u ir e d t o achie v e phas e l o ck can b e det e r m in e d b y sta n da r d p l l tran sien t anal ysis m e t h o d s. n o t e t h a t t h e cha r g e p u m p c u r r en t s o ur ces as s o ci a t e d w i t h t h e f r e q uen c y dete c t m o de a r e co n n e c te d to pin 6 4 , w h i l e t h e clo s e d lo o p c u r r en t s o ur ces a r e co nn e c t e d t o p i n s 65 a nd 66. p i n 64 is co nne c t e d dir e c t ly to t h e lo o p f i l t er zer o co m p e n s a t i on ca p a c i t o r , as sh o w n in f i gur e 29. this co nn ec tion al lo ws th e s m oo th e s t t r a n s i t i o n fr o m th e f r e q u e n c y d e t e ct m o d e t o th e c l os e d -lo o p m o des a nd enab les fas t er o v eral l swi t c h in g tim e s. p i n s 65 an d 66 a r e co nn e c t e d to t h e lo o p f i l t er in t h e co n v e n t i o n a l m a nner . r2 c2 cp cp cpfl AD9858 03166-a - 032 f i gure 29. s y mbo l i c r e presentat i on of char ge p u mp to l o op f ilter conn ec ti o n AD9858 rev. a | page 17 of 32 the f r e q uen c y dete c t ion b l o c k w o rks as fol l o w s. th e co m p a r is o n log i c in t h e f r e q ue n c y det e c t ion ci r c ui t r y o p era t es one e i g h t h of t h e dd s s y ste m cl o c k . a c o m p ar i s on i s m a d e of t h e f r e q ue n c ies p r es en t a t t h e pd in pu t and t h e d i v in p u t o v er 1 9 dds cl o c k c y cl es . t o en s u r e t h a t f r e q uen c y lo ck det e c t io n is achi e v e d w h i l e t h e f r e q uen c y dif f er en c e is w i t h i n t h e pll lo ck ra ng e , t h e s l e w r a t e o f th e v c o in p u t sh o u ld be lim i t e d s u ch th a t th e lock ra n g e ca nn o t be tr a v ers e d wi thin 152 sys t em c l o c k c y c l es. th e s l ew ra t e o f t h e v c o in p u t is det e r m in e d b y t h e p r og ra mm e d le ve l o f f r e q uen c y det e c t c u r r en t an d t h e si ze o f t h e zer o co m p en s a t i o n c a p a ci t o r ac co r d in g t o the f o l l o w in g r e l a tio n s h i p : z det f c i dt dv = on ce f r e q ue n c y dete c t ion o c c u rs, t h e lo o p is clo s e d and t h e lo o p is lo ck b a s e d o n t h e c u r r en t p r og ra mm e d fo r t h e wi de c l os ed-lo o p m o de . i t is im p o r t a n t tha t t h e lo o p be desig n e d f o r c l osed - l oo p s t a b ili t y while i n t h e w i de c l osed - l oo p m o d e . i n t h i s m o de , les s p h as e ma rg in c a n usual l y be t o lera t e d , be ca us e this m o de is o n l y us ed t o enhan c e t h e lo ck tim e , b u t is n o t us e d in t h e lo c k e d f r e e r u nnin g st a t e. on ce t h e w i de clo s e d -lo o p m o d e achi e v es phas e lo ck as de t e r m ine d b y an in t e r n a l lo ck d e t e ct o r , th e p h a s e - de t e ct o r / c ha r g e p u m p tra n si ti o n s in t o t h e f i na l clo s e d -lo o p st a t e. i f n o wi de clo s e d -lo o p c u r r en t is p r ogra m m e d , th e loo p tra n si tio n s d i r e ctl y f r o m th e f r eq ue n c y dete c t m o de i n to t h e f i na l clo s e d -lo o p st a t e. i n t h e f i na l clo s e d - l o op st a t e, t h e l o op ch ar a c te r i st i c s s h ou l d b e opt i m i z e d f o r t h e desir e d f r e e r u nnin g lo o p b a ndwi d t h . the f r e q uen c y det e c t m o de is p r ima r i l y us ef u l in o f fs et o r t r a n s l a t ion lo o p a p plic a t io ns w h er e t h e phas e det e c t o r i n p u t s a r e m o r e li k e l y to det e c t la rg e f r e q uen c y tra n s i tio n s. f o r lo o p a p plic a t ion s wi t h sig n if ican t amo u n t s o f division in t h e fe e d - b a ck lo o p , t h e f r e q uen c y de te c t i o n m o de m a y no t ac t i v a te. t h is is d u e t o t h e limi t e d am o u n t o f f r e q uen c y dif f er en c e t h a t is exp e r i en ce d a t t h e phas e de t e c t o r in p u ts. f o r t h es e a p pli c a t io n s , t h e pr i m ar y me ans of a c c e l e r a t i ng t h e f r e q u e nc y s e tt l i ng t i m e i s t o desig n t h e lo o p t o acq u ir e lo c k wi th t h e wide c l os ed-lo o p s e t t i n g and t h e n sw i t ch to t h e f i na l clo s e d -lo o p s e t t i n g. a s m e n t ion e d e a rlier , ca r e sh o u ld b e t a k e n w h e n pla n nin g fo r a la r g e tra n si ti o n usi n g th e f r eq uen c y d e t e c t m o de t o e n s u r e th a t t h e cha r g e p u m p do es n o t c a us e t h e v c o t o o v ers h o o t t h e cl o s e d -l o o p l o ck r a nge, as c y cl e sl i p p i ng c o u l d o c c u r , w h ich wou l d re su l t in e x te nd e d d e l a y s . f i g u re 3 0 show s two s y ste m r e s p o n s e s. i n t h e f i rs t, t h e cha r g e p u m p o u t p u t c u r r en t is max i mi ze d d u r i n g t h e f r e q ue n c y - dete c t m o de s o t h a t , a f ter 152 c l o c k c y c l es , th e v c o v o l t ag e has exceede d th e c l os ed-lo o p lo ck ra n g e . th e s e con d syst em p r o v ides les s c u r r en t d u r i n g t h e f r e q uen c y dete c t m o de. w h i l e t h is r e su l t s in a l o n g er del a y in a p p r o a ching t h e cl o s e d -l o o p l o ck r a nge, b e c a u s e t h e s y ste m do es n o t exce e d t h e clos e d -lo o p ra n g e , t h e f a s t -lo c kin g log i c shif ts t h e ch a r ge p u m p i n t o i n ter m e d ia r y clos e d -lo o p m o de , re su lt i n g i n a s h or te r ove r a l l f r e q u e nc y s w itch i n g t i me. time vc o volta ge 031 66-a - 033 f i gure 30. s y mbo l i c r e presentat i on of char ge p u mp to l o op f ilter conn ec ti o n analog mixer the a n a l og mixer is in cl ude d for t r a n sla t io n lo ops, a l s o k n o w n a s o f fse t l o o p s . t h e ra d i o f r eq u e n c y (r f) a n d loc a l osc i lla t o r (l o) in p u ts a r e desig n e d t o o p e r a t e a t f r e q ue n c ies u p t o 2 gh z. b o t h in p u ts a r e dif f er en t i al a n al og in p u t st a g es. b o t h in p u t st a g es a r e in ter n a l ly dc b i as e d and sh o u ld b e conn e c te d t h r o ug h a n ext e r n a l ac c o u p lin g m e chan ism. the exp e c t e d i n p u t l e vel is in t h e ra n g e o f 800 mv p-p (dif f e r e n t ial). th e if (in t er m e dia t e f r e q uen c y) o u t p u t is a dif f er en t i al a n alog o u t p ut s t a g e desig n e d t o o p era t e a t f r e q uen c ies les s tha n 400 mh z. this mixer is bas e d o n t h e g i lb er t c e l l a r chi t e c t u r e . modes of operation the AD9858 dds s e c t ion has t h r e e mo des o f o p era t ionsin g l e to ne, f r e q uen c y sw e e p i n g , and f u l l sle e p . the r f b u i l din g b l o c ks (pf d , cp , a n d mixer ) ca n b e a c t i ve o r p o w e r e d do w n , us e d o r un us ed , in ei t h er o f th e ac ti v e m o des. i n t h e sin g le -t on e m o de , t h e de vice g e n e r a t e s a sin g le o u t p u t f r eq ue n c y d e t e rm in ed b y a 32-b i t w o r d (f r e q u e n c y t u ni n g w o r d ft w ) l o ade d t o an in t e r n a l r e g i st er . this f r e q uen c y can b e chan ge d as d e sir e d , a nd f r e q uen c y h o pp in g ca n b e a c co m p l - i s he d a t a r a te l i mi te d on ly b y t h e t i me re qu i r e d to up d a te t h e a p p r o p r i a t e r e g i s t ers. i f e v en f a st er h o pp in g is ne e d e d , t h e fo ur prof i l e s a l l o w r a pi d hoppi ng a m ong t h e f o u r f r e q u e nc i e s s t ore d in t h em b y m e an s o f ext e r n al s e le c t p i n s . t h e f r eq ue n c y-s w ee p i n g m o d e all o w s f o r th e a u t o m a t i o n o f mo st of t h e f r e q u e nc y - s w e e pi ng t a sk , m a k i ng ch i r p and ot he r f r e q uen c y - sw e e p in g a p plic a t io ns p o ssi b le w i t h ou t t h e in con v e n ie n c e and p o ssib le sp e e d lim i t a t i o n s i m p o s e d b y m u l t i p l e r e gis t er o p e r a t i o n s vi a th e i/o po r t . i n w h ich e ver mo de t h e de vice is o p era t in g, c h an g e s in f r eq uen c y a r e p h as e con t in uo us, whic h m e a n s tha t t h ey do n o t ca us e dis c o n t i n u i t ies i n t h e phas e o f t h e o u t p ut sig n al . the f i rs t phas e va l u e a f t e r a f r e q uen c y cha n ge is an i n cr e m e n t o f t h e la st AD9858 rev. a | page 18 of 32 the maxim u m us a b le f r e q uen c y in t h e f u ndamen t al ra n g e o f t h e d d s is typ i ca l l y b e tw e e n 4 0 % an d 45 % o f t h e n y q u ist f r eq ue n c y , d e pen d i n g o n th e r e co n s tr ucti o n f i l t e r . w i th a 1 gh z s y sclk, t h e AD9858 is ca p a b l e o f p r o d ucin g maxim u m o u t p u t f r eq uen c ies o f b e tw een 400 m h z an d 450 m h z, dep e n d in g on th e r e co n s tr ucti o n f i l t e r a n d t h e a p p l i c a t i o n sys t e m re qu i r e m e n t s . phas e val u e b e fo r e t h e chan g e , b u t a t t h e ne w t u nin g w o r d s phas e i n cr e m e n t val u e (ft w ). (n o t e t h a t t h is is n o t t h e s a me as phas e-coh e r e n t o v er f r e q uen c y cha n g e s; s e e f i g u r e 31.) reference signal f ref = a f ref = a f ref = a f out = 2a f out = 2a f out = a f out = a f out = 2a f out = a phase coherent phase continuous w here = phase of output signal, = phase at time of first frequency transition, and ' = phase at time of second frequency transition. = 2 re f = 2 re f + + ' = 2 re f = ref = re f = re f 03166-a-034 f o r a desir e d o u t p u t f r e q ue n c y (f o) a nd s a m p l i n g r a te (s y s clk), the f r eq uen c y t u ning w o r d (ft w ) o f th e AD9858 is calc u l a t ed acco r d in g t o t h e f o l l o w in g eq ua tion ( ) sysclk fo ftw n / 2 = w h er e n is t h e phas e acc u m u l a to r r e s o l u t i o n in b i ts (32 in t h e AD9858), fo is in h z , an d t h e ft w is a decima l n u m b er . on ce a de c i ma l n u m b er has b e e n ca lc u l a t e d , i t m u st b e r o unde d to an i n te g e r and c o n v e r te d to a 3 2 - bi t bi nar y v a lu e. th e f r eq uen c y r e s o l u tio n o f the AD9858 is 0.233 h z w h en the s y sclk is 1 g h z. f i g u re 31. the d i f f e r e nce be t w e e n a phas e cont i n u o us f r equ e nc y ch ang e and a p h as e cohe rent f r equenc y cha n g e single-tone m o de fre que nc y-sw e e p ing mode w h en in sin g le-t o n e m o de , t h e AD9858 g e n e ra t e s a sig n al , o r to ne, o f a sin g le desir e d f r e q uenc y . this f r e q uenc y is s e t b y t h e val u e lo ade d b y t h e us er i n t o t h e chi p s f r e q ue nc y t u nin g w o r d (ft w ) r e gi s t e r . t h i s f r eq ue n c y ca n be bet w een 0 h z a n d s o me wha t b e lo w o n e-half o f the d a c s a m p ling f r e q uen c y (s y s clk). o n e - half o f th e s a m p lin g f r e q uen c y is co mm onl y cal l e d t h e n y q u is t f r e q uen c y . th e p r ac t i cal u p p e r limi t t o t h e f u ndam e n t a l f r e q uen c y r a n g e o f a dds is deter m i n e d b y t h e char ac te r i st ic s of t h e e x te r n a l l o w-p a ss f i lte r , k n own as t h e re c o nst r u c t i on f i lte r , w h i c h m u s t f o l l ow t h e d a c output of t h e d d s. this f i l t er r e co n s tr uc ts the desir e d a n alog sin e wa v e output s i g n a l f r om t h e st re a m of s a m p l e d a m p l itu d e v a lu e s o u t p ut b y t h e d a c a t t h e s a m p l e ra t e (s y s clk ) . the AD9858 p r o v ides a u t o ma ted f r eq uen c y sweep i n g ca p a b i li ty . this al lo ws th e AD9858 t o g e n e ra t e f r eq uen c y-s w ep t sig n als f o r c h ir p e d rad a r o r o t h e r a p p l ica t io n s . th e AD9858 in c l ud es fe a t ur es t h a t a u to ma t e m u ch o f t h e t a s k o f exe c u t in g f r e q ue n c y sw e e ps. the f r e q uen c y s w e e p fe a t ur e is i m ple m en t e d t h r o ug h t h e us e o f a f r e q uen c y acc u m u la t o r (n ot to b e co nf us e d w i t h t h e pha s e acc u m u l a t o r). t h e f r e q ue n c y ac c u m u la t o r r e p e a t e d ly adds a f r eq ue n c y i n cr em en tal q u a n ti t y t o th e curr e n t val u e , th e r e b y c r e a t i ng n e w i n st an t a ne ou s f r e q u e nc y tu n i ng word s , c a u s i n g t h e f r e q u e nc y ge ne r a te d b y t h e dd s to ch ange w i t h t i me. t h e f r eq ue n c y i n cr em en t , o r s t e p s i ze , i s l o a d ed i n t o a r e gi s t e r k n o w n as t h e d e l t a f r e q ue n c y t u nin g w o r d (dft w). t h e ra t e a t wh i c h t h e f r eq ue n c y i s in cr em en t e d i s se t b y a n o t h e r r e gi s t e r , t h e de l t a f r e q uen c y ra m p ra t e wo r d (d frr w ). t o get h er t h es e tw o r e g i s t ers ena b le t h e a d 985 8 t o sw e e p f r o m a b e g i nnin g f r e q uen c y s e t b y th e f t w , u p wa r d s o r do wn war d s, a t a desir e d ra t e and f r e q uen c y st ep si ze. t h e r e su l t is a li ne a r f r e q uen c y sw e e p o r c h ir p . a d d s i s a sa m p led - da ta syst em . a s th e fun d a m en tal f r eq uen c y o f t h e d d s a p pr o a ch es t h e n y quis t f r e q uen c y , t h e lo w e r f i rs t ima g e a p p r o a ches t h e n y q u is t f r e q uen c y f r o m a b o v e . a s t h e f u ndam e n t al f r e q uen c y a p p r o a ch es t h e n y q u is t f r e q uen c y , i t b e com e s dif f i c u l t , a nd f i na l l y i m p o ssib le, to de sig n an d co n s tr uct a lo w - pa s s f i l t e r th a t w i ll p r o v i d e a d e q ua t e a t t e n u a t io n fo r t h e f i rs t i m a g e f r e q uen c y com p on e n t. AD9858 rev. a | page 19 of 32 40ns 80ns time fre q ue ncy 120ns 160ns delta frequency ramp rate word ( 8ns) 8ns 16ns time fre q ue ncy 24ns 32ns delta frequency tuning word 03166-a - 035 f i g u re 32. f r equen c y v s . tim e p l ot s f o r a g i ven sweep pro f ile the del t a f r e q u e n c y ra m p ra t e w o r d (dfrr w ) f u n c t i o n s as a co un t d own t i mer , in w h ich t h e val u e o f t h e d f rr w is de cr e- m e n t ed a t th e ra t e o f s y s c l k / 8 . t h i s m e a n s th a t th e m o s t ra p i d f r eq uen c y w o r d u p da te o c c u rs when a val u e o f 1 is lo aded in t o th e d f rr w , a n d r e s u l t s in a f r e q ue n c y in cr em en t a t 1/ 8 o f th e sy s c l k r a t e . w i t h a sy s c l k o f 1 g h z , t h e f r e q u e n c y c a n b e in cr em en t e d a t a maxim u m ra te o f 125 mh z ( d frr w = 1). t h e d e lt a f r e q u e nc y tu n i ng wo rd ( d f t w ) m u st sp e c i f y w h e t h e r t h e f r e q u e nc y s w e e p s h ou l d pro c e e d up or d o w n f r om t h e st a r t i n g f r e q uen c y (ft w ). ther efo r e , t h e d f t w is exp r es s e d as a t w os co m p le m e n t b i na r y val u e , in w h ich p o si t i ve indic a tes u p and n e ga t i ve i ndic a tes down. a df r r w v a lu e of 0 w r i tte n to t h e re g i s t e r stop s a l l f r e q u e nc y s w ee p i n g . th e r e i s n o a u t o ma ti c s t o p -a t - a - gi v e n- f r eq ue n c y f u n c t i on. th e us er m u s t calc u l a t e t h e t i m e in ter v al r e q u ir e d t o r e ach t h e f i na l f r e q uen c y an d t h e n issue a co m m a nd to wr i t e 0 in t o t h e d f r r w r e g i s t er . th e t i me r e q u ir e d fo r a f r e q uen c y s w ee p i s cal c ula t ed b y t h e f o ll o w in g f o rm ul a dftw dfrrw syscl k f f t 2 s f ? = 34 2 w h er e: t i s th e d u ra ti o n o f th e sw ee p in seco n d s . f s i s th e s t a r ti n g f r eq ue n c y d e t e rm in ed b y sysclk ftw f s = 32 2 . f f i s t h e fi n a l fr eq u e n c y . the del t a f r e q u e n c y s t ep si ze is g i v e n b y 31 2 sysclk dftw f = ? , r e m e m b er in g t h a t d f t w is a sig n e d (tw o s com p le m e n t ) val u e . t h e tim e bet w e e n ea ch f r eq ue n c y s t e p (? t ) is gi v e n b y syscl k dfrrw t = ? 8 the val u e o f t h e s t o p f r e q uen c y f f is det e r m i n e d b y t f t f f s f ? ? + = return in g to st artin g frequen c y the o r ig ina l f r e q uen c y t u nin g w o r d (ft w), w h ich wa s wr i t te n in t o t h e f r e q ue nc y t u nin g r e g i ster , do es n o t chan g e a t an y t i m e d u r i n g a s w eep i n g o p era t io n. this m e a n s tha t t h e d d s m a y be r e t u rn e d t o th e s w ee p s t a r tin g f r eq u e n c y a t a n y ti m e d u ri n g a s w ee p . s e t t in g t h e co n t r o l b i t na m e d a u t o c l ea r f r eq ue n c y ac c u m u l a tor forc e s t h e f r e q u e nc y ac c u m u l a tor to ze ro , i n st an t l y r e t u r n in g t h e dds t o t h e f r e q uen c y st o r e d as f t w . full-sleep mo de s e t t in g a l l o f t h e p o w e r - do w n b i ts in t h e co n t rol f u n c t i o n r e g i s t er ac t i v a t e s f u l l -s le ep mo de . d u r i n g t h e p o w e r - do wn co ndi t ion, t h e clo c ks ass o c i a t e d wi t h t h e va r i o u s f u n c t i o n a l b l o c ks o f t h e de vice a r e t u r n e d o f f, t h er eb y o f fe r i n g a sig n if ican t p o w e r s a vin gs. synchr oni atio n synclk and fud pins t i min g f o r th e AD9858 is p r o v ided via t h e us er -s u p p l ie d refclk i n p u t. the refcl k in p u t is b u f f er e d and is t h e s o ur ce f o r th e in t e r n all y g e n e ra t e d s y sclk . th e f r eq uen c y o f s y sclk ca n be ei t h er the s a m e as refclk o r half tha t o f refclk (via a p r o g r a mma b l e divide -b y - 2 f u n c t i on s e t i n t h e co n t r o l f u n c t i on r e g i st e r cfr). th e re fclk i n p u t is c a p a b l e o f ha nd lin g i n p u t f r e q uen c ies as hi g h as 2 g h z. h o w e v e r , t h e de vice is desig n e d fo r a max i m u m s y scl k f r e q uen c y o f 1 ghz. t h u s , i t i s m a n d at o r y t h at t h e d i v i d e - b y - 2 sy s c l k f u n c t i o n b e e n a b led w h en th e f r eq uen c y o f r e fc l k i s gr ea t e r th a n 1 gh z . AD9858 rev. a | page 20 of 32 s y sclk s e r v es as t h e s a m p le cl o c k fo r t h e d a c a n d is fe d t o a divide -b y - 8 f r e q uen c y divider to p r o d uce s y nclk. s y n c l k is p r o v ide d t o t h e us er o n t h e s y n c l k p i n. this ena b les syn c hr o n iza t ion o f ext e r n al ha r d wa r e wi t h t h e AD9858 s in t e r n al d d s c l o c k. e x t e r n al ha r d wa r e tha t is s y n c hr o n ized t o t h e s y nclk si g n al ca n t h e n b e us e d t o p r o v ide t h e f r e q ue n c y u p da te (fud) s i g n al t o the AD9858. th e f u d sig n al a n d s y nclk a r e us e d t o t r a n sfer t h e in ter n al b u f f er r e g i s t er co n t e n ts i n t o t h e m e m o r y r e g i st ers o f t h e de vic e . f i gur e 33 show s a bl o c k d i ag r a m of t h e s y nch r on i z a t i o n me t h o d o l o g y , a n d f i gur e 34 sh o w s a n i / o sy n c hr o n iza t ion t i min g dia g ra m. n o t e tha t s y nclk is als o us ed t o syn c hr o n ize t h e as s e r t io n o f t h e p r o f i l e s e le c t p i n s (ps0, ps1 ) . th e fud , ps0 , a n d ps1 p i n s m u s t be s e t u p and he ld a r o u nd th e r i sin g edge o f s y n c lk. th es e de vice in p u ts a r e desig n e d f o r zer o h o ld t i m e an d 3.5 n s se t u p tim e . up date re gs register memory edge detection logic refclk p0, p1 fud synclk 0 2 ghz divider disable synclk disable to core logic buffer memory 2 10 10 d q wr addr data synclk d q 03166-a - 036 8 f i gure 33. i/o s y n c hr oniz ation block d i agr a m synclk sysclk fud registered fud edge dete cted fud registere d fud edge d e tected valu e 2 value 1 io buffer memory control register data value 0 value 1 valu e 2 (asynch ronously loa d ed via i/o port) fud * * fud is an input provided by the user that must be set up and held around rising edges of synclk. the occurrence of the rising edge of synclk during the high state of the updateregs signal causes the buffer memory contents to be transferred into the control registers. similarly, a state change on the ps0 or ps1 pins is equivalent to asserting a valid fud sequence. note: i/o updates are synchronous to the synclk signal, regardless of the synchronization mode selected. (asyn ch ronously lo aded via i/o port) 03166-a - 037 f i gure 34. i/o s y n c hr oniz ation t i ming d i ag r a m AD9858 rev. a | page 21 of 32 frequency planning to achieve the best possible spurious performance when using the AD9858 in a hybrid synthesizer configuration, frequency planning can be employed. frequency planning consists of being aware of the mechanisms that determine the location of the worst-case spurs and then using the appropriate loop tuning parameters to place these spurs either outside the loop bandwidth, such that they are attenuated, or completely outside the frequency range of interest. when using the fractional divider configuration, the worst-case spurs occur whenever the images of the dac harmonics fold back such that they are close to the dac fundamental or carrier frequency. if these images fall within the loop bandwidth, they will be gained up by approximately 20 log n , where n is the gain in the loop. if n is relatively high, these spurs can still realize significant gain even if they are slightly outside the loop bandwidth, since the loop attenuation rate is typically 20 db/decade in this region. dac images occur at n f clock m f out where n and m are integer multiples of f clock and f out , respectively. figure 20 shows a high spurious condition where the low-order odd harmonics are folding back around the fundamental. figure 21 shows that the worst spurs are confined to a narrow region around the carrier and that wideband spurs are attenuated. figure 17 shows an alternate frequency plan that results in the same carrier frequency. recall that the output frequency of the dac is set by the equation ( f out = f clock ftw /2 n ) this makes it possible to produce the same f out by different combinations of f clock and ftw . in this case, the worst dac spurs are placed well outside the loop bandwidth such that they are attenuated below the noise floor. figure 24 shows a wideband plot for this frequency plan. other frequency combinations that can result in high spurious signals are when subharmonics of f clock fall within or near the loop bandwidth. to avoid this, ensure that the dac f out is sufficiently offset from the subharmonics of f clock such that these products are attenuated by the loop. frequency planning for the translation loop is similar in that the dac images and the f clock subharmonics need to be considered. figure 25 and figure 26 show results for a high spurious configuration where odd order images are folding back close to the carrier. figure 22 and figure 23 show an alternative frequency plan that generates the same carrier frequency with low spurious content. because this loop also requires a mixer lo frequency, additional care is required in planning for this frequency arrangement. generally there is some mixer lo feedthrough. the amount of feedthrough depends on the pcb board layout isolation as well as the mixer lo power level, but levels of C80 dbc can typically be achieved. figure 26 shows results for a situation where the mixer lo component shows up in the spectrum at 1.41 ghz, and another spur component shows up at mixer lo + f clock /8. this places the mixer lo frequency well outside the bandwidth of interest, resulting in the spectrum shown in figure 25. programming the AD9858 the transfer of data from the user to the dds core of the device is a 2-step process. in a write operation, the user first writes the data to the i/o buffer using either the parallel port (which includes bits for address and data) or serial mode (where the address and data are combined in a serial word). regardless of the method used to enter data to the i/o buffer, the dds core cannot access the data until the data is latched into the memory registers from the i/o buffer. toggling the fud pin or changing one of the profile select pins causes an update of all elements of the i/o buffer memory into the dds cores register memory. i/o port functionality the i/o port can be operated in either serial or parallel programming mode. mode selection is accomplished via the s/p select pin. logic 0 on this pin configures the i/o port for serial programming, while logic 1 configures the i/o port for parallel programming. the ability to read back the contents of a register is provided in both modes to facilitate the debug process during the users prototyping phase of a design. in either mode, however, the reading back of profile registers requires that the profile select pins (p0, p1) be configured to select the desired register bank. when reading a register that resides in one of the profiles, the register address acts as an offset to select one of the registers among the group of registers defined by the profile. the profile select pins control the base address of the register bank and select the appropriate register grouping. parallel progra mming mode in parallel programming mode, the i/o port makes use of eight bidirectional data pins (d7 to d0), six address input pins (addr5 to addr0), a read input pin ( rd ), and a write input pin ( wr ). a register is selected by providing the proper address combination as defined in the register map. read or write functionality is invoked by pulsing the appropriate pin ( rd or wr ); the two operations are mutually exclusive. the read or write data is transported on the d7 to d0 pins. the correlation between the d7 to d0 data bits and their functionality at a specific register address is detailed in the register map and register bit description. parallel i/o operation allows write access to each byte of any register in the i/o buffer memory in a single i/o operation at a 100 mhz rate. however, unlike write operation, readback capability is not guaranteed at the 100 mhz rate. it is intended as a low speed function for debug purposes. timing for both write and read cycles is depicted in figure 35 and figure 36. AD9858 rev. a | page 22 of 32 a 3 a 1 a 2 d 3 d 1 d 2 t wrhigh t wrlow t ahd t dhd t dou t asu t wr t asu t dou t adh t dhd t wrlow t wrhigh t wr specification 3ns 3.5ns 0ns 0ns 3ns 6ns 9ns value address setup time to wr signal active data setup time to wr signal inactive address hold time to wr signal inactive data hold time to wr signal inactive wr signal minimum low time wr signal minimum high time wr signal minimum period description d< 7: 0> a< 5: 0> wr 03166-a - 038 f i gu r e 3 5 . i / o p o r t w r it e c y cl e t i mi n g (p ar al le l ) a 3 a 1 a 2 d 3 d 1 d 2 t rdhoz t rdlov t adv t ahd t asu t adh t rdlov t rdhoz specification 15ns 5ns 15ns 10ns value address to data valid time (maximum) address hold time to rd signal inactive (minimum) rd low to output valid (maximum) rd high to data three-state (maximum) description d< 7: 0> a< 5: 0 > rd 03166-a - 039 f i gur e 3 6 . i/ o p o r t re a d c y cl e t i mi ng (p ar al le l ) AD9858 rev. a | page 23 of 32 serial programming mode in serial programming mode, the i/o port uses a chip select pin ( cs ), a serial clock pin (sclk), an i/o reset pin (ioreset), and either 1 or 2 serial data pins (sdio and/or sdo). the number of serial data pins used depends on the configuration of the i/o port; i.e., whether it has been configured for 2-wire or 3-wire serial operation as defined by the control function register. in 2-wire mode, the sdio pin operates as a bidirectional serial data pin. in 3-wire mode, the sdio pin operates only as a serial data input pin, and the sdo pin acts as the serial output. the maximum rate of sclk is 10 mhz; however, during read operation, the 10 mhz rate is not guaranteed. the serial port is an spi compatible serial interface and its operation is virtually identical to that of the ad9852/ad9854. serial port communication occurs in two phases. phase 1 is an instruction cycle consisting of an 8-bit word. the msb of the instruction byte flags the ensuing operation as a read or write operation. the 6 lsbs define the serial address of the target register as defined in the register map. the instruction byte format is given in table 5. table 5. d7 (msb) d6 d5 d4 d3 d2 d1 do (lsb) 1: read 0: write x a5 a4 a3 a2 a1 a0 phase 2 of a serial port communication contains the data to be routed to/from the addressed register. the number of bytes transferred during phase 2 depends on the length of the target register. serial operation requires that all bits associated with a serial register address be transferred. both phases of a serial port communication require the serial data clock (sclk) to be operating. when writing to the device, serial bits are transferred on the rising edge of sclk. when reading from the device, serial output bits are transferred on the falling edge of sclk. the bit order for both phases of a serial port communication is selectable via the control function register. the cs pin serves as a chip select control line. when cs is at a logic 1 state, the sdo and sdio pins are disabled (forced into a high impedance state). only when the cs pin is at a logic 0 state are the sdo and sdio pins active. this allows multiple devices to exist on a single serial bus. if multiple devices are connected to the same serial bus, then communication with a single device is accomplished by setting cs to a logic 0 state on the target device, but to a logic 1 state on all other devices. in this way, serial communication occurs only between the controller and the target device. in the case where i/o synchronization is lost between the AD9858 and the external controller, the ioreset pin provides a means to re-establish synchronization without initializing the entire device. asserting the active high ioreset pin resets the serial port state machine. this terminates the current i/o operation and puts the device into a state in which the next eight sclk pulses are expected to be the instruction byte of the next i/o transfer. note that any information previously written to the memory registers during the last valid communication cycle prior to loss of synchronization remains intact. register map the registers are listed in table 6. the serial address and parallel address numbers associated with each of the registers are shown in hexadecimal format. angle brackets <> are used to reference specific bits or ranges of bits. for example, <3> designates bit 3, while <7:3> designates the range of bits from 7 down to 3, inclusive. AD9858 rev. a | page 24 of 32 table 6. register map register address (lsb) name ser par (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value profile 0x00 <7:0> not used 2 ghz divider disable synclk out disable mixer power down phase detect pwrdwn power down sdio input only lsb first 0x18 n/a 0x01 <15:8> freq. sweep enable enable sine output charge pump offset bit phase detector divider ratio (n) (see table 10) charge pump polarity phase detector divider ratio (m) (see table 11) 0x00 n/a 0x02 <23:16> autoclr freq. accum autoclr phase accum load delta- freq timer clear freq accum clear phase accum open fast- lock enable dont use ftw for fast- lock 0x00 n/a control function register (cfr) 0x00 0x03 <31:24> frequency detect charge pump current (see table 7) final closed-loop charge pump current (see table 8) wide closed-loop charge pump current (see table 9) 0x00 n/a 0x04 delta frequency word <7:0> C n/a 0x05 delta frequency word <15:8> C n/a 0x06 delta frequency word <23:16> C n/a delta-freq tuning word (dftw) 0x01 0x07 delta frequency word <31:24> C n/a 0x08 delta frequency ramp rate word <7:0> C n/a delta-freq ramp rate (dfrrw) 0x02 0x09 delta frequency ramp rate word <15:8> C n/a 0x0a frequency tuning word no. 0 <7:0> 0x00 0 0x0b frequency tuning word no. 0 <15:8> 0x00 0 0x0c frequency tuning word no. 0 <23:16> 0x00 0 frequency tuning word no. 0 (ftw0) 0x03 0x0d frequency tuning word no. 0 <31:24> 0x00 0 0x0e phase offset word no. 0 <7:0> 0x00 0 phase offset word 0 (pow0) 0x04 0x0f not used not used phase o ffset word no. 0 <13:8> 0x00 0 0x10 frequency tuning word no. 1 <7:0> C 1 0x11 frequency tuning word no. 1 <15:8> C 1 0x12 frequency tuning word no. 1 <23:16> C 1 frequency tuning word no.1(ftw1) 0x05 0x13 frequency tuning word no. 1 <31:24> C 1 0x14 phase offset word no. 1 <7:0> C 1 phase offset word 1 (pow1) 0x06 0x15 not used not used phase o ffset word no. 1 <13:8> C 1 0x16 frequency tuning word no. 2 <7:0> C 2 0x17 frequency tuning word no. 2 <15:8> C 2 0x18 frequency tuning word no. 2 <23:16> C 2 frequency tuning word no. 2 (ftw2) 0x07 0x19 frequency tuning word no. 2 <31:24> C 2 0x1a phase offset word no. 2 <7:0> C 2 phase offset word 2 (pow2) 0x08 0x1b not used not used phase offset word no. 2 <13:8> C 2 0x1c frequency tuning word no. 3 <7:0> C 3 0x1d frequency tuning word no. 3 <15:8> C 3 0x1e frequency tuning word no. 3 <23:16> C 3 frequency tuning word no. 3 (ftw3) 0x09 0x1f frequency tuning word no. 3 <31:24> C 3 0x20 phase offset word no. 3 <7:0> C 3 phase offset word 3 (pow3) 0x0a 0x21 not used not used phase o ffset word no. 3 <13:8> C 3 0x22 reserved, do not write, leave at 0xff 0xff n/a reserved 0x0b 0x23 reserved, do not write, leave at 0xff 0xff n/a AD9858 rev. a | page 25 of 32 register bit descriptions cont rol f u nct i on r e gi s t er ( c f r ) the cf r is com p r i s e d o f fo ur b y tes lo ca te d in p a r a l l el addr ess e s 0x03 t o 0x00. th e cfr is us e d t o co n t r o l th e va r i o u s f u n c tio n s, f e a t ur es, an d mo des o f th e AD9858. th e f u n c t i o n ali t y o f eac h b i t is det a i l e d b e lo w . n o t e t h a t t h e r e g i st er b i ts a r e iden t i f i e d a c c o r d i n g t o th e i r se ri al r e gi s t er b i t l o ca ti o n s be gi n n i n g w i t h t h e m o st sig n if ican t b i t. cfr<31:30>: f r equency- dete ct mode charge pump current th e s e b i ts a r e us e d t o s e t t h e s c ale fac t o r fo r t h e f r e q uen c y- d e t e ct m o d e c h a r g e p u m p o u t p u t cu rr e n t pe r ta b l e 7 . th e cha r g e p u m p deli v e rs t h e s c ale d o u t p u t c u r r en t w h en t h e co n t r o l log i c f o r c es th e c h a r g e p u m p in t o i t s f r e q uen c y detec t o p era t i n g m o de. th e cha r g e p u m p s b a s e li n e o u t p u t c u r r en t (i cp0 ) is det e r m in e d b y the ext e r n al cp is et r e sis t o r an d is gi v e n b y t 1.24/cpise i cp0 = the r e co mm e n de d n o minal value o f t h e cp i s et r e sis t o r is 2.4 k?, which y i e l ds a b a s e line c u r r en t o f 500 a . table 7. cfr<31:3 0 > frequenc y- det e c t charge pump scale val u e no tes 0 0 b 0 i ou t = 0 ( d efault) 0 1 b 2 i ou t = 20 i cp0 1 0 b 3 i ou t = 40 i cp0 1 1 b 4 i ou t = 60 i cp0 cfr<29:27>: f i nal closed-l o o p mode charge pump output current th e s e b i ts a r e us e d t o s e t t h e s c ale fac t o r fo r t h e f i nal clos e d - lo o p m o de c h a r g e p u m p o u t p u t c u r r en t p e r table 8. th e c h a r ge p u m p de l i v e rs t h e s c ale d ou t p ut c u r r en t w h en t h e con t r o l log i c fo r c es t h e cha r g e p u m p i n t o i t s f i nal clos e d -lo o p m o de . table 8. cfr<29:2 7 > final closed - loop cp scale val u e no tes 0 x x b 0 i ou t = 0 ( default) 1 0 0 b 1 i ou t = i cp0 1 0 1 b 2 i ou t = 2 i cp0 1 1 0 b 3 i ou t = 3 i cp0 1 1 1 b 4 i ou t = 4 i cp0 cfr<26:24>: wide closed-l oop charge pu mp output current th e s e b i ts a r e us e d t o s e t t h e s c ale fac t o r fo r t h e wi de clos e d - lo o p cha r g e p u m p o u t p u t c u r r en t, s e e table 9. the cha r g e p u m p de li v e rs t h e s c ale d o u t p u t c u r r en t w h e n t h e con t r o l log i c fo r c es th e c h a r g e p u m p in t o i t s wide clos ed-lo o p o p er a t in g m o de . table 9. cfr<26:2 4 > wid e closed -l oop cp scale val u e no tes 0 0 0 b 0 i ou t = 0 ( default ) 0 0 1 b 2 i ou t = 2 i cp0 0 1 0 b 4 i ou t = 4 i cp0 0 1 1 b 6 i ou t = 6 i cp0 1 0 0 b 8 i ou t = 8 i cp0 1 0 1 b 1 0 i ou t = 10 i cp0 1 1 0 b 1 2 i ou t = 12 i cp0 1 1 1 b 1 4 i ou t = 14 i cp0 cfr<23>: autoclear frequen c y accumulator bit w h en cfr<23 > = 0 (defa u l t ), a ne w de l t a f r eq uen c y w o r d is a p plie d to t h e i n p u t o f t h e acc u m u l a to r an d ad de d to t h e cu rr e n tl y s t o r ed v a l u e . w h en cfr<23 > = 1, this b i t a u t o ma tical l y sy n c hr o n o u s l y c l ea rs (lo a ds zer o s in to) t h e f r e q uen c y acc u m u la t o r fo r o n e c y cle u p o n r e cep t io n o f t h e fud s e q u e n c e indic a t o r . cfr<22>: autoclear phase accumulator bit w h en cfr<22 > = 0 (defa u l t ), a ne w f r eq uen c y t u nin g w o rd is a p plie d t o t h e i n p u t o f t h e phas e acc u m u l a t o r a n d adde d t o t h e cu rr e n tl y s t o r ed v a l u e . w h en cfr<22 > = 1, this b i t a u t o ma tical l y sy n c hr o n o u s l y c l ea rs (lo a ds zer o s in to) t h e phas e acc u m u la t o r fo r o n e c y cle u p o n r e cep t io n o f t h e fud s e q u e n c e indic a t o r . cfr<21>: loa d d e lta-frequency timer w h en cfr < 21 > = 1 (defa u l t ), t h e con t e n ts o f t h e de l t a f r eq uen c y ra m p ra t e w o r d a r e lo ad ed in t o t h e ra m p ra t e tim e r ( d ow n c o u n te r ) up on d e te c t i o n of a f u d s e qu e n c e . w h en cfr < 21 > = 0, t h e con t e n ts o f t h e de lt a f r e q uen c y ra m p ra t e w o r d a r e lo ad ed in t o t h e ram p ra te tim e r u p o n tim e o u t wi t h n o r e ga r d to t h e s t a t e o f t h e fud s e q u enc e indic a t o r (i . e ., t h e fu d s e q u e n ce i n di ca t o r is ig n o r e d). cfr<20>: clear frequency ac cumulator bit w h en cfr<20 > = 1, th e f r eq uen c y acc u m u la to r is s y nc h r onou sly c l e a re d a n d i s h e l d cl e a r u n t i l c f r < 2 0 > i s r e t u r n e d t o a l o g i c 0 s t a t e (def a u l t ). AD9858 rev. a | page 26 of 32 cfr<19>: clear phase accumulator bit when cfr<19> = 1, the phase accumulator is synchronously cleared and is held clear until cfr<19> is returned to a logic 0 state (default). cfr<18>: not used. cfr<17>: pll fast-lock enable bit when cfr<17> = 0 (default), the plls fast-lock algorithm is disabled. when cfr<17> = 1, the plls fast-lock algorithm is active. cfr<16> this bit allows the user to control whether or not the plls fast- locking algorithm uses the tuning word value to determine whether or not to enter fast-locking mode. when cfr<16> = 0 (default), the plls fast-locking algorithm considers the relationship between the programmed frequency tuning word and the instantaneous frequency as part of the locking process. when cfr<16> = 1, the plls fast-locking algorithm does not use the frequency tuning word as part of the locking process. cfr<15>: frequency sweep enable bit when cfr<15> = 0 (default), the device is in the single- tone mode. when cfr<15> = 1, the device is in the frequency- sweep mode. cfr<14>: sine/cosine select bit when cfr<14> = 0 (default), the angle-to-amplitude conversion logic employs a cosine function. when cfr<14> = 1, the angle-to-amplitude conversion logic employs a sine function. cfr<13>: charge pump current offset bit when cfr<13> = 0 (default), the charge pump operates with normal current settings. when cfr<13> = 1, the charge pump operates with offset current settings (see charge pump description). cfr<12:11>: phase detector reference input frequency divider ratio these bits set the phase detector divide value per table 10. table 10. cfr<12:11> phase detector divider ratio (n) notes 00b 1 default value 01b 2 1xb 4 lsb ignored cfr<10>: charge pump polarity select bit when cfr<10> = 0 (default), the charge pump is set up for operation with a ground-referenced vco. in this mode, the charge pump sources current when the frequency at pd in is less than the frequency at div in . it sinks current when the opposite is true. when cfr<10> = 1, the charge pump is set up for a supply- referenced vco. in this mode, the charge pumps source/sink operation is opposite that for a ground-referenced vco. cfr<9:8>: phase detector feedback input frequency divider ratio these bits set the phase detector divide value per table 11. table 11. cfr<9:8> phase detector divider ratio (m) notes 00b 1 default value 01b 2 1xb 4 lsb ignored cfr<7>: not used cfr<6>: disable bit for the 2 ghz refclk divider when cfr<6> = 0 (default), the refclk divide-by-2 function is not bypassed. refclk input can be up to 2 ghz. when cfr<6> = 1, the refclk divide-by-2 function is disabled. refclk input must be no more than 1 ghz. cfr<5>: synclk disable bit when cfr<5> = 0 (default), the synclk pin is active. when cfr<5> = 1, the synclk pin assumes a static logic 0 state (disabled). in this state, the pin drive logic is shut down to keep noise generated by the digital circuitry at a minimum. however, the synchronization circuitry remains active (internally) to maintain normal device timing. cfr<4:2>: power-down bits active high (logic 1) powers down the respective function. writing a logic 1 to all three bits causes the device to enter full- sleep mode. cfr<4> is used to shut down the analog mixer stage (default = 1). AD9858 rev. a | page 27 of 32 cfr<3> is us e d t o s h u t do wn t h e p h as e det e c t o r a n d cha r g e pu m p c i rc u i t r y ( d e f a u lt = 1 ) . cfr<2> is us e d t o s h u t do wn t h e d d s co r e and d a c and t o s t o p al l in t e r n al c l o c ks ex cep t s y n c lk (def a u l t = 0). cfr<1>: sdio input onl y w h en cfr < 1> = 0 (defa u l t ), t h e s d i o p i n has b i dir e c t io nal o p er a t ion ( 2 - w i r e s e r i a l p r o g r a mmin g mo de) . w h en cfr<1> = 1, th e s e r i al da ta i / o p i n (s d i o) is co nf igur ed a s an i n pu t on l y pi n ( 3 - w i r e s e r i a l pro g r a m m i n g mo d e ) . cfr<0>: lsb first n o t e tha t this b i t has an ef f e c t o n device o p er a t io n o n l y if th e i/o p o r t is co nf igur ed as a s e r i a l p o r t . w h en cfr<0> = 0 (defa u l t ), ms b f i rs t f o r m a t is ac ti v e . w h en cfr<0> = 1, ls b f i rs t f o r m a t is ac ti v e . other registers delta-frequency tu ning wor d (dftw) the d f t w r e g i s t er is co m p r i s e d o f f o ur b y t e s l o ca t e d in p a ral l e l addr es s e s 0x04 t o 0x07. the co n t en ts o f th e d f t w a r e a p p l i e d t o th e i n p u t o f th e fr e q u e n c y a c cu m u la t o r . u n l i k e th e f r e q uen c y t u ni ng w o r d as s o c i a t e d wi t h t h e phas e r e g i s t er (whic h is a 32-b i t un sig n e d in t e g e r), th e d t f w is a 32-b i t sig n e d in t e g e r . b e ca us e i t co n t r o ls th e ra te o f c h a n g e o f f r eq u e n c y , wh i c h ca n e i t h e r be a pos i ti v e o r n e g a ti v e v a l u e , th e d t f w is b y def i ni t i on a sig n e d n u m b er . w h e n t h e de vice is in t h e f r e q ue n c y-s w e e p mo de , t h e o u t p ut o f t h e f r e q uen c y acc u m u l a to r is adde d to t h e f r e q uen c y t u n i n g w o r d an d fe d to t h e phas e acc u m u l a t o r . this p r o v ides t h e f r e q uen c y sw e e p ca p a b i li ty o f th e AD9858. th e dft w co n t r o ls th e f r eq uen c y r e so l u ti o n a s soci a t e d wi th a f r eq u e n c y s w ee p . a s sh o w n i n t a b l e 6, t h e m o s t s i g n if ican t b y t e of t h e del t a f r eq uen c y t u ning w o r d is lo ca t e d in p a ral l e l r e g i s t er addr es s 0x07. th e less er sig n if ica n t b y t e s a p p e a r in de s c endin g o r der a t p a ral l e l r e g i s t er addr es s e s 0x06, 0x05, a n d 0x04. delta-frequency ramp rate word (dfrrw) the d f rr w is co m p r i s e d o f tw o b y t e s lo ca te d in p a ral l e l addr es s e s 0x08 to 0x09. th e d f rr w is a 16-b i t un sig n e d n u m b er t h a t s e r v es as a di v i der fo r t h e t i m e r us e d t o clo c k t h e f r e q u e nc y a c c u m u l a tor . t h e t i me r r u ns a t t h e dd s c l k r a te and ge ne r a te s a cl o c k t i ck to t h e f r e q u e nc y ac c u m u l a tor . t h e n u m b er s t o r e d i n t h e d f rr w reg i s t er deter m i n es t h e n u m b er o f d d s c l k c y c l e s be tw een s u b s eq uen t ti c k s t o th e f r eq ue n c y a c cu m u la t o r . e f f e cti v e l y , th e d f r r w c o n t r o l s th e ra t e a t wh i c h th e d f t w i s a ccu m u l a t e d . a s sh o w n i n t a b l e 6, t h e m o s t s i g n if ican t b y t e of t h e d f rr w is lo ca te d i n p a r a l l el r e g i ster ad dr ess 0x 09 a n d t h e le ast sig n if ic a n t b y t e a t addr es s 0x08. user profile r e gisters the us er p r o f i l e r e g i s t ers a r e com p r i s e d o f t h e fo ur f r e q uen c y t u nin g w o r d s and f o ur p h as e ad j u s t m e n t w o r d s. e a c h p a ir o f f r eq uen c y a n d p h as e r e g i s t ers fo r m s a co nf igura b le us er p r o f ile , s e le c t e d b y t h e us er p r o f i l e p i n s . user profiles the AD9858 f e a t ur es f o ur us er p r o f iles (0C3), se lec t e d b y p r o f ile s e l e c t pi ns ( p s 0 , p s 1 ) on t h e d e v i c e . e a c h prof i l e h a s it s ow n f r e q uen c y t u ni ng w o r d . this al l o ws t h e us er t o lo ad a dif f er en t f r e q uen c y t u ni ng w o r d in to e a ch p r o f i l e, w h ich ca n t h e n b e s e lec t e d as desir e d b y the p r o f ile s e lec t p i n s . this m a k e s i t p o ss ibl e to hop among t h e di f f e r e n t f r e q u e nc i e s a t r a te s u p to 1/8 o f t h e s y s c lk w h i l e i n t h e sin g le-t on e mo de . the AD9858 als o p r o v ides a 14-b i t p h as e-o f fs et w o r d (po w ) f o r eac h p r o f ile . the val u e in this r e g i s t er is a 14 -b i t un sig n e d n u m b er (po w ) t h a t r e p r es en ts t h e p r o p o r t i o n a l (po/2 14 ) p h ase o f fs et t o b e adde d t o t h e ins t an t a n e o u s phas e va l u e . this al lo ws th e p h as e o f the o u t p u t sig n al to be ad j u s t e d in f i n e in cr em en ts o f p h as e (a bo u t 0.022). i t is p o s s i b le t o u p da te t h e f t w an d po w o f a n y p r o f ile while t h e AD9858 is o p er a t in g a t t h e f r eq ue n c y s p ecif i e d b y a n o t h e r p r o f ile a n d t h en s w i t ch t o th e prof i l e c o n t ai n i ng t h e n e w l y l o a d e d f r e q u e nc y . c h ang i ng t h e c u r r en t p r o f ile u p da t e s bo t h p a ra m e ter s s o ca r e m u s t be ta k e n t o en s u r e tha t no un wan t e d p a r a m e t e r c h a n g e s tak e p l ac e . i t is als o p o s s i b l e t o r e p e a t edl y wr i t e a new f r eq uen c y in t o t h e ft w r e g i s t er o f a s e le c t e d p r o f i l e a n d t o j u m p to t h e n e w f r e q u e nc y b y st ro b i ng t h e f r e q u e nc y up d a te pi n ( f u d ) . t h i s a l l o w s hoppi ng to ar b i t r ar y f r e q u e nc i e s b u t i s l i mi te d i n t h e r a t e a t w h ic h this can b e accom p lished b y th e s p e e d o f th e i/ o po r t (100 mh z in p a ral l e l m o de) and the n e ces s i t y to tra n sf er s e v e ral b y te s of d a t a for e a ch ne w f r e q u e nc y tu n i ng wo rd. t h i s c a n b e a c c o m p l i s h e d r a pi d l y e n ou g h f o r m a n y app l i c at i o n s . f r equency tun i ng cont rol the o u t p u t f r eq uen c y o f th e dds is det e r m in e d b y th e 32 -b i t f r eq uen c y t u n i n g w o r d (ft w ) a n d t h e sys t em c l o c k (s y s clk ) . t h e r e la ti o n s h i p i s d e scri be d in th e f o llo w i n g eq ua ti o n () n o sysclk ftw f 2 = wher e f o r th e AD9858 n = 32. i n sin g le -t on e m o de , t h e ft w is s u p p lie d b y t h e ac t i v e p r o f i l e. i n f r eq u e n c y- sw ee p i n g m o d e , th e ft w i s th e o u t p u t o f th e fr e q u e n c y a c c u m u l a t o r . AD9858 rev. a | page 28 of 32 phase offset control a 14-bit phase offset () may be added to the output of the phase accumulator by means of the phase offset words stored in the memory registers. this feature provides the user with three different methods of phase control. the first method is a static phase adjustment, where a fixed phase offset is loaded into the appropriate phase-offset register and left unchanged. the result is that the output signal is offset by a constant angle relative to the nominal signal. this allows the user to phase align the dds output with an external signal, if necessary. the second method of phase control is where the user regularly updates the appropriate phase-offset register via the i/o port. by properly modifying the phase offset as a function of time, the user can implement a phase modulated output signal. the rate at which phase modulation can be performed is limited by both the speed of the i/o port and the frequency of sysclk. the third method of phase control involves the profile registers, in which the user loads up to four different phase-offset values into the appropriate profiles. the user can then select among the four preloaded phase-offset values via the AD9858 profile select pins. thus, the phase changes are accomplished by driving the hardware pins rather than writing to the i/o port, thereby avoiding the speed limitation imposed by the i/o port. however, this method is restricted to only four phase-offset values (one phase-offset value per profile). each profile has an associated frequency and phase value. changing the current profile updates both parameters, so care must be taken to ensure that no unwanted parameter changes take place. note that the phase-offset value is routed through a unit delay (z C1 ) block. this is done to ensure that updates of the phase- offset values exhibit the same amount of latency as updates of the frequency tuning word. otherwise, if the user decides to update both frequency and phase-offset values, the phase-offset change would propagate through the device before the tuning word change. the presence of the unit delay in the phase-offset path ensures that both frequency and phase-offset changes exhibit similar latency. profile selection a profile consists of a specific group of memory registers (see table 6). in the AD9858 each profile contains a 32-bit frequency tuning word and a 14-bit phase-offset word. each profile is selectable via two external profile select pins (ps0 and ps1) as defined in table 12. the specific mapping of registers to profiles is detailed in the register bit descriptions section. the user should be aware that selection of a profile is internally synchronized with dds clk using the synclk timing. that is, synclk is used to synchronize the assertion of the profile select pins (ps0, ps1). therefore, the ps0 and ps1 pins must be set up and held around the rising edge of synclk. the ps0 and ps1 inputs are designed for zero hold time and 3.5 ns setup time. table 12. ps1 ps0 profile 0 0 0 0 1 1 1 0 2 1 1 3 the profiles are available to the user to provide rapid changing of device parameters via external hardware, which alleviates the speed limitations imposed by the i/o port. for example, the user might preprogram the four phase offset registers with values that correspond to phase increments of 90. by controlling the ps0 and ps1 pins, the user can implement /2 phase modulation. the data modulation rate would be much higher than that possible by repeatedly reloading a single phase- offset register via the i/o port. AD9858 rev. a | page 29 of 32 AD9858 application suggestions dac filter phase/ frequency detector 150mhz divider 1/2/4 divider 1/2 analog mixer charge pump 0.5ma?2ma (0.5ma steps) pll loop filter fixed loop (lo1) dds 1000msps frequency tuning word dc ? 400mhz 2ghz 2ghz 150mhz AD9858 2ghz dds/dac clock 1000mhz f ref dc ? 150mhz 10 32 filter vco 03166-a - 040 f i g u re 37. dds sy n t hes i zer t r ans l at i o n l oop o s c i ll ato r (i mpl e m e nt ed i n t r a n s l at i o n l o op ev al uat i on bo ar d) dac filter phase/ frequency detector 150mhz divider 1/2/4 charge pump 0.5ma ? 2ma (0.5ma steps) loop filter dds 1000msps frequency tuning word dc ?400mhz vco dds/dac clock AD9858 f = mx f ref 03166-a - 041 f ref dc?150mhz 10 32 divider f i gure 38. dds s y n t hes i zer s i ng le -l o o p pll u p - c on ve rs i o n dac filter phase/ frequency detector 150mhz dds 1000msps divider 1/2/4 divider 1/2 charge pump 0.5ma?2ma (0.5ma steps) loop filter 150mhz reference frequency tuning word 150mhz 1000 mhz vco 2ghz max AD9858 32 03166-a - 042 f i gur e 3 9 . dds s y nthe si z e r ad9 858 a s f r acti onal n s y nthe si zer (i mp le mente d in f r a c tio n a l d i v i de ev aluati on b o ard) AD9858 rev. a | page 30 of 32 evaluation boards the AD9858 has three different ev aluation board designs. the first design is the traditional dds evaluation board. in this design, the dds is clocked and the output is taken directly from the dac. the analog mixer and pll blocks are made available for separate evaluation. the second design is a fractional-divide loop. this evaluation board was designed to incorporate the dds, the phase-detector, and the charge pump. in this application, the dds is used in a pll loop. unlike a fixed divider used in traditional pll loops, the output signal is divided and fed back to the phase detector by the dds. to do this, the output signal of the pll loop is fed to the dds as refclk. the dds is programmed to match the reference input frequency. because the dds output frequency can take on 2 32 potential values between 0 hz and one half of the pll loop output frequency, this enables frequency resolution on the order of 470 mhz, assuming a pll loop output frequency of 2 ghz. the third design is a translation loop or offset loop. in this design, the rf mixer is incorporated into the feedback path of the loop. this allows direct up-conversion to the transmission frequency. the three evaluation boards have separate schematics, boms, and instructions. see www.analog.com/dds for more information. table 13. part number description AD9858pcb AD9858 frequency synthesizer board AD9858fdpcb AD9858 fractional-divide loop frequency synthesizer board AD9858tlpcb AD9858 translation loop frequency synthesizer board AD9858 rev. a | page 31 of 32 outline dimensions 0.27 0.22 0.17 1 25 26 49 76 100 75 50 14.00 sq 16.00 sq 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max top view (pins down) 0.20 0.09 7 3.5 0 9.50 sq coplanarit y 0.08 1 25 26 49 76 100 75 50 bottom view compliant to jedec standards ms-026-aed-hd f i g u re 40. 1 00-l e a d thin p l as t i c q u ad f l at p a ckag e , e x po s e d p a d [ t qfp /e p ] (sv - 10 0) di me nsio ns sho w n i n mi ll im e t e r s warning ep ad (th e r m al s l ug) m u s t be a t tac h ed t o g r o u nd p l an e f o r s o m e o t h e r la rg e m e tal mas s f o r ther mal tra n sf er . f a il ur e t o do s o ma y ca u s e exces s i v e die t e m p er a t ur e r i s e a n d da ma g e t o t h e de vice. ordering guide models temperature r a nge package descri ption package option AD9858bsv C40c to +85c 100-lead epad sv-100 AD9858pcb 25c generic evaluati on board AD9858fdpcb 25c fractional-divide evaluation board a d 9 8 5 8 t l p c b 2 5 c translation lo op evaluation board AD9858 rev. a | page 32 of 32 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03166C0 C 11/03(a) |
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