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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers description the 38B4 group is the 8-bit microcomputer based on the 740 family core technology. the 38B4 group has six 8-bit timers, a 16-bit timer, a fluorescent display automatic display circuit, 12-channel 10-bit a-d converter, a serial i/o with automatic transfer function, which are available for controlling musical instruments and household appliances. features ? basic machine-language instructions ....................................... 71 ? minimum instruction execution time ................................. 0.48 s (at 4.2 mhz oscillation frequency) ? memory size rom ............................................. 48k to 60k bytes ram .......................................... 1024 to 2048 bytes ? programmable input/output ports ............................................. 51 ? high-breakdown-voltage output ports ...................................... 36 ? software pull-up resistors (ports p5, p6 1 to p6 5 , p7, p8 4 to p8 7 , p9) ? interrupts .................................................. 21 sources, 16 vectors ? timers ........................................................... 8-bit 5 6, 16-bit 5 1 ? serial i/o1 (clock-synchronized) ................................... 8-bit 5 1 ...................... (max. 256-byte automatic transfer function) ? serial i/o2 (uart or clock-synchronized) .................... 8-bit 5 1 ? pwm ............................................................................ 14-bit 5 1 8-bit 5 1 (also functions as timer 6) ? a-d converter .............................................. 10-bit 5 12 channels ? fluorescent display function ......................... total 40 control pins ? interrupt interval determination function ..................................... 1 ? watchdog timer ............................................................ 20-bit 5 1 fig. 1 pin configuration of m38B4xmxh-xxxxfp package type : 80p6n-a 80-pin plastic-molded qfp pin configuration (top view) ? buzzer output ............................................................................. 1 ? clock generating circuit ...................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) ? power source voltage in high-speed mode ................................................... 4.0 to 5.5 v (at 4.2 mhz oscillation frequency) 2.7 to 5.5 v (at 2.0 mhz oscillation frequency) in middle-speed mode ................................................ 2.7 to 5.5 v (at 4.2 mhz oscillation frequency) in low-speed mode ..................................................... 2.7 to 5.5 v (at 32 khz oscillation frequency) ? power dissipation in high-speed mode .......................................................... 35 mw (at 4.2 mhz oscillation frequency) in low-speed mode ............................................................. 60 w (at 32 khz oscillation frequency, at 3 v power source voltage) in stop mode ......................................................................... 1 a (at clock stop) ? operating temperature range ................................... C20 to 85 c application musical instruments, vcr, household appliances, etc. 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p 2 0 / b u z 0 2 / f l d 0 p 2 1 / f l d 1 p 2 2 / f l d 2 p 2 3 / f l d 3 p 2 4 / f l d 4 p 2 5 / f l d 5 p 2 6 / f l d 6 p 2 7 / f l d 7 p 0 0 / f l d 8 p 0 3 / f l d 1 1 p 0 4 / f l d 1 2 p 0 5 / f l d 1 3 p 0 6 / f l d 1 4 p 0 7 / f l d 1 5 p 1 1 / f l d 1 7 p 1 2 / f l d 1 8 p 1 3 / f l d 1 9 p 1 4 / f l d 2 0 p 1 5 / f l d 2 1 p 1 6 / f l d 2 2 p 1 7 / f l d 2 3 p 7 1 / a n 1 p 7 0 / a n 0 p 6 5 / s s t b 1 / a n 1 1 p 6 4 / i n t 4 / s b u s y 1 / a n 1 0 m 3 8 b 4 x m x h - x x x x f p p 6 0 / c n t r 1 p 6 3 / a n 9 p 6 2 / s r d y 1 / a n 8 r e s e t p 9 1 / x c o u t p 9 0 / x c i n p 4 4 / p w m 1 p 4 3 / b u z 0 1 p 4 2 / i n t 3 p 4 1 / i n t 1 p 4 0 / i n t 0 v e e p 7 5 / a n 5 p 7 6 / a n 6 p 7 7 / a n 7 v r e f a v s s p 5 0 / s i n 1 p 5 1 / s o u t 1 p 5 2 / s c l k 1 1 p 5 3 / s c l k 1 2 p 5 4 / r x d p 5 5 / t x d p 5 6 / s c l k 2 1 p 5 7 / s r d y 2 / s c l k 2 2 p 8 7 / p w m 0 / f l d 3 9 p 8 6 / r t p 1 / f l d 3 8 p 8 3 / f l d 3 5 p 8 2 / f l d 3 4 p 8 1 / f l d 3 3 p 8 0 / f l d 3 2 p 3 7 / f l d 3 1 p 3 6 / f l d 3 0 p 3 5 / f l d 2 9 p 3 4 / f l d 2 8 p 3 3 / f l d 2 7 p 3 2 / f l d 2 6 p 3 1 / f l d 2 5 p 3 0 / f l d 2 4 p 8 5 / r t p 0 / f l d 3 7 p 6 1 / c n t r 0 / c n t r 2 p 4 5 / t 1 o u t x i n x o u t v c c p 4 6 / t 3 o u t v s s p 1 0 / f l d 1 6 p 0 1 / f l d 9 p 0 2 / f l d 1 0 p 4 7 / i n t 2 p 8 4 / f l d 3 6 p 7 4 / a n 4 p 7 3 / a n 3 p 7 2 / a n 2 ( n o t e ) ( n o t e ) n o t e : i n t h e m a s k o p t i o n t y p e p , i n t 3 a n d c n t r 1 c a n n o t b e u s e d .
2 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 2 functional block diagram functional block diagram (package : 80p6n-a) functional block p o r t p 0 ( 8 ) 8 p o r t p 1 ( 8 ) 8 p o r t p 2 ( 8 ) 8 p o r t p 3 ( 8 ) 8 p o r t p 4 ( 8 ) 7 p o r t p 5 ( 8 ) 8 p o r t p 6 ( 6 ) 6 p o r t p 7 ( 8 ) 8 p o r t p 8 ( 8 ) 8 p o r t p 9 ( 2 ) 2 s y s t e m c l o c k g e n e r a t i o n x i n - x o u t ( m a i n - c l o c k ) x c i n - x c o u t ( s u b - c l o c k ) t i m e r s t i m e r x ( 1 6 - b i t ) t i m e r 1 ( 8 - b i t ) t i m e r 2 ( 8 - b i t ) t i m e r 3 ( 8 - b i t ) t i m e r 4 ( 8 - b i t ) t i m e r 5 ( 8 - b i t ) t i m e r 6 ( 8 - b i t ) a - d c o n v e r t e r ( 1 0 - b i t 5 1 2 c h a n n e l ) c p u c o r e w a t c h d o g t i m e r r o m r a m b u i l d - i n p e r i p h e r a l f u n c t i o n s m e m o r y i / o p o r t s p w m 0 ( 1 4 - b i t ) p w m 1 ( 8 - b i t ) s e r i a l i / o s e r i a l i / o 1 ( c l o c k - s y n c h r o n i z e d ) ( 2 5 6 b y t e a u t o m a t i c t r a n s f e r ) s e r i a l i / o 2 ( c l o c k - s y n c h r o n i z e d o r u a r t ) f l d d i s p l a y f u n c t i o n 4 0 c o n t r o l p i n s ( 3 6 h i g h - b r e a k d o w n v o l t a g e p o r t s ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n f u n c t i o n 1 b u z z e r o u t p u t
3 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pin description table 1 pin description (1) pin name function v cc , v ss power source apply voltage of 4.0e5.5 v to v cc , and 0 v to v ss . v ee pull-down apply voltage supplied to pull-down resistors of ports p0, p1, and p3. power source v ref reference reference voltage input pin for a-d converter. voltage av ss analog power analog power source input pin for a-d converter. source connect to v ss . reset reset input reset input pin for active l. x in clock input input and output pins for the main clock generating circuit. feedback resistor is built in between x in pin and x out pin. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. the clock is used as the oscillating source of system clock. p0 0 /fld 8 e i/o port p0 8-bit i/o port. fld automatic display p0 7 /fld 15 i/o direction register allows each pin to be individually programmed as either pins input or output. at reset, this port is set to input mode. a pull-down resistor is built in between port p0 and the v ee pin. cmos compatible input level. high-breakdown-voltage p-channel open-drain output structure. at reset, this port is set to v ee level. p1 0 /fld 16 e output port p1 8-bit output port. fld automatic display p1 7 /fld 23 a pull-down resistor is built in between port p1 and the v ee pin. pins high-breakdown-voltage p-channel open-drain output structure. at reset, this port is set to v ee level. p2 0 /b uz02 / i/o port p2 8-bit i/o port with the same function as port p0. fld automatic display fld 0 e low-voltage input level. pins p2 7 /fld 7 high-breakdown-voltage p-channel open-drain output structure. buzzer output pin (p2 0 ) p3 0 /fld 24 e output port p3 8-bit output port. fld automatic display p3 7 /fld 31 a pull-down resistor is built in between port p3 and the v ee pin. pins high-breakdown-voltage p-channel open-drain output structure. at reset, this port is set to v ee level. p4 0 /int 0 , i/o port p4 7-bit i/o port with the same function as port p0. interrupt input pins p4 1 /int 1 , cmos compatible input level in the mask option type p, p4 2 /int 3 n-channel open-drain output structure. int 3 cannot be used. p4 3 /b uz01 buzzer output pin p4 4 /pwm 1 pwm output pin (timer output pin) p4 5 /t 1out , timer output pin p4 6 /t 3out p4 7 /int 2 input port p4 1-bit input port. interrupt input pin cmos compatible input level. function except a port function x out clock output
4 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 2 pin description (2) function except a port function pin name function p5 0 /s in1 , i/o port p5 ? 8-bit cmos i/o port with the same function as port p0. ? serial i/o1 function pins p5 1 /s out1 , ? cmos compatible input level. p5 2 /s clk11 , ? cmos 3-state output structure. p5 3 /s clk12 p5 4 /r x d, ? serial i/o2 function pins p5 5 /t x d, p5 6 /s clk21 , p5 7 /s rdy2 / s clk22 p6 0 /cntr 1 i/o port p6 ? 1-bit i/o port with the same function as port p0. ? timer input pin ? cmos compatible input level. in the mask option type p, ? n-channel open-drain output structure. cntr 1 cannot be used. p6 1 /cntr 0 / ? 5-bit cmos i/o port with the same function as port p0. ? timer i/o pin cntr 2 ? cmos compatible input level. p6 2 /s rdy1 / ? cmos 3-state output structure. ? serial i/o1 function pin an 8 ? a-d conversion input pin p6 3 /an 9 ? a-d conversion input pin ? dimmer signal output pin p6 4 /int 4 / ? serial i/o1 function pin s busy1 /an 10 , ? a-d conversion input pin p6 5 /s stb1 / ? interrupt input pin (p6 4 ) an 11 p7 0 /an 0 C i/o port p7 ? 8-bit cmos i/o port with the same function as port p0. ? a-d conversion input pin p7 7 /an 7 ? cmos compatible input level. ? cmos 3-state output structure. p8 0 /fld 32 C i/o port p8 ? 4-bit i/o port with the same function as port p0. ? fld automatic display pins p8 3 /fld 35 ? low-voltage input level. ? high-breakdown-voltage p-channel open-drain output structure. p8 4 /fld 36 ? 4-bit cmos i/o port with the same function as port p0. p8 5 /rtp 0 / ? low-voltage input level. ? fld automatic display pins fld 37, ? cmos 3-state output structure ? real time port output p8 6 /rtp 1 / fld 38 p8 7 /pwm 0 / ? fld automatic display pins fld 39 ? 14-bit pwm output p9 0 /x cin , i/o port p9 ? 2-bit cmos i/o port with the same function as port p0. ? i/o pins for sub-clock generating p9 1 /x cout ? cmos compatible input level. circuit (connect a ceramic resona- ? cmos 3-state output structure. tor or a quarts-crystal oscillator)
5 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers part numbering fig. 3 part numbering m 3 8 b 4 9 m f h - x x x x f p p r o d u c t p a c k a g e t y p e f p : 8 0 p 6 n - a p a c k a g e r o m n u m b e r r o m s i z e 1 2 3 4 5 6 7 8 9 a b c d e f : 4 0 9 6 b y t e s : 8 1 9 2 b y t e s : 1 2 2 8 8 b y t e s : 1 6 3 8 4 b y t e s : 2 0 4 8 0 b y t e s : 2 4 5 7 6 b y t e s : 2 8 6 7 2 b y t e s : 3 2 7 6 8 b y t e s : 3 6 8 6 4 b y t e s : 4 0 9 6 0 b y t e s : 4 5 0 5 6 b y t e s : 4 9 1 5 2 b y t e s : 5 3 2 4 8 b y t e s : 5 7 3 4 4 b y t e s : 6 1 4 4 0 b y t e s t h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f r o m a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d f o r u s e r s . m e m o r y t y p e m e : m a s k r o m v e r s i o n : e p r o m o r o n e t i m e p r o m v e r s i o n r a m s i z e 0 1 2 3 4 5 6 7 8 9 : 1 9 2 b y t e s : 2 5 6 b y t e s : 3 8 4 b y t e s : 5 1 2 b y t e s : 6 4 0 b y t e s : 7 6 8 b y t e s : 8 9 6 b y t e s : 1 0 2 4 b y t e s : 1 5 3 6 b y t e s : 2 0 4 8 b y t e s h i g h - b r e a k d o w n v o l t a g e p u l l - d o w n o p t i o n r e g a r d i n g o p t i o n c o n t e n t s , r e f e r t o s e c t i o n m a s k o p t i o n o f p u l l - d o w n r e s i s t o r .
6 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers group expansion mitsubishi plans to expand the 38B4 group as follows: memory type support for mask rom version. memory size mask rom size ..................................................... 48k to 60k bytes ram size ............................................................ 1024 to 2048 bytes package 80p6n-a ..................................... 0.8 mm-pitch plastic molded qfp fig. 4 memory expansion plan currently supported products are listed below. table 3 list of supported products note : products under development or planning : the development schedule and specifications may be revised without notice. as of mar. 2000 product m38B49mfh-xxxxfp m38B47mch-xxxxfp rom size (bytes) rom size for user ( ) 61440 (61310) 49152 (49022) ram size (bytes) 2048 1024 package 80p6n-a 80p6n-a remarks mask rom version mask rom version 6 0 k 5 6 k 5 2 k 4 8 k 4 4 k 3 6 k 3 2 k 2 8 k 2 4 k 2 0 k 1 6 k 1 2 k 8 k 4 k 4 0 k r o m s i z e ( b y t e s ) 2 5 65 1 27 6 81 , 0 2 41 , 5 3 62 , 0 4 8 r a m s i z e ( b y t e s ) u n d e r d e v e l o p m e n t m 3 8 b 4 9 m f h u n d e r d e v e l o p m e n t m 3 8 b 4 7 mc
7 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional description central processing unit (cpu) the 38B4 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1, the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 6. store registers other than those described in figure 6 with pro- gram when the user needs them during interrupts or subroutine calls (see table 4). [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
8 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
9 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1. bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1. bit 5: index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag z flag i flag d flag b flag t flag v flag n flag sec clc _ _ sei cli sed cld _ _ set clt clv _ _ _
10 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit etc. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 s t a c k p a g e s e l e c t i o n b i t 0 : p a g e 0 1 : p a g e 1 n o t a v a i l a b l e p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n 1 : x c i n x c o u t o s c i l l a t i n g f u n c t i o n m a i n c l o c k ( x i n x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t 0 : f ( x i n ) ( h i g h - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( m i d d l e - s p e e d m o d e ) i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t 0 : x i n - x o u t s e l e c t i o n ( m i d d l e - / h i g h - s p e e d m o d e ) 1 : x c i n - x c o u t s e l e c t i o n ( l o w - s p e e d m o d e )
11 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers memory special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing, and the other areas are user areas for storing pro- grams. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 0 1 0 0 1 6 0 0 0 0 1 6 0 0 4 0 1 6 0 4 4 0 1 6 f f 0 0 1 6 f f d c 1 6 f f f e 1 6 f f f f 1 6 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 1 5 3 6 2 0 4 8 x x x x 1 6 0 0 f f 1 6 0 1 3 f 1 6 0 1 b f 1 6 0 2 3 f 1 6 0 2 b f 1 6 0 3 3 f 1 6 0 3 b f 1 6 0 4 3 f 1 6 0 6 3 f 1 6 0 8 3 f 1 6 4 0 9 6 8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0 f 0 0 0 1 6 e 0 0 0 1 6 d 0 0 0 1 6 c 0 0 0 1 6 b 0 0 0 1 6 a 0 0 0 1 6 9 0 0 0 1 6 8 0 0 0 1 6 7 0 0 0 1 6 6 0 0 0 1 6 5 0 0 0 1 6 4 0 0 0 1 6 3 0 0 0 1 6 2 0 0 0 1 6 1 0 0 0 1 6 f 0 8 0 1 6 e 0 8 0 1 6 d 0 8 0 1 6 c 0 8 0 1 6 b 0 8 0 1 6 a 0 8 0 1 6 9 0 8 0 1 6 8 0 8 0 1 6 7 0 8 0 1 6 6 0 8 0 1 6 5 0 8 0 1 6 4 0 8 0 1 6 3 0 8 0 1 6 2 0 8 0 1 6 1 0 8 0 1 6 y y y y 1 6 z z z z 1 6 r a m r o m 0 e f 0 1 6 0 f 0 0 1 6 0 e f f 1 6 0 f f f 1 6 r e s e r v e d a r e a s f r a r e a 1 n o t u s e d ( n o t e ) i n t e r r u p t v e c t o r a r e a r o m a r e a r e s e r v e d r o m a r e a ( c o m m o n r o m a r e a , 1 2 8 b y t e ) z e r o p a g e s p e c i a l p a g e r a m a r e a r a m s i z e ( b y t e ) a d d r e s s x x x x 1 6 r o m s i z e ( b y t e ) a d d r e s s y y y y 1 6 r e s e r v e d r o m a r e a a d d r e s s z z z z 1 6 s f r a r e a 2 r a m a r e a f o r s e r i a l i / o a u t o m a t i c t r a n s f e r r a m a r e a f o r f l d a u t o m a t i c d i s p l a y n o t e : w h e n 1 0 2 4 b y t e s o r m o r e a r e u s e d a s r a m a r e a , t h i s a r e a c a n b e u s e d .
12 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 9 memory map of special function register (sfr) 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 s e r i a l i / o 2 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( t b / r b ) p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) p o r t p 8 ( p 8 ) p o r t p 8 d i r e c t i o n r e g i s t e r ( p 8 d ) p w m r e g i s t e r ( h i g h - o r d e r ) ( p w m h ) p w m r e g i s t e r ( l o w - o r d e r ) ( p w m l ) b a u d r a t e g e n e r a t o r ( b r g ) u a r t c o n t r o l r e g i s t e r ( u a r t c o n ) s e r i a l i / o 1 a u t o m a t i c t r a n s f e r d a t a p o i n t e r ( s i o 1 d p ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 1 ( s i o 1 c o n 1 ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 2 ( s i o 1 c o n 2 ) s e r i a l i / o 1 r e g i s t e r / t r a n s f e r c o u n t e r ( s i o 1 ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 ( s i o 1 c o n 3 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n ) s e r i a l i / o 2 s t a t u s r e g i s t e r ( s i o 2 s t s ) p o r t p 9 ( p 9 ) p o r t p 9 d i r e c t i o n r e g i s t e r ( p 9 d ) 0 e f 0 1 6 0 e f 1 1 6 0 e f 2 1 6 0 e f 3 1 6 0 e f 4 1 6 0 e f 5 1 6 0 e f 6 1 6 0 e f 7 1 6 t o f f 2 t i m e s e t r e g i s t e r ( t o f f 2 ) p u l l - u p c o n t r o l r e g i s t e r 1 ( p u l l 1 ) p u l l - u p c o n t r o l r e g i s t e r 2 ( p u l l 2 ) f l d c m o d e r e g i s t e r ( f l d m ) t d i s p t i m e s e t r e g i s t e r ( t d i s p ) t o f f 1 t i m e s e t r e g i s t e r ( t o f f 1 ) 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 t i m e r x m o d e r e g i s t e r 1 ( t x m 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r 5 ( t 5 ) t i m e r 6 ( t 6 ) p w m c o n t r o l r e g i s t e r ( p w m c o n ) t i m e r 6 p w m r e g i s t e r ( t 6 p w m ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) t i m e r 5 6 m o d e r e g i s t e r ( t 5 6 m ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n ) t i m e r x ( l o w - o r d e r ) ( t x l ) t i m e r x ( h i g h - o r d e r ) ( t x h ) t i m e r x m o d e r e g i s t e r 2 ( t x m 2 ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r ( i i d ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c o n t r o l r e g i s t e r ( i i d c o n ) a - d c o n t r o l r e g i s t e r ( a d c o n ) a - d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( a d l ) a - d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( a d h ) i n t e r r u p t s o u r c e s w i t c h r e g i s t e r ( i f r ) i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( i n t e d g e ) c p u m o d e r e g i s t e r ( c p u m ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) 0 e f 8 1 6 0 e f 9 1 6 0 e f a 1 6 0 e f b 1 6 0 e f c 1 6 0 e f d 1 6 0 e f e 1 6 0 e f f 1 6 f l d d a t a p o i n t e r ( f l d d p ) p o r t p 0 f l d / p o r t s w i t c h r e g i s t e r ( p 0 f p r ) p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r ( p 2 f p r ) p o r t p 8 f l d / p o r t s w i t c h r e g i s t e r ( p 8 f p r ) p o r t p 8 f l d o u t p u t c o n t r o l r e g i s t e r ( p 8 f l d c o n ) b u z z e r o u t p u t c o n t r o l r e g i s t e r ( b u z c o n )
13 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers i/o ports [direction registers] pid the 38B4 group has 51 programmable i/o pins arranged in eight individual i/o ports (p0, p2, p4 0 ep4 6 , and p5ep9). the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin becomes an input pin. when 1 is written to that pin, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input (the bit corresponding to that pin must be set to 0) are floating and the value of that pin can be read. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. [high-breakdown-voltage output ports] the 38B4 group has 5 ports with high-breakdown-voltage pins (ports p0ep3 and p8 0 ep8 3 ). the high-breakdown-voltage ports have p- channel open-drain output with vcc- 45 v of breakdown voltage. each pin in ports p0, p1, and p3 has an internal pull-down resistor con- nected to v ee . at reset, the p-channel output transistor of each port latch is turned off, so that it goes to v ee level (l) by the pull-down resistor. writing 1 (weak drivability) to bit 7 of the fldc mode register (ad- dress 0ef4 16 ) shows the rising transition of the output transistors for reducing transient noise. at reset, bit 7 of the fldc mode register is set to 0 (strong drivability). [pull-up control register] pull ports p5, p6 1 ep6 5 , p7, p8 4 ep8 7 and p9 have built-in programmable pull-up resistors. the pull-up resistors are valid only in the case that the each control bit is set to 1 and the corresponding port direction registers are set to input mode. fig. 10 structure of pull-up control registers (pull1 and pull2) 0 : n o p u l l - u p 1 : p u l l - u p p u l l - u p c o n t r o l r e g i s t e r 2 ( p u l l 2 : a d d r e s s 0 e f 1 1 6 ) p 7 0 , p 7 1 p u l l - u p c o n t r o l b i t p 7 2 , p 7 3 p u l l - u p c o n t r o l b i t p 7 4 , p 7 5 p u l l - u p c o n t r o l b i t p 7 6 , p 7 7 p u l l - u p c o n t r o l b i t p 8 4 , p 8 5 p u l l - u p c o n t r o l b i t p 8 6 , p 8 7 p u l l - u p c o n t r o l b i t p 9 0 , p 9 1 p u l l - u p c o n t r o l b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) b 7 b 0 0 : n o p u l l - u p 1 : p u l l - u p p u l l - u p c o n t r o l r e g i s t e r 1 ( p u l l 1 : a d d r e s s 0 e f 0 1 6 ) p 5 0 , p 5 1 p u l l - u p c o n t r o l b i t p 5 2 , p 5 3 p u l l - u p c o n t r o l b i t p 5 4 , p 5 5 p u l l - u p c o n t r o l b i t p 5 6 , p 5 7 p u l l - u p c o n t r o l b i t p 6 1 p u l l - u p c o n t r o l b i t p 6 2 , p 6 3 p u l l - u p c o n t r o l b i t p 6 4 , p 6 5 p u l l - u p c o n t r o l b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) b 7 b 0
14 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 6 list of i/o port functions (1) zpin name input/output i/o format non-port function related sfrs ref.no. p0 0 /fld 8 e port p0 input/output, cmos compatible input level fld automatic display function fldc mode register (1) p0 7 /fld 15 individual bits high-breakdown voltage p- port p0fld/port switch register channel open-drain output with pull-down resistor p1 0 /fld 16 e port p1 output high-breakdown voltage p- fldc mode register (2) p1 7 /fld 23 channel open-drain output with pull-down resistor p2 0 /b uz02 / port p2 input/output, low-voltage input level buzzer output (p2 0 ) fldc mode register (3) fld 0 individual bits high-breakdown voltage p- fld automatic display function port p2fld/port switch register p2 1 /fld 1 e channel open-drain output fld automatic display function buzzer output control register (1) p2 7 /fld 7 p3 0 /fld 24 e port p3 output high-breakdown voltage p- fldc mode register (2) p3 7 /fld 31 channel open-drain output with pull-down resistor p4 0 /int 0 , port p4 input/output, cmos compatible input level external interrupt input interrupt edge selection register (5) p4 1 /int 1 individual bits n-channel open-drain output in the mask option type p, int 3 p4 2 /int 3 cannot be used. p4 3 /b uz01 buzzer output buzzer output control register (4) p4 4 /pwm 1 pwm output timer 56 mode register (6) p4 5 /t 1out timer output timer 12 mode register (8-1) p4 6 /t 3out timer output timer 34 mode register (8-2) p4 7 /int 2 input cmos compatible input level external interrput input i nterrupt edge selection register (9) interrupt interval determination control register p5 0 /s in1 port p5 input/output, cmos compatible input level serial i/o1 function i/o serial i/o1 control register 1, 2 (10) p5 1 /s out1 , individual bits cmos 3-state output (11) p5 2 /s clk11 , p5 3 /s clk12 p5 4 /r x d serial i/o2 function i/o serial i/o2 control register (10) p5 5 /t x d, uart control register (11) p5 6 /s clk21 p5 7 /s rdy2 / (12) s clk22 p6 0 /cntr 1 port p6 cmos compatible input level external count input interrupt edge selection register (7-1) n-channel open-drain output in the mask option type p, (7-2) p6 1 /cntr 0 / cmos compatible input level cntr 1 cannot be used. (13) cntr 2 cmos 3-state output p6 2 /s rdy1 / serial i/o1 function i/o serial i/o1 control register 1, 2 (14) an 8 a-d conversion input a-d control register p6 3 /an 9 a-d conversion input a-d control register (15) dimmer signal output p8fld output control bit p6 4 /int 4 / serial i/o1 function i/o serial i/o1 control register 1, 2 (16) s busy1 / an 10 a-d conversion input a-d control register external interrupt input interrupt edge selection register p6 5 /s stb1 / serial i/o1 function i/o serial i/o1 control register 1, 2 (17) an 11 a-d conversion input a-d control register p7 0 /an 0 e port p7 a-d conversion input a-d control register (15) p7 7 /an 7 (7- 1) (7-2)
15 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers table 7 list of i/o port functions (2) pin name input/output i/o format non-port function related sfrs ref.no. p8 0 /fld 32 e port p8 input/output, low-voltage input level fld automatic display function fldc mode register (1) p8 3 /fld 35 individual bits high-breakdown voltage p- port p8fld/port switch register channel open-drain output p8 4 /fld 36 low-voltage input level (18) p8 5 /rtp 0 / cmos 3-state output fld automatic display function fldc mode register (19) fld 37 , real time port output port p8fld/port switch register p8 6 /rtp 1 / timer x mode register 2 fld 38 p8 7 /pwm 0 / fld automatic display function fldc mode register (20) fld 39 pwm output port p8fld/port switch register pwm control register p9 0 /x cin port p9 cmos compatible input level sub-clock generating circuit i/o cpu mode register (21) p9 1 /x cout cmos 3-state output (22) notes 1 : make sure that the input level at each pin is either 0 v or vcc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from vcc to vss through the input-stage gate. 2 : how to use double-function ports as function i/o ports, refer to the applicable sections.
16 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 11 port block diagram (1) ( 2 ) p o r t s p 1 , p 3 ( 3 ) p o r t p 2 0 ( 4 ) p o r t p 4 3 ( 6 ) p o r t p 4 4 * h i g h - b r e a k d o w n - v o l t a g e p - c h a n n e l t r a n s i s t o r # m i d d l e - b r e a k d o w n - v o l t a g e n - c h a n n e l t r a n s i s t o r n o t e s 1 : t h e d i m m e r s i g n a l s e t s t h e t o f f t i m i n g . 2 : a p u l l - d o w n r e s i s t o r i s n o t b u i l t i n t o p o r t s p 2 a n d p 8 . v e e * d i m m e r s i g n a l ( n o t e 1 ) * r e a d b u z z e r c o n t r o l s i g n a l b u z z e r s i g n a l o u t p u t ( 1 ) p o r t s p 0 , p 2 1 p 2 7 , p 8 0 p 8 3 d a t a b u s l o c a l d a t a b u s p o r t l a t c h d i m m e r s i g n a l ( n o t e 1 ) * f l d / p o r t s w i t c h r e g i s t e r d i r e c t i o n r e g i s t e r r e a d v e e ( n o t e 2 ) v e e f l d / p o r t s w i t c h r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s l o c a l d a t a b u s ( n o t e 2 ) d a t a b u s l o c a l d a t a b u s p o r t l a t c h d i m m e r s i g n a l ( n o t e 1 ) ( 5 ) p o r t s p 4 0 , p 4 1 b u z z e r c o n t r o l s i g n a l b u z z e r s i g n a l o u t p u t d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h r e a d # i n t 0 , i n t 1 i n t e r r u p t i n p u t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s t i m e r 6 o u t p u t s e l e c t i o n b i t d a t a b u s r e a d # d i r e c t i o n r e g i s t e r p o r t l a t c h t i m e r 6 o u t p u t
17 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 12 port block diagram (2) ( 1 0 ) p o r t s p 5 0 , p 5 4 s e r i a l i / o i n p u t p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r ( 9 ) p o r t p 4 7 i n t 2 i n t e r r u p t i n p u t d a t a b u s # m i d d l e - b r e a k d o w n - v o l t a g e n - c h a n n e l t r a n s i s t o r ( 7 - 1 ) p o r t s p 4 2 , p 6 0 # r e a d # t i m e r 1 o u t p u t b i t t i m e r 3 o u t p u t b i t # r e a d # i n t 3 i n t e r r u p t i n p u t c n t r 1 i n p u t d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s ( 7 - 2 ) p o r t s p 4 2 , p 6 0 ( m a s k o p t i o n t y p e p ) d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s ( 8 - 1 ) p o r t s p 4 5 , p 4 6 t i m e r 1 o u t p u t t i m e r 3 o u t p u t t i m e r 1 o u t p u t b i t t i m e r 3 o u t p u t b i t t i m e r 1 o u t p u t t i m e r 3 o u t p u t ( 8 - 2 ) p o r t s p 4 5 , p 4 6 ( m a s k o p t i o n t y p e p )
18 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 13 port block diagram (3) s e r i a l r e a d y o u t p u t ( 1 4 ) p o r t p 6 2 ( 1 3 ) p o r t p 6 1 ( 1 1 ) p o r t s p 5 1 p 5 3 , p 5 5 , p 5 6 s e r i a l c l o c k i n p u t s e r i a l i / o 2 m o d e s e l e c t i o n b i t o u t p u t o f f c o n t r o l s i g n a l t x d , s o u t o r s c l k p 5 2 , p 5 3 , p 5 6 p - c h a n n e l o u t p u t d i s a b l e s i g n a l ( p 5 1 , p 5 5 ) t i m e r x o u t p u t t i m e r x o p e r a t i n g m o d e b i t c n t r 0 , c n t r 2 i n p u t t i m e r 2 , t i m e r x e x t e r n a l c l o c k i n p u t ( 1 2 ) p o r t p 5 7 s r d y 2 o u t p u t e n a b l e b i t s e r i a l c l o c k i n p u t p 6 2 / s r d y 1 p 6 4 / s b u s y 1 p i n c o n t r o l b i t s e r i a l r e a d y o u t p u t a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t s e r i a l r e a d y i n p u t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r ( 1 6 ) p o r t p 6 4 d a t a b u s s b u s y 1 o u t p u t i n t 4 i n t e r r u p t i n p u t , s b u s y 1 i n p u t a - d c o n v e r s i o n i n p u t p 6 2 / s r d y 1 p 6 4 / s b u s y 1 p i n c o n t r o l b i t p u l l - u p c o n t r o l p o r t l a t c h d i r e c t i o n r e g i s t e r a n a l o g i n p u t p i n s e l e c t i o n b i t ( 1 5 ) p o r t s p 6 3 , p 7 p u l l - u p c o n t r o l d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r a - d c o n v e r s i o n i n p u t a n a l o g i n p u t p i n s e l e c t i o n b i t d i m m e r o u t p u t c o n t r o l b i t ( p 6 3 ) d i m m e r s i g n a l o u t p u t ( p 6 3 )
19 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 14 port block diagram (4) ( 1 9 ) p o r t s p 8 5 , p 8 6 ( 2 0 ) p o r t p 8 7 ( 2 1 ) p o r t p 9 0 ( 2 2 ) p o r t p 9 1 p o r t p 9 0 o s c i l l a t o r p o r t x c s w i t c h b i t ( 1 8 ) p o r t p 8 4 ( 1 7 ) p o r t p 6 5 s u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t p o r t x c s w i t c h b i t p 8 7 / p w m o u t p u t e n a b l e b i t p w m 0 o u t p u t r t p o u t p u t r e a l t i m e p o r t c o n t r o l b i t s s t b 1 o u t p u t p u l l - u p c o n t r o l p 6 5 / s s t b 1 p i n c o n t r o l b i t d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r a - d c o n v e r s i o n i n p u t p u l l - u p c o n t r o l p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s l o c a l d a t a b u s d i m m e r s i g n a l ( n o t e ) f l d / p o r t s w i t c h r e g i s t e r p u l l - u p c o n t r o l p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s l o c a l d a t a b u s d i m m e r s i g n a l ( n o t e ) f l d / p o r t s w i t c h r e g i s t e r p u l l - u p c o n t r o l p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s l o c a l d a t a b u s d i m m e r s i g n a l ( n o t e ) f l d / p o r t s w i t c h r e g i s t e r p u l l - u p c o n t r o l p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s p o r t x c s w i t c h b i t p u l l - u p c o n t r o l p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s * h i g h - b r e a k d o w n - v o l t a g e p - c h a n n e l t r a n s i s t o r n o t e : t h e d i m m e r s i g n a l s e t s t h e t o f f t i m i n g .
20 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupts interrupts occur by twenty one sources: five external, fifteen internal, and one software. interrupt control each interrupt except the brk instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the interrupt disable flag is 0. interrupt enable bits can be set or cleared by software. inter- rupt request bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the contents of the program counter and processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. n notes on use when the active edge of an external interrupt (int 0 eint 4 ) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. therefore, please take following sequence: (1) disable the external interrupt which is selected. (2) change the active edge in interrupt edge selection register (3) clear the set interrupt request bit to 0. (4) enable the external interrupt which is selected.
21 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers vector addresses (note 1) interrupt request interrupt source priority remarks high low generating conditions reset (note 2) 1 fffd 16 fffc 16 at reset non-maskable int 0 2 fffb 16 fffa 16 at detection of either rising or falling edge of external interrupt int 0 input (active edge selectable) int 1 3 fff9 16 fff8 16 at detection of either rising or falling edge of external interrupt int 1 input (active edge selectable) int 2 4 fff7 16 fff6 16 at detection of either rising or falling edge of external interrupt int 2 input (active edge selectable) remote control/ at 8-bit counter overflow valid when interrupt interval counter overflow determination is operating serial i/o1 5 fff5 16 fff4 16 at completion of data transfer valid when serial i/o ordinary mode is selected serial i/o auto- at completion of the last data transfer valid when serial i/o automatic matic transfer transfer mode is selected timer x 6 fff3 16 fff2 16 at timer x underflow timer 1 7 fff1 16 fff0 16 at timer 1 underflow timer 2 8 ffef 16 ffee 16 at timer 2 underflow stp release timer underflow timer 3 9 ffed 16 ffec 16 at timer 3 underflow timer 4 10 ffeb 16 ffea 16 at timer 4 underflow (note 3) timer 5 11 ffe9 16 ffe8 16 at timer 5 underflow timer 6 12 ffe7 16 ffe6 16 at timer 6 underflow serial i/o2 receive 13 ffe5 16 ffe4 16 at completion of serial i/o2 data receive int 3 14 ffe3 16 ffe2 16 at detection of either rising or falling edge of external interrupt (note 4) int 3 input (active edge selectable) serial i/o2 transmit at completion of serial i/o2 data transmit int 4 15 ffe1 16 ffe0 16 at detection of either rising or falling edge of external interrupt int 4 input (active edge selectable) valid when int 4 interrupt is selected a-d conversion at completion of a-d conversion valid when a-d conversion is selected fld blanking 16 ffdf 16 ffde 16 at falling edge of the last timing immediately valid when fld blanking before blanking period starts interrupt is selected fld digit at rising edge of digit (each timing) valid when fld digit interrupt is selected brk instruction 17 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt table 8 interrupt vector addresses and priority notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. 3 : in the mask option type p, timer 4 interrupt whose count source is cntr 1 input cannot be used. 4 : in the mask option type p, int 3 interrupt cannot be used.
22 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 16 structure of interrupt related registers fig. 15 interrupt control i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g i b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t i n t 0 i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t i n t 2 i n t e r r u p t e n a b l e b i t r e m o t e c o n t r o l l e r / c o u n t e r o v e r f l o w i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o a u t o m a t i c t r a n s f e r i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t t i m e r 3 i n t e r r u p t e n a b l e b i t i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t r e m o t e c o n t r o l l e r / c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o a u t o m a t i c t r a n s f e r i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 3 i n t e r r u p t r e q u e s t b i t i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 3 i n t e r r u p t e d g e s e l e c t i o n b i t ( n o t e 1 ) i n t 4 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) c n t r 0 p i n e d g e s w i t c h b i t c n t r 1 p i n e d g e s w i t c h b i t ( n o t e 1 ) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t c o n t r o l r e g i s t e r 1 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d ( i r e q 1 : a d d r e s s 0 0 3 c 1 6 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d ( i c o n 2 : a d d r e s s 0 0 3 f 1 6 ) i n t e r r u p t s o u r c e s w i t c h r e g i s t e r i n t 3 / s e r i a l i / o 2 t r a n s m i t i n t e r r u p t s w i t c h b i t ( n o t e 1 ) 0 : i n t 3 i n t e r r u p t 1 : s e r i a l i / o 2 t r a n s m i t i n t e r r u p t i n t 4 / a d c o n v e r s i o n i n t e r r u p t s w i t c h b i t 0 : i n t 4 i n t e r r u p t 1 : a - d c o n v e r s i o n i n t e r r u p t n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h e s e b i t s . ) ( i f r : a d d r e s s 0 0 3 9 1 6 ) 0 : r i s i n g e d g e c o u n t 1 : f a l l i n g e d g e c o u n t i n t 3 / s e r i a l i / o 2 t r a n s m i t i n t e r r u p t e n a b l e b i t ( n o t e 3 ) i n t 4 i n t e r r u p t e n a b l e b i t a d c o n v e r s i o n i n t e r r u p t e n a b l e b i t f l d b l a n k i n g i n t e r r u p t e n a b l e b i t f l d d i g i t i n t e r r u p t e n a b l e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) i n t 3 / s e r i a l i / o 2 t r a n s m i t i n t e r r u p t r e q u e s t b i t ( n o t e 2 ) i n t 4 i n t e r r u p t r e q u e s t b i t a d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t f l d b l a n k i n g i n t e r r u p t r e q u e s t b i t f l d d i g i t i n t e r r u p t r e q u e s t b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) t i m e r 4 i n t e r r u p t r e q u e s t b i t ( n o t e 2 ) t i m e r 5 i n t e r r u p t r e q u e s t b i t t i m e r 6 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 r e c e i v e i n t e r r u p t r e q u e s t b i t t i m e r 4 i n t e r r u p t e n a b l e b i t ( n o t e 3 ) t i m e r 5 i n t e r r u p t e n a b l e b i t t i m e r 6 i n t e r r u p t e n a b l e b i t s e r i a l i / o 2 r e c e i v e i n t e r r u p t e n a b l e b i t n o t e s 1 : i n t h e m a s k o p t i o n t y p e p , t h e s e b i t s a r e n o t a v a i l a b l e b e c a u s e c n t r 1 f u n c t i o n a n d i n t 3 f u n c t i o n c a n n o t b e u s e d . 2 : i n t h e m a s k o p t i o n t y p e p , i f t i m e r 4 i n t e r r u p t w h o s e c o u n t s o u r c e i s c n t r 1 i n p u t a n d i n t 3 i n t e r r u p t a r e s e l e c t e d , t h e s e b i t s d o n o t b e c o m e 1 . 3 : i n t h e m a s k o p t i o n t y p e p , t i m e r 4 i n t e r r u p t w h o s e c o u n t s o u r c e i s c n t r 1 i n p u t a n d i n t 3 i n t e r r u p t a r e n o t a v a i l a b l e . b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0
23 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timers 8-bit timer the 38B4 group has six built-in timers : timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. each timer has the 8-bit timer latch. all timers are down-counters. when the timer reaches 00 16 , an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. the count can be stopped by setting the stop bit of each timer to 1. the internal system clock can be set to either the high-speed mode or low-speed mode with the cpu mode register. at the same time, timer internal count source is switched to either f(x in ) or f(x cin ). l timer 1, timer 2 the count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. a rectangular waveform of timer 1 under- flow signal divided by 2 can be output from the p4 5 /t 1out pin. the active edge of the external clock cntr 0 can be switched with the bit 6 of the interrupt edge selection register. at reset or when executing the stp instruction, all bits of the timer 12 mode register are cleared to 0, timer 1 is set to ff 16 , and timer 2 is set to 01 16 . l timer 3, timer 4 the count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. a rectangular waveform of timer 3 under- flow signal divided by 2 can be output from the p4 6 /t 3out pin. the active edge of the external clock cntr 1 (note) can be switched with the bit 7 of the interrupt edge selection register. note: in the mask option type p, cntr 1 function cannot be used. l timer 5, timer 6 the count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. a rectangular waveform of timer 6 under- flow signal divided by 2 can be output from the p4 4 /pwm 1 pin. (1) timer 6 pwm 1 mode timer 6 can output a pwm rectangular waveform with h duty cycle n/(n+m) from the p4 4 /pwm 1 pin by setting the timer 56 mode regis- ter (refer to figure 19). the n is the value set in timer 6 latch (address 0025 16 ) and m is the value in the timer 6 pwm register (address 0027 16 ). if n is 0, the pwm output is l, if m is 0, the pwm output is h (n = 0 is prior than m = 0). in the pwm mode, interrupts occur at the rising edge of the pwm output. fig. 17 structure of timer related register t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m : a d d r e s s 0 0 2 8 1 6 ) t i m e r 1 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 2 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : f ( x c i n ) 1 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : u n d e r f l o w o f t i m e r 1 0 1 : f ( x c i n ) 1 0 : e x t e r n a l c o u n t i n p u t c n t r 0 1 1 : n o t a v a i l a b l e t i m e r 1 o u t p u t s e l e c t i o n b i t ( p 4 5 ) 0 : i / o p o r t 1 : t i m e r 1 o u t p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m : a d d r e s s 0 0 2 9 1 6 ) t i m e r 3 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 4 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : u n d e r f l o w o f t i m e r 2 1 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 1 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : u n d e r f l o w o f t i m e r 3 1 0 : e x t e r n a l c o u n t i n p u t c n t r 1 ( n o t e ) 1 1 : n o t a v a i l a b l e t i m e r 3 o u t p u t s e l e c t i o n b i t ( p 4 6 ) 0 : i / o p o r t 1 : t i m e r 3 o u t p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) t i m e r 5 6 m o d e r e g i s t e r ( t 5 6 m : a d d r e s s 0 0 2 a 1 6 ) t i m e r 5 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 6 c o u n t s t o p b i t 0 : c o u n t o p e r a t i o n 1 : c o u n t s t o p t i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 1 : u n d e r f l o w o f t i m e r 4 t i m e r 6 o p e r a t i o n m o d e s e l e c t i o n b i t 0 : t i m e r m o d e 1 : p w m m o d e t i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 : u n d e r f l o w o f t i m e r 5 1 0 : u n d e r f l o w o f t i m e r 4 1 1 : n o t a v a i l a b l e t i m e r 6 ( p w m ) o u t p u t s e l e c t i o n b i t ( p 4 4 ) 0 : i / o p o r t 1 : t i m e r 6 o u t p u t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) b 7 b 0 b 7 b 0 b 7 b 0 n o t e : i n t h e m a s k o p t i o n t y p e p , c n t r 1 f u n c t i o n c a n n o t b e u s e d .
24 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 18 block diagram of timer x i n 1 / 8 p 4 6 / t 3 o u t 1 / 2 x c i n 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 p 4 5 / t 1 o u t 1 / 2 p 6 1 / c n t r 0 / c n t r 2 1 0 1 / 2 p w m p 4 4 / p w m 1 1 0 p 6 0 / c n t r 1 1 / 6 4 1 / 2 1 1 1 1 1 / 1 6 1 0 1 0 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 1 i n t e r r u p t r e q u e s t d a t a b u s t i m e r 1 l a t c h ( 8 ) t i m e r 1 ( 8 ) f f 1 6 t i m e r 1 c o u n t s t o p b i t r e s e t s t p i n s t r u c t i o n p 4 5 l a t c h t i m e r 1 o u t p u t s e l e c t i o n b i t p 4 5 d i r e c t i o n r e g i s t e r t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 2 l a t c h ( 8 ) t i m e r 2 ( 8 ) t i m e r 2 c o u n t s t o p b i t 0 1 1 6 t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 3 l a t c h ( 8 ) t i m e r 3 ( 8 ) t i m e r 3 c o u n t s t o p b i t t i m e r 2 i n t e r r u p t r e q u e s t t i m e r 3 i n t e r r u p t r e q u e s t p 4 6 l a t c h r i s i n g / f a l l i n g a c t i v e e d g e s w i t c h t i m e r 3 o u t p u t s e l e c t i o n b i t p 4 6 d i r e c t i o n r e g i s t e r t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 4 l a t c h ( 8 ) t i m e r 4 ( 8 ) t i m e r 4 c o u n t s t o p b i t r i s i n g / f a l l i n g a c t i v e e d g e s w i t c h t i m e r 4 i n t e r r u p t r e q u e s t t i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t t i m e r 5 l a t c h ( 8 ) t i m e r 5 ( 8 ) t i m e r 5 c o u n t s t o p b i t t i m e r 5 i n t e r r u p t r e q u e s t p 4 4 l a t c h t i m e r 6 o u t p u t s e l e c t i o n b i t p 4 4 d i r e c t i o n r e g i s t e r t i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t s t i m e r 6 l a t c h ( 8 ) t i m e r 6 ( 8 ) t i m e r 6 c o u n t s t o p b i t t i m e r 6 p w m r e g i s t e r ( 8 ) t i m e r 6 o p e r a t i o n m o d e s e l e c t i o n b i t t i m e r 6 i n t e r r u p t r e q u e s t ( n o t e ) n o t e : i n t h e m a s k o p t i o n t y p e p , c n t r 1 f u n c t i o n c a n n o t b e u s e d .
25 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 19 timing chart of timer 6 pwm 1 mode t s t i m e r 6 c o u n t s o u r c e t i m e r 6 p w m m o d e n 5 t s ( n + m ) 5 t s t i m e r 6 i n t e r r u p t r e q u e s t n o t e : p w m w a v e f o r m ( d u t y : n / ( n + m ) a n d p e r i o d : ( n + m ) 5 t s ) i s o u t p u t . n : s e t t i n g v a l u e o f t i m e r 6 m : s e t t i n g v a l u e o f t i m e r 6 p w m r e g i s t e r t s : p e r i o d o f t i m e r 6 c o u n t s o u r c e m 5 t s t i m e r 6 i n t e r r u p t r e q u e s t
26 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 16-bit timer timer x is a 16-bit timer that can be selected in one of four modes by the timer x mode registers 1, 2 and can be controlled the timer x write and the real time port by setting the timer x mode registers. read and write operation on 16-bit timer must be performed for both high- and low-order bytes. when reading a 16-bit timer, read from the high-order byte first. when writing to 16-bit timer, write to the low- order byte first. the 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. l timer x timer x is a down-counter. when the timer reaches 0000 16 , an underflow occurs with the next count pulse. then the contents of the timer latch is reloaded into the timer and the timer continues down- counting. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1. (1) timer mode a count source can be selected by setting the timer x count source selection bits (bits 1 and 2) of the timer x mode register 1. (2) pulse output mode each time the timer underflows, a signal output from the cntr 2 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 2 pin to output. (3) event counter mode the timer counts signals input through the cntr 2 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 2 pin to input. (4) pulse width measurement mode a count source can be selected by setting the timer x count source selection bits (bits 1 and 2) of the timer x mode register 1. when cntr 2 active edge switch bit is 0, the timer counts while the input signal of the cntr 2 pin is at h. when it is 1, the timer counts while the input signal of the cntr 2 pin is at l. when using a timer in this mode, set the port shared with the cntr 2 pin to input. n note timer x write control if the timer x write control bit is 0, when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1, when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. when the value is written in latch only, unexpected value may be set in the high-order counter if the writing in high-order latch and the underflow of timer x are performed at the same timing. real time port control while the real time port function is valid, data for the real time port are output from ports p8 5 and p8 6 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1, data are output without the timer x.) when the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction regis- ters to output mode.
27 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 21 structure of timer x related registers fig. 20 block diagram of timer x c n t r 2 a c t i v e e d g e s w i t c h b i t c n t r 2 a c t i v e e d g e s w i t c h b i t r e a l t i m e p o r t c o n t r o l b i t r e a l t i m e p o r t c o n t r o l b i t s 0 1 0 1 1 0 0 0 , 0 1 , 1 1 q q t p 6 1 / c n t r 0 / c n t r 2 c n t r 0 1 0 1 0 1 0 q d q d p 8 5 p 8 6 1 0 x i n x c i n 1 0 1 / 2 1 / 2 1 / 8 1 / 6 4 p 6 1 l a t c h t i m e r x ( l o w - o r d e r ) ( 8 )t i m e r x ( h i g h - o r d e r ) ( 8 ) t i m e r x l a t c h ( h i g h - o r d e r ) ( 8 ) t i m e r x l a t c h ( l o w - o r d e r ) ( 8 ) d a t a b u s p u l s e o u t p u t m o d e p 6 1 d i r e c t i o n r e g i s t e r p u l s e w i d t h m e a s u r e m e n t m o d e t i m e r x o p e r a t i n g m o d e b i t s t i m e r x s t o p c o n t r o l b i t p u l s e o u t p u t m o d e c o u n t s o u r c e s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t d i v i d e r t i m e r x w r i t e c o n t r o l b i t t i m e r x i n t e r r u p t r e q u e s t t i m e r x m o d e r e g i s t e r w r i t e s i g n a l p 8 6 l a t c h p 8 6 d i r e c t i o n r e g i s t e r p 8 5 l a t c h p 8 5 d i r e c t i o n r e g i s t e r l a t c h l a t c h p 8 5 d a t a f o r r e a l t i m e p o r t r e a l t i m e p o r t c o n t r o l b i t ( p 8 5 ) p 8 6 d a t a f o r r e a l t i m e p o r t r e a l t i m e p o r t c o n t r o l b i t ( p 8 6 ) t i m e r x m o d e r e g i s t e r w r i t e s i g n a l b 7b 0 t i m e r x m o d e r e g i s t e r 1 ( t x m 1 : a d d r e s s 0 0 2 e 1 6 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e d a t a t o b o t h t i m e r l a t c h a n d t i m e r 1 : w r i t e d a t a t o t i m e r l a t c h o n l y t i m e r x c o u n t s o u r c e s e l e c t i o n b i t s b 2b 1 00 : f ( x i n ) / 2 o r f ( x c i n ) / 4 01 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 10 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 11 : n o t a v a i l a b l e n o t u s e d ( r e t u r n s 0 w h e n r e a d ) t i m e r x o p e r a t i n g m o d e b i t s b 5b 4 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 2 a c t i v e e d g e s w i t c h b i t 0 : e v e n t c o u n t e r m o d e ; c o u n t s r i s i n g e d g e s p u l s e o u t p u t m o d e ; o u t p u t s t a r t s w i t h h l e v e l p u l s e w i d t h m e a s u r e m e n t m o d e ; m e a s u r e s h p e r i o d s 1 : e v e n t c o u n t e r m o d e ; c o u n t s f a l l i n g e d g e s p u l s e o u t p u t m o d e ; o u t p u t s t a r t s w i t h l l e v e l p u l s e w i d t h m e a s u r e m e n t m o d e ; m e a s u r e s l p e r i o d s t i m e r x s t o p c o n t r o l b i t 0 : c o u n t o p e r a t i n g 1 : c o u n t s t o p r e a l t i m e p o r t c o n t r o l b i t ( p 8 5 ) 0 : r e a l t i m e p o r t f u n c t i o n i s i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n i s v a l i d r e a l t i m e p o r t c o n t r o l b i t ( p 8 6 ) 0 : r e a l t i m e p o r t f u n c t i o n i s i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n i s v a l i d p 8 5 d a t a f o r r e a l t i m e p o r t p 8 6 d a t a f o r r e a l t i m e p o r t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) t i m e r x m o d e r e g i s t e r 2 ( t x m 2 : a d d r e s s 0 0 2 f 1 6 ) b 7b 0
28 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o serial i/o1 serial i/o1 is used as the clock synchronous serial i/o and has an ordinary mode and an automatic transfer mode. in the automatic transfer mode, serial transfer is performed through the serial i/o automatic transfer ram which has up to 256 bytes (addresses 0f00 16 to 0fff 16 : addresses 0f60 16 to 0fff 16 are also used as fig. 22 block diagram of serial i/o1 fld automatic display ram). the p6 2 /s rdy1 /an 8 , p6 4 /int 4 /s busy1 /an 10 , and p6 5 /s stb1 /an 11 pins each have a handshake i/o signal function and can select either h active or l active for active logic. m a i n d a t a b u s s e r i a l i / o 1 a u t o m a t i c t r a n s f e r c o n t r o l l e r l o c a l d a t a b u s s e r i a l i / o a u t o m a t i c t r a n s f e r r a m ( 0 f 0 0 1 6 0 f f f 1 6 ) s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 x c i n x i n i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t s e r i a l i / o 1 a u t o m a t i c t r a n s f e r d a t a p o i n t e r a d d r e s s d e c o d e r m a i n a d d r e s s b u s l o c a l a d d r e s s b u s 1 0 1 / 8 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 s e r i a l i / o 1 i n t e r r u p t r e q u e s t p 6 4 l a t c h s e r i a l i / o 1 c o u n t e r s y n c h r o n o u s c i r c u i t s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 1 p 6 2 l a t c h p 5 2 / s c l k 1 1 0 1 s c l k 1 0 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 1 / 2 5 6 p 6 5 l a t c h p 6 4 / s b u s y 1 p 6 5 / s s t b 1 ( p 6 5 / s s t b 1 p i n c o n t r o l b i t ) s e r i a l t r a n s f e r s t a t u s f l a g 0 1 0 1 p 6 2 / s r d y 1 0 1 p 5 2 l a t c h p 5 1 / s o u t 1 p 5 0 / s i n 1 p 5 1 l a t c h s e r i a l i / o 1 r e g i s t e r ( 8 ) 0 1 s e r i a l t r a n s f e r s e l e c t i o n b i t s 1 / 2 d i v i d e r 1 / 4 s e r i a l i / o 1 c l o c k p i n s e l e c t i o n b i t p 5 3 / s c l k 1 2 1 0 p 5 3 l a t c h 0 1 0 1 s e r i a l i / o 1 c l o c k p i n s e l e c t i o n b i t s p 6 2 / s r d y 1 p 6 4 / s b u s y 1 p i n c o n t r o l b i t p 6 2 / s r d y 1 p 6 4 / s b u s y 1 p i n c o n t r o l b i t
29 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 23 structure of serial i/o1 control registers 1, 2 p 6 2 / s r d y 1 p 6 4 / s b u s y 1 p i n c o n t r o l b i t s 0 0 0 0 : p i n s p 6 2 a n d p 6 4 a r e i / o p o r t s 0 0 0 1 : n o t u s e d 0 0 1 0 : p 6 2 p i n i s a n s r d y 1 o u t p u t , p 6 4 p i n i s a n i / o p o r t . 0 0 1 1 : p 6 2 p i n i s a n s r d y 1 o u t p u t , p 6 4 p i n i s a n i / o p o r t . 0 1 0 0 : p 6 2 p i n i s a n i / o p o r t , p 6 4 p i n i s a n s b u s y 1 i n p u t . 0 1 0 1 : p 6 2 p i n i s a n i / o p o r t , p 6 4 p i n i s a n s b u s y 1 i n p u t . 0 1 1 0 : p 6 2 p i n i s a n i / o p o r t , p 6 4 p i n i s a n s b u s y 1 o u t p u t . 0 1 1 1 : p 6 2 p i n i s a n i / o p o r t , p 6 4 p i n i s a n s b u s y 1 o u t p u t . 1 0 0 0 : p 6 2 p i n i s a n s r d y 1 i n p u t , p 6 4 p i n i s a n s b u s y 1 o u t p u t . 1 0 0 1 : p 6 2 p i n i s a n s r d y 1 i n p u t , p 6 4 p i n i s a n s b u s y 1 o u t p u t . 1 0 1 0 : p 6 2 p i n i s a n s r d y 1 i n p u t , p 6 4 p i n i s a n s b u s y 1 o u t p u t . 1 0 1 1 : p 6 2 p i n i s a n s r d y 1 i n p u t , p 6 4 p i n i s a n s b u s y 1 o u t p u t . 1 1 0 0 : p 6 2 p i n i s a n s r d y 1 o u t p u t , p 6 4 p i n i s a n s b u s y 1 i n p u t . 1 1 0 1 : p 6 2 p i n i s a n s r d y 1 o u t p u t , p 6 4 p i n i s a n s b u s y 1 i n p u t . 1 1 1 0 : p 6 2 p i n i s a n s r d y 1 o u t p u t , p 6 4 p i n i s a n s b u s y 1 i n p u t . 1 1 1 1 : p 6 2 p i n i s a n s r d y 1 o u t p u t , p 6 4 p i n i s a n s b u s y 1 i n p u t . s e r i a l i / o 1 c o n t r o l r e g i s t e r 2 ( s i o 1 c o n 2 ( s c 1 2 ) : a d d r e s s 0 0 1 a 1 6 ) p 5 1 / s o u t 1 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 1 : n - c h a n n e l o p e n - d r a i n ( p - c h a n n e l o u t p u t i s i n v a l i d . ) s o u t 1 p i n c o n t r o l b i t ( a t n o - t r a n s f e r s e r i a l d a t a ) 0 : o u t p u t a c t i v e 1 : o u t p u t h i g h - i m p e d a n c e s b u s y 1 o u t p u t s s t b 1 o u t p u t f u n c t i o n s e l e c t i o n b i t ( v a l i d i n a u t o m a t i c t r a n s f e r m o d e ) 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g b 7b 0 s e r i a l i / o 1 c o n t r o l r e g i s t e r 1 ( s i o 1 c o n 1 ( s c 1 1 ) : a d d r e s s 0 0 1 9 1 6 ) s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( p 6 5 / s s t b 1 p i n c o n t r o l b i t s ) 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( p 6 5 p i n i s a n i / o p o r t . ) 0 1 : e x t e r n a l s y n c h r o n o u s c l o c k ( p 6 5 p i n i s a n i / o p o r t . ) 1 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( p 6 5 p i n i s a n s s t b 1 o u t p u t . ) 1 1 : i n t e r n a l s y n c h r o n o u s c l o c k ( p 6 5 p i n i s a n s s t b 1 o u t p u t . ) t r a n s f e r m o d e s e l e c t i o n b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( p 5 0 p i n i s a n s i n 1 i n p u t . ) 1 : t r a n s m i t - o n l y m o d e ( p 5 0 p i n i s a n i / o p o r t . ) s e r i a l i / o i n i t i a l i z a t i o n b i t 0 : s e r i a l i / o i n i t i a l i z a t i o n 1 : s e r i a l i / o e n a b l e d s e r i a l i / o 1 c l o c k p i n s e l e c t i o n b i t 0 : s c l k 1 1 ( p 5 3 / s c l k 1 2 p i n i s a n i / o p o r t . ) 1 : s c l k 1 2 ( p 5 2 / s c l k 1 1 p i n i s a n i / o p o r t . ) t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l t r a n s f e r s e l e c t i o n b i t s 0 0 : s e r i a l i / o d i s a b l e d ( p i n s p 6 2 , p 6 4 , p 6 5 , a n d p 5 0 p 5 3 a r e i / o p o r t s ) 0 1 : 8 - b i t s e r i a l i / o 1 0 : n o t a v a i l a b l e 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t s ) b 7b 0
30 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l serial i/o1 operation either the internal synchronous clock or external synchronous clock can be selected by the serial i/o1 synchronous clock selection bits (b2 and b3 of address 0019 16 ) of serial i/o1 control register 1 as synchronous clock for serial transfer. the internal synchronous clock has a built-in dedicated divider where 7 different clocks are selected by the internal synchronous clock selection bits (b5, b6 and b7 of address 001c 16 ) of serial i/o1 control register 3. the p6 2 /s rdy1 /an 8 , p6 4 /int 4 /s busy1 /an 10, and p6 5 /s stb1 /an 11 pins each select either i/o port or handshake i/o signal by the serial i/o1 synchronous clock selection bits (b2 and b3 of address 0019 16 ) of serial i/o1 control register 1 as well as the p6 2 /s rdy1 ? p6 4 /s busy1 pin control bits (b0 to b3 of address 001a 16 ) of serial i/o1 control register 2. for the s out1 being used as an output pin, either cmos output or n-channel open-drain output is selected by the p5 1 /s out1 p-channel output disable bit (b7 of address 001a 16 ) of serial i/o1 control register 2. either output active or high-impedance can be selected as a s out1 pin state at serial non-transfer by the s out1 pin control bit (b6 of address 001a 16 ) of serial i/o1 control register 2. however, when the external synchronous clock is selected, perform the following setup to put the s out1 pin into a high-impedance state. when the s clk1 input is h after completion of transfer, set the s out1 pin control bit to 1. when the s clk1 input goes to l after the start of the next serial transfer, the s out1 pin control bit is automatically reset to 0 and put into an output active state. regardless of whether the internal synchronous clock or external synchronous clock is selected, the full duplex mode and the trans- mit-only mode are available for serial transfer, one of which is se- lected by the transfer mode selection bit (b5 of address 0019 16 ) of serial i/o1 control register 1. either lsb first or msb first is selected for the i/o sequence of the serial transfer bit strings by the transfer direction selection bit (b6 of address 0019 16 ) of serial i/o1 control register 1. when using serial i/o1, first select either 8-bit serial i/o or auto- matic transfer serial i/o by the serial transfer selection bits (b0 and b1 of address 0019 16 ) of serial i/o1 control register 1, after comple- tion of the above bit setup. next, set the serial i/o initialization bit (b4 of address 0019 16 ) of serial i/o1 control register 1 to 1 (serial i/o enable) . when stopping serial transfer while data is being transferred, re- gardless of whether the internal or external synchronous clock is selected, reset the serial i/o initialization bit (b4) to 0. fig. 24 structure of serial i/o1 control register 3 s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 ( s i o 1 c o n 3 ( s c 1 3 ) : a d d r e s s 0 0 1 c 1 6 ) i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s 0 0 0 : f ( x i n ) / 4 o r f ( x c i n ) / 8 0 0 1 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 0 1 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 0 1 1 : f ( x i n ) / 3 2 o r f ( x c i n ) / 6 4 1 0 0 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 1 0 1 : f ( x i n ) / 1 2 8 o r f ( x c i n ) / 2 5 6 1 1 0 : f ( x i n ) / 2 5 6 o r f ( x c i n ) / 5 1 2 a u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s 0 0 0 0 0 : 2 c y c l e s o f t r a n s f e r c l o c k s 0 0 0 0 1 : 3 c y c l e s o f t r a n s f e r c l o c k s : 1 1 1 1 0 : 3 2 c y c l e s o f t r a n s f e r c l o c k s 1 1 1 1 1 : 3 3 c y c l e s o f t r a n s f e r c l o c k s d a t a i s w r i t t e n t o a l a t c h a n d r e a d f r o m a d e c r e m e n t c o u n t e r . b 7 b 0
31 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (1) 8-bit serial i/o mode address 001b 16 is assigned to the serial i/o1 register. when the internal synchronous clock is selected, a serial transfer of the 8-bit serial i/o is started by a write signal to the serial i/o1 register (address 001b 16 ). the serial transfer status flag (b5 of address 001a 16 ) of serial i/o1 control register 2 indicates the shift register status of serial i/o1, and is set to 1 by writing into the serial i/o1 register, which be- comes a transfer start trigger and reset to 0 after completion of 8- bit transfer. at the same time, a serial i/o1 interrupt request occurs. when the external synchronous clock is selected, the contents of the serial i/o1 register are continuously shifted while transfer clocks are input to s clk1 . therefore, the clock needs to be controlled ex- ternally. (2) automatic transfer serial i/o mode the serial i/o1 automatic transfer controller controls the write and read operations of the serial i/o1 register, so the function of ad- dress 001b 16 is used as a transfer counter (1-byte units). when performing serial transfer through the serial i/o automatic transfer ram (addresses 0f00 16 to 0fff 16 ), it is necessary to set the serial i/o1 automatic transfer data pointer (address 0018 16 ) beforehand. input the low-order 8 bits of the first data store address to be seri- ally transferred to the automatic transfer data pointer set bits. when the internal synchronous clock is selected, the transfer inter- val for each 1-byte data can be set by the automatic transfer inter- val set bits (b0 to b4 of address 001c 16 ) of serial i/o1 control regis- ter 3 in the following cases: 1. when using no handshake signal 2. when using the s rdy1 output, s busy1 output, and s stb1 output of the handshake signal independently 3. when using a combination of s rdy1 output and s stb1 output or a combination of s busy1 output and s stb1 output of the handshake signal it is possible to select one of 32 different values, namely 2 to 33 cycles of the transfer clock, as a setting value. when using the s busy1 output and selecting the s busy1 output s stb1 output function selection bit (b4 of address 001a 16 ) of serial i/o1 control register 2 as the signal for all transfer data, provided that the automatic transfer interval setting is valid, a transfer inter- val is placed before the start of transmission/reception of the first data and after the end of transmission/reception of the last data. for s stb1 output, regardless of the contents of the s busy1 output s stb1 output function selection bit (b4), the transfer interval for each 1-byte data is longer than the set value by 2 cycles. furthermore, when using a combination of s busy1 output and s stb1 output as a signal for all transfer data, the transfer interval after the end of transmission/reception of the last data is longer than the set value by 2 cycles. when the external synchronous clock is selected, automatic trans- fer interval setting is disabled. after completion of the above bit setup, if the internal synchronous clock is selected, automatic serial transfer is started by writing the value of number of transfer bytes - 1 into the transfer counter (address 001b 16 ). when the external synchronous clock is selected, write the value of number of transfer bytes - 1 into the transfer counter and input an internal system clock interval of 5 cycles or more. after that, input transfer clock to s clk1 . as a transfer interval for each 1-byte data transfer, input an internal system clock interval of 5 cycles or more from the clock rise time of the last bit. regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decremented after each 1-byte data is received and then written into the automatic transfer ram. the serial transfer status flag (b5 of address 001a 16 ) is set to 1 by writing data into the transfer counter. writing data becomes a transfer start trigger, and the serial transfer status flag is reset to 0 after the last data is written into the automatic transfer ram. at the same time, a serial i/o1 interrupt request occurs. the values written in the automatic transfer data pointer set bits (b0 to b7 of address 0018 16 ) and the automatic transfer interval set bits (b0 to b4 of address 001c 16 ) are held in the latch. when data is written into the transfer counter, the values latched in the automatic transfer data pointer set bits (b0 to b7) and the auto- matic transfer interval set bits (b0 to b4) are transferred to the decrement counter. fig. 25 structure of serial i/o1 automatic transfer data pointer s e r i a l i / o 1 a u t o m a t i c t r a n s f e r d a t a p o i n t e r ( s i o 1 d p : a d d r e s s 0 0 1 8 1 6 ) a u t o m a t i c t r a n s f e r d a t a p o i n t e r s e t b i t s s p e c i f y t h e l o w - o r d e r 8 b i t s o f t h e f i r s t d a t a s t o r e a d d r e s s o n t h e s e r i a l i / o a u t o m a t i c t r a n s f e r r a m . d a t a i s w r i t t e n i n t o t h e l a t c h a n d r e a d f r o m t h e d e c r e m e n t c o u n t e r . b 7b 0
32 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 26 automatic transfer serial i/o operation f f f 1 6 a u t o m a t i c t r a n s f e r r a m t r a n s f e r c o u n t e r a u t o m a t i c t r a n s f e r d a t a p o i n t e r s e r i a l i / o 1 r e g i s t e r f 5 2 1 6 f 5 1 1 6 f 5 0 1 6 f 4 f 1 6 f 4 e 1 6 f 0 0 1 6 0 4 1 6 5 2 1 6 s i n 1 s o u t 1
33 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers when the external synchronous clock is selected, input an h level signal into the s busy1 input and an l level signal into the s busy1 input in the initial status in which transfer is stopped. at this time, the transfer clocks to be input in s clk1 become invalid. during serial transfer, the transfer clocks to be input in s clk1 be- come valid, enabling a transmit/receive operation, while an l level signal is input into the s busy1 input and an h level signal is input into the s busy1 input. when changing the input values in the s busy1 input and the s busy1 input at these operations, change them when the s clk1 input is in a high state. when the high impedance of the s out1 output is selected by the s out1 pin control bit (b6), the s out1 output becomes active, en- abling serial transfer by inputting a transfer clock to s clk1 , while an l level signal is input into the s busy1 input and an h level signal is input into the s busy1 input. 3. s busy1 output signal the s busy1 output is a signal which requests a stop of transmis- sion/reception to the serial transfer destination. in the automatic transfer serial i/o mode, regardless of the internal or external syn- chronous clock, whether the s busy1 output is to be active at trans- fer of each 1-byte data or during transfer of all data can be selected by the s busy1 output ? s stb1 output function selection bit (b4). in the initial status, the status in which the serial i/o initialization bit (b4) is reset to 0, the s busy1 output goes to h and the s busy1 output goes to l. fig. 28 s busy1 input operation (internal synchronous clock) fig. 29 s busy1 input operation (external synchronous clock) l handshake signal 1. s stb1 output signal the s stb1 output is a signal to inform an end of transmission/re- ception to the serial transfer destination. the s stb1 output signal can be used only when the internal synchronous clock is selected. in the initial status, namely, in the status in which the serial i/o initialization bit (b4) is reset to 0, the s stb1 output goes to l, or the s stb1 output goes to h. at the end of transmit/receive operation, when the data of the serial i/o1 register is all output from s out1 , pulses are output in the pe- riod of 1 cycle of the transfer clock so as to cause the s stb1 output to go h or the s stb1 output to go l. after that, each pulse is returned to the initial status in which s stb1 output goes to l or the s stb1 output goes to h. furthermore, after 1 cycle, the serial transfer status flag (b5) is re- set to 0. in the automatic transfer serial i/o mode, whether the s stb1 output is to be active at an end of each 1-byte data or after completion of transfer of all data can be selected by the s busy1 output ? s stb1 output function selection bit (b4 of address 001a 16 ) of serial i/o1 control register 2. 2. s busy1 input signal the s busy1 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. when the internal synchronous clock is selected, input an h level signal into the s busy1 input and an l level signal into the s busy1 input in the initial status in which transfer is stopped. when starting a transmit/receive operation, input an l level signal into the s busy1 input and an h level signal into the s busy1 input in the period of 1.5 cycles or more of the transfer clock. then, transfer clocks are output from the s clk1 output. when an h level signal is input into the s busy1 input and an l level signal into the s busy1 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immedi- ately and the transfer clocks from the s clk1 output is not stopped until the specified number of bits are transmitted and received. the handshake unit of the 8-bit serial i/o is 8 bits and that of the automatic transfer serial i/o is 8 bits. fig. 27 s stb1 output operation s s t b 1 s c l k 1 s o u t 1 s e r i a l t r a n s f e r s t a t u s f l a g s b u s y 1 s c l k 1 s o u t 1 s b u s y 1 s c l k 1 s o u t 1 i n v a l i d ( o u t p u t h i g h - i m p e d a n c e )
34 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers when the internal synchronous clock is selected, in the 8-bit serial i/o mode and the automatic transfer serial i/o mode (s busy1 out- put function outputs in 1-byte units), the s busy1 output goes to l and the s busy1 output goes to h before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the s clk1 output goes to l at a start of transmit/receive operation. in the automatic transfer serial i/o mode (the s busy1 output func- tion outputs all transfer data), the s busy1 output goes to l and the s busy1 output goes to h when the first transmit data is written into the serial i/o1 register (address 001b 16 ). when the external synchronous clock is selected, the s busy1 out- put goes to l and the s busy1 output goes to h when transmit data is written into the serial i/o1 register to start a transmit opera- tion, regardless of the serial i/o transfer mode. at termination of transmit/receive operation, the s busy1 output re- turns to h and the s busy1 output returns to l, the initial status, when the serial transfer status flag is set to 0, regardless of whether the internal or external synchronous clock is selected. furthermore, in the automatic transfer serial i/o mode (s busy1 out- put function outputs in 1-byte units), the s busy1 output goes to h and the s busy1 output goes to l each time 1-byte of receive data is written into the automatic transfer ram. fig. 30 s busy1 output operation (internal synchronous clock, 8-bits serial i/o) fig. 31 s busy1 output operation (external synchronous clock, 8-bits serial i/o) fig. 32 s busy1 output operation in automatic transfer serial i/o mode (internal synchronous clock, s busy1 output function outputs each 1-byte) s b u s y 1 s c l k 1 s o u t 1 s e r i a l t r a n s f e r s t a t u s f l a g s e r i a l t r a n s f e r s t a t u s f l a g s b u s y 1 s c l k 1 w r i t e t o s e r i a l i / o 1 r e g i s t e r s c l k 1 s b u s y 1 s o u t 1 a u t o m a t i c t r a n s f e r i n t e r v a l s e r i a l t r a n s f e r s t a t u s f l a g a u t o m a t i c t r a n s f e r r a m ? s e r i a l i / o 1 r e g i s t e r s e r i a l i / o 1 r e g i s t e r ? a u t o m a t i c t r a n s f e r r a m
35 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 4. s rdy1 output signal the s rdy1 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. in the initial status, when the serial i/o initialization bit (b4) is reset to 0, the s rdy1 output goes to l and the s rdy1 output goes to h. after transmitted data is stored in the serial i/o1 register (address 001b 16 ) and a transmit/receive operation becomes ready, the s rdy1 output goes to h and the s rdy1 output goes to l. when a transmit/ receive operation is started and the transfer clock goes to l, the s rdy1 output goes to l and the s rdy1 output goes to h. 5. s rdy1 input signal the s rdy1 input signal becomes valid only when the s rdy1 input and the s busy1 output are used. the s rdy1 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. when the internal synchronous clock is selected, input a low level signal into the s rdy1 input and a high level signal into the s rdy1 input in the initial status in which the transfer is stopped. when an h level signal is input into the s rdy1 input and an l level signal is input into the s rdy1 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the s clk1 output and a transmit/receive operation is started. after the transmit/receive operation is started and an l level sig- nal is input into the s rdy1 input and an h level signal into the s rdy1 input, this operation cannot be immediately stopped. after the specified number of bits are transmitted and received, the transfer clocks from the s clk1 output is stopped. the handshake unit of the 8-bit serial i/o and that of the automatic transfer serial i/o are of 8 bits. when the external synchronous clock is selected, the s rdy1 input becomes one of the triggers to output the s busy1 signal. to start a transmit/receive operation (s busy1 output: l, s busy1 output: h), input an h level signal into the s rdy1 input and an l level signal into the s rdy1 input, and also write transmit data into the serial i/o1 register. fig. 33 s rdy1 output operation fig. 34 s rdy1 input operation (internal synchronous clock) s r d y 1 s c l k 1 w r i t e t o s e r i a l i / o 1 r e g i s t e r s r d y 1 s c l k 1 s o u t 1
36 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 35 handshake operation at serial i/o1 mutual connecting (1) fig. 36 handshake operation at serial i/o1 mutual connecting (2) a : b : s c l k 1 s r d y 1 s b u s y 1 s b u s y 1 s r d y 1 s c l k 1 a : b : w r i t e t o s e r i a l i / o 1 r e g i s t e r s c l k 1 s r d y 1 s b u s y 1 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n e x t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n w r i t e t o s e r i a l i / o 1 r e g i s t e r a : b : s c l k 1 s r d y 1 s b u s y 1 s b u s y 1 s r d y 1 s c l k 1 a : b : w r i t e t o s e r i a l i / o 1 r e g i s t e r s c l k 1 s r d y 1 s b u s y 1 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n e x t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n w r i t e t o s e r i a l i / o 1 r e g i s t e r
37 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o2 serial i/o2 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation during serial i/o2 operation. (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode can be selected by setting the serial i/o2 mode selection bit (b6) of the serial i/o2 control reg- fig. 38 operation of clock synchronous serial i/o2 function fig. 37 block diagram of clock synchronous serial i/o2 ister (address 001d 16 ) to 1. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock for serial i/o2 operation. if an internal clock is used, transmit/receive is started by a write signal to the serial i/o2 transmit/receive buffer register (tb/ rb) (address 001f 16 ). when p5 7 (s clk22 ) is selected as a clock i/o pin, s rdy2 output function is invalid, and p5 6 (s clk21 ) is used as an i/o port. 1 / 4 1 / 4 f / f p 5 6 / s c l k 2 1 p 5 4 / r x d p 5 5 / t x d p 5 7 / s r d y 2 / s c l k 2 2 0 1 0 1 x i n 1 / 2 x c i n 1 0 p 5 7 / s r d y 2 / s c l k 2 2 s e r i a l i / o 2 s t a t u s r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 f 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t b a u d r a t e g e n e r a t o r d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 1 6 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r d a t a b u s a d d r e s s 0 0 1 f 1 6 s h i f t c l o c k t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 1 e 1 6 d a t a b u s a d d r e s s 0 0 1 d 1 6 t r a n s m i t s h i f t r e g i s t e r s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t b r g c l o c k s w i t c h b i t s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 t b e = 1 t s c = 0 t r a n s m i t / r e c e i v e s h i f t c l o c k ( 1 / 2 1 / 2 0 4 8 o f i n t e r n a l c l o c k o r e x t e r n a l c l o c k ) s e r i a l i / o 2 o u t p u t t x d s e r i a l i / o 2 i n p u t r x d w r i t e - i n s i g n a l t o s e r i a l i / o 2 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 f 1 6 ) o v e r r u n e r r o r ( o e ) d e t e c t i o n n o t e s 1 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e s e l e c t e d t o o c c u r e i t h e r w h e n t h e t r a n s m i t b u f f e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . r e c e i v e e n a b l e s i g n a l s r d y 2
38 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (2) asynchronous serial i/o (uart) mode the asynchronous serial i/o (uart) mode can be selected by clear- ing the serial i/o2 mode selection bit (b6) of the serial i/o2 control register (address 001d 16 ) to 0. eight serial data transfer formats can be selected and the transfer formats used by the transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer can receive 2-byte data continuously. fig. 40 operation of uart serial i/o2 function fig. 39 block diagram of uart serial i/o2 o e p ef e 1 / 1 6 1 / 1 6 t r a n s m i t b u f f e r r e g i s t e r c l o c k c o n t r o l c i r c u i t p 5 6 / s c l k 2 1 p 5 4 / r x d p 5 5 / t x d p 5 7 / s r d y 2 / s c l k 2 2 0 1 1 / 4 0 1 x i n 1 / 2 x c i n 1 d a t a b u s r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 f 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) b a u d r a t e g e n e r a t o r d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 1 6 1 6 s t / s p / p a g e n e r a t o r d a t a b u s t r a n s m i t s h i f t r e g i s t e r a d d r e s s 0 0 1 f 1 6 t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) a d d r e s s 0 0 1 e 1 6 s t d e t e c t o r u a r t c o n t r o l r e g i s t e r a d d r e s s 0 0 1 7 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 d 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t 8 b i t s e r i a l i / o 2 c o n t r o l r e g i s t e r s e r i a l i / o 2 s t a t u s r e g i s t e r s p d e t e c t o r s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t b r g c l o c k s w i t c h b i t t r a n s m i t o r r e c e i v e c l o c k * g e n e r a t e d a t 2 n d b i t i n 2 - s t o p b i t m o d e s e r i a l i / o 2 i n p u t r x d w r i t e - i n s i g n a l t o t r a n s m i t b u f f e r r e g i s t e r s e r i a l i / o 2 o u t p u t t x d r e a d - o u t s i g n a l f r o m r e c e i v e b u f f e r r e g i s t e r t s c = 0 t b e = 1 r b f = 0 t b e = 0 t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t s p t b e = 1 t s c = 1 * s t d 0 d 1 s p d 0 d 1 s t s p 1 s t a r t b i t 7 o r 8 d a t a b i t 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t
39 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [serial i/o2 control register] sio2con (001d 16 ) the serial i/o2 control register contains eight control bits for serial i/o2 functions. [uart control register] uartcon (0017 16 ) this is a 7 bit register containing four control bits, which are valid when uart is selected, two control bits, which are valid when using serial i/o2, and one control bit, which is always valid. data format of serial data receive/transfer and the output structure of the p5 5 /txd pin, etc. are set by this register. [serial i/o2 status register] sio2sts (001e 16 ) the read-only serial i/o2 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial i/o2 function and various errors. three of the flags (b4 to b6) are only valid in the uart mode. the receive buffer full flag (b1) is cleared to 0 when the receive buffer is read. the error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a writing to the serial i/o2 status regis- ter clears error flags oe, pe, fe, and se (b3 to b6, respectively). writing 0 to the serial i/o2 enable bit (sioe : b7 of the serial i/o2 control register) also clears all the status flags, including the error flags. all bits of the serial i/o2 status register are initialized to 0 at reset, but if the transmit enable bit (b4) of the serial i/o2 control register has been set to 1, the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become 1. [serial i/o2 transmit buffer register/receive buffer register] tb/rb (001f 16 ) the transmit buffer and the receive buffer are located in the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. [baud rate generator] brg (0016 16 ) the baud rate generator determines the baud rate for serial transfer. with the 8-bit counter having a reload register, the baud rate genera- tor divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. fig. 41 structure of serial i/o2 related register b 7 b 7 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o 2 s t a t u s r e g i s t e r ( s i o 2 s t s : a d d r e s s 0 0 1 e 1 6 ) s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n : a d d r e s s 0 0 1 d 1 6 ) b 0 b 0 b 7 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 0 1 7 1 6 ) c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p 5 5 / t x d p - c h a n n e l o u t p u t d i s a b l e b i t ( p o f f ) 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e ) b r g c l o c k s w i t c h b i t 0 : x i n o r x c i n / 2 ( d e p e n d s o n i n t e r n a l s y s t e m c l o c k ) 1 : x c i n s e r i a l i / o 2 c l o c k i / o p i n s e l e c t i o n b i t 0 : s c l k 2 1 ( p 5 7 / s c l k 2 2 p i n i s u s e d a s i / o p o r t o r s r d y 2 o u t p u t p i n . ) 1 : s c l k 2 2 ( p 5 6 / s c l k 2 1 p i n i s u s e d a s i / o p o r t . ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) o r f ( x c i n ) / 2 o r f ( x c i n ) 1 : f ( x i n ) / 4 o r f ( x c i n ) / 8 o r f ( x c i n ) / 4 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g / 4 ( w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d ) b r g / 1 6 ( u a r t i s s e l e c t e d ) 1 : e x t e r n a l c l o c k i n p u t ( w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d ) e x t e r n a l c l o c k i n p u t / 1 6 ( u a r t i s s e l e c t e d ) s r d y 2 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 5 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 5 7 p i n o p e r a t e s a s s r d y 2 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 2 m o d e s e l e c t i o n b i t ( s i o m ) 0 : a s y n c h r o n o u s s e r i a l i / o ( u a r t ) 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 2 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 2 d i s a b l e d ( p i n s p 5 4 t o p 5 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 2 e n a b l e d ( p i n s p 5 4 t o p 5 7 o p e r a t e a s s e r i a l i / o p i n s )
40 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fld controller the 38B4 group has fluorescent display (fld) drive and control cir- cuits. the fld controller consists of the following components: 40 pins for fld control pins fldc mode register fld data pointer fld data pointer reload register tdisp time set register toff1 time set register toff2 time set register port p0fld/port switch register port p2fld/port switch register port p8fld/port switch register port p8 fld output control register fld automatic display ram (max. 160 bytes) a gradation display mode can be used for bright/dark display as a display function. fig. 42 block diagram for fld control circuit p 2 0 / f l d 0 p 2 1 / f l d 1 p 2 2 / f l d 2 p 2 3 / f l d 3 p 2 4 / f l d 4 p 2 5 / f l d 5 p 2 6 / f l d 6 p 2 7 / f l d 7 f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p 0 0 0 4 1 6 0 e f a 1 6 8 0 0 0 0 1 6 0 e f 9 1 6 8 p 0 0 / f l d 8 p 0 1 / f l d 9 p 0 2 / f l d 1 0 p 0 3 / f l d 1 1 p 0 4 / f l d 1 2 p 0 5 / f l d 1 3 p 0 6 / f l d 1 4 p 0 7 / f l d 1 5 f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p 0 0 0 2 1 6 8 p 1 0 / f l d 1 6 p 1 1 / f l d 1 7 p 1 2 / f l d 1 8 p 1 3 / f l d 1 9 p 1 4 / f l d 2 0 p 1 5 / f l d 2 1 p 1 6 / f l d 2 2 p 1 7 / f l d 2 3 0 0 0 6 1 6 8 p 3 0 / f l d 2 4 p 3 1 / f l d 2 5 p 3 2 / f l d 2 6 p 3 3 / f l d 2 7 p 3 4 / f l d 2 8 p 3 5 / f l d 2 9 p 3 6 / f l d 3 0 p 3 7 / f l d 3 1 0 0 1 0 1 6 0 e f b 1 6 8 p 8 0 / f l d 3 2 p 8 1 / f l d 3 3 p 8 2 / f l d 3 4 p 8 3 / f l d 3 5 p 8 4 / f l d 3 6 p 8 5 / f l d 3 7 p 8 6 / f l d 3 8 p 8 7 / f l d 3 9 f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p f l d / p 0 f 6 0 1 6 0 f f f 1 6 m a i n a d d r e s s b u s l o c a l a d d r e s s b u s f l d a u t o m a t i c d i s p l a y r a m m a i n d a t a b u s l o c a l d a t a b u s f l d b l a n k i n g i n t e r r u p t f l d d i g i t i n t e r r u p t f l d c m o d e r e g i s t e r ( 0 e f 4 1 6 ) f l d d a t a p o i n t e r r e l o a d r e g i s t e r ( 0 e f 8 1 6 ) f l d d a t a p o i n t e r ( 0 e f 8 1 6 ) t i m i n g g e n e r a t o r a d d r e s s d e c o d e r
41 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [fldc mode register] fldm the fldc mode register is a 8-bit register respectively which is used to control the fld automatic display and to set the blanking time tscan for key-scan. fig. 43 structure of fldc mode register f l d c m o d e r e g i s t e r ( f l d m : a d d r e s s 0 e f 4 1 6 ) a u t o m a t i c d i s p l a y c o n t r o l b i t ( p 0 , p 1 , p 2 , p 3 , p 8 ) 0 : g e n e r a l - p u r p o s e m o d e 1 : a u t o m a t i c d i s p l a y m o d e d i s p l a y s t a r t b i t 0 : s t o p d i s p l a y 1 : d i s p l a y ( s t a r t t o d i s p l a y b y s w i t c h i n g 0 t o 1 ) t s c a n c o n t r o l b i t s 0 0 : f l d d i g i t i n t e r r u p t ( a t r i s i n g e d g e o f e a c h d i g i t ) 0 1 : 1 5 t d i s p 1 0 : 2 5 t d i s p 1 1 : 3 5 t d i s p t i m i n g n u m b e r c o n t r o l b i t 0 : 1 6 t i m i n g m o d e 1 : 3 2 t i m i n g m o d e g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 0 : n o t s e l e c t i n g 1 : s e l e c t i n g ( n o t e 1 ) t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 1 6 o r f ( x c i n ) / 3 2 1 : f ( x i n ) / 6 4 o r f ( x c i n ) / 1 2 8 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t i o n b i t 0 : d r i v a b i l i t y s t r o n g 1 : d r i v a b i l i t y w e a k b 7 b 0 f l d b l a n k i n g i n t e r r u p t ( a t f a l l i n g e d g e o f t h e l a s t d i g i t ) n o t e s 1 : w h e n a g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d , a n u m b e r o f t i m i n g i s m a x . 1 6 t i m i n g . ( s e t t h e t i m i n g n u m b e r c o n t r o l b i t t o 0 . ) 2 : w h e n c h a n g i n g b i t 4 ( t i m i n g n u m b e r c o n t r o l b i t ) o r b i t 5 ( g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t ) , s e t 0 t o b i t 1 ( d i s p l a y s t a r t b i t ) t o p e r f o r m a t d i s p l a y s t o p s t a t e .
42 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 44 segment/digit setting example fld automatic display pins when the automatic display control bits of the fldc mode register (address 0ef4 16 ) are set to 1, the ports of p0, p1, p2, p3 and p8 are used as fld automatic display pins. when using the fld automatic display mode, set each port to the fld pin or the general-purpose port using the respective switch reg- ister in accordance with the number of segments and the number of digits. this setting is performed by writing a value into the fld/port switch register (addresses 0ef9 16 to 0efb 16 ) of each port. this setting can be performed in units of bit. when 0 is set, the port is set to the general-purpose port. when 1 is set, the port is set to the fld pin. there is no restriction on whether the fld pin is to be used as a segment pin or a digit pin. table 9 pins in fld automatic display mode port name automatic display pins setting method p0, p2, fld 0 efld 15 the individual bits of the fld/port switch register (addresses 0ef9 16 e0efb 16 ) can be set each pin p8 0 ep8 3 fld 32 efld 35 either fld port (1) or general-purpose port (0). p1, p3 fld 16 efld 31 none (fld only) p8 4 ep8 7 fld 36 efld 39 the individual bits of the fld/port switch register (address 0efb 16 ) can be set each pin to either fld port (1) or general-purpose port (0). the output can be reversed by the port p8 fld output control register (address 0efc 16 ). the port output format is the cmos output format. when using the port as a display pin, a driver must be installed externally. 1 5 8 p 2 4 p 2 5 p 2 6 p 2 7 p 2 0 p 2 1 p 2 2 p 2 3 0 0 0 0 0 0 0 0 f l d 1 6 ( d i g 1 ) f l d 1 7 ( d i g 2 ) f l d 1 8 ( d i g 3 ) f l d 1 9 ( d i g 4 ) f l d 2 0 ( s e g 4 ) f l d 2 1 ( s e g 5 ) f l d 2 2 ( s e g 6 ) f l d 2 3 ( s e g 7 ) p 0 4 p 0 5 f l d 1 4 ( s e g 2 ) f l d 1 5 ( s e g 3 ) f l d 8 ( s e g 1 ) p 0 1 p 0 2 p 0 3 1 0 0 0 0 0 1 1 f l d 3 2 ( s e g 1 2 ) f l d 3 3 ( s e g 1 3 ) f l d 3 4 ( s e g 1 4 ) f l d 3 5 ( s e g 1 5 ) p 8 4 p 8 5 p 8 6 p 8 7 f l d 2 4 ( s e g 8 ) f l d 2 5 ( s e g 9 ) f l d 2 6 ( s e g 1 0 ) f l d 2 7 ( s e g 1 1 ) f l d 2 8 ( d i g 5 ) f l d 2 9 ( d i g 6 ) f l d 3 0 ( d i g 7 ) f l d 3 1 ( d i g 8 ) 1 1 1 1 0 0 0 0 2 5 1 5 f l d 8 ( s e g 9 ) f l d 9 ( s e g 1 0 ) f l d 1 0 ( s e g 1 1 ) f l d 1 1 ( s e g 1 2 ) f l d 1 2 ( s e g 1 3 ) f l d 1 3 ( s e g 1 4 ) f l d 1 4 ( s e g 1 5 ) f l d 1 5 ( s e g 1 6 ) 1 1 1 1 1 1 1 1 f l d 0 ( s e g 1 ) f l d 1 ( s e g 2 ) f l d 2 ( s e g 3 ) f l d 3 ( s e g 4 ) f l d 4 ( s e g 5 ) f l d 5 ( s e g 6 ) f l d 6 ( s e g 7 ) f l d 7 ( s e g 8 ) f l d 1 6 ( d i g 1 ) f l d 1 7 ( d i g 2 ) f l d 1 8 ( d i g 3 ) f l d 1 9 ( d i g 4 ) f l d 2 0 ( d i g 5 ) f l d 2 1 ( d i g 6 ) f l d 2 2 ( d i g 7 ) f l d 2 3 ( d i g 8 ) 1 1 1 1 1 1 1 1 f l d 2 4 ( d i g 9 ) f l d 2 5 ( d i g 1 0 ) f l d 2 6 ( d i g 1 1 ) f l d 2 7 ( d i g 1 2 ) f l d 2 8 ( d i g 1 3 ) f l d 2 9 ( d i g 1 4 ) f l d 3 0 ( d i g 1 5 ) f l d 3 1 ( s e g 1 7 ) f l d 3 2 ( s e g 1 8 ) f l d 3 3 ( s e g 1 9 ) f l d 3 4 ( s e g 2 0 ) f l d 3 5 ( s e g 2 1 ) 1 1 1 1 1 1 1 1 f l d 3 6 ( s e g 2 2 ) f l d 3 7 ( s e g 2 3 ) f l d 3 8 ( s e g 2 4 ) f l d 3 9 ( s e g 2 5 ) 1 8 2 0 f l d 8 ( d i g 1 ) f l d 9 ( d i g 2 ) f l d 1 0 ( d i g 3 ) f l d 1 1 ( d i g 4 ) f l d 1 2 ( d i g 5 ) f l d 1 3 ( d i g 6 ) f l d 1 4 ( d i g 7 ) f l d 1 5 ( d i g 8 ) 1 1 1 1 1 1 f l d 2 ( s e g 1 ) f l d 3 ( s e g 2 ) f l d 4 ( s e g 3 ) f l d 5 ( s e g 4 ) f l d 6 ( s e g 5 ) f l d 7 ( s e g 6 ) f l d 1 6 ( d i g 9 ) f l d 1 7 ( d i g 1 0 ) f l d 1 8 ( d i g 1 1 ) f l d 1 9 ( d i g 1 2 ) f l d 2 0 ( d i g 1 3 ) f l d 2 1 ( d i g 1 4 ) f l d 2 2 ( d i g 1 5 ) f l d 2 3 ( d i g 1 6 ) 1 1 1 1 1 1 1 1 f l d 2 4 ( d i g 1 7 ) f l d 2 5 ( d i g 1 8 ) f l d 2 6 ( d i g 1 9 ) f l d 2 7 ( d i g 2 0 ) f l d 2 8 ( s e g 7 ) f l d 2 9 ( s e g 8 ) f l d 3 2 ( s e g 1 1 ) f l d 3 3 ( s e g 1 2 ) f l d 3 4 ( s e g 1 3 ) f l d 3 5 ( s e g 1 4 ) 1 1 1 1 1 1 1 1 f l d 3 6 ( s e g 1 5 ) f l d 3 7 ( s e g 1 6 ) f l d 3 8 ( s e g 1 7 ) f l d 3 9 ( s e g 1 8 ) 1 6 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p 2 0 p 2 1 p 2 2 p 2 3 f l d 4 ( s e g 1 ) f l d 5 ( s e g 2 ) f l d 6 ( s e g 3 ) f l d 7 ( s e g 4 ) f l d 8 ( s e g 5 ) f l d 9 ( s e g 6 ) f l d 1 0 ( s e g 7 ) f l d 1 1 ( s e g 8 ) f l d 1 2 ( s e g 9 ) f l d 1 3 ( s e g 1 0 ) f l d 1 4 ( s e g 1 1 ) f l d 1 5 ( s e g 1 2 ) f l d 1 6 ( d i g 1 ) f l d 1 7 ( d i g 2 ) f l d 1 8 ( d i g 3 ) f l d 1 9 ( d i g 4 ) f l d 2 0 ( d i g 5 ) f l d 2 1 ( d i g 6 ) f l d 2 2 ( d i g 7 ) f l d 2 3 ( d i g 8 ) f l d 2 4 ( d i g 9 ) f l d 2 5 ( d i g 1 0 ) f l d 2 6 ( s e g 1 3 ) f l d 2 7 ( s e g 1 4 ) f l d 2 8 ( s e g 1 5 ) f l d 2 9 ( s e g 1 6 ) p 8 1 p 8 0 p 8 2 p 8 3 p 8 4 p 8 5 p 8 6 p 8 7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 p 2 0 p 2 1 f l d 3 0 ( s e g 9 ) f l d 3 1 ( s e g 1 0 ) 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 p 2 4 p 2 5 n u m b e r o f s e g m e n t s n u m b e r o f d i g i t s p o r t p 2 s e t t i n g e x a m p l e 1 s e t t i n g e x a m p l e 2s e t t i n g e x a m p l e 3s e t t i n g e x a m p l e 4 p o r t p 0 p o r t p 1 p o r t p 3 p o r t p 8 v a l u e o f f l d r a m w r i t e d i s a b l e r e g i s t e r i f d a t a i s s e t t o 1 , d a t a i s p r o t e c t e d . t h i s s e t t i n g d o e s n o t d e c i d e t h e f l d p o r t f u n c t i o n ( s e g / d i g ) . v a l u e o f f l d / p o r t s w i t c h r e g i s t e r
43 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fld automatic display ram the fld automatic display ram uses the 160 bytes of addresses 0f60 16 to 0fff 16 . for fld, the 3 modes of 16-timing ordinary mode, 16-timinggradation display mode and 32-timing mode are available depending on the number of timings and the presence/absence of gradation display. the automatic display ram in each mode is as follows: (1) 16-timingordinary mode the 80 bytes of addresses 0fb0 16 to 0fff 16 are used as a fld display data store area. because addresses 0f60 16 to 0faf 16 are not used as the automatic display ram, they can be the ordi- nary ram or serial i/o automatic transfer ram. (2) 16-timinggradation display mode the 160 bytes of addresses 0f60 16 to 0fff 16 are used. the 80 bytes of addresses 0fb0 16 to 0fff 16 are used as an fld dis- play data store area, while the 80 bytes of addresses 0f60 16 to 0faf 16 are used as a gradation display control data store area. (3) 32-timing mode the 160 bytes of addresses 0f60 16 to 0fff 16 are used as an fld display data store area. [fld data pointer and fld data pointer reload register] flddp (0ef8 16 ) both the fld data pointer and fld data pointer reload register are 8-bit registers assigned at address 0ef8 16 . when writing data to this address, the data is written to the fld data pointer reload register; when reading data from this address, the value in the fld data pointer is read. fig. 45 fld automatic display ram assignment 1 6 - t i m i n g o r d i n a r y m o d e 0 f f f 1 6 0 f b 0 1 6 0 f 6 0 1 6 0 f f f 1 6 0 f 6 0 1 6 0 f f f 1 6 0 f b 0 1 6 0 f 6 0 1 6 1 6 - t i m i n g g r a d a t i o n d i s p l a y m o d e 3 2 - t i m i n g m o d e 1 t o 3 2 t i m i n g d i s p l a y d a t a s t o r e d a r e a g r a d a t i o n d i s p l a y c o n t r o l d a t a s t o r e d a r e a 1 t o 1 6 t i m i n g d i s p l a y d a t a s t o r e d a r e a 1 t o 1 6 t i m i n g d i s p l a y d a t a s t o r e d a r e a n o t u s e d
44 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers data setup (1) 16-timing?ordinary mode the area of addresses 0fb0 16 to 0fff 16 are used as a fld automatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p2 is stored at address 0fb0 16 , the last data of fld port p0 is stored at address 0fc0 16 , the last data of fld port p1 is stored at address 0fd0 16 , the last data of fld port p3 is stored at address 0fe0 16 , and the last data of fld port p8 is stored at address 0ff0 16 , to assign in sequence from the last data respectively. the first data of the fld port p2, p0, p1, p3, and p8 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0fb0 16 , 0fc0 16 , 0fd0 16 , 0fe0 16 , and 0ff0 16 . set the fld data pointer reload register to the value given by the timing number C 1. 1 is always written to bits 7, 6, and 5. note that 0 is always read from bits 7, 6, and 5 when reading. 1 is always set to bit 4, but this bit become written value when read- ing. (2) 16-timing?gradation display mode display data setting is performed in the same way as that of the 16-timing?ordinary mode. gradation display control data is ar- ranged at an address resulting from subtracting 0050 16 from the display data store address of each timing and pin. bright dis- play is performed by setting 0, and dark display is performed by setting 1. set the fld data pointer reload register to the value given by the timing number C 1. 1 is always written to bits 7, 6, and 5. note that 0 is always read from bits 7, 6, and 5 when reading. 1 is always set to bit 4, but this bit become written value when read- ing. (3) 32-timing mode the area of addresses 0f60 16 to 0fff 16 are used as a fld au- tomatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p2 is stored at address 0f60 16 , the last data of fld port p0 is stored at address 0f80 16 , the last data of fld port p1 is stored at address 0fa0 16 , the last data of fld port p3 is stored at address 0fc0 16 , and the last data of fld port p8 is stored at address 0fe0 16 , to assign in sequence from the last data respectively. the first data of the fld port p2, p0, p1, p3, and p8 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0f60 16 , 0f80 16 , 0fa0 16 , 0fc0 16 , and 0fe0 16 . set the fld data pointer reload register to the value given by the timing number C1. 1 is always written to bits 7, 6, and 5. note that 0 is always read from bits 7, 6, and 5 when reading. fig. 46 example of using fld automatic display ram in 16-timing?ordinary mode n u m b e r o f f l d s e g m e n t s : 1 5 n u m b e r o f t i m i n g : 8 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 7 ) a d d r e s s 0 f c f 1 6 0 f b 1 1 6 0 f b 2 1 6 0 f b 3 1 6 0 f b 4 1 6 0 f b 5 1 6 0 f b 6 1 6 0 f b 7 1 6 0 f b 8 1 6 0 f b 9 1 6 0 f b a 1 6 0 f b b 1 6 0 f b c 1 6 0 f b d 1 6 0 f b e 1 6 0 f b f 1 6 0 f c 0 1 6 0 f c 1 1 6 0 f c 2 1 6 0 f c 3 1 6 0 f c 4 1 6 0 f c 5 1 6 0 f c 6 1 6 0 f c 7 1 6 0 f c 8 1 6 0 f c 9 1 6 0 f c a 1 6 0 f c b 1 6 0 f c c 1 6 0 f c d 1 6 0 f c e 1 6 0 f d 0 1 6 0 f d 1 1 6 0 f d 2 1 6 0 f d 3 1 6 0 f d 4 1 6 0 f d 5 1 6 0 f d 6 1 6 0 f d 7 1 6 0 f d 8 1 6 0 f d 9 1 6 0 f d a 1 6 0 f d b 1 6 0 f d c 1 6 0 f d d 1 6 0 f d e 1 6 0 f d f 1 6 0 f e 1 1 6 0 f e 2 1 6 0 f e 3 1 6 0 f e 4 1 6 0 f e 5 1 6 0 f e 6 1 6 0 f e 7 1 6 0 f e 8 1 6 0 f e 9 1 6 0 f e a 1 6 0 f e b 1 6 0 f e c 1 6 0 f e d 1 6 0 f e e 1 6 0 f e f 1 6 0 f e 0 1 6 0 f f 1 1 6 0 f f 2 1 6 0 f f 3 1 6 0 f f 4 1 6 0 f f 5 1 6 0 f f 6 1 6 0 f f 7 1 6 0 f f 8 1 6 0 f f 9 1 6 0 f f a 1 6 0 f f b 1 6 0 f f c 1 6 0 f f d 1 6 0 f f e 1 6 0 f f f 1 6 0 f f 0 1 6 0 f b 0 1 6 t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) 76543210 b i t t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 8 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) f l d p 2 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) f l d p 1 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) f l d p 3 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 8 ) f l d p 8 d a t a a r e a n o t e : s h a d e d a r e a i s u s e d f o r s e g m e n t . s h a d e d a r e a i s u s e d f o r d i g i t .
45 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 47 example of using fld automatic display ram in 16-timing?gradation display mode 0 f c f 1 6 0 f b 1 1 6 0 f b 2 1 6 0 f b 3 1 6 0 f b 4 1 6 0 f b 5 1 6 0 f b 6 1 6 0 f b 7 1 6 0 f b 8 1 6 0 f b 9 1 6 0 f b a 1 6 0 f b b 1 6 0 f b c 1 6 0 f b d 1 6 0 f b e 1 6 0 f b f 1 6 0 f c 0 1 6 0 f c 1 1 6 0 f c 2 1 6 0 f c 3 1 6 0 f c 4 1 6 0 f c 5 1 6 0 f c 6 1 6 0 f c 7 1 6 0 f c 8 1 6 0 f c 9 1 6 0 f c a 1 6 0 f c b 1 6 0 f c c 1 6 0 f c d 1 6 0 f c e 1 6 0 f d 0 1 6 0 f d 1 1 6 0 f d 2 1 6 0 f d 3 1 6 0 f d 4 1 6 0 f d 5 1 6 0 f d 6 1 6 0 f d 7 1 6 0 f d 8 1 6 0 f d 9 1 6 0 f d a 1 6 0 f d b 1 6 0 f d c 1 6 0 f d d 1 6 0 f d e 1 6 0 f d f 1 6 0 f e 1 1 6 0 f e 2 1 6 0 f e 3 1 6 0 f e 4 1 6 0 f e 5 1 6 0 f e 6 1 6 0 f e 7 1 6 0 f e 8 1 6 0 f e 9 1 6 0 f e a 1 6 0 f e b 1 6 0 f e c 1 6 0 f e d 1 6 0 f e e 1 6 0 f e f 1 6 0 f e 0 1 6 0 f f 1 1 6 0 f f 2 1 6 0 f f 3 1 6 0 f f 4 1 6 0 f f 5 1 6 0 f f 6 1 6 0 f f 7 1 6 0 f f 8 1 6 0 f f 9 1 6 0 f f a 1 6 0 f f b 1 6 0 f f c 1 6 0 f f d 1 6 0 f f e 1 6 0 f f f 1 6 0 f f 0 1 6 0 f b 0 1 6 0 f 7 f 1 6 0 f 6 0 1 6 0 f 6 1 1 6 0 f 6 2 1 6 0 f 6 3 1 6 0 f 6 4 1 6 0 f 6 5 1 6 0 f 6 6 1 6 0 f 6 7 1 6 0 f 6 8 1 6 0 f 6 9 1 6 0 f 6 a 1 6 0 f 6 b 1 6 0 f 6 c 1 6 0 f 6 d 1 6 0 f 6 e 1 6 0 f 6 f 1 6 0 f 7 0 1 6 0 f 7 1 1 6 0 f 7 2 1 6 0 f 7 3 1 6 0 f 7 4 1 6 0 f 7 5 1 6 0 f 7 6 1 6 0 f 7 7 1 6 0 f 7 8 1 6 0 f 7 9 1 6 0 f 7 a 1 6 0 f 7 b 1 6 0 f 7 c 1 6 0 f 7 d 1 6 0 f 7 e 1 6 7654 210 0 f 8 0 1 6 0 f 8 1 1 6 0 f 8 2 1 6 0 f 8 3 1 6 0 f 8 4 1 6 0 f 8 5 1 6 0 f 8 6 1 6 0 f 8 7 1 6 0 f 8 8 1 6 0 f 8 9 1 6 0 f 8 a 1 6 0 f 8 b 1 6 0 f 8 c 1 6 0 f 8 d 1 6 0 f 8 e 1 6 0 f 8 f 1 6 0 f 9 1 1 6 0 f 9 2 1 6 0 f 9 3 1 6 0 f 9 4 1 6 0 f 9 5 1 6 0 f 9 6 1 6 0 f 9 7 1 6 0 f 9 8 1 6 0 f 9 9 1 6 0 f 9 a 1 6 0 f 9 b 1 6 0 f 9 c 1 6 0 f 9 d 1 6 0 f 9 e 1 6 0 f 9 f 1 6 0 f 9 0 1 6 0 f a 1 1 6 0 f a 2 1 6 0 f a 3 1 6 0 f a 4 1 6 0 f a 5 1 6 0 f a 6 1 6 0 f a 7 1 6 0 f a 8 1 6 0 f a 9 1 6 0 f a a 1 6 0 f a b 1 6 0 f a c 1 6 0 f a d 1 6 0 f a e 1 6 0 f a f 1 6 0 f a 0 1 6 3 76543210 b i t a d d r e s s n u m b e r o f f l d s e g m e n t s : 2 5 n u m b e r o f t i m i n g : 1 5 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 1 4 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) n o t e : s h a d e d a r e a i s u s e d f o r s e g m e n t . s h a d e d a r e a i s u s e d f o r d i g i t . f l d p 2 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 1 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) f l d p 3 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 8 ) f l d p 8 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 8 ) b i t a d d r e s s t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) f l d p 2 g r a d a t i o n d i s p l a y d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 g r a d a t i o n d i s p l a y d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 1 g r a d a t i o n d i s p l a y d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) f l d p 3 g r a d a t i o n d i s p l a y d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 8 ) f l d p 8 g r a d a t i o n d i s p l a y d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 8 ) n o t e : s h a d e d a r e a i s u s e d f o r g r a d a t i o n d i s p l a y d a t a .
46 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 48 example of using fld automatic display ram in 32-timing mode 0 f 7 f 1 6 0 f 6 0 1 6 0 f 6 1 1 6 0 f 6 2 1 6 0 f 6 3 1 6 0 f 6 4 1 6 0 f 6 5 1 6 0 f 6 6 1 6 0 f 6 7 1 6 0 f 6 8 1 6 0 f 6 9 1 6 0 f 6 a 1 6 0 f 6 b 1 6 0 f 6 c 1 6 0 f 6 d 1 6 0 f 6 e 1 6 0 f 6 f 1 6 0 f 7 0 1 6 0 f 7 1 1 6 0 f 7 2 1 6 0 f 7 3 1 6 0 f 7 4 1 6 0 f 7 5 1 6 0 f 7 6 1 6 0 f 7 7 1 6 0 f 7 8 1 6 0 f 7 9 1 6 0 f 7 a 1 6 0 f 7 b 1 6 0 f 7 c 1 6 0 f 7 d 1 6 0 f 7 e 1 6 7654 21 0 f 8 0 1 6 0 f 8 1 1 6 0 f 8 2 1 6 0 f 8 3 1 6 0 f 8 4 1 6 0 f 8 5 1 6 0 f 8 6 1 6 0 f 8 7 1 6 0 f 8 8 1 6 0 f 8 9 1 6 0 f 8 a 1 6 0 f 8 b 1 6 0 f 8 c 1 6 0 f 8 d 1 6 0 f 8 e 1 6 0 f 8 f 1 6 b i t a d d r e s s 0 f 9 1 1 6 0 f 9 2 1 6 0 f 9 3 1 6 0 f 9 4 1 6 0 f 9 5 1 6 0 f 9 6 1 6 0 f 9 7 1 6 0 f 9 8 1 6 0 f 9 9 1 6 0 f 9 a 1 6 0 f 9 b 1 6 0 f 9 c 1 6 0 f 9 d 1 6 0 f 9 e 1 6 0 f 9 f 1 6 0 f 9 0 1 6 0 f a 1 1 6 0 f a 2 1 6 0 f a 3 1 6 0 f a 4 1 6 0 f a 5 1 6 0 f a 6 1 6 0 f a 7 1 6 0 f a 8 1 6 0 f a 9 1 6 0 f a a 1 6 0 f a b 1 6 0 f a c 1 6 0 f a d 1 6 0 f a e 1 6 0 f a f 1 6 0 f a 0 1 6 3 0 76543210 b i t a d d r e s s 0 f c f 1 6 0 f b 1 1 6 0 f b 2 1 6 0 f b 3 1 6 0 f b 4 1 6 0 f b 5 1 6 0 f b 6 1 6 0 f b 7 1 6 0 f b 8 1 6 0 f b 9 1 6 0 f b a 1 6 0 f b b 1 6 0 f b c 1 6 0 f b d 1 6 0 f b e 1 6 0 f b f 1 6 0 f c 0 1 6 0 f c 1 1 6 0 f c 2 1 6 0 f c 3 1 6 0 f c 4 1 6 0 f c 5 1 6 0 f c 6 1 6 0 f c 7 1 6 0 f c 8 1 6 0 f c 9 1 6 0 f c a 1 6 0 f c b 1 6 0 f c c 1 6 0 f c d 1 6 0 f c e 1 6 0 f d 0 1 6 0 f d 1 1 6 0 f d 2 1 6 0 f d 3 1 6 0 f d 4 1 6 0 f d 5 1 6 0 f d 6 1 6 0 f d 7 1 6 0 f d 8 1 6 0 f d 9 1 6 0 f d a 1 6 0 f d b 1 6 0 f d c 1 6 0 f d d 1 6 0 f d e 1 6 0 f d f 1 6 0 f e 1 1 6 0 f e 2 1 6 0 f e 3 1 6 0 f e 4 1 6 0 f e 5 1 6 0 f e 6 1 6 0 f e 7 1 6 0 f e 8 1 6 0 f e 9 1 6 0 f e a 1 6 0 f e b 1 6 0 f e c 1 6 0 f e d 1 6 0 f e e 1 6 0 f e f 1 6 0 f e 0 1 6 0 f f 1 1 6 0 f f 2 1 6 0 f f 3 1 6 0 f f 4 1 6 0 f f 5 1 6 0 f f 6 1 6 0 f f 7 1 6 0 f f 8 1 6 0 f f 9 1 6 0 f f a 1 6 0 f f b 1 6 0 f f c 1 6 0 f f d 1 6 0 f f e 1 6 0 f f f 1 6 0 f f 0 1 6 0 f b 0 1 6 n u m b e r o f f l d s e g m e n t s : 1 8 n u m b e r o f t i m i n g : 2 0 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 1 9 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) n o t e : s h a d e d a r e a i s u s e d f o r s e g m e n t . s h a d e d a r e a i s u s e d f o r d i g i t . f l d p 3 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 8 ) f l d p 8 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 8 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) f l d p 2 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 1 d a t a a r e a
47 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 50 example of using fld automatic display ram using grid scan type setting method when using grid scan type fld when using the grid scan type fld, set 1 in the ram area corre- sponding to the digit ports that output 1 at each timing. set 0 in the ram area corresponding to the other digit ports. fig. 49 example of digit timing using grid scan type d i g 1 0 ( p 3 1 ) d i g 9 ( p 3 0 ) d i g 8 ( p 1 7 ) d i g 2 ( p 1 1 ) d i g 1 ( p 1 0 ) n u m b e r o f t i m i n g : 1 0 t h e f i r s t s e c o n d t h i r d . . . . . . . . . . . . . . . . . . . . . . . 9 t h 1 0 t h s e g m e n t o u t p u t 0 f c f 1 6 0 f b 0 1 6 0 f b 1 1 6 0 f b 2 1 6 0 f b 3 1 6 0 f b 4 1 6 0 f b 5 1 6 0 f b 6 1 6 0 f b 7 1 6 0 f b 8 1 6 0 f b 9 1 6 0 f b a 1 6 0 f b b 1 6 0 f b c 1 6 0 f b d 1 6 0 f b e 1 6 0 f b f 1 6 0 f c 0 1 6 0 f c 1 1 6 0 f c 2 1 6 0 f c 3 1 6 0 f c 4 1 6 0 f c 5 1 6 0 f c 6 1 6 0 f c 7 1 6 0 f c 8 1 6 0 f c 9 1 6 0 f c a 1 6 0 f c b 1 6 0 f c c 1 6 0 f c d 1 6 0 f c e 1 6 7654 210 0 f d 0 1 6 0 f d 1 1 6 0 f d 2 1 6 0 f d 3 1 6 0 f d 4 1 6 0 f d 5 1 6 0 f d 6 1 6 0 f d 7 1 6 0 f d 8 1 6 0 f d 9 1 6 0 f d a 1 6 0 f d b 1 6 0 f d c 1 6 0 f d d 1 6 0 f d e 1 6 0 f d f 1 6 b i t a d d r e s s 0 f e 1 1 6 0 f e 2 1 6 0 f e 3 1 6 0 f e 4 1 6 0 f e 5 1 6 0 f e 6 1 6 0 f e 7 1 6 0 f e 8 1 6 0 f e 9 1 6 0 f e a 1 6 0 f e b 1 6 0 f e c 1 6 0 f e d 1 6 0 f e e 1 6 0 f e f 1 6 0 f e 0 1 6 0 f f 1 1 6 0 f f 2 1 6 0 f f 3 1 6 0 f f 4 1 6 0 f f 5 1 6 0 f f 6 1 6 0 f f 7 1 6 0 f f 8 1 6 0 f f 9 1 6 0 f f a 1 6 0 f f b 1 6 0 f f c 1 6 0 f f d 1 6 0 f f e 1 6 0 f f f 1 6 0 f f 0 1 6 3 1 1 1 1 1 1 1 1 1 1 0000000 0000000 0000000 0000000 000000 000000 00000 00000 0000 0000 000 000 00 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 n u m b e r o f f l d s e g m e n t s : 1 6 n u m b e r o f t i m i n g : 1 0 ( f l d d a t a p o i n t e r r e l o a d r e g i s t e r = 9 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 2 ) n o t e : s h a d e d a r e a i s u s e d f o r s e g m e n t . s h a d e d a r e a i s u s e d f o r d i g i t . f l d p 2 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 2 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 0 ) f l d p 0 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 0 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 1 ) f l d p 1 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 1 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 3 ) f l d p 3 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 3 ) t h e l a s t t i m i n g ( t h e l a s t d a t a o f f l d p 8 ) f l d p 8 d a t a a r e a t i m i n g f o r s t a r t ( t h e f i r s t d a t a o f f l d p 8 )
48 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing setting each timing is set by the fldc mode register, tdisp time set regis- ter, toff1 time set register, and toff2 time set register. l tdisp time setting set the tdisp time by the tdisp counter count source selection bit of the fldc mode register and the tdisp time set register. supposing that the value of the tdisp time set register is n, the tdisp time is represented as tdisp = (n+1) 5 t (t: count source synchronization). when the tdisp counter count source selection bit of the fldc mode register is 0 and the value of the tdisp time set register is 200 (c8 16 ), the tdisp time is: tdisp = (200+1) 5 4 (at x in = 4 mhz) = 804 s. when reading the tdisp time set register, the value in the counter is read out. l toff1 time setting set the toff1 time by the toff1 time set register. supposing that the value of the toff1 time set register is n1, the toff1 time is represented as toff1 = n1 5 t. when the tdisp counter count source selection bit of the fldc mode register is 0 and the value of the toff1 time set register is 30 (1e 16 ), toff1 = 30 5 4 (at x in = 4 mhz) = 120 s. set a value of 03 16 or more to the toff1 time set register (address 0ef6 16 ). l toff2 time setting set the toff2 time by the toff2 time set register. supposing that the value of the toff2 time set register is n2, the toff2 time is represented as toff2 = n2 5 t. when the tdisp counter count source selection bit of the fldc mode register is 0 and the value of the toff2 time set register is 180 (b4 16 ), toff2 = 180 5 4 (at x in = 4 mhz) = 720 s. this toff2 time setting is valid only for fld ports which are in the gradation display mode and whose gradation display control ram value is 1. when setting 1 to bit 7 of the p8fld output control register (ad- dress 0efc 16 ), set a value of 03 16 or more to the toff2 time set register (address 0ef7 16 ). fld automatic display start to perform fld automatic display, set the following registers. port p0fld/port switch register port p2fld/port switch register port p8fld/port switch register fldc mode register tdisp time set register toff1 time set register toff2 time set register fld data pointer fld automatic display mode is selected by writing 1 to the bit 0 of the fldc mode register (address 0ef4 16 ), and the automatic dis- play is started by writing 1 to bit 1. during fld automatic display, bit 1 of the fldc mode register (address 0ef4 16 ) always keeps 1, and fld automatic display can be interrupted by writing 0 to bit 1. key-scan when a key-scan is performed with the segment during key-scan blanking period tscan, take the following sequence: 1. write 0 to bit 0 of the fldc mode register (address 0ef4 16 ). 2. set the port corresponding to the segment for key-scan to the output port. 3. perform the key-scan. 4. after the key-scan is performed, write 1 to bit 0 of fldc mode register (address 0ef4 16 ). n note when performing a key-scan according to the above step 1 to 4, take the following points into consideration. 1. do not set 0 in bit 1 of the fldc mode register (address 0ef4 16 ). 2. do not set 1 in the ports corresponding to digits.
49 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 51 fldc timing t o f f 1 t d i s p s e g m e n t d i g i t s e g m e n t d i g i t o u t p u t s e g m e n t s e t t i n g b y s o f t w a r e f l d b l a n k i n g i n t e r r u p t r e q u e s t o c c u r s a t t h e f a l l i n g e d g e o f t h e l a s t t i m i n g . f l d d i g i t i n t e r r u p t r e q u e s t o c c u r s a t t h e r i s i n g e d g e o f d i g i t ( e a c h t i m i n g ) . t d i s p t s c a n r e p e a t s y n c h r o n o u s t nt n - 1t n - 2t 4t 3t 2t 1 t o f f 1 t o f f 2 s e g m e n t d i g i t w h e n a g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d p i n u n d e r t h e c o n d i t i o n t h a t b i t 5 o f t h e f l d c m o d e r e g i s t e r i s 1 , a n d t h e c o r r e s p o n d i n g g r a d a t i o n d i s p l a y c o n t r o l d a t a v a l u e i s 1 . t d i s p n : n u m b e r o f t i m i n g
50 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p8 4 to p8 7 fld output reverse function p8 4 to p8 7 are provided with a function to reverse the polarity of the fld output. this function is useful in adjusting the polarity when using an externally installed driver. the output polarity can be reversed by setting 1 to bit 0 of the port p8 fld output control register. p8 4 to p8 7 toff invalid function p8 4 to p8 7 can output waveform in which toff is invalid, when p8 4 to p8 7 is selected fld ports (see figure 52). the function is useful when using a 4 bits ? 16 bits decoder. the toff can be invalid by setting 1 to bit 2 of the port p8fld output control register (address 0efc 16 ). p8 4 to p8 7 output delay function p8 4 to p8 7 can output waveform in which is delayed for 16 m s, when selecting fld port and selecting toff invalid function (see figure 52). when using a 4 bits ? 16 bits decoder, the function can be use- ful for prevention of leak radiation caused by phase discrepancy be- tween segment output waveform and digit output waveform. this func- tion can be set by setting 1 to bit 3 of the port p8fld output control register (address 0efc 16 ). dimmer signal output function p6 3 can output the dimmer signal. when using a 4 bits ? 16 bits decoder, the dimmer signal can be used as a control signal for a 4 bits ? 16 bits decoder. when using m35501fp, the dimmer signal can be used as the clk signal. the dimmer signal can be output by setting 1 to bit 4 of the port p8fld output control register (address 0efc 16 ). fig. 52 p8 4 to p8 7 fld output waveform toff2 control bit the value of the toff2 time set register is valid when gradation dis- play mode is selected. the fld ports output (set) the data of display ram at the end of the toff1 time and output 0 (reset) at the end of the toff2 time, when bit 7 of the port p8fld output control register is 0. the fld ports output (set) the data of display ram at the end of the toff2 time and output 0 (reset) at the end of tdisp time, when bit 7 of the port p8fld output control register is 1. fig. 53 structure of port p8 fld output control register s e g m e n t d i g i t a t t o f f 2 c o n t r o l b i t = 0 i n g r a d a t i o n d i s p l a y m o d e ( a t g r a d a t i o n d i s p l a y c o n t r o l d a t a = 1 ) t d i s p t o f f 2 t o f f 1 1 6 m s p 8 4 p 8 7 t o f f i n v a l i d p 8 4 p 8 7 t o f f i n v a l i d d e l a y d i m m e r s i g n a l a t t o f f 2 c o n t r o l b i t = 1 i n g r a d a t i o n d i s p l a y m o d e ( a t g r a d a t i o n d i s p l a y c o n t r o l d a t a = 1 ) p o r t p 8 f l d o u t p u t c o n t r o l r e g i s t e r ( p 8 f l d c o n : a d d r e s s 0 e f c 1 6 ) p 8 4 p 8 7 f l d o u t p u t r e v e r s e b i t 0 : o u t p u t n o r m a l l y 1 : r e v e r s e o u t p u t n o t u s e d ( 0 a t r e a d i n g ) p 8 4 p 8 7 t o f f i n v a l i d b i t 0 : o p e r a t i n g n o r m a l l y 1 : t o f f i n v a l i d p 8 4 p 8 7 d e l a y c o n t r o l b i t ( n o t e ) 0 : n o d e l a y 1 : d e l a y p 6 3 / a n 9 d i m m e r o u t p u t c o n t r o l b i t 0 : o r d i n a r y p o r t 1 : d i m m e r o u t p u t n o t u s e d ( 0 a t r e a d i n g ) t o f f 2 c o n t r o l b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 ) 1 : g r a d a t i o n d i s p l a y d a t a i s s e t a t t o f f 2 ( r e s e t a t t d i s p ) b 7 b 0 n o t e : v a l i d o n l y w h e n s e l e c t i n g f l d p o r t a n d p 8 4 p 8 7 t o f f i n v a l i d f u n c t i o n
51 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter the 38B4 group has a 10-bit a-d converter. the a-d converter per- forms successive approximation conversion. [a-d conversion register] ad one of these registers is a high-order register, and the other is a low- order register. the high-order 8 bits of a conversion result is stored in the a-d conversion register (high-order) (address 0034 16 ), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the a-d conversion register (low-order) (address 0033 16 ). during a-d conversion, do not read these registers. [a-d control register] adcon this register controls a-d converter. bits 3 to 0 are analog input pin selection bits. bit 4 is an ad conversion completion bit and 0 during a-d conversion. this bit is set to 1 upon completion of a-d conver- sion. a-d conversion is started by setting 0 in this bit. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref , and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports p7 7 /an 7 ep7 0 / an 0 , and p6 5 /s stb1 /an 11 ep6 2 /s rdy1 /an 8 and inputs it to the com- parator. when port p6 4 is selected as an analog input pin, an external inter- rupt function (int 4 ) is invalid. [comparator and control circuit] the comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad fig. 55 block diagram of a-d converter conversion interrupt request bit to 1. note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 250 khz during a-d conversion. use a cpu system clock dividing the main clock x in as the internal system clock. fig. 54 structure of a-d control register a d c o n v e r s i o n r e s u l t s t o r e d b i t s a - d c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( a d h : a d d r e s s 0 0 3 4 1 6 ) b 7 b 0 a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 0 : p 7 0 / a n 0 0 0 0 1 : p 7 1 / a n 1 0 0 1 0 : p 7 2 / a n 2 0 0 1 1 : p 7 3 / a n 3 0 1 0 0 : p 7 4 / a n 4 0 1 0 1 : p 7 5 / a n 5 0 1 1 0 : p 7 6 / a n 6 0 1 1 1 : p 7 7 / a n 7 1 0 0 0 : p 6 2 / s r d y 1 / a n 8 1 0 0 1 : p 6 3 / a n 9 1 0 1 0 : p 6 4 / i n t 4 / s b u s y 1 / a n 1 0 1 0 1 1 : p 6 5 / s s t b 1 / a n 1 1 a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 2 1 6 ) a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d n o t u s e d ( r e t u r n s 0 w h e n r e a d ) b 7b 0 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) a d c o n v e r s i o n r e s u l t s t o r e d b i t s a - d c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( a d l : a d d r e s s 0 0 3 3 1 6 ) b 7 b 0 d a t a b u s a v s s a - d i n t e r r u p t r e q u e s t b 7b 0 4 p 7 0 / a n 0 p 7 1 / a n 1 p 7 2 / a n 2 p 7 3 / a n 3 p 7 4 / a n 4 p 7 5 / a n 5 p 7 6 / a n 6 p 7 7 / a n 7 p 6 2 / s r d y 1 / a n 8 p 6 3 / a n 9 p 6 4 / i n t 4 / s b u s y 1 / a n 1 0 p 6 5 / s s t b 1 / a n 1 1 a - d c o n t r o l r e g i s t e r c h a n n e l s e l e c t o r c o m p a r a t o r a - d c o n t r o l c i r c u i t a - d c o n v e r s i o n r e g i s t e r ( h ) a - d c o n v e r s i o n r e g i s t e r ( l ) ( a d d r e s s 0 0 3 4 1 6 ) ( a d d r e s s 0 0 3 3 1 6 ) r e s i s t o r l a d d e r v r e f
52 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pulse width modulation (pwm) the 38B4 group has a pwm function with a 14-bit resolution. when the oscillation frequency x in is 4 mhz, the minimum resolution bit width is 250 ns and the cycle period is 4096 s. the pwm timing generator supplies a pwm control signal based on a signal that is the frequency of the x in clock. the explanation in the rest assumes x in = 4 mhz. fig. 56 pwm block diagram 1 4 1 / 2 x i n ( 4 m h z ) p 8 7 / p w m 0 b i t 7 b i t 0 b i t 5 m s b l s b p w m b i t 7 b i t 0 d a t a b u s x c i n 1 0 p w m r e g i s t e r ( h i g h - o r d e r ) ( a d d r e s s 0 0 1 4 1 6 ) p w m r e g i s t e r ( l o w - o r d e r ) ( a d d r e s s 0 0 1 5 1 6 ) i t i s s e t t o 1 w h e n w r i t e . p w m l a t c h ( 1 4 - b i t ) 1 4 - b i t p w m c i r c u i t w h e n a n i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t i s s e t t o 0 t i m i n g g e n e r a t i n g u n i t f o r p w m ( 6 4 m s c y c l e ) ( 4 0 9 6 m s c y c l e ) p 8 7 / p w m o u t p u t s e l e c t i o n b i t p 8 7 d i r e c t i o n r e g i s t e r p 8 7 / p w m o u t p u t s e l e c t i o n b i t p 8 7 l a t c h
53 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers low-order 6-bit data data setup the pwm output pin also function as port p8 7 . set port p8 7 to be the pwm output pin by setting bit 0 of the pwm control register (address 0026 16 ) to 1. the high-order 8 bits of output data are set in the high-order pwm register pwmh (address 0014 16 ) and the low-order 6 bits are set in the low-order pwm register pwml (address 0015 16 ). pwm operation the timing of the 14-bit pwm function is shown in figure 57. the 14-bit pwm data is divided into the low-order 6 bits and the high-order 8 bits in the pwm latch. the high-order 8 bits of data determine how long an h level signal is output during each sub-period. there are 64 sub-periods in each period, and each sub-period t is 256 5 t (= 64 s) long. the signals h has a length equal to n times t , and its minimum resolution = 250 ns. the last bit of the sub-period becomes the add bit which is specified either h or l, by the contents of pwml. as shown in table 10, the add bit is decided either h or l. that is, only in the sub-period tm shown in table 10 in the pwm cycle period t = 64t, the h duration is lengthened during the mini- mum resolution width t period in comparison with the other period. for example, if the high-order eight bits of the 14-bit data are 03 16 and the low-order six bits are 05 16 , the length of the h level output in sub-periods t 8 , t 24 , t 32 , t 40 and t 56 is 4 t, and its length 3 t in all other sub-periods. time at the h level of each sub-period almost becomes equal be- cause the time becomes length set in the high-order 8 bits or be- comes the value plus t , and this sub-period t (= 64 m s, approximate 15.6 khz) becomes cycle period approximately. transfer from register to latch data written to the pwml register is transferred to the pwm latch once in each pwm period (every 4096 s), and data written to the pwmh register is transferred to the pwm latch once in each sub- period (every 64 s). when the pwml register is read, the contents of the latch are read. however, bit 7 of the pwml register indicates whether the transfer to the pwm latch is completed; the transfer is completed when bit 7 is 0. table 10 relationship between low-order 6-bit data and setting period of add bit 0 0 0 0 0 0 none 0 0 0 0 0 1 m = 32 0 0 0 0 1 0 m = 16, 48 0 0 0 1 0 0 m = 8, 24, 40, 56 0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60 0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63 lsb fig. 57 pwm timing sub-periods tm lengthened (m = 0 to 63) 1 5 . 7 5 m s 6 4 m s 6 4 m s6 4 m s6 4 m s 6 4 m s m = 0m = 7m = 8m = 9m = 6 3 1 6 . 0 m s 1 5 . 7 5 m s1 5 . 7 5 m s1 5 . 7 5 m s1 5 . 7 5 m s1 5 . 7 5 m s p u l s e w i d t h m o d u l a t i o n r e g i s t e r h : 0 0 1 1 1 1 1 1 p u l s e w i d t h m o d u l a t i o n r e g i s t e r l : 0 0 0 1 0 1 s u b - p e r i o d s w h e r e h p u l s e w i d t h i s 1 6 . 0 m s : m = 8 , 2 4 , 3 2 , 4 0 , 5 6 s u b - p e r i o d s w h e r e h p u l s e w i d t h i s 1 5 . 7 5 m s : m = a l l o t h e r v a l u e s 4 0 9 6 m s
54 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 59 14-bit pwm timing fig. 58 structure of pwm control register p 8 7 / p w m o u t p u t s e l e c t i o n b i t 0 : i / o p o r t 1 : p w m o u t p u t n o t u s e d ( r e t u r n 0 w h e n r e a d ) p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 2 6 1 6 ) b 7 b 0 6 a6 a6 a6 a6 a6 b6 a6 a6 a6 a6 a6 a6 a6 a 6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 a 6 a 6 b 6 b 6 b 6 a 6 b 6 b 6 b 6 a 6 b 6 b 6 b 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 6 a 4 3 4 4 3 4 4 3 4 6 b 6 a 6 9 6 8 6 7 0 2 0 1 6 a 6 9 6 8 6 7 0 2 0 1 0 2 0 1 0 0 f f f e f d 9 7 9 6 9 5 0 2 0 1 0 0 f c f f f e f d 9 7 9 6 9 5 f c a d d a d d 1 6 5 3 1 6 1 a 9 3 1 6 1 a a 4 1 6 1 a a 4 1 6 1 e e 4 1 6 1 e f 5 1 6 t = 4 0 9 6 m s t = 6 4 m s 1 3 1 6 a 4 1 6 2 4 1 6 3 5 1 6 7 b 1 6 6 a 1 6 5 9 1 6 d a t a 3 5 1 6 s t o r e d a t a d d r e s s 0 0 1 5 1 6 t = 6 4 m s t = 0 . 2 5 m s h p e r i o d l e n g t h s p e c i f i e d b y p w m h 1 2 b 5 1 6 2 p w m r e g i s t e r ( h i g h - o r d e r ) p w m r e g i s t e r ( l o w - o r d e r ) p w m l a t c h ( 1 4 - b i t ) d a t a 6 a 1 6 s t o r e d a t a d d r e s s 0 0 1 4 1 6 d a t a 2 4 1 6 s t o r e d a t a d d r e s s 0 0 1 5 1 6 b i t 7 c l e a r e d a f t e r t r a n s f e r t r a n s f e r f r o m r e g i s t e r t o l a t c h d a t a 7 b 1 6 s t o r e d a t a d d r e s s 0 0 1 4 1 6 t r a n s f e r f r o m r e g i s t e r t o l a t c h w h e n b i t 7 o f p w m l i s 0 , t r a n s f e r f r o m r e g i s t e r t o l a t c h i s d i s a b l e d . p w m o u t p u t ( e x a m p l e 1 ) l o w - o r d e r 6 - b i t s o u t p u t h = 6 a 1 6 l = 2 4 1 6 6 b 1 6 . . . . . . . . . . . . 3 6 t i m e s ( 1 0 7 ) 6 a 1 6 . . . . . . . . . . . . 2 8 t i m e s ( 1 0 6 ) p w m o u t p u t ( e x a m p l e 2 ) l o w - o r d e r 6 b i t s o u t p u t h = 6 a 1 6 l = 1 8 1 6 6 b 1 6 . . . . . . . . . . . . 2 4 t i m e s6 a 1 6 . . . . . . . . . . . . 4 0 t i m e s p w m o u t p u t 8 - b i t c o u n t e r t h e a d d p o r t i o n s w i t h a d d i t i o n a l t a r e d e t e r m i n e d e i t h e r h o r l b y l o w - o r d e r 6 - b i t d a t a . m i n i m u m b i t w i d t h ( 6 4 6 4 m s ) 5 1 0 6 5 6 4 2 4 ( 2 5 6 0 . 2 5 m s ) 2 5 6 ( 6 4 m s ) , f i x e d t 1 0 6 5 6 4 3 6 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupt interval determination function the 38B4 group has an interrupt interval determination circuit. this interrupt interval determination circuit has an 8-bit binary up counter. using this counter, it determines a duration of time from the rising edge (falling edge) of an input signal pulse on the p4 7 /int 2 pin to the rising edge (falling edge) of the signal pulse that is input next. how to determine the interrupt interval is described below. 1. enable the int 2 interrupt by setting bit 2 of the interrupt control register 1 (address 003e 16 ). select the rising interval or falling interval by setting bit 2 of the interrupt edge selection register (address 003a 16 ). 2. set bit 0 of the interrupt interval determination control register (address 0031 16 ) to 1 (interrupt interval determination operat- ing). 3. select the sampling clock of 8-bit binary up counter by setting bit 1 of the interrupt interval determination control register. when writing 0, f(x in )/128 is selected (the sampling interval: 32 s at f(x in ) = 4.19 mhz); when 1, f(x in )/256 is selected (the sampling interval: 64 s at f(x in ) = 4.19 mhz). 4. when the signal of polarity which is set on the int 2 pin (rising or falling edge) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock. 5. when the signal of polarity above 4 is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval determination register (address 0030 16 ), and the remote control interrupt request occurs. immediately after that, the 8-bit binary up counter continues to count up again from 00 16 . 6. when count value reaches ff 16 , the 8-bit binary up counter stops counting up. then, simultaneously when the next counter sam- pling clock is input, the counter sets value ff 16 to the interrupt interval determination register to generate the counter overflow interrupt request. fig. 60 interrupt interval determination circuit block diagram noise filter the p4 7 /int 2 pin builds in the noise filter. the noise filter operation is described below. 1. select the sampling clock of the input signal with bits 2 and 3 of the interrupt interval determination control register. when not using the noise filter, set 00. 2. the p4 7 /int 2 input signal is sampled in synchronization with the selected clock. when sampling the same level signal in a series of three sampling, the signal is recognized as the interrupt signal, and the interrupt request occurs. when setting bit 4 of interrupt interval determination control register to 1, the interrupt request can occur at both rising and falling edges. when using the noise filter, set the minimum pulse width of the int 2 input signal to 3 cycles or more of the sample clock. note: in the low-speed mode (cm 7 = 1), the interrupt interval deter- mination function cannot operate. f ( x i n ) / 1 2 8 f ( x i n ) / 2 5 6 1 / 1 2 8 1 / 6 4 1 / 3 2 f ( x i n ) c o u n t e r s a m p l i n g c l o c k s e l e c t i o n b i t i n t 2 i n t e r r u p t i n p u t n o i s e f i l t e r 8 - b i t b i n a r y u p c o u n t e r i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r a d d r e s s 0 0 3 0 1 6 d a t a b u s d i v i d e r o n e - s i d e d / b o t h - s i d e d d e t e c t i o n s e l e c t i o n b i t n o i s e f i l t e r s a m p l i n g c l o c k s e l e c t i o n b i t c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t o r r e m o t e c o n t r o l i n t e r r u p t r e q u e s t
56 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 63 interrupt interval determination operation example (at both-sided edge active) fig. 62 interrupt interval determination operation example (at rising edge active) fig. 61 structure of interrupt interval determination control register i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c o n t r o l r e g i s t e r ( i i d c o n : a d d r e s s 0 0 3 1 1 6 ) i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c i r c u i t o p e r a t i n g s e l e c t i o n b i t 0 : s t o p p e d 1 : o p e r a t i n g c o u n t e r s a m p l i n g c l o c k s e l e c t i o n b i t 0 : f ( x i n ) / 1 2 8 1 : f ( x i n ) / 2 5 6 n o i s e f i l t e r s a m p l i n g c l o c k s e l e c t i o n b i t s ( i n t 2 ) 0 0 : f i l t e r s t o p 0 1 : f ( x i n ) / 3 2 1 0 : f ( x i n ) / 6 4 1 1 : f ( x i n ) / 1 2 8 o n e - s i d e d / b o t h - s i d e d e d g e d e t e c t i o n s e l e c t i o n b i t 0 : o n e - s i d e d e d g e d e t e c t i o n 1 : b o t h - s i d e d e d g e d e t e c t i o n ( c a n b e u s e d w h e n u s i n g a n o i s e f i l t e r ) n o t u s e d ( r e t u r n 0 w h e n r e a d ) b 7 b 0 r e m o t e c o n t r o l i n t e r r u p t r e q u e s t 0 1 2 3 4 5 6 1 2 3 0 f e f f n f f 0 f f 6 6 n 1 n ( w h e n i i d c o n 4 = 0 ) n o i s e f i l t e r s a m p l i n g c l o c k i n t 2 p i n a c c e p t a n c e o f i n t e r r u p t c o u n t e r s a m p l i n g c l o c k 8 - b i t b i n a r y u p c o u n t e r v a l u e i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r v a l u e r e m o t e c o n t r o l i n t e r r u p t r e q u e s t c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t 0 1 1 0 f e f f 2 f f 2 3 3 f f 2 n n n 3 2 2 2 0 1 2 1 0 1 0 2 r e m o t e c o n t r o l i n t e r r u p t r e q u e s t ( w h e n i i d c o n 4 = 1 ) n o i s e f i l t e r s a m p l i n g c l o c k i n t 2 p i n a c c e p t a n c e o f i n t e r r u p t c o u n t e r s a m p l i n g c l o c k 8 - b i t b i n a r y u p c o u n t e r v a l u e i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r v a l u e r e m o t e c o n t r o l i n t e r r u p t r e q u e s t c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t r e m o t e c o n t r o l i n t e r r u p t r e q u e s t r e m o t e c o n t r o l i n t e r r u p t r e q u e s t
57 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 65 structure of watchdog timer control register 0, the underflow signal of watchdog timer l becomes the count source. the detection time is set then to f(x in ) = 2.1 s at 4 mhz frequency and f(x cin ) = 512 s at 32 khz frequency. when this bit is set to 1, the count source becomes the signal divided by 8 for f(x in ) (or divided by 16 for f(x cin )). the detection time in this case is set to f(x in ) = 8.2 ms at 4 mhz frequency and f(x cin ) = 2 s at 32 khz frequency. this bit is cleared to 0 after resetting. l operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 002b 16 ) permits disabling the stp instruction when the watchdog timer is in opera- tion. when this bit is 0, the stp instruction is enabled. when this bit is 1, the stp instruction is disabled. once the stp instruction is executed, an internal resetting occurs. when this bit is set to 1, it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. n note when releasing the stop mode, the watchdog timer performs its count operation even in the stop release waiting time. be careful not to cause the watchdog timer h to underflow in the stop release waiting time, for example, by writing data in the watchdog timer control reg- ister (address 002b 16 ) before executing the stp instruction. fig. 64 block diagram of watchdog timer watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). the watchdog timer consists of an 8-bit watch- dog timer l and a 12-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control register (address 002b 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 002b 16 ) and an internal reset occurs at an underflow of the watchdog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 002b 16 ) may be started before an underflow. when the watchdog timer control register (address 002b 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watchdog timer h count source selection bit are read. l initial value of watchdog timer at reset or writing to the watchdog timer control register (address 002b 16 ), a watchdog timer h is set to fff 16 and a watchdog timer l to ff 16 . l watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 002b 16 ) permits selecting a watchdog timer h count source. when this bit is set to x i n d a t a b u s x c i n 1 0 i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( n o t e ) 0 1 1 / 8 w a t c h d o g t i m e r h c o u n t s o u r c e s e l e c t i o n b i t r e s e t c i r c u i t s t p i n s t r u c t i o n d i s a b l e b i t w a t c h d o g t i m e r h ( 1 2 ) f f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . i n t e r n a l r e s e t r e s e t w a t c h d o g t i m e r l ( 8 ) n o t e : e i t h e r h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t 7 o f c p u m o d e r e g i s t e r . s t p i n s t r u c t i o n f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . 1 / 2 b 0 s t p i n s t r u c t i o n d i s a b l e b i t 0 : s t p i n s t r u c t i o n e n a b l e d 1 : s t p i n s t r u c t i o n d i s a b l e d w a t c h d o g t i m e r h c o u n t s o u r c e s e l e c t i o n b i t 0 : w a t c h d o g t i m e r l u n d e r f l o w 1 : f ( x i n ) / 8 o r f ( x c i n ) / 1 6 w a t c h d o g t i m e r h ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n : a d d r e s s 0 0 2 b 1 6 ) b 7
58 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers buzzer output circuit the 38B4 group has a buzzer output circuit. one of 1 khz, 2 khz and 4 khz (at x in = 4.19 mhz) frequencies can be selected by the buzzer output control register (address 0efd 16 ). either p4 3 /b uz01 or p2 0 / b uz02 /fld 0 can be selected as a buzzer output port by the output port selection bits (b2 and b3 of address 0efd 16 ). the buzzer output is controlled by the buzzer output on/off bit (b4). fig. 66 block diagram of buzzer output circuit fig. 67 structure of buzzer output control register f ( x i n ) 1 / 1 0 2 4 1 / 2 0 4 8 1 / 4 0 9 6 p o r t l a t c h b u z z e r o u t p u t b u z z e r o u t p u t o n / o f f b i t o u t p u t p o r t c o n t r o l s i g n a l p o r t d i r e c t i o n r e g i s t e r d i v i d e r b u z z e r o u t p u t c o n t r o l r e g i s t e r ( b u z c o n : a d d r e s s 0 e f d 1 6 ) o u t p u t f r e q u e n c y s e l e c t i o n b i t s ( x i n = 4 . 1 9 m h z ) 0 0 : 1 k h z ( f ( x i n ) / 4 0 9 6 ) 0 1 : 2 k h z ( f ( x i n ) / 2 0 4 8 ) 1 0 : 4 k h z ( f ( x i n ) / 1 0 2 4 ) 1 1 : n o t a v a i l a b l e o u t p u t p o r t s e l e c t i o n b i t s 0 0 : p 2 0 a n d p 4 3 f u n c t i o n a s o r d i n a r y p o r t s . 0 1 : p 4 3 / b u z 0 1 f u n c t i o n s a s a b u z z e r o u t p u t . 1 0 : p 2 0 / b u z 0 2 / f l d 0 f u n c t i o n s a s a b u z z e r o u t p u t . 1 1 : n o t a v a i l a b l e b u z z e r o u t p u t o n / o f f b i t 0 : b u z z e r o u t p u t o f f ( 0 o u t p u t ) 1 : b u z z e r o u t p u t o n n o t u s e d ( r e t u r n 0 w h e n r e a d ) b 7 b 0
59 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers reset circuit ______ to reset the microcomputer, reset pin should be held at an l ______ level for 2 s or more. then the reset pin is returned to an h level (the power source voltage should be between 2.7 v and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.5 v for v cc of 2.7 v (switching to the high-speed mode, a power source voltage must be between 4.0 v and 5.5 v). fig. 69 reset sequence fig. 68 reset circuit example ( n o t e ) 0 . 2 v c c 0 v 0 v p o w e r o n v c c r e s e t v c c r e s e t p o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t p o w e r s o u r c e v o l t a g e r e s e t i n p u t v o l t a g e n o t e : r e s e t r e l e a s e v o l t a g e ; v c c = 2 . 7 v r e s e t i n t e r n a l r e s e t d a t a f a d d r e s s s y n c x i n : a b o u t 4 0 0 0 c y c l e s x i n ? ? ? ? ? f f f cf f f d a d h , a d l 1 : t h e f r e q u e n c y r e l a t i o n o f f ( x i n ) a n d f ( f ) i s f ( x i n ) = 4 f ( f ) . 2 : t h e q u e s t i o n m a r k s ( ? ) i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e . n o t e s a d l a d h
60 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 70 internal status at reset 0 0 1 6 0 0 1 6 3 f 1 6 f f 1 6 f f 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 2 1 6 5 : n o t f i x e d s i n c e t h e i n i t i a l v a l u e s f o r o t h e r t h a n a b o v e m e n t i o n e d r e g i s t e r s a n d r a m c o n t e n t s a r e i n d e f i n i t e a t r e s e t , t h e y m u s t b e s e t . a d d r e s s r e g i s t e r c o n t e n t s a d d r e s s r e g i s t e r c o n t e n t s 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 f f 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 7 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 8 1 6 t i m e r 4 p o r t p 0 p o r t p 0 d i r e c t i o n r e g i s t e r p o r t p 1 p o r t p 2 p o r t p 2 d i r e c t i o n r e g i s t e r p o r t p 3 p o r t p 4 p o r t p 4 d i r e c t i o n r e g i s t e r p o r t p 5 p o r t p 5 d i r e c t i o n r e g i s t e r p o r t p 6 p o r t p 6 d i r e c t i o n r e g i s t e r p o r t p 7 p o r t p 7 d i r e c t i o n r e g i s t e r p o r t p 8 p o r t p 8 d i r e c t i o n r e g i s t e r u a r t c o n t r o l r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r 1 s e r i a l i / o 1 c o n t r o l r e g i s t e r 2 s e r i a l i / o 1 c o n t r o l r e g i s t e r 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r s e r i a l i / o 2 s t a t u s r e g i s t e r t i m e r 1 t i m e r 2 t i m e r 3 t i m e r 5 t i m e r 6 p w m c o n t r o l r e g i s t e r t i m e r 1 2 m o d e r e g i s t e r ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 1 ) ( 1 2 ) ( 1 3 ) ( 1 4 ) ( 1 5 ) ( 1 6 ) ( 1 7 ) ( 1 8 ) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) ( 2 9 ) ( 3 0 ) ( 3 1 ) ( 3 2 ) 0 0 1 6 0 0 2 9 1 6 t i m e r 3 4 m o d e r e g i s t e r ( 3 3 ) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) ( 3 9 ) ( 4 0 ) ( 4 1 ) t i m e r 5 6 m o d e r e g i s t e r w a t c h d o g t i m e r c o n t r o l r e g i s t e r t i m e r x ( l o w - o r d e r ) t i m e r x ( h i g h - o r d e r ) t i m e r x m o d e r e g i s t e r 1 t i m e r x m o d e r e g i s t e r 2 i n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c o n t r o l r e g i s t e r a - d c o n t r o l r e g i s t e r 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 f f 1 6 0 0 1 6 0 0 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 e f 0 1 6 0 e f 1 1 6 0 e f 4 1 6 0 e f 5 1 6 0 e f 6 1 6 0 e f 7 1 6 0 e f 9 1 6 0 e f a 1 6 0 e f b 1 6 0 e f c 1 6 0 e f d 1 6 ( 4 2 ) ( 4 3 ) ( 4 4 ) ( 4 5 ) ( 4 6 ) ( 4 7 ) ( 4 8 ) ( 4 9 ) ( 5 0 ) ( 5 1 ) ( 5 2 ) ( 5 3 ) ( 5 4 ) ( 5 5 ) ( 5 6 ) ( 5 7 ) ( 5 8 ) p o r t p 8 f l d o u t p u t c o n t r o l r e g i s t e r f l d c m o d e r e g i s t e r i n t e r r u p t s o u r c e s w i t c h r e g i s t e r i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r c p u m o d e r e g i s t e r i n t e r r u p t r e q u e s t r e g i s t e r 1 i n t e r r u p t r e q u e s t r e g i s t e r 2 i n t e r r u p t c o n t r o l r e g i s t e r 1 i n t e r r u p t c o n t r o l r e g i s t e r 2 p u l l - u p c o n t r o l r e g i s t e r 1 p u l l - u p c o n t r o l r e g i s t e r 2 t d i s p t i m e s e t r e g i s t e r t o f f 1 t i m e s e t r e g i s t e r t o f f 2 t i m e s e t r e g i s t e r p o r t p 0 f l d / p o r t s w i t c h r e g i s t e r p o r t p 2 f l d / p o r t s w i t c h r e g i s t e r p o r t p 8 f l d / p o r t s w i t c h r e g i s t e r f f 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 1 0 1 6 p o r t p 9 p o r t p 9 d i r e c t i o n r e g i s t e r ( 3 4 ) f f f c 1 6 c o n t e n t s ( p s ) ( p c h ) ( p c l ) ( 5 9 ) ( 6 0 ) ( 6 1 ) p r o g r a m c o u n t e r b u z z e r o u t p u t c o n t r o l r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r f f f d 1 6 c o n t e n t s 1 5 0 0 3 1 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 8 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 8 0 1 6 f f 1 6 0 1 1 6 f f 1 6 010010 0 0 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 5 5 5 55 5
61 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers clock generating circuit the 38B4 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no external resistor is needed between x in and x out since a feedback resistor exists on-chip. however, an external feedback resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal system clock is the frequency of x in divided by 4. after reset, this mode is selected. (2) high-speed mode the internal system clock is the frequency of x in . (3) low-speed mode the internal system clock is the frequency of x cin divided by 2. n note if you switch the mode between middle/high-speed and low-speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). (4) low power consumption mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is re- started (by setting the main clock stop bit to 0), set enough time for oscillation to stabilize. by clearing furthermore the x cout drivability selection bit (b3) of cpu mode register to 0, low power consumption operation of less than 200 a (f(x cin ) = 32 khz) can be realized by reducing the drivability between x cin and x cout . at reset or during stp instruction execu- tion this bit is set to 1 and a strong drivability that has an easy oscillation start is set. oscillation control (1) stop mode if the stp instruction is executed, the internal system clock stops at an h level, and x in and x cin oscillators stop. timer 1 is set to ff 16 and timer 2 is set to 01 16 . either x in divided by 8 or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 12 mode register are cleared to 0. set the interrupt enable bits of the timer 1 and timer 2 to disabled (0) before execut- ing the stp instruction. oscillator restarts when an external interrupt is received or reset, but the internal system clock is not supplied to the cpu until timer 1 underflows. this allows time for the clock cir- cuit oscillation to stabilize. (2) wait mode if the wit instruction is executed, the internal system clock stops at an h level. the states of x in and x cin are the same as the state before executing the wit instruction. the internal system clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 71 ceramic resonator circuit fig. 72 external clock input circuit x c i n x c o u t x i n x o u t c i n c o u t c c i n c c o u t r f r d x i n x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v c c v s s o p e n x c i n x c o u t e x t e r n a l o s c i l l a t i o n c i r c u i t o r e x t e r n a l p u l s e o p e n v c c v s s
62 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 73 clock generating circuit block diagram w i t i n s t r u c t i o n s t p i n s t r u c t i o n t i m i n g f ( i n t e r n a l c l o c k ) s r q s t p i n s t r u c t i o n s r q m a i n c l o c k s t o p b i t ( n o t e 3 ) s r q 1 / 4 x i n x o u t x c o u t x c i n i n t e r r u p t r e q u e s t r e s e t i n t e r r u p t d i s a b l e f l a g l 1 / 2 1 / 2 p o r t x c s w i t c h b i t ( n o t e 3 ) 1 0 1 t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t ( n o t e 2 ) l o w - s p e e d m o d e h i g h - s p e e d o r m i d d l e - s p e e d m o d e m i d d l e - s p e e d m o d e h i g h - s p e e d o r l o w - s p e e d m o d e i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t ( n o t e s 1 , 3 ) 1 0 t i m e r 1 t i m e r 2 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t ( n o t e 2 ) 0 m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t ( n o t e 3 ) 1 0 1 0 n o t e s 1 : w h e n l o w - s p e e d m o d e i s s e l e c t e d , s e t t h e p o r t x c s w i t c h b i t ( b 4 ) t o 1 . 2 : r e f e r t o t h e s t r u c t u r e o f t h e t i m e r 1 2 m o d e r e g i s t e r . 3 : r e f e r t o t h e s t r u c t u r e o f t h e c p u m o d e r e g i s t e r .
63 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 74 state transitions of system clock c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) 1 : s w i t c h t h e m o d e b y t h e a l l o w s s h o w n b e t w e e n t h e m o d e b l o c k s . ( d o n o t s w i t c h b e t w e e n t h e m o d e d i r e c t l y w i t h o u t a n a l l o w . ) 2 : t h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e a n d r e t u r n t o t h e s o u r c e m o d e w h e n t h e s t o p m o d e o r t h e w a i t m o d e i s e n d e d . 3 : t i m e r o p e r a t e s i n t h e w a i t m o d e . 4 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 1 m s o c c u r s b y t i m e r 1 i n m i d d l e - / h i g h - s p e e d m o d e . 5 : w h e n t h e s t o p m o d e i s e n d e d , a d e l a y o f a p p r o x i m a t e l y 0 . 2 5 s o c c u r s b y t i m e r 1 i n l o w - s p e e d m o d e . 6 : t h e e x a m p l e a s s u m e s t h a t 4 m h z i s b e i n g a p p l i e d t o t h e x i n p i n a n d 3 2 k h z t o t h e x c i n p i n . f i n d i c a t e s t h e i n t e r n a l s y s t e m c l o c k . m i d d l e - s p e e d m o d e ( f = 1 m h z ) m i d d l e - s p e e d m o d e ( f = 1 m h z ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) h i g h - s p e e d m o d e ( f = 4 m h z ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) h i g h - s p e e d m o d e ( f = 4 m h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f = 1 6 k h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 0 ( h i g h - s p e e d ) c m 5 = 1 ( x i n s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) c m 7 = 0 ( 4 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( x i n o s c i l l a t i n g ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - s p e e d m o d e ( f = 1 6 k h z ) c m 7 = 1 ( 3 2 k h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 1 ( x i n s t o p p e d ) c m 4 = 1 ( 3 2 k h z o s c i l l a t i n g ) l o w - p o w e r d i s s i p a t i o n m o d e ( f = 1 6 k h z ) n o t e s c m 4 : p o r t x c s w i t c h b i t 0 : i / o p o r t f u n c t i o n 1 : x c i n - x c o u t o s c i l l a t i n g f u n c t i o n c m 5 : m a i n c l o c k ( x i n - x o u t ) s t o p b i t 0 : o s c i l l a t i n g 1 : s t o p p e d c m 6 : m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t 0 : f ( x i n ) ( h i g h - s p e e d m o d e ) 1 : f ( x i n ) / 4 ( m i d d l e - s p e e d m o d e ) c m 7 : i n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t 0 : x i n e x o u t s e l e c t e d ( m i d d l e - / h i g h - s p e e d m o d e ) 1 : x c i n e x c o u t s e l e c t e d ( l o w - s p e e d m o d e ) r e s e t c m 4 c m 7 c m 4 c m 5 c m 6 c m 6 c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7b 4 c m 7 c m 5 c m 6 c m 6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 c m 4 1 0 c m 4 0 1 0 1 c m 5 1 0 0 1 c m 5 0 1 0 1 0 1 c m 6 c m 6 c m 6 c m 6 l o w - p o w e r d i s s i p a t i o n m o d e ( f = 1 6 k h z )
64 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immediately after they have been written. after writing to an interrupt request reg- ister, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before ex- ecuting a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the addressing mode which uses the value of a direction register as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. serial i/o using an external clock when using an external clock, input h to the external clock input pin and clear the serial i/o interrupt request bit before executing serial i/o transfer and serial i/o automatic transfer. using an internal clock when using an internal clock, set the synchronous clock to the in- ternal clock, then clear the serial i/o interrupt request bit before ex- ecuting a serial i/o transfer and serial i/o automatic transfer. automatic transfer serial i/o when using the automatic transfer serial i/o mode of the serial i/o1, set an automatic transfer interval as the following. otherwise the serial data might be incorrectly transmitted/received. set an automatic transfer interval for each 1-byte data transfer as the following: (1) not using fld controller keep the interval for 5 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. (2) using fld controller (a) not using gradation display keep the interval for 12 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. (b) using gradation display keep the interval for 18 cycles or more of internal system clock from clock rising of the last bit of 1-byte data. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 250 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the frequency of the internal system clock by the number of cycles needed to ex- ecute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal system clock is the same of the x in frequency in high-speed mode. at stp instruction release at the stp instruction release, all bits of the timer 12 mode register are cleared. the x cout drivability selection bit (the cpu mode register) is set to 1 (high drive) in order to start oscillating. data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical cop- ies)
65 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers mask option of pull-down resistor (object product: m38B4xmxh-xxxxfp) whether built-in pull-down resistors are connected or not to high- breakdown voltage ports p2 0 to p2 7 and p8 0 to p8 3 can be specified in ordering mask rom. the option type can be specified from among 8 types; a to g, p as shown table 11. table 11 mask option type of pull-down resistor a ($41) b ($42) c ($43) d ($44) e ($45) f ($46) g ($47) connective port of pull-down resistor (connected at 1 writing) p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p8 0 p8 1 p8 2 p8 3 1 1 11 11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 111 notes 1: the electrical characteristics of high-breakdown voltage ports p2 0 to p2 7 and p8 0 to p8 3 s built-in pull-down resistors are the same as that of high-breakdown voltage ports p0 0 to p0 7 . 2: the absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. after calculating the power dissipation, specify the option type. 3: one time prom version and eprom version cannot be specified whether built-in pull-down resistors are connected or not likewise option type a. 4: int 3 function and cntr 1 function cannot be used in the option type p. power dissipation calculating method l fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 43 v / 900 m a = 48 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v 5 15 ma = 75 mw l fixed number depending on use condition ? apply voltage to v ee pin: vcc C 45 v ? timing number a; digit number b; segment number c ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: d ? all segment number during repeat cycle: e (= a 5 c) ? total number of built-in resistor: for digit; f, for segment; g ? digit pin current value h (ma) ? segment pin current value i (ma) (1) digit pin power dissipation {h 5 b 5 (1Ctoff/tdisp) 5 voltage} / a (2) segment pin power dissipation {i 5 d 5 (1Ctoff/tdisp) 5 voltage} / a (3) pull-down resistor power dissipation (digit) {power dissipation per 1 digit 5 (b 5 f / b) 5 (1Ctoff/tdisp) } / a (4) pull-down resistor power dissipation (segment) { power dissipation per 1 segment 5 (d 5 g / c) 5 (1Ctoff/tdisp) } / a (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = x mw power dissipation calculating example 1 l fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 43 v / 900 m a = 48 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v 5 15 ma = 75 mw l fixed number depending on use condition ? apply voltage to v ee pin: vcc C 45 v ? timing number 17; digit number 16; segment number 20 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 31 ? all segment number during repeat cycle: 340 (= 17 5 20) ? total number of built-in resistor: for digit; 16, for segment; 20 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 5 16 5 (1C1/16) 5 2} / 17 = 31.77 mw (2) segment pin power dissipation {3 5 31 5 (1C1/16) 5 2} / 17 = 10.26 mw (3) pull-down resistor power dissipation (digit) (45 C 2) 2 /48 5 (16 5 16/16) 5 (1 C 1/16) / 17 = 33.99 mw (4) pull-down resistor power dissipation (segment) (45 C 2) 2 /48 5 (31 5 20/20) 5 (1 C 1/16) / 17 = 65.86 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = 217 mw fig. 75 digit timing waveform (1) option type restriction p ($50) 1 111 11 11 (note 4) d i g 0 d i g 1 d i g 2 d i g 3 d i g 1 4 d i g 1 5 d i g 1 6 t i m i n g n u m b e r 123 1 61 7 1 5 1 4 t s c a n r e p e a t c y c l e
66 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers power dissipation calculating example 2 (when 2 or more digit is turned on at same time) l fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 43 v / 900 m a = 48 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v 5 15 ma = 75 mw l fixed number depending on use condition ? apply voltage to v ee pin: vcc C 45 v ? timing number 11; digit number 12; segment number 24 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 114 ? all segment number during repeat cycle: 264 (= 11 5 24) ? total number of built-in resistor: for digit; 10, for segment; 22 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 5 12 5 (1C1/16) 5 2} / 11 = 36.82 mw (2) segment pin power dissipation {3 5 114 5 (1C1/16) 5 2} / 11 = 58.30 mw (3) pull-down resistor power dissipation (digit) (45 C 2) 2 /48 5 (12 5 10/12) 5 (1 C 1/16) / 11 = 32.84 mw (4) pull-down resistor power dissipation (segment) (45 C 2) 2 /48 5 (114 5 22/24) 5 (1 C 1/16) / 11 = 343.08 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 75 mw (1) + (2)+ (3) + (4) + (5) = 547 mw fig. 76 digit timing waveform (2) d i g 0 d i g 1 d i g 2 d i g 3 d i g 7 d i g 8 d i g 9 t i m i n g n u m b e r 12 34567 891 01 1 d i g 4 d i g 5 d i g 6 t s c a n r e p e a t c y c l e
67 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers conditions symbol ratings unit parameter v cc v ee v i v i v i v i v i v o v o v o p d t opr t stg power source voltage pull-down power source voltage input voltage p4 7 , p5 0 ep5 7 , p6 1 ep6 5 , p7 0 e p7 7 , p8 4 ep8 7 , p9 0 , p9 1 input voltage p4 0 ep4 6 , p6 0 input voltage p0 0 ep0 7 , p2 0 ep2 7 , p8 0 ep8 3 input voltage reset, x in input voltage x cin output voltage p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 7 , p8 0 ep8 3 output voltage p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 , p9 0 , p9 1 , x out , x cout output voltage p4 0 ep4 6 , p6 0 power dissipation operating temperature storage temperature v v v v v v v v v v v v v mw mw ?c ?c absolute maximum ratings table 12 absolute maximum ratings all voltages are based on v ss . output transistors are cut off. ta = e20 to 65 ?c ta = 65 to 85 ?c e0.3 to 6.5 v cc e 45 to v cc +0.3 (note 1) v cc e 42 to v cc +0.3 (note 2) e0.3 to v cc +0.3 e0.3 to 13 v cc e 45 to v cc +0.3 (note 1) v cc e 42 to v cc +0.3 (note 2) e0.3 to v cc +0.3 e0.3 to v cc +0.3 v cc e 45 to v cc +0.3 (note 1) v cc e 42 to v cc +0.3 (note 2) e0.3 to v cc +0.3 e0.3 to 13 800 800 e 12.5 5 (ta e 65) e20 to 85 e40 to 125 notes 1: when vcc is 4.0 to 5.5 v. 2: when vcc is 2.7 to 4.0 v.
68 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers v cc v ss v ee v ref av ss v ia v ih v ih v ih v ih v ih v ih v il v il v il v il v il power source voltage power source voltage pull-down power source voltage analog reference voltage (when a-d converter is used) analog power source voltage analog input voltage an 0 ean 11 h input voltage p4 0 ep4 7 , p5 0 ep5 7 , p6 0 ep6 5 , p7 0 ep7 7 , p9 0 , p9 1 h input voltage p8 4 ep8 7 h input voltage p0 0 ep0 7 h input voltage p2 0 ep2 7 , p8 0 ep8 3 h input voltage reset h input voltage x in , x cin l input voltage p4 0 ep4 7 , p5 0 ep5 7 , p6 0 ep6 5 , p7 0 ep7 7 , p9 0 , p9 1 l input voltage p8 4 ep8 7 l input voltage p0 0 ep0 7 , p2 0 ep2 7 , p8 0 ep8 3 l input voltage reset l input voltage x in , x cin v v v v v v v v v v v v v v v v v v v v v v v 4.0 2.7 v cc e43 v cc e40 2.0 0 0.75v cc 0.8v cc 0.4v cc 0.5vcc 0.8v cc 0.52v cc 0.75v cc 0.8v cc 0.8v cc 0 0 0 0 0 0 symbol limits parameter in high-speed mode in middle-/low-speed mode, 2 mhz or less in high-speed mode 5.0 5.0 0 0 5.5 5.5 v cc v cc v cc v cc v cc v cc v cc vcc v cc v cc v cc v cc v cc 0.25v cc 0.2v cc 0.16v cc 0.2v cc 0.2v cc 0.2v cc unit min. typ. max. recommended operating conditions table 13 recommended operating conditions (1) (vcc = 2.7 to 5.5 v, ta = e20 to 85 ?c, unless otherwise noted) v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v
69 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 32.768 s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) h total peak output current (note 1) p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 7 , p8 0 ep8 3 h total peak output current (note 1) p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p9 0 , p9 1 l total peak output current (note 1) p5 0 ep5 7 , p6 0 ep6 5 , p7 0 ep7 7 , p9 0 , p9 1 l total peak output current (note 1) p4 0 ep4 6 , p8 4 ep8 7 h total average output current (note 1) p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 7 , p8 0 ep8 7 h total average output current (note 1) p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p9 0 , p9 1 l total average output current (note 1) p5 0 ep5 7 , p6 0 ep6 5 , p7 0 ep7 7 , p9 0 , p9 1 l total average output current (note 1) p4 0 ep4 6 , p8 4 ep8 7 h peak output current (note 2) p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 7 , p8 0 ep8 3 h peak output current (note 2) p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 , p9 0 , p9 1 l peak output current (note 2) p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 , p9 0 , p9 1 l peak output current (note 2) p4 0 ep4 6 , p6 0 h average output current (note 3) p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 7 , p8 0 ep8 3 h average output current (note 3) p5 0 ep5 7 , p6 0 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 , p9 0 , p9 1 l average output current (note 3) p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 , p9 0 , p9 1 l average output current (note 3) p4 0 ep4 6 , p6 0 clock input frequency for timers 2, 4, and x (duty cycle 50 %) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma khz khz mhz mhz khz symbol limits parameter e240 e60 100 60 e120 e30 50 30 e40 e10 10 30 e18 e5 5 15 250 100 4.2 2 50 unit min. typ. max. notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50%. 5: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. table 14 recommended operating conditions (2) (vcc = 2.7 to 5.5 v, ta = e20 to 85 ?c, unless otherwise noted) v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v
70 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers electrical characteristics table 15 electrical characteristics (1) (v cc = 2.7 to 5.5 v, ta = e20 to 85 ?c, unless otherwise noted) min. typ. max. symbol parameter limits unit h output voltage p0 0 ep0 7 , p1 0 ep1 7 , p2 0 e p2 7 , p3 0 ep3 7 , p8 0 ep8 3 h output voltage p5 0 ep5 7 , p6 0 ep6 5 , p7 0 e p7 7 , p8 4 ep8 7 , p9 0, p9 1 l output voltage p5 0 ep5 7 , p6 1 ep6 5 , p8 4 e p8 7 , p9 0, p9 1 l output voltage p4 0 ep4 6 , p6 0 v oh v oh v ol v ol v t+ ev te v t+ ev te v t+ ev te i ih i ih i ih i ih i ih i il i il i il i il i il r pulld i leak i readh v ram i oh = e18 ma i oh = e10 ma i oh = e10 ma i oh = e10 ma i ol = 10 ma i ol = 1.6 ma i ol = 15 ma i ol = 5 ma v i = v cc v i = 12 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss pull-up off v cc = 5 v , v i = v ss pull-up on v cc = 3 v , v i = v ss pull-up on v i = v ss v i = v ss v i = v ss v ee = v cce 43 v , v ol =v cc output transistors off v ee = v cce 43 v , v ol =v cce 43 v output transistors off v i = 5 v when clock is stopped test conditions v cc e2.0 v cc e1.5 v cc e2.0 v cc e1.0 2.0 0.4 2.0 1.0 5.0 10.0 5.0 5.0 e5.0 e5.0 e5.0 e5.0 47 e10 vcc 0.6 0.3 0.4 0.5 0.5 4.0 e70 e25 e4.0 72 1 143 2 notes 1: p4 2 , p4 5 , p4 6 , and p6 0 of the mask option type p do not have hysteresis characteristics. 2: except when reading ports p0, p2, or p8. v v v v v v v v v v a a a a a a a a a a a a a k w a a v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v v cc = 4.0 to 5.5 v v cc = 2.7 to 4.0 v hysteresis p4 0 ep4 2 , p4 5 ep4 7 , p5, p6 0 , p6 1 ,p6 4 (note 1) hysteresis reset, x in hysteresis x cin h input current p4 7 , p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 h input current p4 0 ep4 6 , p6 0 h input current p0 0 ep0 7 , p2 0 ep2 7 , p8 0 ep8 3 (note 2) h input current reset, x cin h input current x in l input current p4 0 ep4 7 , p6 0 l input current p5 0 ep5 7 , p6 1 ep6 5 , p7 0 ep7 7 , p8 4 ep8 7 , p9 0 , p9 1 l input current p0 0 ep0 7 , p2 0 ep2 7 , p8 0 ep8 3 (note 2) l input current reset, x cin l input current x in pull-down resistor p0 0 ep0 7 , p1 0 ep1 7 , p3 0 ep3 7 (p2 0 ep2 7 , p8 0 ep8 3 at option) output leak current p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 7 , p8 0 ep8 3 h read current p0 0 ep0 7 , p2 0 ep2 7 , p8 0 ep8 3 ram hold voltage
71 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 61 30 3 95 0.5 35 10 6 62 120 5.0 bits lsb tc( f ) a a k w table 16 electrical characteristics (2) (v cc =2.7 to 5.5 v, ta = e20 to 85 ?c, unless otherwise noted) min. typ. max. symbol parameter limits unit test conditions i cc power source current 7.5 1 3 1 60 20 0.6 0.1 1 10 ma ma ma ma a a ma a a high-speed mode f(x in ) = 4.2 mhz f(x cin ) = 32 khz output transistors off high-speed mode f(x in ) = 4.2 mhz (in wit state) f(x cin ) = 32 khz output transistors off middle-speed mode f(x in ) = 4.2 mhz f(x cin ) = stopped output transistors off middle-speed mode f(x in ) = 4.2 mhz (in wit state) f(x cin ) = stopped output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32 khz low-power dissipation mode (cm 3 = 0) output transistors off low-speed mode f(x in ) = stopped f(x cin ) = 32 khz (in wit state) low-power dissipation mode (cm 3 = 0) output transistors off increment when a-d conversion is executed all oscillation stopped (in stp state) output transistors off ta = 25 ?c ta = 85 ?c a-d converter characteristics table 17 a-d converter characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = e20 to 85 ?c, f(x in ) = 250 khz to 4.2 mhz in high-speed mode, unless otherwise noted) min. typ. max. symbol parameter limits unit test conditions ? ? t conv iv ref i ia r ladder resolution absolute accuracy (excluding quantization error) conversion time reference input current analog port input current ladder resistor v cc = v ref = 5.12 v v ref = 5.0 v 61 50 1 150 0.5 35 10 2.5 62 200 5.0 bits lsb tc( f ) a a k w table 18 a-d converter characteristics (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, ta = e20 to 85 ?c, f(x in ) = 250 khz to 2 mhz in high-speed mode, unless otherwise noted) min. typ. max. symbol parameter limits unit test conditions v cc = v ref = 3.3 v v ref = 3.3 v ? ? t conv iv ref i ia r ladder resolution absolute accuracy (excluding quantization error) conversion time reference input current analog port input current ladder resistor
72 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing requirements table 19 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = e20 to 85 ?c, unless otherwise noted) min. typ. max. symbol parameter limits unit ____________ t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (s clk es in ) t h (s clk es in ) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width sub-clock input cycle time (x cin input) sub-clock input h pulse width sub-clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input h pulse width int 0 to int 4 input l pulse width serial i/o clock input cycle time serial i/o clock input h pulse width serial i/o clock input l pulse width serial i/o input set up time serial i/o input hold time 2.0 238 60 60 20 5.0 5.0 4.0 1.6 1.6 80 80 0.95 400 400 200 200 s ns ns ns s s s s s s ns ns s ns ns ns ns min. typ. max. symbol parameter limits unit ____________ t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk ) t wh (s clk ) t wl (s clk ) t su (s clk es in ) t h (s clk es in ) reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width sub-clock input cycle time (x cin input) sub-clock input h pulse width sub-clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input h pulse width int 0 to int 4 input l pulse width serial i/o clock input cycle time serial i/o clock input h pulse width serial i/o clock input l pulse width serial i/o input set up time serial i/o input hold time 2.0 500 120 120 20 5.0 5.0 10 4.0 4.0 230 230 2.0 950 950 400 300 s ns ns ns s s s s s s ns ns s ns ns ns ns table 20 timing requirements (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = e20 to 85 ?c, unless otherwise noted)
73 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers t c (s clk )/2e240 t c (s clk )/2e240 0 ns ns ns ns ns ns ns s 0.4 tc 60 60 switching characteristics table 21 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = e20 to 85 ?c, unless otherwise noted) min. typ. max. symbol parameter limits unit ns ns ns ns ns ns ns s t wh (s clk ) t wl (s clk ) t d (s clk es out ) t v (s clk es out ) t r (s clk ) t f (s clk ) t r (pchestrg) t r (pcheweak) serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time serial i/o output valid time serial i/o clock output rising time serial i/o clock output falling time p-channel high-breakdown voltage output rising time (note 1) p-channel high-breakdown voltage output rising time (note 2) 0.2 tc 40 40 55 1.8 t c (s clk )/2e160 t c (s clk )/2e160 0 test conditions c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf v ee = v cc e43 v c l = 100 pf v ee = v cc e43 v notes 1: when bit 7 of the fldc mode register (address 0ef4 16 ) is at 0. 2: when bit 7 of the fldc mode register (address 0ef4 16 ) is at 1. table 22 switching characteristics (2) (v cc = 2.7 to 4.0 v, v ss = 0 v, ta = e20 to 85 ?c, unless otherwise noted) min. typ. max. symbol parameter limits unit t wh (s clk ) t wl (s clk ) t d (s clk es out ) t v (s clk es out ) t r (s clk ) t f (s clk ) t r (pchestrg) t r (pcheweak) serial i/o clock output h pulse width serial i/o clock output l pulse width serial i/o output delay time serial i/o output valid time serial i/o clock output rising time serial i/o clock output falling time p-channel high-breakdown voltage output rising time (note 1) p-channel high-breakdown voltage output rising time (note 2) 140 3.6 test conditions c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf c l = 100 pf v ee = v cc e40 v c l = 100 pf v ee = v cc e40 v notes 1: when bit 7 of the fldc mode register (address 0ef4 16 ) is at 0. 2: when bit 7 of the fldc mode register (address 0ef4 16 ) is at 1.
74 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 77 circuit for measuring output switching characteristics p 5 2 / s c l k 1 1 , p 5 3 / s c l k 1 2 , p 5 6 / s c l k 2 1 , p 5 7 / s c l k 2 2 p 0 , p 1 , p 2 , p 3 , p 8 0 p 8 3 n o t e : p o r t s p 2 a n d p 8 n e e d e x t e r n a l r e s i s t o r s . ( n o t e ) c l s e r i a l i / o c l o c k o u t p u t p o r t c l v e e h i g h - b r e a k d o w n p - c h a n n e l o p e n - d r a i n o u t p u t p o r t
75 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 78 timing diagram t i m i n g d i a g r a m 0 . 2 v c c t w l ( x c i n ) 0 . 8 v c c t w h ( x c i n ) t c ( x c i n ) x c i n 0 . 2 v c c t w l ( x i n ) 0 . 8 v c c t w h ( x i n ) t c ( x i n ) x i n 0 . 2 v c c 0 . 8 v c c t w ( r e s e t ) r e s e t 0 . 2 v c c t w l ( c n t r ) 0 . 8 v c c t w h ( c n t r ) t c ( c n t r ) c n t r 0 , c n t r 1 0 . 2 v c c t w l ( i n t ) 0 . 8 v c c t w h ( i n t ) i n t 0 i n t 4 0 . 2 v c c t d ( s c l k - s o u t ) 0 . 2 v c c 0 . 8 v c c 0 . 8 v c c t r t s u ( s i n - s c l k ) t h ( s c l k - s i n ) t v ( s c l k - s o u t ) t c ( s c l k ) t w l ( s c l k ) t w h ( s c l k ) s o u t s i n s c l k t f ( s c l k )
76 38B4 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers package outline qfp80-p-1420-0.80 1.58 weight(g) jedec code eiaj package code lead material alloy 42 80p6n-a plastic 80pin 14 5 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.5 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.8 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.45 0.35 0.3 2.8 0 3.05 e e e e c h e 1 80 65 40 64 41 25 24 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f x 0.2 b x m
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rev. rev. no. date 1.0 first edition 000510 revision description list 38B4 group data sheet (1/1) revision description

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