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1 features ? compatible with an embedded arm7tdmi ? processor programmable baud rate generator parity, framing and overrun error detection line break generation and detection automatic echo, local loopback and remote loopback channel modes multi-drop mode: address detection and generation interrupt generation two dedicated peripheral data controller channels can be easily implemented 5-, 6-, 7-, 8- and 9-bit character length full scan testable (up to 98%) can be directly connected to the atmel implementation of the amba ? peripheral bus (apb) description the two-channel, full-duplex USART features parity, framing and overrun error detec- tion. a baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the USART can be programmed to operate in three different test modes: automatic echo , local loopback and remote loopback . two dedicated peripheral data controller channels can be easily implemented. one is dedicated to the receiver. the other is dedicated to the transmitter. the generation of interrupts is controlled in the status register by asserting the corre- sponding interrupt line. the USART can be used with any 32-bit microcontroller core if the timing diagram shown on page 8 is respected. when using an arm7tdmi as the core, the atmel bridge must be used to provide the correct bus interface to the peripheral. 32-bit embedded asic core peripheral USART rev. 1242e?12/01
2 USART 1242e?12/01 figure 1. USART symbol p_stb p_write p_stb_rising p_a[13:0] p_sel_USART scan_test_mode USART_int test_so[2:1] USART functional functional test_se test_si[2:1] test scan test scan nreset p_d_out[31:0] rxd USART clk_ext txd USART rxrdy_to_dma txrdy_to_dma clk_txd en_clk_n 2 2 p_d_in[31:0] comm_rx comm_tx arm core clock fdiv1 slow_clock slclk_eq_sysclk power management /clock controller pdc rx_dma_end tx_dma_end
3 USART 1242e ? 12/01 table 1. USART pin description name function type active level comments functional nreset reset system input low resets all the counters and signals p_a[13:0] address bus input ? the address takes into account the 2 lsbs [1:0], but the macrocell does not take these bits into account (left unconnected). p_d_in[31:0] input data bus input ? from host (bridge) p_d_out[31:0] output data bus output ? to host (bridge) p_write write enable input high from host (bridge) p_stb peripheral strobe input high from host (bridge) p_stp_rising user interface clock signal input ? from host (bridge). clock for all dffs controlling the configuration registers. p_sel_USART selection of the block input high from host (bridge) USART_int interrupt signal to aic output high power management/clock controller clock system clock input ? system clock for the USART output waveforms fdiv1 USART clock enable input ? system clock (clock) divided slow_clock arm ? core operation input slclk_eq_sysclk arm ? core operation input arm ? core comm_rx arm ? core operation input high must be connected to arm core. comm_tx arm ? core operation input high must be connected to arm core. USART clk_ext baud rate signal input ? from sck pad rxd receive serial data pin input ? txd transmit serial data pin output ? rxrdy_to_dma output signal to dma channel output high byte available in the receiver holding register (rhr). this signal connects to the pdc (1) txrdy_to_dma output signal to the dma channel output high there are no more characters in the transmitter holding register (thr). this signal connects to the pdc (1) clk_txd output of the baud rate generator output ? to sck pad en_clk_n direction signal for sck pad output ? active in synchronous mode pdc rx_dma_end end of receive dma transfer input high generated by pdc (1) tx_dma_end end of transmit dma transfer input high generated by pdc (1)
4 USART 1242e ? 12/01 note: 1. the peripheral data controller (pdc) is a separate block. please refer to the corresponding datasheet. scan test configuration the fault coverage is maximum if all non-scan inputs can be controlled and all non-scan out- puts can be observed. in order to achieve this, the atpg vectors must be generated on the entire circuit (top-level), which includes the USART, or all USART i/os must have a top-level access and atpg vectors must be applied to these pins. test scan scan_test_mode must be set when running the scan vectors input high test_se scan test enable input high/low scan shift/scan capture test_si[2:1] scan test input input high entry of scan chain test_so[2:1] scan test output output ? output of scan chain table 1. USART pin description name function type active level comments
5 USART 1242e ? 12/01 figure 2. USART block diagram peripheral data controller (pdc) when the dedicated atmel pdc is used, four additional registers are available in the USART (see page 16). these registers are physically located in the pdc and accessed when select- ing the USART. for more details concerning these registers, please refer to the pdc datasheet. the following pins are exclusively reserved for use with the pdc: rxrdy_to_dma, txrdy_to_dma, rx_dma_end, tx_dma_end. if the pdc is not used, rx_dma_end and tx_dma_end must be tied to zero. peripheral data controller (pdc) receiver channel transmitter channel control logic interrupt control baud rate generator receiver transmitter atmel bridge asb apb USART_int clock fdiv1 rxd txd sck USART channel baud rate clock pio or pad clk_ext slow_clock slclk_eq_sysclk
6 USART 1242e ? 12/01 figure 3. connecting the USART to an arm ? -based microcontroller pin description each USART channel has the following external signals: 32-bit core (arm) atmel bridge asb clock nreset USART en_clk_n clk_txd clk_ext txd rx_dma_end tx_dma_end pad or pio pdc to advanced interrupt controller (aic) USART_int fdiv1 sck p_write p_d_in[31:0] p_a[13:0] p_stb p_sel_USART p_d_out[31:0] p_stb_rising p_write p_d_in[31:0 ] p_d_out[31:0] p_stb p_a[13:0] p_sel_USART atmel bus interface p_stb_rising rxd rxd txd rxrdy_to_dma txrdy_to_dma slow_clock slclk_eq_sysclk name description sck USART serial clock can be configured as input or output: sck is configured as input if an external clock is selected (usclks = 11) sck is driven as output if the external clock is disabled (usclks[1] = 0) and clock output is enabled (clko = 1) txd transmit serial data is an output rxd receive serial data is an input
7 USART 1242e ? 12/01 timing diagrams figure 4. USART timing diagram: write/read cycle valid p_stb p_a[13:0] p_d_in[31:0] p_write p_d_out[31:0] t pd1 t su_write t hold_write t hold_din t su_din p_stb_rising t su_a t hold_a t pd2 t hold_sel t hold_sel p_sel_USART
8 USART 1242e ? 12/01 figure 5. USART timing diagram: propagation delays, control signals clock t pd_int , t pd_rxrdy_to_dma, USART_int rxrdy_to_dma txrdy_to_dma clk_ext t pd_txrdy_to_dma txd t pd_txd clk_txd t pd_clk_txd en_clk_n t pd_en_clk_n t hold t su tx_dma_end rx_dma_end fdiv1 comm_rx comm_tx slclk_eq_sysclk
9 USART 1242e ? 12/01 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator can select between external and internal clock sources. the exter- nal clock source is sck (clk_ext) or slow_clock. the internal clock sources can be either the master clock (clock) or the master clock divided (fdiv1). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the system clock (clock) period. the external clock frequency must be at least 4.5 times lower than the system clock. when the USART is programmed to operate in asynchronous mode (sync = 0 in the mode register us_mr), the selected clock is divided by 16 times the value (cd) written in us_brgr (baud rate generator register). if us_brgr is set to 0, the baud rate clock is disabled. when the USART is programmed to operate in synchronous mode (sync = 1) and the selected clock is internal (usclks[1] = 0 in the mode register us_mr), the baud rate clock is the internal selected clock divided by the value written in us_brgr. if us_brgr is set to 0, the baud rate clock is disabled. in synchronous mode with external clock selected (usclks = 11), the clock is provided directly by the signal on the sck pin (clk_ext). no division is active. the value written in us_brgr has no effect. figure 6. baud rate generator baud rate selected clock 16 cd --------------------------------------- - = baud rate selected clock cd --------------------------------------- - = 00 01 clock fdiv1 selected clock 16-bit counter 0 0 1 baud rate clock sync usclks = 11 cd cd out 0 1 divide by 16 sync 0 1 >1 usclks slow_clock 10 11 clk_ext ext_clock
10 USART 1242e ? 12/01 receiver asynchronous receiver the USART is configured for asynchronous operation when sync = 0 (bit 7 of us_mr). in asynchronous mode, the USART detects the start of a received character by sampling the rxd signal until it detects a valid start bit. a low level (space) on rxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the rxd at the theoretical mid- point of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the sampling point is eight cycles (0.5 bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 7. asynchronous mode: start bit detection figure 8. asynchronous mode: character reception 16 x baud rate clock rxd true start detection d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period
11 USART 1242e ? 12/01 synchronous receiver when configured for synchronous operation (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. see the example in figure 9. figure 9. synchronous mode: character reception receiver ready when a complete character is received, it is transferred to the us_rhr and the rxrdy sta- tus bit in us_csr is set. if us_rhr has not been read since the last transfer, the ovre status bit in us_csr is set. parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in us_mr. it then compares the result with the received par- ity bit. if different, the parity error bit pare in us_csr is set. framing error if a character is received with a stop bit at low level and with at least one data bit at high level, a framing error is generated. this sets frame in us_csr. time-out this function allows an idle condition on the rxd line to be detected. the maximum delay for which the USART should wait for a new character to arrive while the rxd line is inactive (high level) is programmed in us_rtor (receiver time-out). when this register is set to 0, no time-out is detected. otherwise, the receiver waits for a first character and then initializes a counter, which is decremented at each bit period and reloaded at each byte reception. when the counter reaches 0, the timeout bit in us_csr is set. the user can restart the wait for a first character with the sttto (start time-out) bit in us_cr. calculation of time-out duration: generating clk_txd in synchronous mode, clk_txd is the clock as defined in figure 9. in asynchronous mode, as defined in figure 7. d0 d1 d2 d3 d4 d5 d6 d7 rxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop clk_ext duration us_rtor value 4 bit period = clk_txd 16 baud rate clock =
12 USART 1242e ? 12/01 transmitter the transmitter has the same behavior in both synchronous and asynchronous operating modes. start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of the serial clock. see the example in figure 10. the number of data bits is selected in the chrl field in us_mr. the parity bit is set according to the par field in us_mr. the number of stop bits is selected in the nbstop field in us_mr. when a character is written to us_thr (transmit holding), it is transferred to the shift regis- ter as soon as it is empty. when the transfer occurs, the txrdy bit in us_csr is set until a new character is written to us_thr. if transmit shift register and us_thr are both empty, the txempty bit in us_csr is set. time-guard the time-guard function allows the transmitter to insert an idle state on the txd line between two characters. the duration of the idle state is programmed in us_ttgr (transmitter time- guard). when this register is set to zero, no time-guard is generated. otherwise, the transmit- ter holds a high level on txd after each transmitted byte during the number of bit periods programmed in us_ttgr: multi-drop mode when the field par in us_mr equals 11x (binary value), the USART is configured to run in multi-drop mode. in this case, the parity error bit pare in us_csr is set when data is detected with a parity bit set to identify an address byte. pare is cleared with the reset sta- tus bits command (rststa) in us_cr. if the parity bit is detected low, identifying a data byte, pare is not set. the transmitter sends an address byte (parity bit set) when a send address command (senda) is written to us_cr. in this case, the next byte written to us_thr will be transmit- ted as an address. after this, any byte transmitted will have the parity bit cleared. figure 10. synchronous and asynchronous modes: character transmission idle state duration between two characters time-guard value bit period = d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock
13 USART 1242e ? 12/01 break a break condition is a low signal level that has a duration of at least one character (including start/stop bits and parity). transmit break the transmitter generates a break condition on the txd line when sttbrk is set in us_cr (control register). in this case, the character present in the transmit shift register is com- pleted before the line is held low. to cancel a break condition on the txd line, the stpbrk command in us_cr must be set. the USART completes a minimum break duration of one character length. the txd line then returns to high level (idle state) for at least 12 bit periods, or the value of the time-guard regis- ter if it is greater than 12, to ensure that the end of break is correctly detected. then the transmitter resumes normal operation. the break is managed like a character: the sttbrk and the stpbrk commands are performed only if the transmitter is ready (bit txrdy = 1 in us_csr). the sttbrk command blocks the transmitter holding register (bit txrdy is cleared in us_csr) until the break has started. a break is started when the shift register is empty (any previous character is fully transmitted). us_csr.txempty is cleared. the break blocks the transmitter shift register until it is completed (high level for at least 12 bit periods after the stpbrk command is requested). in order to avoid unpredictable states: sttbrk and stpbrk commands must not be requested at the same time. once an sttbrk command is requested, further sttbrk commands are ignored until the break is ended (high level for at least 12 bit periods). all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending but not started (bit txrdy = 0 in us_csr) is ignored. it is not permitted to write new data in the transmit holding register while a break is in progress (stpbrk has not been requested), even though txrdy = 1 in us_csr. a new sttbrk command must not be issued until an existing break has ended (txempty=1 in us_csr). the standard break transmission sequence is: 1. wait for the transmitter ready. (us_csr.txrdy = 1) 2. send the sttbrk command. (write 0x0200 to us_cr) 3. wait for the transmitter ready. (bit txrdy = 1 in us_csr) 4. send the stpbrk command. (write 0x0400 to us_cr) the next byte can then be sent: 5. wait for the transmitter ready. (bit txrdy = 1 in us_csr) 6. send the next byte. (write byte to us_thr) each of these steps can be scheduled by using the interrupt if the bit txrdy in us_imr is set. for character transmission, the USART channel must be enabled before sending a break.
14 USART 1242e ? 12/01 receive break the receiver detects a break condition when all data, parity and stop bits are low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or at least one sample in synchronous operating mode. rxbrk is also asserted when an end-of-break is detected. both the beginning and the end of a break can be detected by interrupt if the bit us_imr.rxbrk is set. peripheral data controller channels (pdc) each USART channel is closely connected to a corresponding peripheral data controller channel. one is dedicated to the receiver. the other is dedicated to the transmitter. the pdc channel is programmed using us_tpr (transmit pointer) and us_tcr (transmit counter) for the transmitter and us_rpr (receive pointer) and us_rcr (receive counter) for the receiver. the status of the pdc is given in us_csr by the endtx bit for the transmit- ter and by the endrx bit for the receiver. the pointer registers (us_tpr and us_rpr) are used to store the address of the transmit or receive buffers. the counter registers (us_tcr and us_rcr) are used to store the size of these buffers. the receiver data transfer is triggered by the rxrdy bit and the transmitter data transfer is triggered by txrdy. when a transfer is performed, the counter is decremented and the pointer is incremented. when the counter reaches 0, the status bit is set (endrx for the receiver, endtx for the transmitter in us_csr) and can be programmed to generate an inter- rupt. while the counter is at zero, the status bit is asserted and transfers are disabled. interrupt generation each status bit in us_csr has a corresponding bit in us_ier (interrupt enable) and us_idr (interrupt disable), which controls the generation of interrupts by asserting the USART inter- rupt line connected to the advanced interrupt controller. us_imr (interrupt mask register) indicates the status of the corresponding bits. when a bit is set in us_csr and the same bit is set in us_imr, the interrupt line is asserted.
15 USART 1242e ? 12/01 channel test configurations the USART can be programmed to operate in three different test modes, using the field chmode in us_mr. automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd line, it is sent to the txd line. programming the transmitter has no effect. local loopback mode allows the transmitted characters to be received. txd and rxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the rxd pin level has no effect and the txd pin is held high, as in idle state. remote loopback mode directly connects the rxd pin to the txd pin. the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. figure 11. channel modes receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
16 USART 1242e ? 12/01 USART user interface notes: 1. the address takes into account the 2 lsbs [1:0], but the macrocell does not take these bits into account (left unconnec ted). therefore loading 0x0001, 0x0002 or 0x0003 on p_a[13:0] addresses the control register. 2. in the following register description, all undefined bits ( ??? ) read ? 0 ? . 3. if the user selects an address that is not defined in the above table, the value of p_d_out[31:0] is 0x00000000. table 2. USART memory map offset register name access reset state 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read/write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0 0x0014 channel status register us_csr read-only 0x18 0x0018 receiver holding register us_rhr read-only 0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read/write 0 0x0024 receiver time-out register us_rtor read/write 0 0x0028 transmitter time-guard register us_ttgr read/write 0 0x002c reserved ??? 0x0030 reserved for pdc connection ??? 0x0034 reserved for pdc connection ??? 0x0038 reserved for pdc connection ??? 0x003c reserved for pdc connection ???
17 USART 1242e ? 12/01 USART control register name: us_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset, disabling the receive function (rxdis is set internally). rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset, disabling the transmit function (txdis and stpbrk are set internally). rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. txen: transmitter enable 0 = no effect. 1 = the transmitter is enabled if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame, ovre and rxbrk in the us_csr. sttbrk: start break 0 = no effect. 1 = if break is not being transmitted, start transmission of a break after the characters present in us_thr and the transmit shift register have been transmitted. stpbrk: stop break 0 = no effect. 1 = if a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
18 USART 1242e ? 12/01 sttto: start time-out 0 = no effect. 1 = start waiting for a character before clocking the time-out counter. senda: send address 0 = no effect. 1 = in multi-drop mode only, the next character written to the us_thr is sent with the address bit set. USART mode register USART mode register name: us_mr access type: read/write usclks: clock selection (baud rate generator input clock) chrl: character length start, stop and parity bits are added to the character length. sync: synchronous mode select 0 = USART operates in asynchronous mode. 1 = USART operates in synchronous mode. 31 30 29 28 27 26 25 24 ??? filter ???? 23 22 21 20 19 18 17 16 ????? clko mode9 ? 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks ???? usclks selected clock 00clock 01fdiv1 10slow_clock (arm) 1 1 external (sck) chrl character length 005 bits 016 bits 107 bits 118 bits
19 USART 1242e ? 12/01 par: parity type nbstop: number of stop bits the interpretation of the number of stop bits depends on sync. note: 1.5 or 2 stop bits are reserved for the tx function. the rx function uses only the 1 stop bit (there is no check on the 2 stop bit timeslot if nbstop = 10). chmode: channel mode mode9: 9-bit character length 0 = chrl defines character length. 1 = 9-bit character length. mode9 has priority on character length. cklo: clock output select 0 = the USART does not drive the sck pin. 1 = the USART drives the sck pin if usclks[1] is 0. filter: receive line filter 0 = the USART does not filter receive line. 1 = the USART filters receive line using a three-sample filter (1/16 bit clock) (2 over 3 majority) pa r par i t y ty pe 000even parity 0 0 1 odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 10xno parity 1 1 x multi-drop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode the USART channel operates as an rx/tx USART. 0 1 automatic echo receiver data input is connected to the txd pin. 1 0 local loopback transmitter output signal is connected to receiver input signal. 1 1 remote loopback rxd pin is internally connected to txd pin.
20 USART 1242e ? 12/01 USART interrupt enable register name: us_ier access type: write-only rxrdy: enable rxrdy interrupt 0 = no effect. 1 = enables rxrdy interrupt. txrdy: enable txrdy interrupt 0 = no effect. 1 = enables txrdy interrupt. rxbrk: enable receiver break interrupt 0 = no effect. 1 = enables receiver break interrupt. endrx: enable end of receive transfer interrupt 0 = no effect. 1 = enables end of receive transfer interrupt. endtx: enable end of transmit interrupt 0 = no effect. 1 = enables end of transmit interrupt. ovre: enable overrun error interrupt 0 = no effect. 1 = enables overrun error interrupt. frame: enable framing error interrupt 0 = no effect. 1 = enables framing error interrupt. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
21 USART 1242e ? 12/01 pare: enable parity error interrupt 0 = no effect. 1 = enables parity error interrupt. timeout: enable time-out interrupt 0 = no effect. 1 = enables reception time-out interrupt. txempty: enable txempty interrupt 0 = no effect. 1 = enables txempty interrupt. comm_tx: enable comm_tx (from arm) interrupt 0 = no effect. 1 = enables comm_tx interrupt. comm_rx: enable comm_rx (from arm) interrupt 0 = no effect. 1 = enables comm_rx interrupt.
22 USART 1242e ? 12/01 USART interrupt disable register name: us_idr access type: write-only rxrdy: disable rxrdy interrupt 0 = no effect. 1 = disables rxrdy interrupt. txrdy: disable txrdy interrupt 0 = no effect. 1 = disables txrdy interrupt. rxbrk: disable receiver break interrupt 0 = no effect. 1 = disables receiver break interrupt. endrx: disable end of receive transfer interrupt 0 = no effect. 1 = disables end of receive transfer interrupt. endtx: disable end of transmit interrupt 0 = no effect. 1 = disables end of transmit interrupt. ovre: disable overrun error interrupt 0 = no effect. 1 = disables overrun error interrupt. frame: disable framing error interrupt 0 = no effect. 1 = disables framing error interrupt. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
23 USART 1242e ? 12/01 pare: disable parity error interrupt 0 = no effect. 1 = disables parity error interrupt. timeout: disable time-out interrupt 0 = no effect. 1 = disables receiver time-out interrupt. txempty: disable txempty interrupt 0 = no effect. 1 = disables txempty interrupt. comm_tx: disable comm_tx (from arm) interrupt 0 = no effect. 1 = disables comm_tx interrupt. comm_rx: disable comm_rx (from arm) interrupt 0 = no effect. 1 = disables comm_rx interrupt.
24 USART 1242e ? 12/01 USART interrupt mask register name: us_imr access type: read-only rxrdy: mask rxrdy interrupt 0 = rxrdy interrupt is disabled. 1 = rxrdy interrupt is enabled. txrdy: mask txrdy interrupt 0 = txrdy interrupt is disabled. 1 = txrdy interrupt is enabled. rxbrk: mask receiver break interrupt 0 = receiver break interrupt is disabled. 1 = receiver break interrupt is enabled. endrx: mask end of receive transfer interrupt 0 = end of receive transfer interrupt is disabled. 1 = end of receive transfer interrupt is enabled. endtx: mask end of transmit interrupt 0 = end of transmit interrupt is disabled. 1 = end of transmit interrupt is enabled. ovre: mask overrun error interrupt 0 = overrun error interrupt is disabled. 1 = overrun error interrupt is enabled. frame: mask framing error interrupt 0 = framing error interrupt is disabled. 1 = framing error interrupt is enabled. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
25 USART 1242e ? 12/01 pare: mask parity error interrupt 0 = parity error interrupt is disabled. 1 = parity error interrupt is enabled. timeout: mask time-out interrupt 0 = receive time-out interrupt is disabled. 1 = receive time-out interrupt is enabled. txempty: mask txempty interrupt 0 = txempty interrupt is disabled. 1 = txempty interrupt is enabled. comm_tx: mask comm_tx (from arm) interrupt 0 = comm_tx interrupt is disabled. 1 = comm_tx interrupt is enabled. comm_rx: mask comm_rx (from arm) interrupt 0 = comm_rx interrupt is disabled. 1 = comm_rx interrupt is enabled.
26 USART 1242e ? 12/01 USART channel status register name: us_csr access type: read-only rxrdy: receiver ready 0 = no complete character has been received since the last read of the us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1 = at least one complete character has been received and the us_rhr has not yet been read. txrdy: transmitter ready 0 = a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1 = there is no character in the us_thr. equal to zero when the USART is disabled or at reset. the transmitter enable command (in us_cr) sets this bit to one if the transmitter was previously disabled. rxbrk: break received/end of break 0 = no break received or end of break detected since the last reset status bits command in the control register. 1 = break received or end of break detected since the last reset status bits command in the control register. endrx: end of receiver transfer 0 = the end of transfer signal from the peripheral data controller channel dedicated to the receiver is inactive. 1 = the end of transfer signal from the peripheral data controller channel dedicated to the receiver is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the peripheral data controller channel dedicated to the transmitter is inactive. 1 = the end of transfer signal from the peripheral data controller channel dedicated to the transmitter is active. ovre: overrun error 0 = no byte has been transferred from the receive shift register to the us_rhr when rxrdy was asserted since the last reset status bits command. 1 = at least one byte has been transferred from the receive shift register to the us_rhr when rxrdy was asserted since the last reset status bits command. frame: framing error 0 = no stop bit has been detected low since the last reset status bits command. 1 = at least one stop bit has been detected low since the last reset status bits command. pare: parity error 1 = at least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command. 0 = no parity bit has been detected false (or a parity bit high in multi-drop mode) since last reset status bits command. 31 30 29 28 27 26 25 24 comm_rx comm_tx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
27 USART 1242e ? 12/01 timeout: receiver time-out 0 = there has not been a time-out since the last start time-out command or the time-out register is 0. 1 = there has been a time-out since the last start time-out command. txempty: transmitter empty 0 = there are characters in either us_thr or the transmit shift register, or the transmitter is disabled. 1 = there are no characters in either us_thr or the transmit shift register. txempty is 1 after parity, stop bit and time- guard have been transmitted. txempty is 1 after stop bit has been sent, or after time-guard has been sent if us_ttgr is not 0. equal to zero when the USART is disabled or at reset. transmitter enable command (in us_cr) sets this bit to one if the transmitter is disabled. comm_tx: (from arm) 0 = comm_tx is at 0. 1 = comm_tx is at 1. comm_rx: (from arm) 0 = comm_rx is at 0. 1 = comm_rx is at 1.
28 USART 1242e ? 12/01 USART receiver holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. when number of data bits is less than 8 bits, the bits are right-aligned. all non-sig- nificant bits read zero. USART transmitter holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. when number of data bits is less than 8 bits, the bits are right-aligned. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr
29 USART 1242e ? 12/01 USART baud rate generator register name: us_brgr access type: read/write cd: clock divisor this register has no effect if synchronous mode is selected with an external clock. notes: 1. in synchronous mode, when either external clock (clk_ext or fdiv1) is selected, the value programmed must be even to ensure a 50:50 mark:space ratio. in synchronous mode, when the internal clock (clock) is selected, the cd can be even and the duty clock is 50:50. 2. clock divisor bypass (cd = 1) must not be used when the internal clock (clock) is selected (usclks = 0). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd description 0 disables clock 1 clock divisor bypass 2 to 65535 baud rate (asynchronous mode) = selected clock / (16 x cd) baud rate (synchronous mode) = selected clock / cd
30 USART 1242e ? 12/01 USART receiver time-out register name: us_rtor access type: read/write to: time-out value when a value is written to this register, a start time-out command is automatically performed. time-out duration = to x 4 x bit period USART transmitter time-guard register name: us_ttgr access type: read/write tg: time-guard value time-guard duration = tg x bit period 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 to to description 0 disables the rx time-out function. 1 - 255 the time-out counter is loaded with to when the start time-out command is given or when each new data character is received (after reception has started). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg tg 0 disables the tx time-guard function. 1 - 255 txd is inactive high after the transmission of each character for the time-guard duration.
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