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d a t a sh eet product speci?cation 2003 feb 19 integrated circuits OM5926HN i 2 c-bus sim card interface
2003 feb 19 2 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN contents 1 features 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning information 7.1 pinning 7.2 pin description 8 functional description 8.1 i 2 c-bus control 8.2 power supply 8.3 dc-to-dc converter 8.4 power-down mode 8.5 off mode 8.6 sequencer and clock counter 8.7 clock circuitry 8.8 protection 8.9 i/o circuitry 9 limiting values 10 handling 11 thermal characteristics 12 characteristics 13 application information 14 package outline 15 soldering 15.1 introduction to soldering surface mount packages 15.2 reflow soldering 15.3 wave soldering 15.4 manual soldering 15.5 suitability of surface mount ic packages for wave and reflow soldering methods 16 data sheet status 17 definitions 18 disclaimers 19 purchase of philips i 2 c components
2003 feb 19 3 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 1 features subscriber identification module (sim) card interface in accordance with gsm11.11, gsm11.12 (global system for mobile communication) and iso 7816 requirements v cc regulation (3 or 5 v 8%) with controlled rise and fall times one protected and buffered pseudo-bidirectional i/o line (i/o referenced to v cc and simi/o referenced to v ddi ) clock generation (up to 10 mhz) with synchronous start and frequency quadrupling clock stop low, clock stop high or 1.25 mhz (from internal oscillator) for cards power-down mode automatic activation and deactivation sequences of an independent sequencer automatic processing of pin rst with the counting of the 41928 clk cycles for the beginning of the answer-to-reset (atr) warm reset command supply voltage supervisor for power-on reset, spike killing and emergency deactivation in case of supply drop-out dc-to-dc converter (doubler, tripler or follower) allowing operation in a 3 or 5 v environment (2.5 v dd 6v) enhanced electrostatic discharge (esd) protection on card side (6 kv minimum) power-down mode with several active features and current reduction off mode with 5 m a current control from a microcontroller via a 400 khz slave i 2 c-bus (address 48h) interface signals supplied by an independent voltage (1.5 v ddi 6 v). 2 applications gsm mobile phones. 3 general description the OM5926HN is a low cost one chip sim interface, in accordance with gsm11.11, gsm11.12 with card current limitation. controlled by the i 2 c-bus, it is optimized in terms of board space, external components count and connection count (see chapter 13). due to the integrated dc-to-dc converter, the device ensures full cross-compatibility between 3 or 5 v cards and 3 or 5 v environments. the very low power consumption in power-down mode and off mode saves battery power. 4 ordering information type number package name description version OM5926HN hvqfn20 plastic, heatsink very thin quad ?at package; no leads; 20 terminals; body 5 5 0.85 mm sot662-1
2003 feb 19 4 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 5 quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage on pins v dds and v ddp 2.5 - 6v i dd supply current on pins v dds and v ddp off mode; v dd =3v -- 5 m a power-down mode; v dd =3v; v cc =5v; i cc = 100 m a; simclk connected to pgnd or v ddi ; clk is stopped -- 500 m a active mode; v dd =3v; v cc =3v; i cc = 6 ma; f clk = 3.25 mhz -- 18 ma active mode; v dd =3v; v cc =5v; i cc = 10 ma; f clk = 3.25 mhz -- 50 ma active mode; v dd =5v; v cc =3v; i cc = 6 ma; f clk = 3.25 mhz -- 10 ma active mode; v dd =5v; v cc =5v; i cc = 10 ma; f clk = 3.25 mhz -- 30 ma v ddi interface signal supply voltage 1.5 - 6v v cc card supply voltage 5 v card; active mode; 0 2003 feb 19 5 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 6 block diagram handbook, full pagewidth dc/dc converter supply supervisor sequencer oscillator i 2 c-bus and registers sad0 del OM5926HN sda 20 k w pull-up to v ddi simi/o simclk mgu806 scl pwroff v ddi 10 nf pres simmerrn sad1 clock counter clock circuitry sgnd 5 s3 100 nf 200 nf vup pgnd v cc rst i/o clk 100 nf 2.2 m f v ddp s4 s1 s2 7 3 8 6 15 18 19 16 9 13 14 10 12 4 20 2 17 1 analog drivers and protections 100 nf v dds 11 fig.1 block diagram.
2003 feb 19 6 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 7 pinning information 7.1 pinning 7.2 pin description table 1 hvqfn20 package handbook, halfpage i/o vup v ddp s2 s4 simi/o scl sda del v ddi OM5926HN mgu807 sgnd v cc clk rst v dds s3 s1 pgnd pwroff simclk 2 1 3 4 5 9 10 8 7 6 16 18 20 17 19 15 13 11 14 12 fig.2 pin configuration (bottom view). symbol pin description simclk 1 external clock input pwr off 2 control input for entering the off mode (active low) s1 3 capacitor connection for the dc-to-dc converter (between s1 and s2) pgnd 4 power ground s3 5 capacitor connection for the dc-to-dc converter (between s3 and s4) v ddp 6 power supply voltage s4 7 capacitor connection for the dc-to-dc converter (between s3 and s4) s2 8 capacitor connection for the dc-to-dc converter (between s1 and s2) vup 9 dc-to-dc converter output (must be decoupled with a 100 nf capacitor to ground) i/o 10 input/output to and from the card reader (c7) sgnd 11 signal ground clk 12 clock output to the card reader (c3) v cc 13 supply voltage to the card reader (c1) rst 14 reset output to the card reader (c2) v dds 15 signal supply voltage del 16 external capacitor connection for the delay on the voltage supervisor simi/o 17 input/output to and from the microcontroller (internal 20 k w pull-up resistor connected to v ddi ) v ddi 18 supply voltage for the interface signals with the system sda 19 i 2 c-bus serial data input/output scl 20 i 2 c-bus serial clock input
2003 feb 19 7 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 8 functional description the block diagram of the OM5926HN is shown in fig.1. the functional blocks will be described in the following sections. it is assumed that the reader of this specification is familiar with gsm11.11 and iso 7816 terminology. 8.1 i 2 c-bus control the i 2 c-bus is used: to configure the clock to the card in active mode ( 1 4 f simclk and f simclk ) to configure the clock to the card in power reduction mode (stop low, stop high or 1.25 mhz derived from the internal oscillator) for selecting operation with a 3 or 5 v card for starting or stopping sessions (cold reset) for initiating a warm reset for entering or leaving the power-down mode to request the card status (hardware problem occurred, unresponsive card after activation, supply drop-out detected by the voltage supervisor, card powered or not) to configure the simi/o and i/o pins in the high-impedance state. 8.1.1 structure of the i 2 c- bus data frames commands to the OM5926HN: C start/address/write C command byte C stop. the fixed address is 0100100. the command bits are described in table 2. commands are executed on the rising edge of the 9th scl pulse of the command byte. status from the OM5926HN (see table 4). the fixed address is 0100100. table 2 description of the command bits; note 1 note 1. all bits are cleared at reset. table 3 clock selection to the card at power-down bit symbol description 0 start/stop logic 1 initiates an activation sequence and a cold reset procedure. logic 0 initiates a deactivation sequence. 1 warm logic 1 initiates a warm reset procedure. it will be automatically reset by hardware when the card starts answering, or when the 2 times 41928 clk pulses have expired without answer from the card. 2 3 v/5 vn logic 1 sets the card supply voltage v cc to 3 v. logic 0 sets the card supply voltage v cc to 5 v. 3 pdown logic 1 applies on the clk pin the frequency de?ned by bits clkpd1 and clkpd2, and enters a reduced current consumption mode. logic 0 sets the circuit back to normal mode. 4 clkpd1 these 2 bits determine the clock to the card at power-down as shown in table 3. 5 clkpd2 6 dt/dfn logic 0 sets f clk to 1 4 f simclk (in active mode). logic 1 sets f clk to f simclk . 7 i/oen logic 1 will transfer i/o to simi/o. logic 0 sets i/o and simi/o to the high-impedance state. clkpd2 clkpd1 function 0 0 clock stop low 0 1 clock is 1 2 f osc 1 0 clock stop high 1 1 dont use
2003 feb 19 8 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN table 4 description of the status bits; note 1 note 1. in the event of supply drop-out during a session, the card will be automatically deactivated, bit start = 0 and the corresponding status bit = 1. the status bit will be logic 0 when the microcontroller reads out the status register, on the 7th scl pulse. after a supply drop-out, bit supl = 1. bit symbol description 0 - bit 0 is not used and is ?xed to logic 1. 1 - bit 1 is not used and is ?xed to logic 0. 2 - bit 2 is not used and is ?xed to logic 0. 3 supl logic 1 when the voltage supervisor has signalled a fault. logic 0 when the status is read-out. 4 - bit 4 is not used and is ?xed to logic 0. 5 mute logic 1 when a card has not answered after 2 times 41928 clk cycles. logic 0 when the status is read-out. 6 early logic 1 when a card has answered between 200 and 352 clk cycles. logic 0 when the status is read-out. 7 active logic 1 when the card is power-on. logic 0 when the card is power-off. 8.2 power supply the circuit operates within a supply voltage range of 2.5 to 6 v. the supply pins are v dds and sgnd. pins v ddp and pgnd only supply the dc-to-dc converter for the analog drivers to the card and must be decoupled externally because of the large current spikes that the card and the dc-to-dc converter can create. an integrated spike killer ensures the card contacts remain inactive during power-up or power-down. an internal voltage reference is generated which is used for the dc-to-dc converter, the voltage supervisor and the v cc generator. all interface signals with the microcontroller ( pwroff, simclk, scl, sda and simi/o) are referenced to a separate supply pin v ddi , which may be different from v dd (1.5 v ddi 6 v). the pull-up resistors on bus lines sda and scl may be referenced to a voltage higher than v ddi . this allows the use of peripherals which do not operate at v ddi . the voltage supervisor (see fig.3) senses v dds and generates an alarm pulse when v dd is too low to ensure proper operation. the alarm pulse width (t w ) is defined by an external capacitor connected to pin del (1 ms per 1 nf typical). during the alarm pulse, the i 2 c-bus is unresponsive but will become operational at the end of the alarm pulse. bit supl is set as long as the status has not been read. the alarm pulse will also block any spurious signals on the card contacts during microcontroller reset, and will force an automatic deactivation of the contacts in the event of supply drop-out. if a supply drop-out occurs during a session, the start bit is cleared and an automatic deactivation is initiated.
2003 feb 19 9 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN handbook, full pagewidth mgr436 v dds del i 2 c-bus unresponsive i 2 c-bus unresponsive i 2 c-bus unresponsive i 2 c-bus ok status read after event i 2 c-bus ok simerr (internal signal) t w t w fig.3 voltage supervisor. 8.3 dc-to-dc converter the whole circuit is powered by v dds , except for the v cc generator, the other card contact buffers and the interface signals. the dc-to-dc converter acts as a doubler or a tripler, depending on the supply voltage v dd and the card supply voltage v cc . there are basically four possible situations: v dd = 3 v and v cc = 3 v; the dc-to-dc converter acts as a doubler with a regulation of v vup at approximately 4.5 v v dd = 3 v and v cc = 5 v; the dc-to-dc converter acts as a tripler with a regulation of v vup at approximately 6.5 v v dd = 5 v and v cc = 3 v; the dc-to-dc converter is disabled and v dd is applied to pin vup v dd = 5 v and v cc = 5 v; the dc-to-dc converter acts as a doubler with a regulation of v vup at approximately 6.5 v. the recognition of the supply voltage is done by the OM5926HN at approximately 3.3 v. when a card session is requested by the microcontroller, the sequencer will first start the dc-to-dc converter, which is a switched capacitors type, clocked by an internal oscillator at a frequency f osc of approximately 2.5 mhz. the output voltage v vup is regulated at approximately 4.5 or 6.5 v and subsequently fed to the v cc generator. v cc and pgnd are used as a reference for all other card contacts.
2003 feb 19 10 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 8.4 power-down mode the power-down mode is used for current consumption reduction when the card is in sleep mode. for entering the power-down mode, the microcontroller must first select the state of clk (stop low, stop high or 1.25 mhz from the internal oscillator) using the clkpd1 and clkpd2 bits. subsequently, the microcontroller sends the command pdown, clk is switched to the value predefined by the clkpd1 and clkpd2 bits, and simclk may be stopped (high or low). if the selected clk is stopped, the biasing currents in the buffers to the card will be reduced. the voltage supervisor and all control functions remain active. the maximum current taken by the card when clk is stopped should be less than 5 ma. before leaving the power-down mode, the clock signal must first be applied to simclk, then the pdown bit must be set to logic 0. 8.5 off mode the off mode is entered when the pwroff signal is low. in this mode, no function is valid. this mode avoids switching off the power supply of the device, and gives a current consumption less than 5 m a. before entering the off mode, the card must be deactivated. the off mode is left when the pwroff signal returns to high. this re-initializes the voltage supervisor, and has the same effect as a reset of the device. 8.6 sequencer and clock counter the sequencer handles the activation and deactivation sequences in accordance with gsm11.11 and iso 7816, even in the event of an emergency (card take-out, short-circuit and supply drop-out). the sequencer is clocked with the internal oscillator frequency (f osc ). the activation is initiated with the start command (only if the card is present, and if the voltage supervisor does not detect a fault on the supply). during activation, v cc goes high and subsequently i/o is enabled and clk is started with rst = low. the clock counter counts the clk pulses until a start bit is detected on i/o. after 41928 clk pulses, if no start bit on i/o has been detected, the sequencer toggles rst to high and counts another 41928 clk pulses. if, again, no start bit has been detected, the mute bit is set in the status register. if a start bit has been detected during the two 41928 clk pulses slots, the clock counter is stopped, rst is kept at the same level and the session can go on between the card and the system. the clock counter ignores any start bit during the first 200 clk pulses of both slots. if a start bit is detected between 200 and 352 clk pulses of both slots, then the early bit is set in the status register. the deactivation is initiated either by the microcontroller (stop command), or automatically by the OM5926HN in the event of a short-circuit or supply voltage drop-out detected by the voltage supervisor. during deactivation, rst will go low, clk is stopped, i/o is disabled and v cc goes low. 8.7 clock circuitry the clock to the card is either derived from the simclk pin (2 to 20 mhz) or from the internal oscillator. during a card session, f clk may be chosen to be 1 4 f simclk or f simclk depending on the state of the dt/dfn bit. for the card sleep mode, clk may be chosen stop low, stop high or 1 2 f osc (1.25 mhz) with bits clkpd1 and clkpd2. this predefined value will be applied to clk when the pdown bit is set to logic 1. the first clk pulse has the correct width, and all frequency changes are synchronous, ensuring that no pulse is smaller than 45% of the shortest period. the duty cycle is within 45 and 55% in the stable state, the rise and fall times are less than 8% of the period and precautions must be taken to ensure that there is no overshoot or undershoot.
2003 feb 19 11 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 8.7.1 a ctivation sequence figure 4 shows the activation sequence. when the card is inactive, v cc , clk, rst and i/o are low, with low-impedance with respect to ground. the dc-to-dc converter is stopped. simi/o is pulled high at v ddi via the 20 k w pull-up resistor. when all conditions are met (supply voltage, card present, no hardware problems), the microcontroller may initiate an activation sequence by setting the start bit to logic 1 (t 0 ) via the i 2 c-bus: 1. the dc-to-dc converter is started (t 1 ). 2. v cc starts rising from 0 to 3 v or 0 to 5 v, according to the state of the 3 v/5 vn control bit, with a controlled rise time of 0.17 v/ m s typically (t 2 ). 3. i/o buffer is enabled in reception mode (t 3 ). 4. clk is sent to the card reader with rst = low, and the count of 41928 clk pulses is started (t 4 =t act ). 5. if a start bit is detected on i/o, the clock counter is stopped with rst = low. if not, rst = high, and a new count of 41928 clk pulses is started (t 5 ). if a start bit is detected on i/o and the clock counter is stopped with rst = high, the card session may continue. if not, the mute bit is set in the status register. the microcontroller may initiate a deactivation sequence by setting the start bit to logic 0. if a start bit is detected during the first 200 clk pulses of each count slot, then it will not be taken into account. if a start bit is detected during 200 and 352 clk pulses of each slot, then bit early is set in the status register. the microcontroller may initiate a deactivation sequence by setting the start bit to logic 0. the sequencer is clocked by 1 64 f osc which leads to a time interval t of 25 m s typically. thus t 1 =0to 1 2 t; t 2 =t 1 + 3 2 t; t 3 =t 1 + 7 2 t; t 4 =t 1 + 4 t and t 5 depends on the simclk frequency. handbook, full pagewidth mgr437 start v cc i/o clk rst simi/o t 0 , t 1 t 2 t 4 (= t act ) t 3 answer to reset (atr) begin the 200 first clk pulses are masked t 5 fig.4 activation sequence.
2003 feb 19 12 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 8.7.2 d eactivation sequence figure 5 shows the deactivation sequence. when the session is completed, the microcontroller sets the start bit to logic 0. the circuit will then execute an automatic deactivation sequence: 1. card reset, rst goes low (t 10 ). 2. clk is stopped (t 11 ). 3. i/o goes low (t 12 ). 4. v cc falls to 0 v with typically 0.17 v/ m s slew rate (t 13 ). the deactivation is completed when v cc reaches 0.4 v (t de ). 5. the dc-to-dc converter is stopped and clk, rst, v cc and i/o become low-impedance with respect to pgnd (t 14 ). t 10 < 1 64 t; t 11 =t 10 + 1 2 t; t 12 =t 10 + t; t 13 =t 12 +5 m s and t 14 =t 10 +4t. handbook, full pagewidth mgr438 start rst i/o v cc clk t 10 t 11 t 12 t 13 t 14 t de fig.5 deactivation sequence.
2003 feb 19 13 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 8.8 protection two hardware fault conditions are monitored by the circuit: short-circuits between v cc and other contacts supply drop-out. when one of these problems is detected during a card session, the security logic block initiates an automatic deactivation of the contacts (see fig.6). 8.9 i/o circuitry the idle state is realized by both i/o and simi/o being pulled high (via a 10 k w pull-up resistor from i/o to v cc and via a20k w pull-up resistor from simi/o to v ddi ). i/o is referenced to v cc and simi/o to v ddi , thus allowing operation with v cc 1 v dd 1 v ddi . when configuration bit i/oen is logic 0, then i/o and simi/o are independent. when bit i/oen is logic 1, then the data transmission between i/o and simi/o is enabled. the first side on which a falling edge occurs becomes the master. an anti-latch circuit disables the detection of falling edges on the other side, which becomes a slave. after a delay time (t d ) of <500 ns on the falling edge, the n transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. when the master goes back to logic 1, the p transistor on the slave side is turned on during t d , and then both sides return to their idle states. the maximum frequency on these lines is 1 mhz. handbook, full pagewidth mgr439 simerr start status readout rst i/o v cc clk (internal signal) fig.6 emergency deactivation.
2003 feb 19 14 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 9 limiting values in accordance with the absolute maximum rating system (iec 60134). 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handle metal oxide semiconductor (mos) devices. 11 thermal characteristics symbol parameter conditions min. max. unit v ddp power supply voltage - 0.5 +6.5 v v dds signal supply voltage - 0.5 +6.5 v v ddi interface signal supply voltage - 0.5 +6.5 v v i(n) input voltage pins 1, 2 and 17 - 0.5 +6.5 v pin 16 - 0.5 v dds + 0.5 v pins 19 and 20 - 0.5 +6.5 v pins 10, 12 and 14 - 0.5 v cc + 0.5 v pin 13 - 0.5 +6.5 v pin 9 - 0.5 +7.5 v pins 3, 5, 7 and 8 - 0.5 v vup + 0.5 v p tot continuous total power dissipation t amb = - 40 to +85 c - 230 mw t j operating junction temperature - 125 c t stg ic storage temperature - 55 +150 c v esd(n) electrostatic discharge voltage on pins 10, 12, 13 and 14 - 6+6kv on any other pin - 2+2kv symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 35 k/w
2003 feb 19 15 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 12 characteristics v dd =3v; v ddi = 1.5 v; f simclk = 13 mhz; f clk = 3.25 mhz; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dd supply voltage on pins v dds and v ddp 2.5 - 6.0 v i dd supply current on pins v dds and v ddp off mode -- 5 m a inactive mode -- 50 m a power-down mode; v cc =5v; i cc = 100 m a; simclk connected to sgnd or v ddi ; clk is stopped -- 500 m a active mode; v cc =3v; i cc =6ma -- 18 ma active mode; v cc =5v; i cc =10ma -- 50 ma active mode; v dd =5v; v cc =3v; i cc =6ma -- 10 ma active mode; v dd =5v; v cc =5v; i cc =10ma -- 30 ma v ddi interface signal supply voltage 1.5 - 6v i ddi interface signals supply current simclk connected to pgnd or v ddi -- 3 m a f simclk = 13 mhz; v ddi = 1.5 v -- 120 m a f simclk = 13 mhz; v ddi =6v -- 1.2 ma v th(vdd) threshold voltage on v dd falling edge 2 - 2.3 v v hys(vdd) hysteresis voltage on v dd 40 - 200 mv v th(del) threshold voltage on pin del - 1.38 - v v del voltage on pin del -- v dd v i ch(del) charge current on pin del - 0.5 - 1 - 2.5 m a i dch(del) discharge current on pin del v del =v dd 0.5 -- ma t w alarm pulse width c del =10nf 15 - 25 ms pin simclk f i(simclk) clock input frequency 0 - 20 mhz t f fall time -- 1 m s t r rise time -- 1 m s v il low-level input voltage 0 - 0.3v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i l leakage current -- 3 m a dc-to-dc converter 1 2 f osc oscillator frequency 1 - 1.6 mhz v vup voltage on pin vup 5 v card - 6.0 - v 3 v card - 4.5 - v
2003 feb 19 16 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN pin sda (open-drain) v il low-level input voltage - 0.3 - +0.3v ddi v v ih high-level input voltage 0.7v ddi - 6v i lh high-level leakage current -- 1 m a i il low-level input current depends on the pull-up resistor ---m a v ol low-level output voltage i ol =3ma -- 0.3 v pin scl (open-drain) v il low-level input voltage - 0.3 - +0.3v ddi v v ih high-level input voltage 0.7v ddi - 6v i li input leakage current -- 1 m a pin pwr off v il low-level input voltage 0 - 0.3v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i li input leakage current -- 1 m a pin rst v o output voltage inactive mode; i o =1ma - 0.3 - +0.3 v i o output current inactive mode; pin rst grounded --- 1ma v ol low-level output voltage i ol = 200 m a - 0.2 - +0.3 v v oh high-level output voltage i oh < - 200 m av cc - 0.5 - v cc + 0.2 v t f fall time c l =30pf -- 0.5 m s t r rise time c l =30pf -- 0.5 m s pin clk v o output voltage inactive mode; i o =1ma - 0.3 - +0.3 v i o output current inactive mode; pin clk grounded --- 1ma v ol low-level output voltage i ol = 200 m a - 0.2 - +0.3 v v oh high-level output voltage i oh = - 200 m av cc - 0.5 - v cc + 0.2 v t f fall time c l =30pf -- 8ns t r rise time c l =30pf -- 8ns f clk clock frequency 1 mhz power-down con?guration 1 - 1.6 mhz regular activity 0 - 10 mhz d duty factor c l =30pf 45 - 55 % pin v cc (with 200 nf capacitor) v o output voltage inactive mode; i o =1ma -- 0.3 v active mode; 5 v card; no load 4.85 5.10 5.40 v active mode; 3 v card; no load 2.8 3.05 3.25 v 5 v card; pdown = 1; i cc < 5 ma 4.6 - 5.4 v 3 v card; pdown = 1; i cc < 5 ma 2.75 - 3.25 v symbol parameter conditions min. typ. max. unit
2003 feb 19 17 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN v o output voltage active mode; 5 v card; with static load 4.60 - 5.40 v 3 v card; with static load 2.75 - 3.25 v 5 v card; 40 nas pulses; note 1 4.60 - 5.40 v 3 v card; 12 nas pulses; note 2 2.75 - 3.25 v i o output current inactive mode; pin v cc grounded --- ma v cc =5v; v dd < 3.7 v -- 15 ma v cc =5v; v dd > 3.7 v -- 20 ma v cc =3v; v dd < 3.7 v -- 10 ma v cc =3v; v dd > 3.7 v -- 15 ma sr slew rate on v cc (rise and fall) c l(max) = 300 nf 0.05 0.17 0.25 v/ m s pin i/o (internal pull-up resistor to v cc ) v o output voltage inactive mode; i o =1ma -- 0.3 v i o output current inactive mode; pin i/o grounded --- 1ma v ol low-level output voltage i ol =1ma - 0.2 - +0.3 v v oh high-level output voltage +25 m a< i oh < - 25 m a 0.8v cc - v cc + 0.2 v v il low-level input voltage - 0.3 - +0.8 v v ih high-level input voltage 1.5 - v cc + 0.3 v i lih high-level input leakage current -- 10 m a i il low-level input current --- 600 m a t t(di) data input transition time c l =30pf -- 1.2 m s t t(do) data output transition time c l =30pf -- 0.5 m s t d delay time on falling edge -- 500 ns r pu(int) internal pull-up resistance between pins i/o and v cc 13 - 20 k w pin simi/o (internal pull-up resistor to v ddi ) v ol low-level output voltage i ol =1ma - 0.2 - +0.3 v v oh high-level output voltage with internal 20 k w pull-up resistor to v ddi ; i o =10 m a v ddi - 0.3 - v ddi + 0.2 v v il low-level input voltage - 0.3 - +0.3v ddi v v ih high-level input voltage 0.7v ddi - v ddi + 0.3 v i lih high-level input leakage current -- 10 m a i il low-level input current with internal 20 k w pull-up resistor to v ddi ; v i =0v -- m a t t(di) data input transition time c l =30pf -- 1.2 m s t t(do) data output transition time c l =30pf -- 0.5 m s t d delay time on falling edge -- 500 ns symbol parameter conditions min. typ. max. unit v ddi C 20 k w ----------------
2003 feb 19 18 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN notes 1. current pulses applied on v cc (5 v card): a) continuous spikes; 20 ma amplitude; i dc = 0; 100 ns duration; pause 100 ns (2 nas; l av = 10 ma; f = 5 mhz). b) continuous spikes; 20 ma amplitude; i dc = 0; 400 ns duration; pause 400 ns (8 nas; l av = 10 ma; f = 1.25 mhz). c) continuous spikes; 15 ma amplitude; i dc = 5 ma; 150 ns duration; pause 300 ns (2.25 nas; l av = 10 ma; f = 2.22 mhz). d) random spikes; 200 ma amplitude; i dc = 5 ma; 200 ns duration; pause between 0.1 and 500 ms (40 nas) (see fig.7). e) random spikes; 100 ma amplitude; i dc = 0; 400 ns duration; pause between 0.1 and 500 ms (40 nas). f) random spikes; 195 ma amplitude; i dc = 5 ma; 200 ns duration; pause between 0.1 and 500 ms (39 nas). 2. current pulses applied on v cc (3 v card): a) continuous spikes; 12 ma amplitude; i dc = 0; 100 ns duration; pause 100 ns (1.2 nas; l av = 6 ma; f = 5 mhz). b) continuous spikes; 12 ma amplitude; i dc = 0; 400 ns duration; pause 400 ns (4.8 nas; l av = 6 ma; f = 1.25 mhz). c) continuous spikes; 9 ma amplitude; i dc = 3 ma; 150 ns duration; pause 300 ns (2.25 nas; l av = 6 ma; f = 2.22 mhz). d) random spikes; 60 ma amplitude; i dc = 5 ma; 200 ns duration; pause between 0.1 and 500 ms (12 nas). e) random spikes; 30 ma amplitude; i dc = 0; 400 ns duration; pause between 0.1 and 500 ms (12 nas). f) random spikes; 57 ma amplitude; i dc = 3 ma; 200 ns duration; pause between 0.1 and 500 ms (11.4 nas). r pu(int) internal pull-up resistance between pins simi/o and v ddi 16 - 26 k w timing t act activation time -- 150 m s t de deactivation time -- 120 m s symbol parameter conditions min. typ. max. unit handbook, full pagewidth time (ns) current (ma) mgu808 200 ma 200 ns fig.7 example of 200 ma and 200 ns current pulse.
2003 feb 19 19 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 13 application information handbook, full pagewidth 2.7 k w 2.7 k w 10 nf 100 nf vbat 100 nf 100 nf (1) (5) (3) (3) (3) (3) (2) 100 nf (1) s3 pgnd s1 pwroff simclk system controller vbat mgu809 vbat 100 nf (1) 100 nf 22 m f OM5926HN scl sda v ddi simi/o v dds v cc rst 14 13 12 11 5 4 3 2 1 10 9 8 7 6 15 16 17 18 19 20 clk (4) c1 sgnd del i/o vup s2 s4 v ddp c2 c3 c5 c6 c7 fig.8 application information. (1) capacitors on the dc-to-dc converter must have esr less than 100 m w and must be placed close to the chip (some mm). (2) capacitor on v cc must have esr less than 100 m w . (3) tracks from the chip to the smart card connector must be as short as possible. if v cc track exceeds 2 cm, then 2 capacitors have to be used: one near the chip, the second near the contact. (4) clk signal has to be routed far from i/o and rst. (5) c5 must be electrically linked to chips gnd without ground loop.
2003 feb 19 20 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 14 package outline 0.65 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 2.6 e 2 2.6 0.38 0.23 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot662-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot662-1 hvqfn20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 610 20 16 15 11 5 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-22 a c c b v m w m e (1) d (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included.
2003 feb 19 21 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 15 soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 15.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferably be kept: below 220 c for all the bga packages and packages with a thickness 3 2.5mm and packages with a thickness <2.5 mm and a volume 3 350 mm 3 so called thick/large packages below 235 c for packages with a thickness <2.5 mm and a volume <350 mm 3 so called small/thin packages. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 feb 19 22 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 15.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso, vssop not recommended (6) suitable
2003 feb 19 23 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 16 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 17 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 feb 19 24 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN 19 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2003 feb 19 25 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN notes
2003 feb 19 26 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN notes
2003 feb 19 27 philips semiconductors product speci?cation i 2 c-bus sim card interface OM5926HN notes
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613502/01/pp 28 date of release: 2003 feb 19 document order number: 9397 750 10124

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