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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a quad, 12-bit dac voltage output with readback dac8412/DAC8413 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram input reg a output reg a dac a a0 a1 data i/o input reg b input reg c input reg d output reg b output reg c output reg d dac b dac c dac d control logic i/o port r/w cs reset ldac dgnd 12 v logic v dd v outa v outb v outc v outd v ss v refh v refl features +5 to 6 15 volt operation unipolar or bipolar operation true voltage output double-buffered inputs reset to min or center scale fast bus access time readback applications automatic test equipment digitally controlled calibration servo controls process control equipment general description the dac8412 and DAC8413 are quad, 12-bit voltage output dacs with readback capability. built using a complementary bicmos process, these monolithic dacs offer the user very high package density. output voltage swing is set by the two reference inputs v refh and v refl . by setting the v refl input to 0 volts and v refh to a positive voltage, the dac will provide a unipolar positive output range. a similar configuration with v refh at 0 volts and v refl at a negative voltage will provide a unipolar negative output range. bipolar outputs are configured by connecting both v refh and v refl to nonzero voltages. this method of setting output voltage range has advantages over other bipolar offsetting meth- ods because it is not dependent on internal and external resis- tors with different temperature coefficients. digital controls allow the user to load or read back data from any dac, load any dac and transfer data to all dacs at one time. an active low reset loads all dac output registers to mid- scale for the dac8412 and zero scale for the DAC8413. the dac8412/DAC8413 are available in 28-pin plastic dip, cerdip, plcc and lcc packages. they can be operated from a wide variety of supply and reference voltages with supplies ranging from single +5 volt to 15 volts, and references from +2.5 to 10 volts. power dissipation is less than 330 mw with 15 volt supplies and only 60 mw with a +5 volt supply. for mil-std-883 applications, contact your local adi sales office for the dac8412/DAC8413/883 data sheet which speci- fies operation over the C55 c to +125 c temperature range. all 883 parts are also available on standard military drawings 5962-91-76401mxa through -76404m3a. inl vs. code over temperature
dac8412/DAC8413Cspecifications electrical characteristics parameter symbol conditions min typ max units integral linearity e inl 0.25 0.5 lsb integral linearity f inl 1 lsb differential linearity dnl monotonic over temperature C1 lsb min scale error v zse r l = 2 k w 2 lsb full-scale error v fse r l = 2 k w 2 lsb min scale tempco tcv zse r l = 2 k w 15 ppm/ c full-scale tempco tcv fse r l = 2 k w 20 ppm/ c matching performance linearity matching 1 lsb reference positive reference input range note 2 v refl + 2.5 v dd C 2 5 v negative reference input range note 2 C10 v refh C 2.5 v reference high input current i refh C2.75 +1.5 +2.75 ma reference low input current i refl 0 +2 +2.75 ma amplifier characteristics output current i out C5 +5 ma settling time t s to 0.01% 6 m s slew rate sr 10% to 90% 2.2 v/ m s logic characteristics logic input high voltage v inh t a = +25 c 2.4 v logic input low voltage v inl t a = +25 c 0.8 v logic output high voltage v oh i oh = +0.4 ma 2.4 v logic output low voltage v ol i ol = C1.6 ma 0.4 v logic input current i in 1 m a input capacitance c in 8pf crosstalk >72 db large signal bandwidth C3 db, v refh = 0 to +10 v p-p 160 khz logic timing characteristics note 3 write chip select write pulse width t wcs 80 40 ns write setup t ws t wcs = 80 ns 0 ns write hold t wh t wcs = 80 ns 0 ns address setup t as 0ns address hold t ah 0ns load setup t ls 70 30 ns load hold t lh 30 10 ns write data setup t wds t wcs = 80 ns 20 ns write data hold t wdh t wcs = 80 ns 0 ns load pulse width t lwd 170 130 ns reset pulse width t reset 140 100 ns read chip select read pulse width t rcs 130 100 ns read data hold t rdh t rcs = 130 ns 0 ns read data setup t rds t rcs = 130 ns 0 ns data to hi z t dz c l = 10 pf 150 ns chip select to data t csd c l = 100 pf 120 160 ns supply characteristics power supply sensitivity pss 14.25 v v dd 15.75 v 150 ppm/v positive supply current i dd v refh = +2.5 v 8.5 12 ma negative supply current i ss C10 C6.5 ma power dissipation p diss 330 mw notes 1 all supplies can be varied 5%, and operation is guaranteed. device is tested with nominal supplies. 2 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 3 all input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. specifications subject to change without notice. rev. c C2C (@ v dd = +15.0 v, v ss = C15.0 v, v logic = +5.0 v, v refh = +10.0 v, v refl = C10.0 v, C40 8 c t a +85 8 c unless otherwise noted. see note 1 for supply variations.)
dac8412/DAC8413 rev. c C3C (@ v dd = v logic = +5.0 v 6 5%, v ss = 0.0 v, v refh = +2.5 v, v refl = 0.0 v, and v ss = C5.0 v 6 5%, v refl = C2.5 v, C40 8 c t a +85 8 c unless otherwise noted. see note 1 for supply variations.) electrical characteristics parameter symbol conditions min typ max units integral linearity e inl 1/2 1 lsb integral linearity f inl 2 lsb integral linearity e inl v ss = 0.0 v; note 2 2 lsb integral linearity f inl v ss = 0.0 v; note 2 4 lsb differential linearity dnl monotonic over temperature C1 lsb min scale error v zse v ss = C5.0 v 4 lsb full-scale error v fse v ss = C5.0 v 4 lsb min scale error v zse v ss = 0.0 v 8 lsb full-scale error v fse v ss = 0.0 v 8 lsb min scale tempco tcv zse 100 ppm/ c full-scale tempco tcv fse 100 ppm/ c matching performance linearity matching 1 lsb reference positive reference input range note 3 v refl + 2.5 v dd C 2 5 v negative reference input range v ss = 0.0 v 0 v refh C 2.5 v negative reference input range v ss = C5.0 v C2.5 v refh C 2.5 v reference high input current i refh code 000h C1.0 +1.0 ma amplifier characteristics output current i out C1.25 +1.25 ma settling time t s to 0.01% 6 m s slew rate sr 10% to 90% 2.2 v/ m s logic characteristics logic input high voltage v inh t a = +25 c 2.4 v logic input low voltage v inl t a = +25 c 0.8 v logic output high voltage v oh i oh = +0.4 ma 2.4 v logic output low voltage v ol i ol = C1.6 ma 0.45 v logic input current i in 1 m a input capacitance c in 8pf logic timing characteristics note 4 write chip select write pulse width t wcs 150 90 ns write setup t ws t wcs = 150 ns 0 ns write hold t wh t wcs = 150 ns 0 ns address setup t as 0ns address hold t ah 0ns load setup t ls 70 30 ns load hold t lh 50 20 ns write data setup t wds t wcs = 150 ns 20 ns write data hold t wdh t wcs = 150 ns 0 ns load pulse width t lwd 180 130 ns reset pulse width t reset 150 110 ns read chip select read pulse width t rcs 170 120 ns read data hold t rdh t rcs = 170 ns 20 ns read data setup t rds t rcs = 170 ns 0 ns data to hi z t dz c l = 10 pf 200 ns chip select to data t csd c l = 100 pf 220 320 ns supply characteristics power supply sensitivity pss 100 ppm/v positive supply current i dd 712 ma negative supply current i ss v ss = C5.0 v C10 ma notes 1 all supplies can be varied 5%, and operation is guaranteed. device is tested with v dd = +4.75 v. 2 for single supply operation only (v refl = 0.0 v, v ss = 0.0 v): due to internal offset errors, inl and dnl are measured beginning at code 2 (002 h ). 3 operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 all input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. specifications subject to change without notice.
dac8412/DAC8413 rev. c C4C wafer test limits dac8412gbc DAC8413gbc parameter symbol conditions limit units integral nonlinearity inl +1 lsb max differential nonlinearity dnl +1 lsb max min scale offset v zse +1 lsb max full-scale offset v fse +1 lsb max logic input high voltage v inh 2.4 v min logic input low voltage v inl 0.8 v max logic input current i in 1 m a max logic output high voltage v oh i oh = +0.4 ma 2.4 v min logic output low voltage v ol i ol = C1.6 ma 0.4 v max positive supply current i dd v refh = +2.5 v 12 ma max negative supply current i ss C10 ma min note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. absolute maximum ratings ( t a = +25 c unless otherwise noted) v ss to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +33.0 v v ss to v logic . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +33.0 v v logic to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 v, +18.0 v v ss to v refl . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +v ss C2.0 v v refh to v dd . . . . . . . . . . . . . . . . . . . . . . . . . +2.0 v, +33.0 v v refh to v refl . . . . . . . . . . . . . . . . . . . . . . . . +2.0 v, v ss Cv dd current into any pin 4 . . . . . . . . . . . . . . . . . . . . . . . 15 ma digital input voltage to dgnd . . . . . C0.3 v, v logic +0.3 v digital output voltage to dgnd . . . . . . . . . . C0.3 v, +7.0 v operating temperature range et, ft, ep, fp, fpc . . . . . . . . . . . . . . . . C40 c to +85 c at, bt, btc . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c dice junction temperature . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c power dissipation package . . . . . . . . . . . . . . . . . . . 1000 mw lead temperature (soldering, 60 sec) . . . . . . . . . . . . . +300 c thermal resistance package type q ja * q jc units 28-pin hermetic dip (t) 50 7 c/w 28-pin plastic dip (p) 48 22 c/w 28-lead hermetic leadless chip carrier (tc) 70 28 c/w 28-lead plastic leaded chip carrier (pc) 63 25 c/w note * q ja is specified for worst case mounting conditions, i. e., q ja is specified for device in socket. dice characteristics caution 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. digital inputs and outputs are protected, however, permanent damage may occur on unpro tected units from high-energy electrostatic fields. keep units in conductive foam or packaging at all times until ready to use. use proper antistatic handling procedures. 3. remove power before inserting or removing units from their sockets. 4. analog outputs are protected from short circuit to ground or either supply. warning! esd sensitive device (@ v dd = +15.0 v, v ss = C15.0 v, v logic = +5.0 v, v refh = +10.0 v, v refl = C10.0 v, t a = +25 8 c unless otherwise noted.)
dac8412/DAC8413 rev. c C5C ordering information 1 extended military 2 industrial 2 inl temperature temperature package (lsb) C55 8 c to +125 8 c C40 8 c to +85 8 c package option 1 dac8412fpc plcc p-28a 1.5 dac8412btc/883 lcc e-28a 0.5 dac8412et cerdip q-28 0.75 dac8412at/883 cerdip q-28 1 dac8412ft cerdip q-28 1.5 dac8412bt/883 cerdip q-28 0.5 dac8412ep plastic n-28 1 dac8412fp plastic n-28 1 dac8412gbc dice 1 DAC8413fpc plcc p-28a 1.5 DAC8413btc/883 lcc e-28a 0.5 DAC8413et cerdip q-28 0.75 DAC8413at/883 cerdip q-28 1 DAC8413ft cerdip q-28 1.5 DAC8413bt/883 cerdip q-28 0.5 DAC8413ep plastic n-28 1 DAC8413fp plastic n-28 1 DAC8413gbc dice notes 1 burn-in is available on extended industrial temperature range parts in cerdip. 2 a complete /883 data sheet is available. for availability and burn-in informa- tion, contact your local sales office. data valid a0/a1 data out t rcs t rds t rdh t csd t as t ah t dz cs r/w data output (read) timing a0/a1 t wcs t ws t wh t lwd t as t ah cs r/w data in ldac reset t lh t reset t ls t ds t dh data write (input and output registers) timing pin configurations cerdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dac8412 DAC8413 top view (not to scale) dgnd db0 (lsb) db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 (msb) a1 a0 v refh v outb v outa v ss v refl v outc v outd v dd v logic cs r/w reset ldac plcc dgnd db0 (lsb) db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 (msb) a1 a0 v ss v dd v logic cs r/w reset ldac dac8412pc DAC8413pc top view (not to scale) 28 27 26 1 2 3 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 v outa v outb v refh v refl v outc v outd lcc dac8412tc DAC8413tc top view (not to scale) 28 27 26 1 2 3 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 dgnd db0 (lsb) db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 (msb) a1 a0 v ss v dd v logic cs r/w reset ldac v outa v outb v refh v refl v outc v outd
dac8412/DAC8413 rev. c C6C table i. dac8412/DAC8413 logic table a1 a0 r/ w cs rs ldac input reg output reg mode dac l l l l h l write write write a l h l l h l write write write b h l l l h l write write write c h h l l h l write write write d l l l l h h write hold write input a l h l l h h write hold write input b h l l l h h write hold write input c h h l l h h write hold write input d l l h l h h read hold read input a l h h l h h read hold read input b h l h l h h read hold read input c h h h l h h read hold read input d x x x h h l hold update all output registers all x x x h h h hold hold hold all x x x x l x *all registers reset to mid/zero-scale all xxxh g x *all registers latched to mid/zero-scale all *dac8412 resets to midscale, and DAC8413 resets to zero scale. l = logic low; h = logic high; x - dont care. db7 db8 db9 db10 db11 a1 a0 v refl v outc v outd v dd v logic cs r/w gnd db0 db1 db2 db3 db4 db5 db6 v refh v outb v outa v ss reset ldac r3 r3 r3 once per port * v dd v refh v refl gnd v ss d1 d1 c1 c1 c1 d1 c2 c2 n/c n/c r6 r1 c1 d1 + ++ + r5 r4 r4 c2 c2 n/c n/c r1 r2 r2 v = +15v, v = ?5v, v = +10v, v = ?0v r1 = 10 w , r2 = 100 w , r3 = 5k w , r4 = 10k w , r5 = 100k w , r6 = 47 w for lcc, r6 = 100 w for dip c1 = 4.7 m f (once per port), c2 = 0.01 m f (each device) d1 = 1n4001 or equivalent (once per port) dd ss refh refl dac8412/DAC8413 burn-in diagram operation introduction the dac8412 and DAC8413 are quad, voltage output, 12-bit dacs featuring a 12-bit data bus with readback capability. the only differences between the dac8412 and DAC8413 are the reset functions. the dac8412 resets to midscale (code 800 h ) and the DAC8413 resets to minimum scale (code 000 h ). the ability to operate from a single +5 volt only supply is a unique feature of these dacs. dividing the system into three separate functional groups: the digital i/o and logic, the digital to analog converters and the output amplifiers. dacs each dac is a voltage switched, high impedance (r = 50 k w ), r-2r ladder configuration. each 2r resistor is driven by a pair of switches that connect the resistor to either v refh or v refl . reference inputs all four dacs share common reference high (v refh ) and refer- ence low (v refl ) inputs. the voltages applied to these reference inputs set the output high and low voltage limits of all four of the dacs. each reference input has voltage restrictions with re- spect to the other reference and to the power supplies. the v refl can be set at any voltage between v ss and v refh C 2.5 volts, and v refh can be set to any value between +v dd C 2.5 volts and v refl + 2.5 volts. note that because of these restrictions the dac8412 references cannot be inverted (i.e., v refl cannot be greater than v refh ). it is important to note that the dac8412s v refh input both sinks and sources current. also the input current of both v refh and v refl are code dependent. many references have limited current sinking capability and must be buffered with an ampli- fier to dr ive v refh . the v refl has no such special re quirements. it is recommended that the reference inputs be bypassed with 0.2 m f capacitors when operating with 10 volt references. digital i/o see table i for digital control logic truth table. digital i/o con- sists of a 12-bit wide bidirectional data bus, two register select inputs, a0 and a1, a r/ w input, a reset input, a chip select ( cs ), and a load dac ( ldac ) input. control of the dacs and bus direction is determined by these inputs as shown in table i. digital data bits are labeled with the msb defined as data bit 11 and the lsb as data bit 0. all digital pins are ttl/cmos compatible.
dac8412/DAC8413 rev. c C7C address decode input reg a output reg a *wra *rda 12 12 12 dac a *rdd *wrd to amplifier reset a0 a1 cs r/w data ldac r/w decode *note: the signals rda, wra, etc., are internal control signals. they are included for clarification only. figure 1. i/o logic diagram see figure 1 for a simplified i/o logic diagram. the register select inputs a0 and a1 select individual dac registers a (binary code 00) through d (binary code 11). decoding of the registers is enabled by the cs input. when cs is high no decoding takes place, and neither the writing nor the reading of the input registers is enabled. the loading of the second bank of registers is controlled by the ldac input. by taking cs low while cs is high, all output registers can be updated simulta- neously. note that the t lwd required pulse width for updating all dacs is a minimum of 170 ns. the r/ w input, when enabled by cs , controls the writing to and reading from the input register. coding both the dac-8412 and DAC8413 use binary coding. the output voltage can be calculated by: v out = v refl + ( v refl _ v refl )* n 4096 where n is the digital code in decimal. reset the reset function can be used either at power-up or at any time during the dacs operation. the reset function is inde- pendent of cs . this pin is active low and sets the dac out- put registers to either center code for the dac8412, or zero code for the DAC8413. the reset to center code is most useful when the dac is configured for bipolar references and an out- put of zero volts after reset is desired. supplies supplies required are v ss , v dd and v logic . the v ss supply can be set between C15 volts and 0 volts. v dd is the positive supply; its operating range is between +5 and +15 volts. v logic is the digital output reference voltage for the readback function. it is normally connected to +5 volts. this pin is a logic reference input only. it does not supply current to the de- vice. if you are not using the readback function, v logic can be hardwired to v dd . while v logic does not supply current to the dac8412, it does supply currents to the digital outputs when readback is used. amplifiers unlike many voltage output dacs, the dac8412 features buff- ered voltage outputs. each output is capable of both sourcing and sinking 5 ma at 10 volts, eliminating the need for external amplifiers in most applications. these amplifiers are short cir- cuit protected. careful attention to grounding is important to accurate opera- tion of the dac8412. this is not because the dac8412 is more sensitive than other 12-bit dacs, but because with four outputs and two references there is greater potential for ground loops. since the dac8412 has no analog ground, the ground must be specified with respect to the reference. reference configurations output voltage ranges can be configured as either unipolar or bipolar, and within these choices a wide variety of options ex- ists. the unipolar configuration can be either positive or nega- tive voltage output, and the bipolar configuration can be either symmetrical or nonsymmetrical. op-400 ref10 dac8412 or DAC8413 + +15v input output trim 10k w v refh 0.2 m f v refl +10v operation figure 2. unipolar +10 v operation dac8412 or DAC8413 +15v v refh 1 m f 5 or 10v operation 0.2 m f 0.2 m f 4 6 12 5 813 7 15 14 1 3 ad688 for 10v ad588 for 5v 39k w 6.2 w 6.2 w v refl balance 100k w gain 100k w figure 3. symmetrical bipolar operation figure 3 (symmetrical bipolar operation) shows the dac8412 configured for 10 volt operation. note: see the ad688 data sheet for a full explanation of reference operation. adjustments may not be required for many applications since the ad688 is a very high accuracy reference. however if additional adjustments are required, adjust the dac8412 full scale first. begin by loading the digital full-scale code (fff h ), and then adjust the gain ad- just potentiometer to attain a dac output voltage of 9.9976 volts. then, adjust the balance adjust to set the center scale output voltage to 0.000 volts. the 0.2 m f bypass capacitors shown at the reference inputs in figure 3 should be used whenever 10 volt references are used. applications with single references or references to 5 volts may not require the 0.2 m f bypassing. the 6.2 w resistor in series with the output of the reference amplifier is to keep the amplifier from oscillating with the capacitive load. we have
dac8412/DAC8413 rev. c C8C found that this is large enough to stabilize this circuit. larger resistor values are acceptable, provided that the drop across the resistor doesnt exceed a v be . assuming a minimum v be of 0.6 volts and a maximum current of 2.75 ma, then the resistor should be under 200 w for the loading of a single dac8412. using two separate references is not recommended. having two references could cause different drifts with time and tempera- ture; whereas with a single reference, most drifts will track. unipolar positive full-scale operation can usually be set with a reference with the correct output voltage. this is preferable to using a reference and dividing down to the required value. for a 10 volt full-scale output, the circuit can be configured as shown in figure 2. in this configuration the full-scale value is set first by adjusting the 10 k w resistor for a full-scale output of 9.9976 volts. ref08 dac8412 or DAC8413 ?5v trim 10k w v refh 0.2 m f v refl zero to ?0v operation gnd .01 m f 10 m f out figure 4. unipolar C10 v operation figure 4 shows the dac8412 configured for C10 volt to zero volt operation. a ref08 with a C10 volt output is connected directly to v refl for the reference voltage. single +5 volt supply operation for operation with a +5 volt supply, the reference should be set between 1.0 and +2.5 volts for optimum linearity. note that lower reference voltages will have greater effects due to noise. figure 5 shows a ref43 used to supply a +2.5 volt reference voltage. the headroom of the reference and dac are both suf- ficient to support a +5 volt supply with 5% tolerance. v dd and v logic should be connected to the same supply and separate bypassing to each pin should be used. ref43 dac8412 or DAC8413 +5v trim 10k w v refh 0.2 m f v refl zero to +2.5v operation single +5v supply gnd 0.01 m f 10 m f output input figure 5. +5 v single supply operation +1 ? 6 0 12 11 10 9 8 7 maximum linearity error ?lsb v ?volts refh v = +15v v = ?5v v = ?0.0v t = +25?c dd refl a ss differential linearity vs. v refh maximum linearity error ?lsb v ?volts refh 0 ? ? +2 +1 3 2 1 v = +5v v = 0v v = 0v t = +25?c dd ss refl a differential linearity vs. v refh maximum linearity error ?lsb v ?volts refh 0.3 0.1 0.2 10 8 6 12 v = +15v v = ?5v v = 0v t = +25?c dd ss refl a inl vs. v refh typical performance characteristics
dac8412/DAC8413 rev. c C9C maximum linearity error ?lsb v ?volts refh +1 ? 0 123 v = +5v v = 0v v = 0v t = +25 c dd ss refl a inl vs. v refh v = +15v v = ?5v v = +10v v = ?0v dd ss refl full-scale error ?lsb 0.4 ?.6 1000 ?.4 0 0 ?.2 0.2 600 400 800 200 t = hours of operation at +125 c refh x x+3 s x? s full-scale error vs. time accelerated by burn-in zero-scale error ?lsb 0.3 ?.7 1000 ?.5 0 ?.1 ?.3 0.1 600 400 800 200 t = hours of operation at +125 c x v = +15v v = ?5v v = +10v v = ?0v dd ss refl refh x+3 s x? s zero-scale error vs. time accelerated by burn-in 150 ?5 75 0 0.2 ?.6 ?.4 ?.2 0 full-scale error ?lsb temperature ? c dac a dac d dac b dac c v = +15v v = ?5v v = +10v v = ?0v dd ss refl refh full-scale error vs. temperature 0.3 ?.5 150 ?.3 ?5 ?.1 0.1 75 0 zero-scale error ?lsb temperature ? c dac a dac d dac c v = +15v v = ?5v v = +10v v = ?0v dd ss refl refh dac b zero-scale error vs. temperature channel-to-channel matching (v supply = 15 v) channel-to-channel matching (v supply = +5 v)
dac8412/DAC8413 rev. c C10C i vrefh vs. code v ?volts refh 13 4 13 ? 7 10 9 5 1 ? i ?ma dd v = +15v v = ?5v v = ?0v dd ss refl i dd vs. v refh all dacs high i nl vs. code settling time (positive) settling time (negative) positive slew rate negative slew rate
dac8412/DAC8413 rev. c C11C temperature ? c 10 ?0 150 ? ?5 2 ? 6 75 0 power supply current ?ma i dd i ss v = +15v v = ?5v dd ss power supply current vs. temperature 100 0 1m 60 20 100 40 10 80 100k 10k 1k frequency ?hz power supply rejection ?db +psrr ?srr +psrr: v = +15v 1v v = ?5v ?srr: v = +15v v = ?5v 1v v = 10v all data 0 dd ss dd ss p p refh psrr vs. frequency 10m 10 01m 100k 10k 1k 100 v = +15v v = ?5v v = 0 100mv v = ?0v data bits = +5v 200mv dd ss refl refh p? ?0 0 ?0 ?0 gain ?db frequency ?hz small signal response 0 0 25 ?0 ?0 ?5 ?0 0 ?0 10 20 30 20 15 10 5 0 ? ?0 ?5 v = +15v v = ?5v v = +10v v = ?0v t = +25?c data = 000 h dd ss refl refh a i ?ma out v ?volts out i out vs. v out outline dimensions dimensions shown in inches and (mm). 28-position leadless chip carrier (tc suffix) side view top view bottom view 0.075 (1.91) ref 0.458 (11.63) 0.442 (11.23) 0.300 (7.62) ref 0.075 (1.91) ref 0.458 (11.63) max plane 2 plane 1 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 0.093 (2.36) 0.077 (1.96) 0.055 (1.40) 0.045 (1.14) 0.200 (5.08) bsc 45 typ 0.050 (1.27) min 0.150 (3.81) ref 0.015 (0.38) min 0.028 (0.71) 0.022 (0.56)
dac8412/DAC8413 rev. c C12C c1544C24C5/91 printed in u.s.a. 28-lead plcc (pc suffix) pin 1 identifier 426 5 11 25 19 12 18 0.430 (10.920) 0.390 (9.910) 0.021 (0.533) 0.013 (0.331) 0.032 (0.812) 0.026 (0.661) 0.180 (4.51) 0.165 (4.20) 0.456 (11.582) 0.450 (11.430) top view 0.020 (0.510) min seating plane x 45 0.050 (1.270) bsc 0.048 (1.219) 0.042 (1.067) 0.495 (12.570) 0.485 (12.320) 28-lead cerdip (t suffix) 28 1 15 14 seating plane 1.490 (37.85) max 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 15 0 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) 0.008 (0.20) 0.610 (15.49) 0.500 (12.70) 0.225 max (5.72) 0.100 (2.54) bsc 0.150 (3.81) min 0.120 (3.05) 0.200 (5.08) 0.005 (0.13) min 0.098 (2.49) max pin 1 0.075 (1.91) 0.015 (0.38) 28-lead epoxy dip (p suffix) 28 1 15 14 seating plane 0.130 (3.32) min 0.022 (0.558) 0.014 (0.36) 0.015 (0.381) 0.008 (0.203) 0.580 (14.73) 0.485 (12.32) 1.565 (39.70) 1.380 (35.10) 0.250 (6.35) max 0.625 (15.87) 0.600 (15.24) 0.100 (2.54) bsc pin 1 0.200 (5.08) 0.115 (2.93) 0.015 (0.39) min 15 0 0.070 (1.78) 0.030 (0.76)

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