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ftg for integrated core logic with 133-mhz fsb W218 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07221 rev. *a revised december 21, 2002 features ? maximized emi suppression using cypress?s spread spectrum technology three copies of cpu clock at 66/100/133 mhz nine copies of 100-mhz sdram clocks seven copies of pci clock two copies of apic clock at 33 mhz, synchronous to cpu clock two copies of 48-mhz clock (non-spread spectrum) op- timized for usb reference input and video dot clock three copies of 3v 66-mhz fixed clock one copy of 14.31818-mhz reference clock power down control smbus interface for turning off unused clocks key specifications cpu, sdram outputs cycle-to-cycle jitter:.............. 250 ps apic, 48-mhz, 3v66, pci outputs cycle-to-cycle jitter:................................................... 500 ps apic, sdram output skew: ...................................... 250 ps cpu, 3v66 output skew:............................................175 ps pci output skew:........................................................500 ps cpu to sdram skew (@ 133 mhz):......................... 0.5 ns cpu to sdram skew (@ 100 mhz):.................4.5 to 5.5 ns cpu to 3v66 skew (@ 66 mhz): .......................7.0 to 8.0 ns 3v66 to pci skew (3v66 lead):..........................1.5 to 3.5 ns pci to apic skew: .....................................................0.5 ns intel is a registered trademark of intel corporation. table 1. pin selectable functions tristate# fsel0 fsel1 cpu sdram 0 0 x three-state three-state 0 1 x test test 1 0 0 66 mhz 100 mhz 1 1 0 100 mhz 100 mhz 1 0 1 133 mhz 133 mhz 1 1 1 133 mhz 100 mhz block diagram pin configuration note: 1. internal pull-down resistors present on input marked with *. design should not solely rely on internal pull-down resister to set i/o pin low. [1] vddq3 vddq2 cpu2_itp pci0_ich xtal pll ref freq pll 1 x2 x1 ref0/fsel1 pci1:6 usb dot pll2 osc vddq3 i 2 c sdata logic sclk 3v66_0:1 cpu0:1 fsel0:1 apic0:1 divider, delay, and phase control logic 7 2 vddq3 2 2 dclk sdram0:7 8 pwr_dwn# 3v66_agp vdda vdda tristate# *ref0/fsel1 vddq3 x1 x2 gnd gnd 3v66_0 3v66_1 3v66_agp vddq3 vddq3 pci0_ich pci1 gnd pci2 pci3 gnd pci4 pci5 pci6 vddq3 vdda gnda gnd W218 gnd apic0 apic1 vddq2 cpu0 vddq2 cpu1 cpu2_itp gnd gnd sdram0 sdram1 vddq3 sdram2 sdram3 gnd sdram4 sdram5 vddq3 sdram6 sdram7 gnd dclk vddq3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 31 30 29 usb dot vddq3 fsel0 pwr_dwn# sclk sdata tristate#
W218 document #: 38-07221 rev. *a page 2 of 17 pin definitions pin name pin no. pin type pin description ref0/fsel1 1 i/o reference clock: 3.3v 14.318-mhz clock output. this pin also serves as a strap option for cpu frequency selection. see table 1 for detailed descriptions. x1 3 i crystal input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 4 o crystal output: a connection for an external 14.318-mhz crystal. if using an ex- ternal reference, this pin must be left unconnected. pci0_ich, pci1:6 12, 13, 15, 16, 18, 19, 20 o pci clock 0 through 6: 3.3v 33-mhz pci clock outputs. pci1:7 can be individually turned off via smbus interface. 3v66_0:1/ 3v66_agp 7, 8, 9 o 66-mhz clock output: 3.3v fixed 66-mhz clock. usb 25 o usb clock output: 3.3v fixed 48-mhz, non-spread spectrum usb clock output. dot 26 o dot clock output: 3.3v 48-mhz, non-spread spectrum signal. fsel0, tristate# 28, 29 i clock function selection pins: lvttl-compatible input to select device func- tions. see table 1 for detailed descriptions. pwr_dwn# 32 i power-down control: lvttl-compatible asynchronous input that places the de- vice in power-down mode when held low. this input can be used as the vtt_pwrgd input to support intel ? vrm 8.5 implementation. cpu2_itp, cpu0:1 49,52,50 o cpu clock outputs: clock outputs for the host bus interface and integrated test port. output frequencies run at 66 mhz, 100 mhz, or 133 mhz depending on the configuration of sel0:1 and sel133. voltage swing set by v ddq2 . sdram0:7, dclk 46, 45, 43, 42, 40, 39, 37, 36, 34 o sdram clock outputs: 3.3v outputs running at 100 mhz. sdram0:7 can be individually turned off via smbus interface. apic0:1 55, 54 o synchronous apic clock outputs: clock outputs running synchronous with the pci clock outputs (33 mhz). voltage swing set by v ddq2 . sdata 30 i/o data pin for smbus circuitry. sclk 31 i clock pin for smbus circuitry. vddq3 2, 10, 11, 21, 27, 33, 38, 44 p 3.3v power connection: power supply for sdram output buffers, pci output buffers, 3v66 output buffers, reference output buffers, and 48-mhz output buffers. connect to 3.3v. vdda 22 p 3.3v power connection: power supply for core logic, pll circuitry. connect to 3.3v. vddq2 51, 53 p 2.5v power connection: power supply for ioapic and cpu output buffers. con- nect to 2.5v or 3.3v. gnd 5, 6, 14, 17, 24, 35, 41, 47, 48, 56 g ground connections: connect all ground pins to the common system ground plane. gnda 23 g ground connections: ground for core logic, pll circuitry.
W218 document #: 38-07221 rev. *a page 3 of 17 overview the W218 is a highly integrated frequency timing generator, supplying all the required clock sources for an intel ? architec- ture platform using graphics integrated core logic. functional description i/o pin operation ref0/fsel1is a dual-purpose l/o pin. upon power-up the pin acts as a logic input. if the pin is strapped to a high state externally, cpu clock outputs will run at 133 mhz. if it is strapped low, cpu clock outputs will be determined by the status of fsel input pin. an external 10-k ? strapping resistor should be used. figure 1 shows a suggested method for strap- ping resistor connections. after 2 ms, the pin becomes an output. assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. if the power supply has not yet reached full value, output frequency initially may be below tar- get but will increase to target once supply voltage has stabi- lized. in either case, a short output clock cycle may be pro- duced from the cpu clock outputs when the outputs are enabled. pin selectable functions table 1 outlines the device functions selectable through threestate#, fsel0 and fsel1. specific outputs available at each pin are detailed in table 2 below. the sel0 pin requires a 220 ? pull-up resistor to 3.3v for the W218 to sense the max- imum host bus frequency of the processor and configure itself accordingly. also note that fsel0, threestate# input levels should be stable within 500 s of the later of v ddq3 , v ddq2 , pwr_dwn# rising edge. notes: 2. provided for board-level ? bed of nails ? testing. 3. ? normal ? mode of operation. 4. tclk is a test clock overdriven on the xtal_in input during test mode. 5. required for dc output impedance verification. 6. range of reference frequency allowed is min. = 14.316 mhz, nominal = 14.31818 mhz, max. = 14.32 mhz. 7. frequency accuracy of 48 mhz must be +167 ppm to match usb default. power-on reset timer output three-state data latch hold qd W218 v dd clock load 10 k ? output buffer (load option 1) 10 k ? (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option table 2. ck whitney truth table tristate# fsel0 fsel1 cpu sdram 3v66 pci 48 mhz ref apic notes 0 0 x hi-z hi-z hi-z hi-z hi-z hi-z hi-z 2 0 1 x tclk/4 tclk/4 tclk/6 tclk/12 tclk/2 tclk tclk/12 4, 5 1 0 0 66 mhz 100 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 3, 6, 7 1 1 0 100 mhz 100 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 3, 6, 7 1 0 1 133 mhz 133 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 3, 6, 7 1 1 1 133 mhz 100 mhz 66 mhz 33 mhz 48 mhz 14.318 mhz 33 mhz 3, 6, 7
W218 document #: 38-07221 rev. *a page 4 of 17 how to use pd# input to support vtt_pwrgd the pd# input can be used to support the vtt_pwrgd sig- nal specified in the intel ? vrm 8.5 specification. the vtt_pwrgd is used to indicated that the frequency select output pins (bsel[0:1]) from the cpu are valid and the clock generator can use them to determine the cpu fsb frequency. the assertion of pd# input pin during initial power up will delay the start of the pll, keep all the multiplexed i/o pins as input and keep all the output inactive. the functionality of pd# will allow system designer to use this input to support the vtt_pwrgd output from the vrm 8.5 module. please refer to the figure 2 for power up sequence details. 3.3v & 2.5v pd# (connected to vtt_pwrgd) outputs input latch (pin 4 & pin21) 1 ms pll & output synchronization figure 2. power up sequence with pd# (vtt_pwrgd) hold low
W218 document #: 38-07221 rev. *a page 5 of 17 offsets among clock signal groups figure 3 and figure 4 represent the phase relationship among the different groups of clock outputs from W218 when it is pro- viding a 66-mhz cpu clock and a 100-mhz cpu clock, re- spectively. it should be noted that when cpu clock is operating at 100 mhz, cpu clock output is 180 degrees out of phase with sdram clock outputs. 0 ns figure 3. group offset waveforms (66-mhz cpu/100-mhz sdram clock) 40 ns 30 ns 20 ns 10 ns cpu 66-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeat apic33-mhz 0 ns figure 4. group offset waveforms (100-mhz cpu/100-mhz sdram clock) 40 ns 30 ns 20 ns 10 ns cpu 100-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz apic 33-mhz cycle repeat
W218 document #: 38-07221 rev. *a page 6 of 17 0 ns figure 5. group offset waveforms (133-mhz cpu/100-mhz sdram clock) 40 ns 30 ns 20 ns 10 ns cpu 133-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic 33-mhz 0 ns figure 6. group offset waveforms (133-mhz cpu/133-mhz sdram clock) 40 ns 30 ns 20 ns 10 ns cpu 100-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz apic 33-mhz cycle repeat
W218 document #: 38-07221 rev. *a page 7 of 17 power down control W218 provides one pwrdwn# signal to place the device in low-power mode. in low-power mode, the plls are turned off and all clock outputs are driven low. notes: 8. once the pwrdwn# signal is sampled low for two consecutive rising edges of cpu, clocks of interest will be held low on the ne xt high-to-low transition. 9. pwrdwn# is an asynchronous input and metastable conditions could exist. this signal is synchronized inside W218. 10. the shaded sections on the sdram, ref, and usb clocks indicate ? don ? t care ? states. 11. diagrams shown with respect to 100 mhz. similar operation when cpu is 66 mhz. table 3. W218 maximum allowed current W218 condition max. 2.5v supply consumption max. discrete cap loads, v ddq2 = 2.625v all static inputs = v ddq3 or v ss max. 3.3v supply consumption max. discrete cap loads v ddq3 = 3.465v all static inputs = v ddq3 or v ss powerdown mode (pwrdwn# = 0) 10 a 10 a full active 66 mhz fsel1:0 = 00 (pwrdwn# =1) 70 ma 280 ma full active 100 mhz fsel1:0 = 01 (pwrdwn# =1) 100 ma 280 ma full active 133 mhz fsel1:0 = 11 (pwrdwn# =1) tbd tbd 1 2 center 0 ns 25 ns 50 ns 75 ns vco internal cpu 100-mhz 3v66 66-mhz pci 33-mhz apic 33-mhz pwrdwn sdram 100-mhz ref 14.318-mhz usb 48-mhz figure 7. W218 pwrdwn# timing diagram [8, 9, 10, 11]
W218 document #: 38-07221 rev. *a page 8 of 17 spread spectrum frequency timing generation the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the am- plitudes of the radiated electromagnetic emissions are re- duced. this effect is depicted in figure 8 . as shown in figure 8 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 9 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is ? 0.5% of the selected fre- quency. figure 9 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by se- lecting the appropriate value for bit 3 in data byte 0 of the i 2 c data stream. refer to page 10 for more details. figure 8. clock harmonic with and without sscg modulation frequency domain representation spread spectrum enabled emi reduction spread spectrum non- max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 9. typical modulation profile
W218 document #: 38-07221 rev. *a page 9 of 17 serial data interface the W218 features a two-pin, serial data interface that can be used to configure internal register settings that control partic- ular device functions. data protocol the clock driver serial protocol accepts only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. indexed bytes are not allowed. a block write begins with a slave address and a write condition. after the command code the core logic issues a byte count which describes how many more bytes will follow in the mes- sage. if the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be 0. a block write command is allowed to transfer a maximum of 32 data bytes. the slave receiver ad- dress for W218 is 11010010. figure 10 shows an example of a block write. the command code and the byte count bytes are required as the first two bytes of any transfer. W218 expects a command code of 0000 0000. the byte count byte is the number of ad- ditional bytes required for the transfer, not counting the com- mand code and byte count bytes. additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. table 4 shows an example of a possible byte count value. a transfer is considered valid after the acknowledge bit corre- sponding to the byte count is read by the controller. the com- mand code and byte count bytes are ignored by the W218. however, these bytes must be included in the data write se- quence to maintain proper byte allocation. notes: 12. the acknowledgment bit is returned by the slave/receiver (W218). 13. data bytes 3 to 7 are reserved. 1 bit 7 bits 1 1 8 bits 1 start bit slave address r/w ack command code ack byte count = n ack data byte 1 ack data byte 2 ack ... data byte n ack stop 1 bit 8 bits 1 8 bits 1 8 bits 1 1 figure 10. an example of a block write [12] table 4. example of possible byte count value byte count byte notes msb lsb 0000 0000 not allowed. must have at least one byte 0000 0001 data for functional and frequency select register (currently byte 0 in spec) 0000 0010 reads first two bytes of data (byte 0 then byte 1) 0000 0011 reads first three bytes (byte 0, 1, 2 in order) 0000 0100 reads first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 reads first five bytes (byte 0, 1, 2, 3, 4 in order) [13] 0000 0110 reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order) [13] 0000 0111 reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 max. byte count supported = 32 table 5. serial data interface control functions summary control function description common application output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and sys- tem power. examples are clock outputs to unused pci slots. spread spectrum enabling enables or disables spread spectrum clocking. for emi reduction. (reserved) reserved function for future device revision or pro- duction device testing. no user application. register bit must be written as 0.
W218 document #: 38-07221 rev. *a page 10 of 17 W218 serial configuration map 1. the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 2. all unused register bits (reserved and n/a) should be writ- ten to a ? 0 ? level. 3. all register bits labeled ? initialize to 0" must be written to zero during initialization. failure to do so may result in high- er than normal operating current. 4. only byte 0, 1 and 2 are defined in W218. byte 3 to byte 7 are reserved and must be written to ? zero. ? note: 14. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. byte 0: control register (1 = enable, 0 = disable) [14] bit pin# name pin description bit 7 - reserved (active/inactive) bit 6 - reserved (active/inactive) bit 5 - reserved (active/inactive) bit 4 - reserved (active/inactive) bit 3 - spread spectrum (1 = on/0 = off) (disabled/enabled) bit 2 26 dot (active/inactive) bit 1 25 usb (active/inactive) bit 0 49 cpu2_itp (active/inactive) byte 1: control register (1 = enable, 0 = disable) [14] bit pin# name pin description bit 7 36 sdram7 (active/inactive) bit 6 37 sdram6 (active/inactive) bit 5 39 sdram5 (active/inactive) bit 4 40 sdram4 (active/inactive) bit 3 42 sdram3 (active/inactive) bit 2 43 sdram2 (active/inactive) bit 1 45 sdram1 (active/inactive) bit 0 46 sdram0 (active/inactive) byte 2: control register (1 = enable, 0 = disable) [14] bit pin# name pin description bit 7 9 3v66_agp (active/inactive) bit 6 20 pci6 (active/inactive) bit 5 19 pci5 (active/inactive) bit 4 18 pci4 (active/inactive) bit 3 16 pci3 (active/inactive) bit 2 15 pci2 (active/inactive) bit 1 13 pci1 (active/inactive) bit 0 -- reserved reserved
W218 document #: 38-07221 rev. *a page 11 of 17 byte 3: reserved register (1 = enable, 0 = disable) bit pin# name pin description bit 7 - reserved drive to ? 0 ? (active/inactive) bit 6 - reserved drive to ? 0 ? (active/inactive) bit 5 - reserved drive to ? 0 ? (active/inactive) bit 4 - reserved drive to ? 0 ? (active/inactive) bit 3 - reserved drive to ? 0 ? (active/inactive) bit 2 - reserved drive to ? 0 ? (active/inactive) bit 1 reserved drive to ? 0 ? (active/inactive) bit 0 - sdram 133-mhz mode enable default is disabled = ? 0 ? , enabled = ? 1 ? (disabled/enabled) byte 4: reserved register (1 = enable, 0 = disable) bit pin# name pin description bit 7 - reserved drive to ? 0 ? (active/inactive) bit 6 - reserved drive to ? 0 ? (active/inactive) bit 5 - reserved drive to ? 0 ? (active/inactive) bit 4 - reserved drive to ? 0 ? (active/inactive) bit 3 - reserved drive to ? 0 ? (active/inactive) bit 2 - reserved drive to ? 0 ? (active/inactive) bit 1 reserved drive to ? 0 ? (active/inactive) bit 0 - reserved drive to ? 0 ? (active/inactive)
W218 document #: 38-07221 rev. *a page 12 of 17 dc electrical characteristics [15] note: 15. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 16. input leakage current does not include inputs with pull-up or pull-down resistors. absolute maximum dc power supply parameter description min. max. unit v dd3 3.3v core supply voltage ? 0.5 4.6 v v ddq2 2.5v i/o supply voltage ? 0.5 3.6 v v ddq3 3.3v supply voltage ? 0.5 4.6 v t s storage temperature ? 65 150 c absolute maximum dc i/o parameter description min. max. unit v ih3 3.3v input high voltage ? 0.5 4.6 v v il3 3.3v input low voltage ? 0.5 v esd prot. input esd protection 2000 v dc operating requirements parameter description condition min. max. unit v dd3 3.3v core supply voltage 3.3v5% 3.135 3.465 v v ddq3 3.3v i/o supply voltage 3.3v5% 3.135 3.465 v v ddq2 2.5v i/o supply voltage 2.5v5% 2.375 2.625 v v dd3 = 3.3v5% v ih3 3.3v input high voltage v dd3 2.0 v dd + 0.3 v v il3 3.3v input low voltage v ss ? 0.3 0.8 v i il input leakage current [16] 0 W218 document #: 38-07221 rev. *a page 13 of 17 ac electrical characteristics [15] t a = 0 c to +70 c, v ddq3 = 3.3v5%, v ddq2 = 2.5v5% f xtl = 14.31818 mhz spread spectrum function turned off ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. [17] ac electrical characteristics parameter description 66.6-mhz host 100-mhz host 133-mhz host unit notes min. max. min. max. min. max. t period host/cpuclk period 15.0 15.5 10.0 10.5 7.5 8.0 ns 17 t high host/cpuclk high time 5.2 n/a 3.0 n/a 1.87 n/a ns 20 t low host/cpuclk low time 5.0 n/a 2.8 n/a 1.67 n/a ns t rise host/cpuclk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t fall host/cpuclk fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t period sdram clk period (100-mhz) 10.0 10.5 10.0 10.5 10.0 10.5 ns 17 t high sdram clk high time (100-mhz) 3.0 n/a 3.0 n/a 3.0 n/a ns 20 t low sdram clk low time (100-mhz) 2.8 n/a 2.8 n/a 2.8 n/a ns t rise sdram clk rise time (100-mhz) 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t fall sdram clk fall time (100-mhz) 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t period sdram clk period (133-mhz) 7.5 8.0 7.5 8.0 7.5 8.0 ns 17 t high sdram clk high time (133-mhz) 1.87 n/a 1.87 n/a 1.87 n/a ns 20 t low sdram clk low time (133-mhz) 1.67 n/a 1.67 n/a 1.67 n/a ns t rise sdram clk rise time (133-mhz) 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t fall sdram clk fall time (133-mhz) 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t period apic 33-mhz clk period 30.0 n/a 30.0 n/a 30.0 n/a ns 17 t high apic 33-mhz clk high time 12.0 n/a 12.0 n/a 12.0 n/a ns 20 t low apic 33-mhz clk low time 12.0 n/a 12.0 n/a 12.0 n/a ns t rise apic clk rise time 0.4 1.6 0.4 1.6 0.4 1.6 ns 21 t fall apic clk fall time 0.4 1.6 0.4 1.6 .04 1.6 ns 21 t period 3v66 clk period 15.0 16.0 15.0 16.0 15.0 16.0 ns 17, 19 t high 3v66 clk high time 5.25 n/a 5.25 n/a 5.25 n/a ns 20 t low 3v66 clk low time 5.05 n/a 5.05 n/a 5.05 n/a ns t rise 3v66 clk rise time 0.5 2.0 0.5 2.0 0.5 2.0 ns 21 t fall 3v66 clk fall time 0.5 2.0 0.5 2.0 0.5 2.0 ns 21 t period pci clk period 30.0 n/a 30.0 n/a 30.0 n/a ns 17, 18 t high pci clk high time 12.0 n/a 12.0 n/a 12.0 n/a ns 20 t low pci clk low time 12.0 n/a 12.0 n/a 12.0 n/a ns t rise pci clk rise time 0.5 2.0 0.5 2.0 0.5 2.0 ns 21 t fall pci clk fall time 0.5 2.0 0.5 2.0 0.5 2.0 ns 21 notes: 17. period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5v clocks and at 1.5v for 3.3v clocks. 18. t high is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. 19. t low is measured at 0.4v for all outputs. 20. the time specified is measured from when v ddq3 achieves its nominal operating level (typical condition v ddq3 = 3.3v) until the frequency output is stable and operating within specification. 21. t rise and t fall are measured as a transition through the threshold region v ol = 0.4v and v oh = 2.0v (1 ma) jedec specification for 2.5v outputs, and v ol = 0.4v and v oh = 2.4v for 3.3v.
W218 document #: 38-07221 rev. *a page 14 of 17 tp zl , tp zh output enable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns tp lz , tp zh output disable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 ns t stable all clock stabilization from power-up 3 3 3 ms 20 group skew and jitter limits output group pin-pin skew max. cycle-cycle jitter duty cycle nom v dd skew, jitter measure point cpu 175 ps 250 ps 45/55 2.5v 1.25v sdram 250 ps 250 ps 45/55 3.3v 1.5v apic 250 ps 500 ps 45/55 2.5v 1.25v 48mhz 250 ps 500 ps 45/55 3.3v 1.5v 3v66 175 ps 500 ps 45/55 3.3v 1.5v pci 500 ps 500 ps 45/55 3.3v 1.5v ref n/a 1000 ps 45/55 3.3v 1.5v ac electrical characteristics (continued) parameter description 66.6-mhz host 100-mhz host 133-mhz host unit notes min. max. min. max. min. max. clock output wave 2.5v clocking 3.3v clocking test point test load t period duty cycle t high 2.0 1.25 0.4 t low t rise t fall t low t rise t fall t period duty cycle t high 2.4 1.5 0.4 output buffer interface interface figure 11. output buffer ordering information ordering code package name package type W218 h 56-pin ssop (300 mils)
W218 document #: 38-07221 rev. *a page 15 of 17 layout diagram 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 6 7 13 19 20 24 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors +2.5v supply 1 2 3 4 5 8 9 11 12 14 15 16 17 22 23 21 25 26 27 28 40 39 18 41 10 31 30 29 36 35 34 33 32 37 38 g v fb +3.3v supply c4 c1 & c3 = 10 ? 22 f c2 & c4 = 0.005 f 10 f fb c1 c2 0.005 f fb = dale ilb1206 - 300 (300 ? @ 100 mhz) 10 f 0.005 f g g g g vddq2 vddq3 c3 c5 = 47 f c6 = 0.1 f g g 10 ? vddq3 c5 c6 g v g v g v g v g v g v g v g v g v W218 core g g g g g g g g g g g g g g g g g g g g g pll2 ceramic caps
W218 document #: 38-07221 rev. *a page 16 of 17 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 56-pin shrink small outline package (ssop, 300 mils) summary of nominal dimensions in inches: body width: 0.296 lead pitch: 0.025 body length: 0.625 body height: 0.102
W218 document #: 38-07221 rev. *a page 17 of 17 document title: W218 ftg for integrated core logic with 133-mhz fsb document number: 38-07221 rev. ecn no. issue date orig. of change description of change ** 110486 10/21/01 szv change from spec number: 38-00885 to 38-07221 *a 122838 12/21/02 rbi add power up requirements to electrical characteristics information

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