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freescale semiconductor data sheet: technical data document number: MCF51JM128 rev. 2, 09/2008 ? freescale semiconductor, inc., 2008. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. MCF51JM128 80 lqfp 14 mm 14 mm 64 lqfp 10 mm 10 mm 64 qfp 14 mm 14 mm 44 lqfp 10 mm 10 mm the MCF51JM128 is a member of the coldfire ? family of 32-bit reduced instruction set computing (risc) microprocessors. this document provides an overview of the MCF51JM128 series, focusing on its highly integrated and diverse feature set. the MCF51JM128 series is based on the v1 coldfire core and operates at processor co re speeds up to 50.33 mhz. as part of freescale?s controller continuum ? , it is an ideal upgrade for designs based on the mc9s08jm60 series of 8-bit microcontrollers. the MCF51JM128 features the following functional units: ? v1 coldfire core with background debug module ? up to 128 kbytes of flash memory ? up to 16 kbytes of static ram (sram) ? multipurpose clock generator (mcg) ? dual-role universal serial bus on-the-go device (usbotg) ? controller-area network (mscan) ? cryptographic acceleration unit (cau) ? random number genera tor accelerator (rnga) ? analog comparators (acmp) ? analog-to-digital converter (adc) with up to 12 channels ? two inter-integrated circuit (iic) modules ? two serial peripheral interfaces (spi) ? two serial communica tions interfaces (sci) ? carrier modulation timer (cmt) ? eight-channel timer/pulse-width modulators (tpm) ? real-time counter (rtc) ? 66 general-purpose input/out put (gpio) modules plus interrupt request input ? eight keyboard interrupts (kbi) ? 16-bit rapid gpio MCF51JM128 coldfire microcontroller
MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 2 table of contents 1 MCF51JM128 family configurations . . . . . . . . . . . . . . . . . . . .3 1.1 device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.1 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.5 pinouts and packaging . . . . . . . . . . . . . . . . . . . . . . . . .10 2 preliminary electrical characteristics . . . . . . . . . . . . . . . . . . .15 2.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .15 2.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .15 2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .16 2.4 electrostatic discharge (esd ) protection characteristics 17 2.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.6 supply current characteristics . . . . . . . . . . . . . . . . . . .22 2.7 analog comparator (acmp) electricals . . . . . . . . . . . .23 2.8 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.9 external oscillator (xosc) characteristics . . . . . . . . .27 2.10 mcg specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.11 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.2 timer/pwm (tpm) module timing . . . . . . . . . .30 2.11.3 mscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.12 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.13 flash specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14 usb electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.15 emc performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.15.1 radiated emissions . . . . . . . . . . . . . . . . . . . . . .36 3 mechanical outline drawings . . . . . . . . . . . . . . . . . . . . . . . . .37 3.1 80-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2 64-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.3 64-pin qfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.4 44-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 list of figures figure 1. MCF51JM128 block diagram . . . . . . . . . . . . . . . . . . . . 5 figure 2. 80-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. 64-pin qfp and lqfp . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. 44-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. typical low-side drive (sink) characteristics ? high drive (ptxdsn = 1) . . . . . . . . . 21 figure 6. typical low-side drive (sink) characteristics ? low drive (ptxdsn = 0). . . . . . . . . . 21 figure 7. typical high- side drive (source) characteristics ? high drive (ptxdsn = 1) . . . . . . . . . 21 figure 8. typical high- side drive (source) characteristics ? low drive (ptxdsn = 0). . . . . . . . . . 22 figure 9. adc input impedance equival ency diagram . . . . . . . 24 figure 10.reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11.irq/kbipx timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12.timer external clock . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13.timer input capture pulse . . . . . . . . . . . . . . . . . . . . . 31 figure 14.spi master timing (cpha = 0) . . . . . . . . . . . . . . . . . 33 figure 15.spi master timing (cpha = 1) . . . . . . . . . . . . . . . . . 33 figure 16.spi slave timing (cpha = 0) . . . . . . . . . . . . . . . . . . 34 figure 17.spi slave timing (cpha = 1) . . . . . . . . . . . . . . . . . . 34 list of tables table 1. MCF51JM128 series device comparison . . . . . . . . . . 3 table 2. MCF51JM128 series functional units . . . . . . . . . . . . . 6 table 3. orderable part number summary. . . . . . . . . . . . . . . . . 9 table 4. pin assignments by package and pin sharing priority 12 table 5. parameter classifications . . . . . . . . . . . . . . . . . . . . . . 15 table 6. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . 16 table 7. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. esd and latch-up test conditions . . . . . . . . . . . . . . . 17 table 9. esd and latch-up protection characteristics. . . . . . . 18 table 10.dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. supply current characteristics. . . . . . . . . . . . . . . . . . 22 table 12.analog comparator electrical specifications. . . . . . . . 23 table 13.5 volt 12-bit adc operating conditions . . . . . . . . . . . 23 table 14.5 volt 12-bit adc characteristics (vrefh = vddad, vrefl = vssad) . . . . . . . . . . . . 25 table 15.oscillator elec trical specifications (temperature range = ?40 to 105c ambient) . . . . . 27 table 16.mcg frequency specifications (temperature range = ?40 to 125c ambient) . . . . . 28 table 17.control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18.tpm input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 19.mscan wake-up pulse characteristics . . . . . . . . . . . 31 table 20.spi electrical characteristic . . . . . . . . . . . . . . . . . . . . 32 table 21.flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 22.internal usb 3.3v voltage regulator characteristics . 36
MCF51JM128 family configurations MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 3 1 MCF51JM128 family configurations 1.1 device comparison the MCF51JM128 series consists of the devices compared in table 1 . table 1. MCF51JM128 series device comparison feature MCF51JM128 mcf51jm64 mcf51jm32 80-pin 64-pin 44-pin 80-pin 64-pi n 44-pin 80-pin 64-pin 44-pin flash memory size (kbytes) 128 64 32 ram size (kbytes) 16 16 16 v1 coldfire core with bdm (background debug module) ye s acmp (analog comparator) yes adc (analog-to-dig ital converter) channels (12-bit) 128128128 can (controller area network) yes no yes no yes no cau (cryptographic acceleration unit) yes no no yes no no yes no no cmt (carrier modulator timer) yes cop (computer operating properly) yes iic1 (inter-integrated circuit) yes iic2 yes no yes no yes no irq (interrupt request input) yes kbi (keyboard interrupts) 8 8 6 8 86886 lvd (low-voltage detector) yes mcg (multipurpose clock generator) yes port i/o 1 66 51 33 66 51 33 66 51 33 rgpio (rapid general-purpose i/o) 16 6 0 16 6 0 16 6 0 rnga (random number generator accelerator) ye s rtc (real-time counter) yes sci1 (serial communications interface) yes sci2 ye s spi1 (serial peripheral interface) yes spi2 ye s
MCF51JM128 coldfire microcontroller, rev. 2 MCF51JM128 family configurations freescale semiconductor 4 1.2 block diagram figure 1 shows the connections between the MCF51JM128 series pins and modules. tpm1 (timer/pulse-width modulator) channels 664664664 tpm2 channels 2 usbotg (usb on-t he-go dual-role controller) ye s xosc (crystal oscillator) yes 1 up to 16 pins on ports a, h, and j are shared with the coldfire rapid gpio module. table 1. MCF51JM128 series device comparison (continued) feature MCF51JM128 mcf51jm64 mcf51jm32 80-pin 64-pin 44-pin 80-pin 64-pi n 44-pin 80-pin 64-pin 44-pin
MCF51JM128 family configurations MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 5 figure 1. MCF51JM128 block diagram port b ptb3/ss2 /adp3 ptb4/kbip4/adp4 ptb5/kbip5/adp5 ptb2/spsck2/adp2 ptb1/mosi2/adp1 ptb0/miso2/adp0 ptb6/adp6 ptb7/adp7 port d ptd3/kbip3/adp10 ptd4/adp11 ptd5 ptd2/kbip2/acmpo ptd1/acmp?/adp9 ptd0/acmp+/adp8 ptd6 ptd7 port c ptc3/txd2 ptc4 ptc5/rxd2 ptc2/iro ptc1/sda1 ptc0/scl1 ptc6/rxcan ptc7 port f ptf3/tpm1ch5 ptf4/tpm2ch0 ptf5/tpm2ch1 ptf2/tpm1ch4 ptf1/tpm1ch3 ptf0/tpm1ch2 ptf6 ptf7/txcan port e pte3/tpm1ch1 pte4/miso1 pte5/mosi1 pte2/tpm1ch0 pte1/rxd1 pte0/txd1 pte6/spsck1 pte7/ss1 port g ptg3/kbip7 ptg4/xtal ptg5/extal ptg2/kbip6 ptg1/kbip1 ptg0/kbip0 ptg6 ptg7 port h pth3/rgpio9 pth4/rgpio10 pth2/rgpio8 pth1/scl2 pth0/sda2 port j ptj3/rgpio14 ptj4/rgpio15 ptj2/rgpio13 ptj1/rgpio12 ptj0/rgpio11 port a pta3/rgpio3 pta4/rgpio4 pta5/rgpio5 pta2/rgpio2 pta1/rgpio1 pta0/rgpio0 pta6/rgpio6 pta7/rgpio7 adc vrefh vrefl vddad vssad can tpmclk tpm1 tpmclk spi1 sci1 mcg iic2 usb vreg sysctl v1 coldfire core cmt port c: iro port h: scl2 sda2 port g: extal xtal port e: rxd1 txd1 port e: ss1 spsck1 mosi1 miso1 port f: tpm1ch5 tpm1ch4 tpm1ch3 tpm1ch2 port e: tpm1ch1 tpm1ch0 tpm2 port f: tpm2ch1 tpm2ch0 port c: rxcan port f: txcan iic1 port c: sda1 scl1 sci2 port c: rxd2 txd2 port b: adp7 adp6 adp5 adp4 adp3 adp2 adp1 adp0 port d: adp11 adp10 adp9 adp8 spi2 port b: ss2 spsck2 mosi2 miso2 kbi port b: kbip5 kbip4 port d: kbip3 kbip2 port g: kbip7 kbip6 kbip1 kbip0 ram rgpio port j: rgpio15 rgpio14 rgpio13 rgpio12 rgpio11 port h: rgpio10 rgpio9 rgpio8 port a: rgpio7 rgpio6 rgpio5 rgpio4 rgpio3 rgpio2 rgpio1 rgpio0 acmp port d: acmpo acmp? acmp+ rtc intc rnga irq/tpmclk vrefh vrefl vddad vssad bkgd/ms reset vdd vss vss usbdn usbdp vusb33 flash 128 or 64 kbytes 16 or 8 kbytes vdd xosc bdm dbg cau cop irq lv d
MCF51JM128 coldfire microcontroller, rev. 2 MCF51JM128 family configurations freescale semiconductor 6 1.3 features table 2 describes the functional units of the MCF51JM128 series. table 2. MCF51JM128 series functional units unit function cf1core (v1 coldfire core) executes programs and interrupt handlers bdm (background debug module) provides a single-pin debugging interface (part of the v1 coldfire core) dbg (debug) provides debugging and emulation capabilities (part of the v1 coldfire core) sysctl (system control) provi des lvd, cop, external interrupt request, and so on flash (flash memory) provides storage for program code and constants ram (random-access memory) provides storage for program code, constants, and variables rgpio (rapid general-purpose input/output) allows i/o port access at cpu clock speeds vreg (voltage regulator) controls power management throughout the device usbotg (usb on-the-go) supports the usb on-the-go dual-role controller adc (analog-to-digital converter) measures anal og voltages at up to 12 bits of resolution tpm1, tpm2 (timer/pulse-width modulators) provide a variety of timing-based features cf1_intc (interrupt controller) controls and prioritizes all device interrupts cau (cryptographic acceleration unit) co-processor support for des, 3des, aes, md5, and sha-1 rnga (random number generator accelerator) 32-bit ran dom number generator that complies with fips-140 rtc (real-time counter) provides a cons tant-time base with optional interrupt acmp (analog comparator) compares two analog inputs cmt (carrier modulator timer) infrared output used for the remote controller iic1, iic2 (inter-integrated circuits) suppo rts the standard iic communications protocol kbi (keyboard interrupt) provides pin interrupt capabilities mcg (multipurpose clock generator) provides clocking options for the device, including a phase-locked loop (pll) and frequency-locked loop (fll) for multiplying slower reference clock sources xosc (crystal oscillator) supports low/high range crystals can (controller area network) supports standard can communications protocol sci1, sci2 (serial communications interfaces) serial communications uarts that can support rs-232 and lin protocols spi1, spi2 (serial peripheral interfaces) provide a 4-pin synchronous serial interface
MCF51JM128 family configurations MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 7 1.3.1 feature list ? 32-bit version 1 coldfire? central processor unit (cpu) ? up to 50.33 mhz at 2.7 v ? 5.5 v ? performance (dhrystone 2.1): ? 0.94 dhrystone 2.1 mips per mhz when running from internal ram ? 0.76 dhrystone 2.1 mips per mhz when running from flash ? implements instruction set revision c (isa_c) ? supports up to 30 peripheral interrupt requests and seven software interrupts ? on-chip memory ? up to 128 kbytes flash memory with read/program/erase over full operating voltage and temperature range ? up to 16 kbytes static random access memory (ram) ? security circuitry to pr event unauthorized access to ram and flash contents ? power-saving modes ? two low-power stop plus wait modes ? peripheral clock enable register can disable clocks to unused modules, thereby reducing currents; this behavior allows clocks to remain enabled to specific perhipherals in stop3 mode ? very lower power real-time counter for use in run, wait , and stop modes with internal and external clock sources ? four clock source options ? oscillator (xosc) ? loop-control pier ce oscillator; crystal or ceramic resona tor range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz ? fll/pll controlled by internal or external reference ? trimmable internal reference allows 0.2% resolution and 2% deviation ? system protection features ? watchdog computer operating properly (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode and illegal address detection with programmable rese t or exception response ? flash block protection ? debug support ? single-wire background debug interface ? 4 program counters plus two address (optional data) break point registers with programmable 1- or 2-level trigger response ? 64-entry processor status and debug data tr ace buffer with programma ble start/sto p conditions ? universal serial bus (usb) on-the-go dual-role controller ? full-speed usb device controller ? fully compliant with usb specification 1.1 and 2.0 ? 16 bidirectional endpoints, with double buffering to provide the maximum throughput ? supports control, bulk, interrupt, and isochronous endpoints ? supports bus-powered capability with low-power consumption ? full-speed / low-sp eed host controller ? host mode allows control, bulk, interrupt, and isochronous transfers ? otg protocol logic ? on-chip usb transceiver ? on-chip 3.3 v usb regulator and pull-up resistors save system cost
MCF51JM128 coldfire microcontroller, rev. 2 MCF51JM128 family configurations freescale semiconductor 8 ? controller area network (mscan) ? implementation of the can protocol ? version 2.0a/b ? five receive buffers with fifo storage scheme ? three transmit buffers with internal prio ritization using a ?lo cal priority? concept ? flexible maskable identifier filter programmable as 2x32-bit, 4x16-bit, or 8x8-bit ? programmable wakeup functionality with integrated low-pass filter ? programmable loopback mode supports self-test operation ? programmable bus-off recovery functionality ? internal timer for time- stamping of received an d transmitted messages ? cryptographic acceleration unit (cau) ? co-processor support of des, 3des, aes, md5, and sha-1 ? random number genera tor accelerator (rnga) ? 32-bit random number generator that complies with fips-140 ? analog-to-digital converter (adc) ? 12-channel, 12-bit resolution ? output formatted in 12-, 10-, or 8-bit right-justified format ? single or continuous conversion, and select able asynchronous hardware conversion trigger ? operation in stop3 mode ? automatic compare function ? internal temperature sensor ? analog comparators (acmp) ? selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output ? option to compare to fixed internal bandgap reference voltage ? option to route output to tpm module ? operation in stop3 mode ? inter-integrated circuit (iic) ? up to 100 kbps with maximum bus loading ? multi-master operation ? programmable slave address ? supports broadcast mode and 10-bit address extension ? serial communications interfaces (sci) ? two scis with full-duplex, non-return-to-zero (nrz) format ? lin master extended break generation ? lin slave extended break detection ? programmable 8-bit or 9-bit character length ? wake up on active edge ? serial peripheral interfaces (spi) ? two serial peripheral interfaces with fu ll-duplex or single -wire bidirectional ? double-buffered tr ansmit and receive ? programmable transmit bit rate, phase, polarity, and slave select output ? msb-first or lsb-first shifting ? timer/pulse width modulator (tpm) ? 16-bit free-running or modulo up/down count operation ? up to eight channels, where each channel can be an input capture, output compar e, or edge-aligned pwm ? one interrupt per channel plus terminal count interrupt
MCF51JM128 family configurations MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 9 ?rtc ? 8-bit modulus counter with binary- or decimal-based prescaler ? external clock source for precise time base, ti me-of-day, calendar or task scheduling functions ? free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components ? carrier modulator timer (cmt) ? carrier generator, modulator, and transm itter drive the infrared out (iro) pin ? operation in independent high/low time control, baseband, fsk, and direct iro control modes ? input/output ? 66 gpios ? eight keyboard interrupt pins with selectable polarity ? hysteresis and configurable pull-up device on all input pins ; configurable slew rate and drive strength on all output pins ? 16 bits of rapid gpio connected to the processor?s local 32-bit platform bus with set, clear, and faster toggle functionality 1.4 part numbers table 3. orderable part number summary freescale part number description flash / sram (kbytes) package temperature MCF51JM128evlk MCF51JM128 coldfire microcontroller with cau enabled 128 / 16 80 lqfp ?40 to +105 c MCF51JM128vlk MCF51JM128 coldfire microcontroller 128 / 16 80 lqfp ?40 to +105 c MCF51JM128vlh MCF51JM128 coldfire microcontroller 128 / 16 64 lqfp ?40 to +105 c MCF51JM128vqh MCF51JM128 coldfire microcontroller 128 / 16 64 qfp ?40 to +105 c MCF51JM128vld MCF51JM128 coldfire microcontroller 128 / 16 44 lqfp ?40 to +105 c mcf51jm64evlk mcf51jm64 co ldfire microcontroller with cau enabled 64 / 16 80 lqfp ?40 to +105 c mcf51jm64vlk mcf51jm64 coldfire microcontroller 64 / 16 80 lqfp ?40 to +105 c mcf51jm64vlh mcf51jm64 coldfire microcontroller 64 / 16 64 lqfp ?40 to +105 c mcf51jm64vqh mcf51jm64 coldfire microcontroller 64 / 16 64 qfp ?40 to +105 c mcf51jm64vld mcf51jm64 coldfire microcontroller 64 / 16 44 lqfp ?40 to +105 c mcf51jm32evlk mcf51jm32 co ldfire microcontroller with cau enabled 32 / 16 80 lqfp ?40 to +105 c mcf51jm32vlk mcf51jm32 coldfire microcontroller 32 / 16 80 lqfp ?40 to +105 c mcf51jm32vlh mcf51jm32 coldfire microcontroller 32 / 16 64 lqfp ?40 to +105 c mcf51jm32vqh mcf51jm32 coldfire microcontroller 32 / 16 64 qfp ?40 to +105 c mcf51jm32vld mcf51jm32 coldfire microcontroller 32 / 16 44 lqfp ?40 to +105 c
MCF51JM128 coldfire microcontroller, rev. 2 MCF51JM128 family configurations freescale semiconductor 10 1.5 pinouts and packaging figure 2 shows the pinout of the 80-pin lqfp. figure 2. 80-pin lqfp ptc4 irq / tpmclk reset ptf0 / tpm1ch2 ptf1 / tpm1ch3 ptf2 / tpm1ch4 ptf3 / tpm1ch5 ptf4 / tpm2ch0 ptc6 / rxcan ptf7 / txcan ptf5 / tpm2ch1 ptf6 pte0 / txd1 pte1 / rxd1 pte2 / tpm1ch0 pte3 / tpm1ch1 ptc7 pth0 / sda2 pth1 / scl2 pth2 / rgpio8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pth3 / rgpio9 pth4 / rgpio10 pte4 / miso1 pte5 / mosi1 pte6 / spsck1 pte7 / s s1 vdd vss usbdn usbdp vusb33 ptg0 / kbip0 ptg1 / kbip1 pta0 / rgpio0 pta1 / rgpio1 pta2 / rgpio2 pta3 / rgpio3 pta4 / rgpio4 pta5 / rgpio5 pta6 / rgpio6 ptj3 / rgpio14 ptj2 / rgpio13 ptj1 / rgpio12 ptj0 / rgpio11 ptd2 / kbip2 / acmpo vssad vrefl vrefh vddad ptd1 / adp9 / acmp? ptd0 / adp8 / acmp+ ptb7 / adp7 ptb6 / adp6 ptb5 / kbip5 / adp5 ptb4 / kbip4 / adp4 ptb3 / ss2 /adp3 ptb2 / spsck2 / adp2 ptb1 / mosi2 / adp1 ptb0 / miso2 / adp0 pta7 / rgpio7 ptc5 / rxd2 ptc3 / txd2 ptc2 / iro ptc1 / sda1 ptc0 / scl1 ptg7 ptg6 vdd vss ptg5 / extal ptg4 / xtal bkgd/ms ptg3 / kbip7 ptg2 / kbip6 ptd7 ptd6 ptd5 ptd4 / adp11 ptd3 / kbip3 / adp10 ptj4 / rgpio15
MCF51JM128 family configurations MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 11 figure 3 shows the pinout of the 64-pin lqfp and qfp. figure 3. 64-pin qfp and lqfp ptc4 irq / tpmclk reset ptf0 / tpm1ch2 ptf1 / tpm1ch3 ptf2 / tpm1ch4 ptf3 / tpm1ch5 ptf4 / tpm2ch0 ptc6 / rxcan ptf7 / txcan ptf5 / tpm2ch1 ptf6 pte0 / txd1 pte1 / rxd1 pte2 / tpm1ch0 pte3 / tpm1ch1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pte4 / miso1 pte5 / mosi1 pte6 / spsck1 pte7 / s s1 vdd vss usbdn usbdp vusb33 ptg0 / kbip0 ptg1 / kbip1 pta0 / rgpio0 pta1 / rgpio1 pta2 / rgpio2 pta3 / rgpio3 pta4 / rgpio4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ptd2 / kbip2 / acmpo vssad vrefl vrefh vddad ptd1 / adp9 / acmp? ptd0 / adp8 / acmp+ ptb7 / adp7 ptb6 / adp6 ptb5 / kbip5 / adp5 ptb4 / kbip4 / adp4 ptb3 / s s2 /adp3 ptb2 / spsck2 / adp2 ptb1 / mosi2 / adp1 ptb0 / miso2 / adp0 pta5 / rgpio5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ptc5 / rxd2 ptc3 / txd2 ptc2 / iro ptc1 / sda1 ptc0 / scl1 vss ptg5 / extal ptg4 / xtal bkgd/ms ptg3 / kbip7 ptg2 / kbip6 ptd7 ptd6 ptd5 ptd4 / adp11 ptd3 / kbip3 / adp10
MCF51JM128 coldfire microcontroller, rev. 2 MCF51JM128 family configurations freescale semiconductor 12 figure 4 shows the pinout of the 44-pin lqfp. figure 4. 44-pin lqfp table 4 shows the package pin assignments. table 4. pin assignments by package and pin sharing priority pin number <-- lowest priority --> highest 80 64 44 port pin alt 1 alt 2 111 ptc4 ? 222 ? irq tpmclk 3 3 3 ? reset ? 4 4 4 ptf0 tpm1ch2 ? 5 5 5 ptf1 tpm1ch3 ? 6 6 ? ptf2 tpm1ch4 ? 7 7 ? ptf3 tpm1ch5 ? 8 8 6 ptf4 tpm2ch0 busclk_out 9 9 ? ptc6 rxcan ? 10 10 ? ptf7 txcan ? 11 11 7 ptf5 tpm2ch1 ? 12 12 ? ptf6 ? ? 13 13 8 pte0 txd1 ? 14 14 9 pte1 rxd1 ? 15 15 10 pte2 tpm1ch0 ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 ptc4 irq / tpmclk reset ptf0 / tpm1ch2 ptf1 / tpm1ch3 ptf4 / tpm2ch0 ptf5 / tpm2ch1 pte0 / txd1 pte1 / rxd1 pte2 / tpm1ch0 pte3 / tpm1ch1 pte4 / miso1 pte5 / mosi1 pte6 / spsck1 pte7 / s s1 vdd vss usbdn usbdp vusb33 ptg0 / kbip0 ptg1 / kbip1 ptd2 / kbip2 / acmpo vssad / vrefl vddad / vrefh ptd1 / adp9 / acmp? ptd0 / adp8 / acmp+ ptb5 / kbip5 / adp5 ptb4 / kbip4 / adp4 ptb3 / s s2 /adp3 ptb2 / spsck2 / adp2 ptb1 / mosi2 / adp1 ptb0 / miso2 / adp0 ptc5 / rxd2 ptc3 / txd2 ptc2 / iro ptc1 / sda1 ptc0 / scl1 vss ptg5 / extal ptg4 / xtal bkgd / ms ptg3 / kbip7 ptg2 / kbip6
MCF51JM128 family configurations MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 13 16 16 11 pte3 tpm1ch1 ? 17 ? ? ptc7 ? ? 18 ? ? pth0 sda2 ? 19 ? ? pth1 scl2 ? 20 ? ? pth2 rgpio8 ? 21 ? ? pth3 rgpio9 ? 22 ? ? pth4 rgpio10 ? 23 17 12 pte4 miso1 ? 24 18 13 pte5 mosi1 ? 25 19 14 pte6 spsck1 ? 26 20 15 pte7 ss1 ? 27 21 16 ? ? vdd 28 22 17 ? ? vss 29 23 18 ? ? usbdn 30 24 19 ? ? usbdp 31 25 20 ? ? vusb33 32 26 21 ptg0 kbip0 usb_alt_clk 33 27 22 ptg1 kbip1 ? 34 28 ? pta0 rgpio0 usb_sessvld 35 29 ? pta1 rgpio1 usb_sessend 36 30 ? pta2 rgpio2 usb_vbusvld 37 31 ? pta3 rgpio3 usb_pullup(d+) 38 32 ? pta4 rgpio4 usb_dm_down 39 33 ? pta5 rgpio5 usb_dp_down 40 ? ? pta6 rgpio6 usb_id 41 ? ? pta7 rgpio7 ? 42 34 23 ptb0 miso2 adp0 43 35 24 ptb1 mosi2 adp1 44 36 25 ptb2 spsck2 adp2 45 37 26 ptb3 ss2 adp3 46 38 27 ptb4 kbip4 adp4 47 39 28 ptb5 kbip5 adp5 48 40 ? ptb6 adp6 ? table 4. pin assignments by package and pin sharing priority (continued) pin number <-- lowest priority --> highest 80 64 44 port pin alt 1 alt 2
MCF51JM128 coldfire microcontroller, rev. 2 MCF51JM128 family configurations freescale semiconductor 14 49 41 ? ptb7 adp7 ? 50 42 29 ptd0 adp8 acmp+ 51 43 30 ptd1 adp9 acmp? 52 44 31 ? ? vddad 53 45 ? ? vrefh 54 46 32 ? ? vrefl 55 47 ? ? vssad 56 48 33 ptd2 kbip2 acmpo 57 ? ? ptj0 rgpio11 ? 58 ? ? ptj1 rgpio12 ? 59 ? ? ptj2 rgpio13 ? 60 ? ? ptj3 rgpio14 ? 61 ? ? ptj4 rgpio15 ? 62 49 ? ptd3 kbip3 adp10 63 50 ? ptd4 adp11 ? 64 51 ? ptd5 ? ? 65 52 ? ptd6 ? ? 66 53 ? ptd7 ? ? 67 54 34 ptg2 kbip6 ? 68 55 35 ptg3 kbip7 ? 69 56 36 ? bkgd ms 70 57 37 ptg4 xtal 71 58 38 ptg5 extal 72 59 39 ? ? vss 73 ? ? ? ? vdd 74 ? ? ptg6 ? ? 75 ? ? ptg7 ? ? 76 60 40 ptc0 scl1 ? 77 61 41 ptc1 sda1 ? 78 62 42 ptc2 iro ? 79 63 43 ptc3 txd2 ? 80 64 44 ptc5 rxd2 ? table 4. pin assignments by package and pin sharing priority (continued) pin number <-- lowest priority --> highest 80 64 44 port pin alt 1 alt 2
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 15 2 preliminary electrical characteristics this section contains electrical specification tables and refe rence timing diagrams for the MCF51JM128 microcontroller, including detailed information on power considerations, dc /ac electrical characteristics, and ac timing specifications. the electrical specificatio ns are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this ear ly stage of the product life cycle. thes e specifications will, however, be met for production silicon. finalized specifications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this data sheet supersede any values found in the module specifications. 2.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following cla ssification is used and the parameters are tagge d accordingly in the tables where appropriate: note the classification is shown in the column labeled c in the parameter tables where appropriate. 2.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 6 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, v ss or v dd ). table 5. parameter classifications p those parameters are guaranteed during pr oduction testing on each individual device. c those parameters are achieved by the design characterizat ion by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design char acterization on a small sample size from typical devices under typical c onditions unless otherwise note d. all values shown in the typical column are within this category. d those parameters are derive d mainly from simulations.
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 16 2.3 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather th an being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd is small. table 6. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to + 5.8 v input voltage v in ? 0.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1 , 2 , 3 1 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load shunt current is greater than maximum injection current. this is the greatest ri sk when the mcu is no t consuming power. examples: if no system clock is present or if the clock rate is lo w, which would reduce overall power consumption. i d 25 ma maximum current into v dd i dd 120 ma storage temperature t stg ?55 to +150 c maximum junction temperature t j 150 c table 7. thermal characteristics rating symbol value unit operating temperature range (packaged) t a ?40 to +105 c thermal resistance 1,2,3,4 80-pin lqfp 1s 2s2p 64-pin lqfp 1s 2s2p 64-pin qfp 1s 2s2p 44-pin lqfp 1s 2s2p 1 junction temperature is a function of die si ze, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, am bient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 junction to ambient natural convection ja 52 40 65 47 54 40 69 48 c/w
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 17 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 where: t a = ambient temperature, c ja = package thermal resistan ce, junction-to-ambient, c/wp d = p int + p i/o p int = i dd v dd , watts ? chip internal powerp i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the particular pa rt. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations 1 and 2 iteratively for any value of t a . 2.4 electrostatic discharge (e sd) protection characteristics although damage from static discharge is much less common on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qualification tests are performe d to ensure that these device s can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with cdf-aec-q00 stress test qualification for automotive grade integrated circuits. (http://www.aecouncil.com/) this device was qualified to aec-q100 rev e. a device is considered to have failed if, after exposure to esd pulses, the devi ce no longer meets the device specification requirements. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 1s - single layer board, one signal layer 4 2s2p - four layer board, 2 signal and 2 power layers table 8. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulse per pin ? 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 18 2.5 dc characteristics this section includes information about power supply requirements , i/o pin characteristics, and po wer supply current in various operating modes. table 9. esd and latch-up protection characteristics num rating symbol min max unit 1 human body model (hbm) v hbm +/? 2000 ? v 2 charge device model (cdm) v cdm +/? 500 ? v 3 latch-up current at t a = 105 ci lat +/? 100 ? ma table 10. dc characteristics num c parameter symbol min typ 1 max unit 1 operating voltage 2 2.7 ? 5.5 v 2p output high voltage ? low drive (ptxdsn = 0) 5 v, i load = ?4 ma 3 v, i load = ?2 ma 5 v, i load = ?2 ma 3 v, i load = ?1 ma v oh v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? v output high voltage ? high drive (ptxdsn = 1) 5 v, i load = ?15 ma 3 v, i load = ?8 ma 5 v, i load = ?8 ma 3 v, i load = ?4 ma v dd ? 1.5 v dd ? 1.5 v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? ? ? ? 3p output low voltage ? low drive (ptxdsn = 0) 5 v, i load = 4ma 3 v, i load = 2 ma 5 v, i load = 2 ma 3 v, i load = 1 ma v ol ? ? ? ? 1.5 1.5 0.8 0.8 v output low voltage ? high drive (ptxdsn = 1) 5 v, i load = 15 ma 3 v, i load = 8 ma 5 v, i load = 8 ma 3 v, i load = 4 ma ? ? ? ? 1.5 1.5 0.8 0.8 4 p output high current ? max total i oh for all ports 5v 3v i oht ? ? ? ? 100 60 ma 5 p output low current ? max total i ol for all ports 5v 3v i olt ? ? ? ? 100 60 ma
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 19 6 p input high voltage; all digital inputs v ih 3.25 2.10 ? ? ?v v dd = 5v v dd = 3v 7 p input low voltage; all digital inputs v il ?? 1.75 1.05 v v dd = 5v v dd = 3v 8 p input hysteresis; all digital inputs v hys 0.06 x v dd mv 9 p input leakage current; input only pins 3 |i in |?0.11 a 10 p high impedance (off-state) leakage current 3 |i oz |?0.11 a 11 p internal pullup resistors 4 r pu 20 45 65 k 12 p internal pulldown resistors 5 r pd 20 45 65 k 13 internal pullup resistor to usbdp (to v usb33 ) idle tr a n s m i t r pupd 900 1425 1300 2400 1575 3090 k 14 c input capacitance; all non-supply pins c in ?? 8pf 15 p por rearm voltage v por 0.9 1.4 2.0 v 16 d por rearm time t por 10 ? ? s table 10. dc characteristics (continued) num c parameter symbol min typ 1 max unit
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 20 17 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d 1 3.9 4.0 4.0 4.1 4.1 4.2 v p low-voltage detection threshold ? low range v dd falling v dd rising v lv d 0 2.48 2.54 2.56 2.62 2.64 2.70 v 18 c low-voltage warning threshold ? high range 1 v dd falling v dd rising v lv w 3 4.5 4.6 4.6 4.7 4.7 4.8 v 19 p low-voltage warning threshold ? high range 0 v dd falling v dd rising v lv w 2 4.2 4.3 4.3 4.4 4.4 4.5 v 20 p low-voltage warning threshold low range 1 v dd falling v dd rising v lv w 1 2.84 2.90 2.92 2.98 3.00 3.06 v 21 c low-voltage warning threshold ? low range 0 v dd falling v dd rising v lv w 0 2.66 2.72 2.74 2.80 2.82 2.88 v 22 23 t low-voltage inhibit reset/recover hysteresis 5 v 3 v v hys ? ? 100 60 ? ? mv 1 typical values are based on characterization data at 25 c unless otherwise stated. 2 operating voltage with usb enabled can be found in section 2.14, ?usb electricals .? 3 measured with v in = v dd or v ss . 4 measured with v in = v ss . 5 measured with v in = v dd . table 10. dc characteristics (continued) num c parameter symbol min typ 1 max unit
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 21 figure 5. typical low-side drive (sink) characteristics ? high drive (ptxdsn = 1) figure 6. typical low-side drive (sink) characteristics ? low drive (ptxdsn = 0) figure 7. typical high-side drive (source) characteristics ? high drive (ptxdsn = 1) typical v ol vs. i ol at v dd = 5v 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i ol (ma) v ol (v) hot (105c) room (25c) cold (-40c) typical v ol vs. i ol at v dd = 3v 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 0 12345678910111213 i ol (ma) v ol (v) hot ( 105c) room ( 25c) cold ( - 40c) typical v ol vs. i ol at v dd = 5 v 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 012345 i ol (ma) v ol (v) hot (105c) room (25c) cold (-40c) typical v ol vs. i ol at v dd = 3v 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 0123 i ol (ma) v ol (v) hot (105c) room (25c) cold (-40c) typical v dd - v oh vs. i oh at v dd = 5 v 0.0 0.2 0.4 0.6 0.8 0 -1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 i oh (ma) v dd - v oh (v) hot (105c) room (25c) col d (-40c) typical v dd - v oh vs. i oh at v dd =3v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 -1-2-3-4-5-6-7-8-9-10-11-12-13 i oh (ma) v dd - v oh (v) hot (105c) room (25c) cold (-40c)
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 22 figure 8. typical high-side drive (source) characteristics ? low drive (ptxdsn = 0) 2.6 supply current characteristics table 11. supply current characteristics num c parameter symbol v dd (v) typical 1 max 2 unit 1 c run supply current 3 measured at (cpu clock = 2mhz, f bus = 1 mhz) ri dd 53.6 7 ma 33.6 7 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 522 30 ma 321.7 30 3 c run supply current 3 measured at (cpu clock = 48 mhz, f bus = 24 mhz) ri dd 560 70 ma 359 70 3 p stop2 mode supply current ?40 c 25 c 105 c ?40 c 25 c 105 c s2i dd 50.80 3 3 20 a 30.80 3 3 20 a 5 p stop3 mode supply current ?40 c 25 c 105 c ?40 c 25 c 105 c s3i dd 50.90 3 3 20 a 30.90 3 3 20 a 6 p rtc adder to stop2 or stop3 4 , 25 c5300na 3300 na typical v dd - v oh vs. i oh at v dd = 5v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 -1-2-3-4-5 i oh (ma) v dd - v oh (v) hot (105c) room (25c) cold (-40c) typical v dd - v oh vs. i oh at v dd =3v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 -1-2-3 i oh (ma) v dd - v oh (v) hot (105c) room (25c) cold (-40c)
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 23 2.7 analog comparator (acmp) electricals 2.8 adc characteristics 7 p lvd adder to stop3 (lvde = lvdse = 1) 5 110 a 390 a 8 p adder to stop3 for oscillator enabled 5 (erclken =1 and erefsten = 1) 55 a 35 a 1 typicals are measured at 25 c. 2 values given here are preliminary estimates prior to completing characterization. 3 all modules? clocks are switched on, code runs from flash, in fei mode, and there are no dc loads on port pins. 4 most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 5 values given under the following conditions: low range operation (range = 0), low power mode (hgo = 0) table 12. analog comparator electrical specifications num c rating symbol min typical max unit 1 supply voltage v dd 2.7 ? 5.5 v 2 supply current (active) i ddac ?2035 a 3 analog input voltage v ain v ss ? 0.3 ? v dd v 4 analog input offset voltage v aio 20 40 mv 5 analog comparator hysteresis v h 3.0 6.0 20.0 mv 6 analog input leakage current i alkg -- -- 1.0 a 7 analog comparator initialization delay t ainit ??1.0 s 8 bandgap voltage reference factory trimmed at v dd = 3.0 v, temp = 25 cv bg 1.19 1.20 1.21 v table 13. 5 volt 12-bit adc operating conditions characteristic conditions symb min typ 1 max unit comment supply voltage absolute v ddad 2.7 ? 5.5 v delta to v dd (v dd -v ddad ) 2 v ddad ?100 0 +100 mv ground voltage delta to v ss (v ss -v ssad ) 2 v ssad ?100 0 +100 mv ref voltage high v refh 2.7 v ddad v ddad v ref voltage low v refl v ssad v ssad v ssad v input voltage v adin v refl ?v refh v input capacitance c adin ?4.55.5pf table 11. supply current characteristics num c parameter symbol v dd (v) typical 1 max 2 unit
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 24 figure 9. adc input impedance equivalency diagram input resistance r adin ?3 5k analog source resistance 12 bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 2 5 k external to mcu 10 bit mode f adck > 4mhz f adck < 4mhz ? ? ? ? 5 10 8 bit mode (all valid f adck )??10 adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz low power (adlpc=1) 0.4 ? 4.0 1 typical values assume v ddad = 5.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 dc potential difference. table 13. 5 volt 12-bit adc op erating conditions (continued) characteristic conditions symb min typ 1 max unit comment + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 25 table 14. 5 volt 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic conditions c symb min typ 1 max unit comment supply currentadlpc= 1adlsmp=1ad co=1 ti ddad ? 133 ? a supply currentadlpc= 1adlsmp=0ad co=1 ti ddad ? 218 ? a supply currentadlpc= 0adlsmp=1ad co=1 ti ddad ? 327 ? a supply currentadlpc= 0adlsmp=0ad co=1 pi ddad ?0.582 1 ma supply current stop, reset, module off i ddad ?0.011 1 a adc asynchronous clock source high speed (adlpc=0) t f adack 23.35mhzt adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp=0) t t adc ? 20 ? adck cycles see ta bl e 9 for conversion time variances long sample (adlsmp=1) ? 40 ? sample time short sample (adlsmp=0) t t ads ? 3.5 ? adck cycles long sample (adlsmp=1) ? 23.5 ? total unadjusted error 12 bit mode t e tue ? 3.0 ? lsb 2 includes quantization 10 bit mode p ? 1 2.5 8 bit mode t ? 0.5 1.0 differential non-linearity 12 bit mode t dnl ? 1.75 ? lsb 2 10 bit mode 3 p? 0.5 1.0 8 bit mode 3 t? 0.3 0.5 integral non-linearity 12 bit mode t inl ? 1.5 ? lsb 2 10 bit mode t ? 0.5 1.0 8 bit mode t ? 0.3 0.5 zero-scale error 12 bit mode t e zs ? 1.5 ? lsb 2 v adin = v ssad 10 bit mode p ? 0.5 1.5 8 bit mode t ? 0.5 0.5 full-scale error 12 bit mode t e fs ? 1?lsb 2 v adin = v ddad 10 bit mode t ? 0.5 1 8 bit mode t ? 0.5 0.5
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 26 quantization error 12 bit mode d e q ? -1 to 0 ? lsb 2 10 bit mode ? ? 0.5 8 bit mode ? ? 0.5 input leakage error 12 bit mode d e il ? 1?lsb 2 pad leakage 4 * r as 10 bit mode ? 0.2 2.5 8 bit mode ? 0.1 1 1 typical values assume v ddad = 5.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. ty pical values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10 bit and 8 bit modes 4 based on input pad leakage current. refer to pad electricals. table 14. 5 volt 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions c symb min typ 1 max unit comment
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 27 2.9 external oscillator (xosc) characteristics table 15. oscillator electrical specifications (temperature range = ?40 to 105 c ambient) num c rating symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit 1 oscillator crystal or resonator (erefs = 1, erclken = 1) ? low range (range = 0) ? high range (range = 1) fee or fbe mode 2 ? high range (range = 1) pee or pbe mode 3 ? high range (range = 1, hgo = 1) blpe mode ? high range (range = 1, hgo = 0) blpe mode 2 when mcg is configured for fee or fbe mode, input clock source must be divisible using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 when mcg is configured for pee or pbe mode , input clock source must be divisible using rdiv to within the range of 1 mhz to 2 mhz. f lo f hi-fll f hi-pll f hi-hgo f hi-lp 32 1 1 1 1 ? ? ? ? ? 38.4 5 16 16 8 khz mhz mhz mhz mhz 2 load capacitors c 1 c 2 see crystal or resonator manufacturer?s recommendation. 3 feedback resistor ? low range (32 khz to 38.4 khz) ? high range (1 mhz to 16 mhz) r f 10 1 m m 4? series resistor ? low range, low gain (range = 0, hgo = 0) ? low range, high gain (range = 0, hgo = 1) 8mhz 4mhz 1 mhz ? high range, low gain (range = 1, hgo = 0) ? high range, high gain (range = 1, hgo = 1) 8mhz 4mhz 1 mhz r s ? ? ? ? ? ? 0 100 0 0 0 0 ? ? ? 0 10 20 k 5t crystal start-up time 4 ? low range, low gain (range = 0, hgo = 0) ? low range, high gain (range = 0, hgo = 1) ? high range, low gain (range = 1, hg0 = 0) 5 ? high range, high gain (range = 1, hg0 = 1) 5 4 this parameter is characterized and not tested on each device. pr oper pc board-layout procedures must be followed to achieve specifications. 5 4 mhz crystal t cstl-lp t cstl-hgo t csth-lp t csth-hgo ? ? ? ? 200 400 5 15 ? ? ? ? ms 6t square wave input clock fr equency (erefs = 0, erclken = 1) ? fee or fbe mode 2 ? pee or pbe mode 3 ? blpe mode f extal 0.03125 1 0 ? ? ? 5 16 40 mhz mhz mhz
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 28 2.10 mcg specifications table 16. mcg frequency specifications (temperature range = ?40 to 125 c ambient) num c rating symbol min typical max unit 1p internal reference frequency - factory trimmed at v dd = 5 v and temperature = 25 c f int_ft ? 31.25 ? khz 2p average internal reference frequency - untrimmed 1 f int_ut 25 32.7 41.66 khz 3p average internal reference frequency - user trimmed f int_t 31.25 ? 39.0625 khz 4 d internal reference startup time t irefst ?60100us 5? dco output frequency range - untrimmed 1 value provided for reference: f dco_ut = 1024 x f int_ut f dco_ut 25.6 33.48 42.66 mhz 6 p dco output frequency range - trimmed f dco_t 32 ? 40 mhz 7c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 8c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco 9p total deviation of trimmed dco output frequency over voltage and temperature f dco_t ? + 0.5 -1.0 2 %f dco 10 c total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 - 70 c f dco_t ? 0.5 1 %f dco 11 c fll acquisition time 2 t fll_acquire ??1ms 12 d pll acquisition time 3 t pll_acquire ??1ms 13 c long term jitter of dco output clock (averaged over 2ms interval) 4 c jitter ?0.020.2 %f dco 14 d vco operating frequency f vco 7.0 ? 55.0 mhz 17 t jitter of pll output clock measured over 625 ns 5 f pll_jitter_625ns ? 0.566 5 ? %f pll 18 d lock entry frequency tolerance 6 d lock 1.49 ? 2.98 %
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 29 2.11 ac characteristics this section describes ac timing charact eristics for each pe ripheral system. 2.11.1 control timing 19 d lock exit frequency tolerance 7 d unl 4.47 ? 5.97 % 20 d lock time - fll t fll_lock ?? t fll_acquire+ 1075(1/ f int_t ) s 21 d lock time - pll t pll_lock ?? t pll_acquire+ 1075(1/ f pll_r ef) s 22 d loss of external clock minimum frequency - range = 0 f loc_low (3/5) x f int ? ? khz 1 trim register at default value (0x80) a nd ftrim control bit at default value (0x0). 2 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, th is specification assumes it is already running. 4 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered s upplies and clocked by a stable external clock signal. noise injected into the fl l circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 5 625 ns represents 5 time quanta for can applications, under wors t case conditions of 8 mhz can bus clock, 1 mbps can bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. 6 below d lock minimum, the mcg is guaranteed to enter lock. above d lock maximum, the mcg does not enter lock. but if the mcg is already in lock, then the mcg may stay in lock. 7 below d unl minimum, the mcg does not exit lock if already in lock. above d unl maximum, the mcg is guaranteed to exit lock. table 17. control timing num c parameter symbol min typ 1 max unit 1 bus frequency (t cyc = 1/f bus )f bus dc ? 24 mhz 2 internal low-power oscillator period t lpo 700 1300 s 3 external reset pulse width 2 (t cyc = 1/f self_reset ) t extrst 100 ? ns 4 reset low drive t rstdrv 66 x t cyc ?ns 5 active background debug mode latch setup time t mssu 500 ? ns table 16. mcg frequency specifications (continued)(temperature range = ?40 to 125 c ambient) num c rating symbol min typical max unit
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 30 figure 10. reset timing figure 11. irq/kbipx timing 2.11.2 timer/pwm (tpm) module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. 6 active background debug mode latch hold time t msh 100 ? ns 7 irq pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 x t cyc ??ns 8 kbipx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 x t cyc ??ns 9 port rise and fall time (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 3 30 ns 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. 2 this is the shortest pulse guaranteed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. 3 this is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 105 c. table 17. control timing num c parameter symbol min typ 1 max unit t extrst reset pin t ihil irq/kbipx t ilih irq/kbipx
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 31 figure 12. timer external clock figure 13. timer input capture pulse 2.11.3 mscan table 18. tpm input timing num c function symbol min max unit 1? external clock frequency f tpmext dc f bus /4 mhz 2? external clock period t tpmext 4? t cyc 3d external clock high time t clkh 1.5 ? t cyc 4d external clock low time t clkl 1.5 ? t cyc 5d input capture pulse width t icpw 1.5 ? t cyc table 19. mscan wake-up pulse characteristics num c parameter symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0v, 25 c unless otherwise stated. max unit 1d mscan wake-up domin ant pulse filtered t wup 2 s 2d mscan wake-up dominant pulse pass t wup 55 s t tpmext t clkh t clkl tpmxclk t icpw tpmxchn t icpw tpmxchn
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 32 2.12 spi characteristics table 20 and figure 14 through figure 17 describe the timing requirements for the spi system. table 20. spi electrical characteristic num 1 1 refer to figure 14 through figure 17 . c characteristic 2 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit 1 d operating frequency master slave f op f op f bus /2048dc f bus /2 f bus /4 hz 2 d cycle time master slave t sck t sck 2 4 2048 ? t cyc t cyc 3 d enable lead time master slave t lead t lead ? 1/2 1/2 ? t sck t s ck 4 d enable lag time master slave t lag t lag ? 1/2 1/2 ? t sck t s ck 5 d clock (spsck) high time master and slave t sckh 1/2 t sck ? 25 ? ns 6 d clock (spsck) low time master and slave t sckl 1/2 t sck ? 25 ? ns 7 d data setup time (inputs) master slave t si(m) t si(s) 30 30 ? ? ns ns 8 d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ? ? ns ns 9 d access time, slave 3 3 time to data active from high-impedance state. t a 040ns 10 d disable time, slave 4 4 hold time to high-impedance state. t dis ?40ns 11 d data setup time (outputs) master slave t so t so 25 25 ? ? ns ns 12 d data hold time (outputs) master slave t ho t ho ?10 ?10 ? ? ns ns
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 33 figure 14. spi master timing (cpha = 0) figure 15. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 34 figure 16. spi slave timing (cpha = 0) figure 17. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character received 2 2 3 4 6 7 8 9 11 12 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character received 2 2 3 4 6 7 8 9 11 12 4 5 5
preliminary electrical characteristics MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 35 2.13 flash specifications this section provides details about program/erase ti mes and program-erase endurance for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. 2.14 usb electricals the usb electricals for the usbotg module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. if the freescale usbotg implementation requir es additional or deviant electrical charac teristics, this space would be used to communicate that information. table 21. flash characteristics num c characteristic symbol min typ 1 1 typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. max unit 1 supply voltage for program/erase v prog/erase 2.7 5.5 v 2 supply voltage for read operation v read 2.7 5.5 v 3 internal fclk frequency 2 2 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz 4 internal fclk period (1/fclk) t fcyc 56.67 s 5 byte program time (random location) (2) t prog 9 t fcyc 6 byte program time (burst mode) (2) t burst 4 t fcyc 7 page erase time 3 3 these values are hardware state machin e controlled. user code does not n eed to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc 8 mass erase time (2) t mass 20,000 t fcyc 9c program/erase endurance 4 t l to t h = ?40 c to + 105 c t = 25 c 4 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale semiconductor defines typical endurance, please refer to engineering bulletin eb619/d, ty p i c a l endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles 10 data retention 5 5 typical data retention values are based on intrinsic capab ility of the technology measur ed at high temperature and de-rated to 25 c using the arrhenius equation. for additional in formation on how freescale semiconductor defines typical data retention, please refer to engineering bulleti n eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
MCF51JM128 coldfire microcontroller, rev. 2 preliminary electrical characteristics freescale semiconductor 36 2.15 emc performance electromagnetic compatibility (emc) performance is highly de pendant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and charact eristics of external components as well as mcu software operation all play a significant role in emc performance. the sy stem designer should consult fr eescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifically targeted at optimizing emc performance. 2.15.1 radiated emissions microcontroller radiated rf emissions ar e measured from 150 khz to 1 ghz usi ng the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurem ent is performed with the microcontroller installed on a custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two packag e orientations (north and east). for more detailed information concerning the evaluation results, conditions and setup, please refe r to the emc evaluation report for this device. table 22. internal usb 3.3v voltage regulator characteristics symbol unit min typ max regulator operating voltage v regin v 3.9 ? 5.5 vreg output v regout v33.33.6 vusb33 input with internal vreg disabled v usb33in v33.33.6 vreg quiescent current i vrq ma ? 0.5 ?
mechanical outline drawings MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 37 3 mechanical outline drawings 3.1 80-pin lqfp
MCF51JM128 coldfire microcontroller, rev. 2 mechanical outline drawings freescale semiconductor 38
mechanical outline drawings MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 39
MCF51JM128 coldfire microcontroller, rev. 2 mechanical outline drawings freescale semiconductor 40 3.2 64-pin lqfp
mechanical outline drawings MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 41
MCF51JM128 coldfire microcontroller, rev. 2 mechanical outline drawings freescale semiconductor 42
mechanical outline drawings MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 43 3.3 64-pin qfp
MCF51JM128 coldfire microcontroller, rev. 2 mechanical outline drawings freescale semiconductor 44
mechanical outline drawings MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 45
MCF51JM128 coldfire microcontroller, rev. 2 mechanical outline drawings freescale semiconductor 46 3.4 44-pin lqfp
mechanical outline drawings MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 47
MCF51JM128 coldfire microcontroller, rev. 2 mechanical outline drawings freescale semiconductor 48
revision history MCF51JM128 coldfire microcontroller, rev. 2 freescale semiconductor 49 4 revision history this section lists major changes between versions of the MCF51JM128 data sheet document. table 23. changes between revisions revision description 1 updated features list updated the figures typical low-side drive (sink) characteristics ? high drive (ptxdsn = 1) , typical low-side drive (sink) characteristics ? low drive (ptxdsn = 0) , and typical high-side drive (source) characteristics ? high drive (ptxdsn = 1) added the figure typical high-side drive (source) char acteristics ? low drive (ptxdsn = 0) updated the supply current characteristics table updated the oscillator electrical specifications (tem perature range = ?40 to 105c ambient) table updated the spi electrical characteristic table updated the dc characteristics table 2 updated the table orderable part number summary , dc characteristics , and supply current characteristics
document number: MCF51JM128 rev. 2 09/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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